US10978112B2

Memory devices having special mode access

Summary by NHIP

Special Mode Memory Device

The memory device operates in distinct modes based on data written to a control register via a serial interface. The controller receives a register write command signal of 1Fh, followed immediately by an address and data signal, with the most significant bit of the command triggering the first clock edge.

Claim Score by NHIP

Read claim 17, the broadest

Abstract

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

US10978112B2, drawing sheet 1 — Sheet 1 of 10

Term

1.1 yearsleft in the term

Expires 17 October 2027.

22 claims: 3 independent, 19 dependent

1
A memory device comprising a memory array, a register configured to control operation of the memory array based on data stored in the register, and a serial interface controller configured to:receive a first rising edge of a clock signal;receive a register write command signal comprising a register write command configured to instruct the serial interface controller to write the data to the register;receive a register address signal immediately following the register write command signal, wherein the register address signal comprises an address of the register;receive a data signal immediately following the register address signal, wherein the data signal comprises the data;andwrite the data to the register at the address.
11
A memory device comprising a memory array, a register configured to control operation of the memory array based on data stored in the register, and a serial interface controller configured to:receive a first rising edge of a clock signal;receive a register read command signal comprising a register read command configured to instruct the serial interface controller to read the data from the register;receive a register address signal immediately following the register read command signal, wherein the register address signal comprises an address of the register;read the data from the address of the register;andtransmit a data signal comprising the data.
17
Broadest claimClaim Score 77, broad(NHIP)A system comprising:a master device configured to generate a clock signal;anda memory device configured to interface with the master device using a serial peripheral interface protocol, wherein the memory device comprises a controller;wherein the master device is configured to: enable the controller;send the clock signal to the controller;send a command signal to the controller comprising a register command;andsend a register address signal immediately following the command signal, wherein the register address signal comprises an address of the register.

Independent claims3

61 paragraphs in 4 sections, as filed

This application is a continuation of U.S. patent application Ser. No. 16/151,845, filed on Oct. 4, 2018, which is a continuation of U.S. patent application Ser. No. 16/013,773, filed on Jun. 20, 2018, which is a continuation of U.S. patent application Ser. No. 14/839,173, filed on Aug. 28, 2015 now U.S. Pat. No. 10,062,420, which issued on Aug. 28, 2018, which is a divisional of U.S. patent application Ser. No. 14/231,393, filed on Mar. 31, 2014 now U.S. Pat. No. 9,122,420, which issued on Sep. 1, 2015, which is a divisional of U.S. patent application Ser. No. 13/357,533, filed on Jan. 24, 2012, now U.S. Pat. No. 8,687,422, which issued on Apr. 1, 2014, which is a divisional of U.S. patent application Ser. No. 11/873,826, filed on Oct. 17, 2007, now U.S. Pat. No. 8,102,710, which issued on Jan. 24, 2012. These are incorporated by reference herein in their entirety for all purposes.

BACKGROUND

Field of the Invention

Embodiments of the present invention relate generally to accessing and modifying settings of a NAND flash memory device, and particularly to accessing and modifying settings of a NAND flash memory device configured for interconnection via serial peripheral interface.

Description of the Related Art

Generally, most NAND flash memory devices employ parallel communication between a NAND flash device and a host device across a multitude of input pins. Though effective, the quantity of pins vastly increases the amount of space a NAND flash memory device occupies on an integrated circuit (IC) chip. As an alternative to parallel communication, serial communication may reduce the number of interconnections. However, critical functionality may be reduced as the quantity of input pins decreases.

Serial peripheral interface (SPI) permits a synchronous serial data link between a master and one or more slave devices. For a synchronous serial connection to one slave device, SPI uses four wires, including chip select (CS), serial clock (SCK), master out slave in (MOSI, or SI), and master in slave out (MISO, or SO). To communicate with additional slave devices, a unique additional CS wire accompanies each device, though the additional devices may share the same SCK, SI, and SO wires. As slave devices are selected by the master one at a time, only one slave device will communicate with the master at any given moment.

The master typically enables a slave device by setting CS low. Once enabled, the slave device may communicate with the master. With data transmission synchronized to the serial clock signal (SCK), the master initiates the data frame, sending data signals on the slave in (SI) wire and receiving data on the slave out (SO) wire. Because both transmitting and receiving take place simultaneously, SPI communication may be referred to as full duplex.

Devices which have been configured to communicate using SPI include EEPROM and NOR flash memory, two forms of nonvolatile memory devices. SPI EEPROM allows ICs with as few as eight pins, while conventional EEPROM may require 32 pins or more. SPI NOR flash memory similarly allows ICs with substantially fewer pins than conventional NOR memory.

NOR flash memory may be considered well suited to SPI. Because NOR flash memory provides full address and data buses, NOR may offer random access to any memory location. Accordingly, with a serial communication protocol such as SPI, NOR may rather easily output a desired point of data.

On the other hand, NOR flash may generally prove less desirable than other memory formats, such as NAND flash, in many applications. NAND flash memory employs shorter erase times while occupying less die space than NOR flash. Additionally, NAND flash memory cells may endure a greater number of write and erase cycles than NOR flash, often by a factor of ten or more.

Due in part to the nature of NAND memory which reads out page by page, rather than providing random access to any memory location, NAND has been historically considered unfit for use with SPI. Moreover, because much standard NAND functionality depends on enabling various input pins at certain times, attempts to combine the two may require an unwieldy translation from SPI to standard NAND, and/or may fail to provide many useful features that may be desired.

Embodiments of the present invention may be directed to one or more of the problems set forth above.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of an SPI NAND memory device configured to communicate with a master in accordance with an embodiment of the invention;

<figref idref="DRAWINGS">FIG. 2</figref> is a flow chart illustrating a method of communication between a master and the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 3</figref> is a flow chart illustrating a method of performing a register write operation using the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 4</figref> is a timing diagram illustrating the timing of signals during the method of performing a register write operation of <figref idref="DRAWINGS">FIG. 3</figref>;

<figref idref="DRAWINGS">FIG. 5</figref> is a flow chart illustrating a method of performing a register read operation using the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 6</figref> is a timing diagram illustrating the timing of signals during the method of performing a register read operation of <figref idref="DRAWINGS">FIG. 5</figref>;

<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart illustrating a method of reading a parameter page of the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of an SPI NAND memory device configured to include a block of one time programmable (OTP) memory in accordance with an embodiment of the invention;

<figref idref="DRAWINGS">FIG. 9</figref> is a flow chart illustrating a method of performing operations on one time programmable (OTP) memory in the memory device of <figref idref="DRAWINGS">FIG. 8</figref>; and

<figref idref="DRAWINGS">FIG. 10</figref> is a flow chart illustrating a method of write protecting one time programmable (OTP) memory by page or block in the memory device of <figref idref="DRAWINGS">FIG. 8</figref>.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring to <figref idref="DRAWINGS">FIG. 1</figref>, an SPI NAND memory device 10 interfaces with a master 12 using a serial peripheral interface (SPI) protocol. Controller 14 includes four interface pins including a chip select (CS) pin to receive a chip select signal CS 16, a clock (SCK) pin to receive a clock signal SCK 18, a slave in (SI) data input pin to receive an input signal SI 20, and a slave out (SO) data output pin to output an output signal SO 22. Data transfer between master 12 and controller 14 takes place serially across input signal SI 20 and output signal SO 22.

The master 12 may enable the controller 14 by setting chip select signal CS 16 from high to low. After enabling the controller 14, master 12 may send a clock signal SCK 18 and a corresponding data signal SI 20. Each bit transmitted by SI 20 (and SO 22) may be synchronous to either a rising or falling edge of clock signal SCK 18. For illustrative purposes, memory device 10 inputs data on SI 20 latched on a rising clock edge and outputs data on SO 22 released on a falling edge. Accordingly, the first rising edge of clock signal SCK 18 corresponds to the first bit of SI 20, and subsequent rising clock edges of SCK 18 correspond to subsequent bits of SI 20. In the same way, each bit output on SO 22 transitions on a falling edge of clock signal SCK 18.

Communication between master 12 and controller 14 generally begins when master 12 sets chip select CS 16 low. Master 12 subsequently sends clock signal SCK 18 and starts to send a message via SI 20. As discussed below, a message may generally comprise a one-byte command, followed by a memory address of one or more whole bytes, often further followed by data of one or more whole bytes. Controller 14 may respond by sending a synchronous message via SO 22. Due to the nature of SPI, controller 14 may continually output garbage data through SO 22 until an appropriate time when master 12 expects a response.

Master 12 may send a write register command or a read register command in a message to controller 14. The write register command or read register command causes controller 14 to access volatile memory registers 24. Data transfer to and from controller 14 and registers 24 occurs across a bus 26 controlled by control wire 28. Possible memory registers 24 may include, for example, a status register to indicate device operation status and/or a special mode enable register such as a block writing lock (BWL) register 25A to prevent certain portions of memory from being written to, a one time programmable (OTP) enable register 25B to enable reading from or writing to an OTP portion of memory, and/or a parameter page (PP) enable register 25C to enable reading from or writing to a parameter page of memory.

Controller 14 may also access registers 24 when performing internal operations. Additionally, when a particular enable bit or flag is set for a given register, controller 14 may alter operations to enter an alternative operational mode, as discussed below.

Access to registers 24 may permit a user to control many functional aspects of memory device 10, such as output buffer drive strength, desired number of clock cycles of latency for outputting data, address cycle format to require whole bytes or to use a minimum number of addresses, and/or whether to enable or disable error correcting codes (ECC). Certain registers may hold, for example, error status, which may be reset upon the issuance of a register write command, while other registers may enable a user to control timing based on varying SCK 18 frequencies. Finally, for flexibility, a register may be configured to enable memory device 10 to switch between SPI NAND and NAND user modes and interfaces.

To perform an operation on nonvolatile NAND flash memory at a particular memory address, controller 14 may send the memory address signal across bus 30 to row and column decoders (not depicted). Controller 14 may control the activation of the row and column decoders using control wire 32. Depending on the operation, the controller may, for example, load data bytes into cache register 34 through bus 36, controlling cache register 34 with control wire 38. NAND memory array 40 receives data one page at a time through data register 42, which works in conjunction with cache register 34.

Communication method 44 of <figref idref="DRAWINGS">FIG. 2</figref> provides an illustrative communication sequence from the perspective of controller 14. Beginning at step 46, controller 14 listens on the chip select input pin for a CS 16 signal. Decision block 48 indicates the moment of controller enablement which occurs when CS 16 transitions to low from high. If CS 16 transitions to high at any point thereafter, however, communication is interrupted and reset.

Once controller 14 is enabled, step 50 begins. Controller 14 reads the first eight bits sent across SI 20 into a state machine in controller 14 circuitry, though alternative embodiments may read in more than eight bits. Decision block 52 illustrates that if the state machine fails to recognize the eight bits as a valid command, the controller returns to listening for a CS 16 enable signal at step 46 and decision block 48, waiting to become re-enabled when master 12 again sets CS 16 from high to low.

If the state machine recognizes the first eight bits of SI 20 as a valid command in decision block 52, the controller 14 continues to read in subsequent data from SI 20. In step 54, controller 14 next reads in a predetermined length of bytes signifying an address, which may vary depending on the command identified by the state machine. In one embodiment, dummy bits may be transmitted as a header to the address to allow for proper byte alignment. For example, a 17 bit address may include a 7 bit dummy header, such that the entire address length conforms to a whole number of bytes. If the command requires data, the controller may next read in a predetermined length of bytes signifying data in optional step 56. A controller 14 may be configured to recognize a number of SPI NAND commands, such as page read, read status, random data read, program load, program random data input, program execute, random data input, etc.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a register write method 58 for instructing a controller 14 to write data to a memory register of registers 24 in accordance with one embodiment of the invention. Master 12 first sets CS 16 low in step 60 to enable controller 14. Once enabled, controller 14 may receive a signal from master 12 through SI 20 synchronized to clock signal SCK 18.

In step 62, master 12 first transmits an eight bit register write command signal, 1Fh in hexadecimal format, to controller 14, though alternative embodiments may use a command signal of any predetermined length that a state machine of controller 14 may accommodate. Immediately after master 12 sends the command signal, step 64 begins and master 12 sends a register address signal indicating the address of the memory register to which to write. Though the present embodiment sends a register address signal of one byte, alternative embodiments may employ a register address of any size, but typically a whole number of bytes. To the extent a register address may comprise a number of bits not a multiple of eight, dummy bits may be sent to fill spaces, which controller 14 may simply ignore as “don't care” bits.

Proceeding to step 66 immediately after sending the register address signal, master 12 next sends a one-byte data signal comprising the data to write to the register. Though the registers 24 of SPI NAND memory device 10 each comprise only one byte of data, alternative embodiments may employ registers 24 comprising a greater whole numbers of data bytes. Once master 12 has sent the data, master 12 thereafter terminates the communication sequence by setting CS 16 high in step 68.

Register write timing diagram 70 of <figref idref="DRAWINGS">FIG. 4</figref> illustrates the timing of the prescribed register write method above. The three signal lines of register write timing diagram 70 include chip select CS line 72, clock signal SCK line 74, and data input SI line 76. As discussed above, master 12 initiates communication with controller 14 by setting the CS 16 signal low, as generally indicated by reference numeral 78.

The first rising edge 80 of clock signal SCK 18, which includes rising edges 80 shown in <figref idref="DRAWINGS">FIG. 4</figref> as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, and continuing, corresponds to the most significant bit (MSB) of register write command signal 82 (represented in hexadecimal format as 1Fh). Immediately following the 8-bit command signal 82, master 12 sends a one-byte register address signal 84 (having bits shown in <figref idref="DRAWINGS">FIG. 4</figref> as 0, 1, 2, 3, 4, 5, 6, and 7) MSB first, subsequently followed by a one-byte data signal 86 (having bits shown in <figref idref="DRAWINGS">FIG. 4</figref> as 0, 1, 2, 3, 4, 5, 6, and 7), also MSB first. Communication terminates when master 12 sets the CS 16 signal, as generally indicated by reference numeral 88.

Turning to <figref idref="DRAWINGS">FIG. 5</figref>, register read method 90 instructs controller 14 to output the contents of one of the memory registers 24. Beginning at step 92, master 12 first enables controller 14 by setting the CS 16 signal low. Next, master 12 sends an eight bit register read command signal across SI 20, represented in hexadecimal format as 0Fh, in step 94. As discussed above, alternative embodiments may employ a command signal of any predetermined length that a state machine of controller 14 may accommodate.

In step 96, master 12 transmits a one-byte address signal representing the address of a memory register from which to read. As above, though the present embodiment sends a register address signal of one byte, alternative embodiments may employ a register address of any size, but typically a whole number of bytes. To the extent a register address may comprise a number of bits not a multiple of eight, dummy bits may be sent to fill spaces, which controller 14 may simply ignore as “don't care” bits.

Controller 14 immediately returns the register data from the requested address via SO 22, and in step 98 master 12 subsequently receives the register data. Though the registers 24 of SPI NAND memory device 10 each comprise only one byte of data, alternative embodiments may employ registers 24 including a greater whole number of data bytes. Once master 12 has received the register data, master 12 thereafter terminates the communication sequence by setting CS 16 high.

<figref idref="DRAWINGS">FIG. 6</figref> provides a register read timing diagram 102 which illustrates the timing of the prescribed register read method above. Communication between master 12 and controller 14 initiates when CS signal line 104 transitions from high to low, as generally indicated by reference numeral 106. Clock signal SCK line 108 provides the timing of clock signal 18, which includes rising edges 110 shown in <figref idref="DRAWINGS">FIG. 6</figref> as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, and continuing. When clock signal 18 issues a first rising edge 110, data input SI line 112 indicates a register read command signal 114 (having bits shown in <figref idref="DRAWINGS">FIG. 6</figref> as 0, 1, 2, 3, 4, 5, 6, and 7) is correspondingly sent by master 12.

Immediately following the register read command signal 114, represented in hexadecimal format as 0Fh, master 12 sends a one-byte register address signal 116 (having bits shown in <figref idref="DRAWINGS">FIG. 6</figref> as 0, 1, 2, 3, 4, 5, 6, and 7). Subsequently, controller 14 sends a one-byte data signal 120 (having bits shown in <figref idref="DRAWINGS">FIG. 6</figref> as 0, 1, 2, 3, 4, 5, 6, and 7) from the requested memory register on data output SO line 118, before which controller 14 holds the SO line 118 at Hi-Z. Communication terminates when master 12 sets the CS 16 signal high, as generally indicated by reference numeral 122.

Referring to <figref idref="DRAWINGS">FIG. 7</figref>, a method 124 illustrates one embodiment of a technique for accessing a parameter page in memory. A parameter page may store device parameters, such as cell type (e.g., SLC or MLC), block size, spare area size, organization, device ID, manufacturer ID, ECC capabilities, etc. Though the parameter page may comprise many bytes of data, five bytes may suffice to encode all parameters.

Rather than introduce additional commands exclusively for performing parameter page operations, the method of accessing a parameter page 124 instead prescribes the use of shared ordinary commands in a special operational mode. When a controller 14 enters a special operational mode, a master 12 may issue a shared ordinary command, such as page read, read status, or random data read, to perform a new operation to achieve a result not possible in an ordinary operational mode. Although the foregoing discussion relates primarily to an application of the method in SPI NAND memory device 10, the technique may apply generally to any NAND flash memory device where a reduced set of commands may be desired.

Referring again to <figref idref="DRAWINGS">FIG. 7</figref>, step 126 provides that a master 12 first sets a parameter page enable bit in a parameter page access register to enter a parameter page access mode. Master 12 may set the enable bit by issuing a register write command addressed to the parameter page access register, sending a data byte in which a prior-designated enable bit is set high. Optionally, master 12 may first perform a register read command to assess current parameter page access register data, copy the current data, then issue a register write command to send the data with only a parameter page enable bit changed to high. Once the parameter page enable bit has been set high, controller 14 enters a parameter page access mode.

Having entered a parameter page access mode in step 126, master 12 may read parameter page contents by issuing standard commands. In step 128, master 12 issues a page read command. When a page read command is performed in an ordinary operational mode, the NAND flash memory device 10 prepares a page of memory to be read from a given address of NAND memory array 40. In a parameter page access mode, however, the page read command prepares to read the contents of the parameter page. Master 12 next polls the controller 14 for read status in step 130 by issuing a read status command. The read status command operates to align the data transmission by indicating when master 12 may begin to read data from the device. Master 12 may issue numerous read status commands before controller 14 returns data indicating master 12 may begin to read the data.

During step 132, master 12 obtains parameter page data by issuing a random data read command, causing controller 14 to output the contents of the parameter page via SO 22. To exit the parameter page access mode and return to an ordinary operational mode, in step 134, master 12 resets the parameter page access enable bit. Issuing a register write command addressed to the parameter page access register, master 12 sends a data byte in which the parameter page enable bit has been set low, and controller 14 returns to an ordinary operational mode.

<figref idref="DRAWINGS">FIG. 8</figref> illustrates a NAND flash memory device 136 having a block of one time programmable (OTP) memory, depicted as OTP block 138. OTP block 138 may appear as a block of the NAND memory array 40, but alternatively may be any nonvolatile memory. Each page of OTP block 138 may be written on a fixed number of times, typically one to four times, before a page lock bit is set, permanently locking the page from modification. Alternatively, a user may choose to lock each page or the entire block of OTP memory of OTP block 138. OTP memory may find a particular use in security applications. For example, a user may program OTP memory to store and protect values for code authentication.

In the same manner as NAND flash memory device 10, NAND flash memory device 136 includes a master 12 interconnected to controller 14 via chip select CS signal 16, clock signal SCK 18, data input signal SI 20, and data output signal SO 22. Controller 14 accesses volatile memory registers 24, which includes an OTP enable register 25B, using bus 26 and control wire 28. The OTP enable register 25B may include an OTP enable (EN) bit 27A, an OTP lock (LOCK) bit 27B, and/or an OTP protect (PROT) bit 27C. The registers 24 may also include an OTP password (OTP PW) register 29. To perform operations on the OTP block 138 in NAND memory, controller 14 may send an OTP page address via bus 30 to a row decoder and column decoder on NAND memory array 40, controlled via control wire 32. Controller 14 may send data to cache register 34 across bus 36, controlled via control wire 38. Cache register 34 may thereafter load the data into a page of OTP block 138 memory in conjunction with data register 42.

<figref idref="DRAWINGS">FIG. 9</figref> illustrates a method of accessing a block of one time programmable (OTP) memory 140. Rather than introduce additional commands exclusively for performing OTP operations, the method of accessing a block of OTP memory 140 instead prescribes the use of shared ordinary commands in a special operational mode. When a controller 14 enters a special operational mode, a master 12 may issue shared ordinary commands, such as page read, read status, and random data read, to perform new operations to achieve a result not possible in an ordinary operational mode. Although the foregoing discussion relates primarily to an application of the method in SPI NAND memory device 136, the technique may apply generally to any NAND flash memory device where a reduced set of commands may be desired.

The method of accessing a block of one time programmable (OTP) memory 140 begins at step 142, when an OTP enable bit 27A in an OTP enable register 25B is set high. Master 12 may set the enable bit 27A by issuing a register write command addressed to the OTP enable register 25B, sending a data byte in which a prior-designated OTP enable bit 27A is set high. Optionally, master 12 may first perform a register read command to assess current OTP enable register 25B data, copy the current data, then issue a register write command to send the data in which only the OTP enable bit 27A has changed. Once the OTP enable bit 27A has been set high, controller 14 enters an OTP block access mode.

Optionally, OTP password protection may preclude writing to or even reading the OTP block. Controller 14 may require master 12 to enter a password of a predetermined number of bits into an OTP password register 29 in registers 24 using a register write command. Checking the entered password against a preexisting password stored in nonvolatile memory, controller 14 may allow master 12 to access OTP memory if the entered and preexisting password match.

Having entered an OTP block access mode in step 142, master 12 may subsequently perform operations on the OTP block by issuing standard commands. In step 144, master 12 may read from the OTP block using commands such as page read, read status, and read random data read. Additionally, master 12 may also write to the OTP block using commands such as program load, program random data input, program execute, page read, and random data input.

After performing a predetermined number of operations on a particular page of OTP block 138, typically one to four operations, the controller 14 may cause the page to become locked such that data may no longer be written to the page. However, as long as controller 14 remains in OTP block access mode, master 12 may perform operations to read OTP page data.

To exit OTP block access mode and return to an ordinary operational mode, step 146 prescribes resetting the OTP enable bit 27B. Issuing a register write command addressed to the OTP enable register 25B, master 12 may send a data byte in which the OTP enable bit 27A has been set low, and controller 14 may return to an ordinary operational mode.

Though completing a predetermined number of operations on a page of OTP memory may lock out additional writing to the page, a user may also lock a given page, as described below. In either case, controller 14 may lock the page by causing an OTP lock bit to be set at a designated separate lock block of memory, with the lock bit associated with the address location of the page in the OTP block. Additionally or alternatively, controller 14 may lock the page by causing an OTP lock bit to be set in a byte in a spare region located at the page.

Turning to <figref idref="DRAWINGS">FIG. 10</figref>, a method 148 illustrates one embodiment of a technique for preventing writing to (i.e., locking) a page of one time programmable (OTP) memory. The method of locking a page of OTP memory 148 begins at step 150, when master 12 sets an OTP enable bit 27A in an OTP enable register 25B, causing the controller 14 to enter an OTP block access mode. Master 12 may set the enable bit 27A by issuing a register write command addressed to the OTP enable register 25B, sending a data byte in which a prior-designated OTP enable bit 27A is set high. Optionally, master 12 may first perform a register read command to assess current OTP enable register 25B data, copy the current data, then issue a register write command to send the data in which only the OTP enable bit 27A has changed. Once the OTP enable bit 27A has been set high, controller 14 enters an OTP block access mode.

Next step 152 provides that master 12 may next set an OTP protect bit 27C in an OTP protect register 31. As above, master 12 may issue a register write command addressed to the OTP protect register 31, sending a data byte in which a prior-designated OTP protect bit 27C is set high. Alternatively, because the OTP protect bit 27C comprises only a single bit, and a register may comprise an entire byte, the OTP protect bit 27C may reside instead in the OTP enable register 25B alongside the OTP enable bit 27A. Accordingly, steps 150 and 152 may be combined, wherein master 12 may issue only a single register write command addressed to the OTP enable register 25B, sending a data byte that sets high both the OTP enable bit 27A and OTP protect bit 27C.

Upon reaching step 154, with both the OTP enable bit 27A and OTP protect bit 27C set high, controller 14 may have entered an OTP write protect mode. To lock a particular page of OTP memory in OTP block 138, master 12 may issue a program execute command addressed to a desired unlocked page. Controller 14 may respond by causing an OTP lock bit to be set at a designated separate lock block of memory, with the lock bit associated with the address location of the page in the OTP block 138. Additionally or alternatively, controller 14 may instead cause an OTP lock bit to be set in a byte in a spare region located at the page.

To return to an ordinary operational mode in step 156, master 12 may issue a write register command to set the OTP enable bit 27A low in the same manner as step 150. In step 158, master 12 may subsequently issue an additional write register command to set the OTP protect bit 27C low in the same manner as step 152. Alternatively, if the OTP protect bit 27C and the OTP enable bit 27A both reside in a single OTP enable register 25B, steps 150 and 152 may be combined, wherein master 12 may issue only a single register write command addressed to the OTP enable register 25B, sending a data byte setting low both the OTP enable bit 27A and OTP protect bit 27C.

While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Contents4

Every citation, both waysCites: the store holds 48 of 49

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US8352833B2	Cites	United States of America	Applicant
US8429329B2	Cites	United States of America	Applicant
US8667368B2	Cites	United States of America	Applicant
US8694860B2	Cites	United States of America	Applicant
US8767464B2	Cites	United States of America	Applicant
US8929146B1	Cites	United States of America	Applicant
US9042172B2	Cites	United States of America	Applicant
US9235546B2	Cites	United States of America	Applicant
TWI237477B	Cites	Taiwan Province of China	Applicant
TWI238941B	Cites	Taiwan Province of China	Applicant
EP1764803	Cites	European Patent Office (EPO)	Applicant
TWI237477	Cites	Taiwan Province of China	Applicant
TWI238941	Cites	Taiwan Province of China	Applicant
US20060067123A1	Cites	United States of America	Search report
US20060236204A1	Cites	United States of America	Search report
US20070115743A1	Cites	United States of America	Applicant
US20090103364A1	Cites	United States of America	Applicant

28 members in 6 offices

This recordMember, by publication datePriority claim

Priority claims26

Priority claims
Document	Office	Kind	Date
87382607	United States of America	A	2007-10-17
87382607	United States of America	A	2007-10-17
201213357533	United States of America	A	2012-01-24
201213357533	United States of America	A	2012-01-24
201414231393	United States of America	A	2014-03-31
201414231393	United States of America	A	2014-03-31
201514839173	United States of America	A	2015-08-28
201514839173	United States of America	A	2015-08-28
201816013773	United States of America	A	2018-06-20
201816013773	United States of America	A	2018-06-20
201816151845	United States of America	A	2018-10-04
201816151845	United States of America	A	2018-10-04
201916454411	United States of America	A	2019-06-27
11873826	–	–	–
13357533	–	–	–
14231393	–	–	–
14839173	–	–	–
16013773	–	–	–
16151845	–	–	–
US20070873826	–	–	–
US201213357533	–	–	–
US201414231393	–	–	–
US201514839173	–	–	–
US201816013773	–	–	–
US201816151845	–	–	–
US201916454411	–	–	–

Members28

Family members, oldest first
Document	Office	Kind
US2009103362A1	United States of America	A1	2009-04-23
WO2009051952A2	World Intellectual Property Organization (WIPO)	A2	2009-04-23
WO2009051952A3	World Intellectual Property Organization (WIPO)	A3	2009-07-09
TW200935234A	Taiwan Province of China	A	2009-08-16
EP2210178A2	European Patent Office (EPO)	A2	2010-07-28
KR20100087324A	Republic of Korea	A	2010-08-04
CN101828175A	China	A	2010-09-08
US8102710B2	United States of America	B2	2012-01-24
US2012124279A1	United States of America	A1	2012-05-17
TWI380181B	Taiwan Province of China	B	2012-12-21
EP2210178B1	European Patent Office (EPO)	B1	2013-10-23
EP2698720A1	European Patent Office (EPO)	A1	2014-02-19
CN101828175B	China	B	2014-02-26
US8687422B2	United States of America	B2	2014-04-01
US2014215139A1	United States of America	A1	2014-07-31
KR101454948B1	Republic of Korea	B1	2014-10-27
US9122420B2	United States of America	B2	2015-09-01
US2015371688A1	United States of America	A1	2015-12-24
US10062420B2	United States of America	B2	2018-08-28
US2018301175A1	United States of America	A1	2018-10-18
US10192591B2	United States of America	B2	2019-01-29
US2019035438A1	United States of America	A1	2019-01-31
US10366731B2	United States of America	B2	2019-07-30
US2019318770A1	United States of America	A1	2019-10-17
US10978112B2This record	United States of America	B2	2021-04-13
US2021272607A1	United States of America	A1	2021-09-02
US11657857B2	United States of America	B2	2023-05-23
US2023335166A1	United States of America	A1	2023-10-19

49 transactions on the USPTO file

Allowed after 2 non-final rejections.

Non-final rejections: 2
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2021-04-13	Recordation of Patent Grant MailedPGM/	PGM/
2021-04-13	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2021-03-25	Email NotificationEML_NTR	EML_NTR
2021-03-24	Issue Notification MailedAllowedWPIR	WPIR
2021-03-11	Dispatch to FDCD1935	D1935
2021-03-11	Application Is Considered Ready for IssuePILS	PILS
2021-03-10	Issue Fee Payment VerifiedN084	N084
2021-03-10	Issue Fee Payment ReceivedIFEE	IFEE
2020-12-15	Electronic ReviewELC_RVW	ELC_RVW
2020-12-15	Email NotificationEML_NTF	EML_NTF
2020-12-15	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2020-12-11	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2020-12-09	Examiner's Amendment CommunicationEX.A	EX.A
2020-12-09	Reasons for AllowanceEX.R	EX.R
2020-11-29	Date Forwarded to ExaminerFWDX	FWDX
2020-11-24	Response after Non-Final ActionA...	A...
2020-11-24	Paralegal or electronic terminal disclaimer approvedP574	P574
2020-11-24	Terminal Disclaimer FiledDIST	DIST
2020-09-03	Electronic ReviewELC_RVW	ELC_RVW
2020-09-03	Electronic ReviewELC_RVW	ELC_RVW
2020-09-03	Email NotificationEML_NTF	EML_NTF
2020-09-03	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2020-08-30	Non-Final RejectionNon-final rejectionCTNF	CTNF
2020-06-10	Date Forwarded to ExaminerFWDX	FWDX
2020-06-08	Response after Non-Final ActionA...	A...
2020-03-19	Electronic ReviewELC_RVW	ELC_RVW
2020-03-19	Email NotificationEML_NTF	EML_NTF
2020-03-19	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2020-03-16	Non-Final RejectionNon-final rejectionCTNF	CTNF
2020-03-16	Information Disclosure Statement consideredIDSC	IDSC
2019-11-29	Case Docketed to Examiner in GAUDOCK	DOCK
2019-10-18	Email NotificationEML_NTR	EML_NTR
2019-10-17	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2019-10-17	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2019-08-13	Preliminary AmendmentA.PE	A.PE
2019-07-11	Email NotificationEML_NTR	EML_NTR
2019-07-11	Application Is Now CompleteCOMP	COMP
2019-07-11	Filing ReceiptFLRCPT.O	FLRCPT.O
2019-07-10	Application Dispatched from OIPEOIPE	OIPE
2019-07-10	FITF set to NO - revise initial settingFTFI	FTFI
2019-07-02	Cleared by OIPE CSRL194	L194
2019-06-27	Information Disclosure Statement (IDS) FiledM844	M844
2019-06-27	Patent Term Adjustment - Ready for ExaminationPTA.RFE	PTA.RFE
2019-06-27	PTO/SB/69-Authorize EPO Access to Search ResultsSREXR141	SREXR141
2019-06-27	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2019-06-27	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2019-06-27	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2019-06-27	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2019-06-27	Initial Exam Team nnIEXX	IEXX

18 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2021-03-24	Information on status: patent grantGrantedSTCF	STCF
2021-03-24	Information on status: patent grantGrantedSTCF	STCF
2021-03-11	Information on status: patent application and granting procedure in generalSTPP	STPP
2021-03-11	Information on status: patent application and granting procedure in generalSTPP	STPP
2021-03-10	Information on status: patent application and granting procedure in generalSTPP	STPP
2021-03-10	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-12-11	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-12-11	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-09-01	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-09-01	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-06-10	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-06-10	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-03-17	Information on status: patent application and granting procedure in generalSTPP	STPP
2020-03-17	Information on status: patent application and granting procedure in generalSTPP	STPP
2019-11-29	Information on status: patent application and granting procedure in generalSTPP	STPP
2019-07-10	Information on status: patent application and granting procedure in generalSTPP	STPP
2019-06-27	Fee payment procedureFEPP	FEPP
2019-06-27	Fee payment procedureFEPP	FEPP

Memory devices having special mode access

Summary by NHIP

Claim Score by NHIP

Abstract