Storage device

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-174321, filed Sep. 18, 2018, the entire contents of which are incorporated herein by reference.

FIELD

0002Embodiments described herein relate generally to a storage device.

BACKGROUND

0003A resistance-variable memory transits between a high resistance state and a low resistance state when applied with a current to a resistance-variable layer of a memory cell. For example, when the high-resistance state is defined as data “0” and the low-resistance state is defined as data “1”, the memory cell stores 1 bit data of “0” and “1”.

0004Examples of the resistance-variable memory include a phase-variable memory using a resistance change caused by a phase change of a material constituting the resistance-variable layer. For example, a chalcogenide is used as the resistance-variable layer of the phase-variable memory. The chalcogenide is a compound containing sulfur (S), selenium (Se), or Te (tellurium), which are Group 16 elements (Group VI elements).

0005However, adhesion between the chalcogenide and silicon oxide or silicon nitride used as an insulating layer is weak. For this reason, for example, during manufacture of the resistance-variable memory, there is a problem that film peeling occurs and the resistance-variable memory cannot be manufactured.

0006Examples of related art include JP-A-2006-352082.

DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a storage device according to a first embodiment.

<figref idref="DRAWINGS">FIG. 2</figref> is a schematic cross-sectional view of a memory cell of the storage device according to the first embodiment.

<figref idref="DRAWINGS">FIG. 3</figref> is a schematic cross-sectional view of a memory cell of a storage device according to a second embodiment.

<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram of a storage device according to a third embodiment.

<figref idref="DRAWINGS">FIG. 5</figref> is an equivalent circuit diagram of a memory cell array of the storage device according to the third embodiment.

<figref idref="DRAWINGS">FIG. 6</figref> is a schematic cross-sectional view of the memory cell array of the storage device according to the third embodiment.

DETAILED DESCRIPTION

0013Embodiments provide a storage device having strong adhesion between a resistance-variable layer and an insulating layer.

0014In general, according to at least one embodiment, a storage device includes: a first conductive layer; a second conductive layer; a resistance-variable layer provided between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium; an insulating layer provided in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer; and a first region provided between the resistance-variable layer and the insulating layer, and having a third concentration of the first element higher than both a first concentration of the first element of the resistance-variable layer and a second concentration of the first element of the insulating layer.

0015Embodiments of the present disclosure will be described below with reference to the drawings. In the following description, the same or similar members are denoted by the same reference signs, and the description thereof will be appropriately omitted.

0016In the present Specification, the terms “upper” and “lower” are used for convenience. The terms “upper” and “lower” are merely terms indicating a relative positional relationship in the drawings, and do not define a positional relationship with respect to gravity.

0017Hereinafter, storage devices according to the embodiments will be described with reference to the drawings.

First Embodiment

0018A storage device according to a first embodiment includes: a first conductive layer; a second conductive layer; a resistance-variable layer provided between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium; insulating layers provided in second directions perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer; and first regions provided between the resistance-variable layer and the insulating layers, and having a third concentration of the first element higher than both a first concentration of the first element of the resistance-variable layer and a second concentration of the first element of the insulating layers.

0019<figref idref="DRAWINGS">FIG. 1</figref> shows a block diagram of the storage device according to the first embodiment. <figref idref="DRAWINGS">FIG. 2</figref> is a schematic cross-sectional view of a memory cell of the storage device according to the first embodiment. <figref idref="DRAWINGS">FIG. 2</figref> shows a cross section of one memory cell MC indicated by, for example, a dotted circle in a memory cell array <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>.

0020The memory cell array <b>100</b> of the storage device according to the first embodiment includes on a semiconductor substrate <b>101</b>, for example, a plurality of word lines <b>104</b> and a plurality of bit lines <b>106</b> intersecting the word lines <b>104</b>, with insulating layers therebetween. The bit lines <b>106</b> are provided above the word lines <b>104</b>. A first control circuit <b>108</b>, a second control circuit <b>110</b>, and a sense circuit <b>112</b> are provided around the memory cell array <b>100</b> as peripheral circuits.

0021A plurality of memory cells MC are provided in a region where the word lines <b>104</b> intersect the bit lines <b>106</b>. The storage device according to the first embodiment is a resistance-variable memory having a cross-point structure. The memory cell MC is a two-terminal resistance-variable device. The storage device according to the first embodiment is a phase-variable memory including a chalcogenide in a resistance-variable layer.

0022Each of the plurality of word lines <b>104</b> is connected to the first control circuit <b>108</b>. Each of the plurality of bit lines <b>106</b> is connected to the second control circuit <b>110</b>. The sense circuit <b>112</b> is connected to the first control circuit <b>108</b> and the second control circuit <b>110</b>.

0023The first control circuit <b>108</b> and the second control circuit <b>110</b> have a function of, for example, selecting a desired memory cell MC, writing data into the memory cell, reading data from the memory cell, erasing data from the memory cell, and the like. When data is read, the data of the memory cell is read as an amount of current flowing between the word lines <b>104</b> and the bit lines <b>106</b>. The sense circuit <b>112</b> has a function of determining the current amount and determining a polarity of the data. For example, the sense circuit <b>112</b> determines whether the data is “0” or “1”.

0024The first control circuit <b>108</b>, the second control circuit <b>110</b>, and the sense circuit <b>112</b> are formed of, for example, an electronic circuit using semiconductor devices formed on the semiconductor substrate <b>101</b>.

0025As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the memory cell MC includes a lower electrode <b>10</b> (an example of a first conductive layer), an upper electrode <b>20</b> (an example of a second conductive layer), a resistance-variable layer <b>30</b>, interlayer insulating layers <b>40</b> (an example of insulating layers), and first interface regions <b>50</b> (an example of a first region).

0026The lower electrode <b>10</b> is connected to the word line <b>104</b>. The lower electrode <b>10</b> is made of, for example, a metal. The lower electrode <b>10</b> is, for example, titanium nitride (TiN) or tungsten (W).

0027The upper electrode <b>20</b> is connected to the bit line <b>106</b>. The upper electrode <b>20</b> is, for example, a metal. The upper electrode <b>20</b> is, for example, titanium nitride (TiN) or tungsten (W).

0028The resistance-variable layer <b>30</b> is provided between the lower electrode <b>10</b> and the upper electrode <b>20</b>. The resistance-variable layer <b>30</b> includes a first chalcogenide. The first chalcogenide includes a first element which may be either silicon (Si) or germanium (Ge).

0029The chalcogenide is a compound containing sulfur (S), selenium (Se), or Te (tellurium), which is a Group 16 element (Group VI element).

0030The first chalcogenide is, for example, a chalcogenide containing germanium (Ge), antimony (Sb), and tellurium (Te). The first element is, for example, germanium.

0031By applying a current to the resistance-variable layer <b>30</b>, the resistance-variable layer <b>30</b> changes from a high resistance state to a low resistance state or from the low resistance state to the high resistance state. The change from the high resistance state to the low resistance state is referred to as, for example, a set operation. The change from the low-resistance state to the high-resistance state is referred to as, for example, a reset operation.

0032Application of a current to the resistance-variable layer <b>30</b> changes the first chalcogenide from crystalline to amorphous or from amorphous to crystalline, thereby changing conductivity of the resistance-variable layer <b>30</b>. An amorphous state is the high resistance state and a crystalline state is the low resistance state. The relationship between the crystal state and the resistance state may be reversed. Further, the resistance may be changed by changing bonding of atoms without changing the crystallinity.

0033The chemical formulation of the first chalcogenide is not limited as long as it is a chalcogenide of which the resistance changes upon phase change.

0034[The film thickness of the resistance-variable layer <b>30</b> is, for example, 5 nm or more and 25 nm or less. The resistance-variable layer <b>30</b> is, for example, a film formed by an atomic layer deposition (ALD) method.

0035The interlayer insulating layers <b>40</b> are provided at least in second directions perpendicular to a first direction from the lower electrode <b>10</b> to the upper electrode <b>20</b> with respect to the resistance-variable layer <b>30</b>. The resistance-variable layer <b>30</b> is sandwiched between the interlayer insulating layers <b>40</b>. The interlayer insulating layers <b>40</b> are provided on both sides of the resistance-variable layer <b>30</b>.

0036The interlayer insulating layers <b>40</b> are, for example, an oxide, a nitride, or an oxynitride. The interlayer insulating layers <b>40</b> are, for example, silicon oxide, silicon nitride, or silicon oxynitride.

0037The first interface regions <b>50</b> are provided between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b>. The first interface regions <b>50</b> are provided on side surfaces of the resistance-variable layer <b>30</b>. The first interface regions <b>50</b> have a third concentration of the first element higher than both a first concentration of the first element of the resistance-variable layer <b>30</b> and a second concentration of the first element of the interlayer insulating layers <b>40</b>.

0038For example, when the first element is germanium, the concentration of germanium in the first interface regions (i.e., the third concentration) is higher than the concentration of germanium of the resistance-variable layer <b>30</b> (i.e., that first concentration) and the concentration of germanium of the interlayer insulating layers <b>40</b> (i.e., the second concentration).

0039The first interface regions <b>50</b> are regions formed by segregation of the first element at the interfaces between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b>. The width in the second direction of the first interface regions <b>50</b> is, for example, less than 0.5 nm or less than 0.4 nm.

0040For example, when the first chalcogenide contained in the resistance-variable layer <b>30</b> is a chalcogenide containing germanium (Ge), antimony (Sb), and tellurium (Te), and the interlayer insulating layers <b>40</b> are silicon oxide, the first interface regions <b>50</b> are, for example, silicon oxide containing germanium.

0041The elements contained in the resistance-variable layer <b>30</b>, the interlayer insulating layers <b>40</b>, and the first interface regions <b>50</b> may be identified by, for example, energy dispersive X-ray (EDX) spectroscopy. The magnitude relationship of the concentrations of the elements contained in the resistance-variable layer <b>30</b>, the interlayer insulating layers <b>40</b>, and the first interface regions <b>50</b> may be determined by, for example, EDX. The concentrations of the elements contained in the resistance-variable layer <b>30</b>, the interlayer insulating layers <b>40</b>, and the first interface regions <b>50</b> may be measured by, for example, electron energy-loss spectroscopy (EELS).

0042In addition, for example, transmission electron microscope (TEM) may be used to measure thicknesses of members constituting the storage device, distances between the members, and the like.

0043Next, an example of a method of manufacturing the memory cell MC according to the first embodiment will be described.

0044For example, when the resistance-variable layer <b>30</b> is formed on the lower electrode <b>10</b> by the ALD method, the first chalcogenide is formed to contain the surplus first element, compared with the first element that can be stably contained in the first chalcogenide.

0045For example, when the first chalcogenide included in the resistance-variable layer <b>30</b> is a chalcogenide containing germanium (Ge), antimony (Sb), and tellurium (Te), the first chalcogenide is formed so that surplus germanium is contained compared with germanium that can be stably contained in the first chalcogenide.

0046Then, the upper electrode <b>20</b> and the interlayer insulating layers <b>40</b> are formed. The interlayer insulating layers <b>40</b> are formed in contact with the side surfaces of the resistance-variable layer <b>30</b>.

0047Next, annealing is performed at, for example, a temperature of 500° C. or higher and 900° C. or lower. The annealing is performed for, for example, 1 second to 3 seconds. Through such annealing, the surplus first element segregates at the interfaces between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b>, and the first interface regions <b>50</b> are formed.

0048Operations and advantageous effects of the storage device according to the first embodiment will be described below.

0049Adhesion between the chalcogenide and silicon oxide or silicon nitride used as an insulating layer is low. For this reason, during manufacture of the resistance-variable memory, there is a problem that film peeling occurs and the resistance-variable memory cannot be manufactured. A chalcogenide is unlikely to form a compound with other elements, and thus is considered to have low adhesion with an insulating layer.

0050The phase change memory according to the first embodiment has the first interface regions <b>50</b> having a high concentration of the first element between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b>. The first interface regions <b>50</b> having the high concentration of the first element improves the adhesion between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b>.

0051For example, when the first chalcogenide contained in the resistance-variable layer <b>30</b> is a chalcogenide containing germanium (Ge), antimony (Sb), and tellurium (Te), and the interlayer insulating layers <b>40</b> are silicon oxide, the first interface regions <b>50</b> are, for example, silicon oxide containing germanium at a high concentration. The first element is germanium.

0052By compounding silicon oxide containing germanium at the high concentration and the first chalcogenide containing germanium, adhesion between the resistance-variable layer <b>30</b> and the interlayer insulating layers <b>40</b> is improved.

0053As described above, according to the storage device according to the first embodiment, the adhesion between the resistance-variable layer and the insulating layers increases. Therefore, film peeling between the resistance-variable layer and the insulating layers is unlikely to occur during manufacture. Thereby, a storage device that can be stably manufactured is achieved.

Second Embodiment

0054A storage device according to a second embodiment differs from the storage device according to the first embodiment in that the storage device according to the second embodiment further includes: an intermediate layer provided between the first conductive layer and the resistance-variable layer, and including a second chalcogenide containing a second element which is either silicon or germanium; and second regions provided between the intermediate layer and the insulating layers, and having a sixth concentration of the second element higher than both a fourth concentration of the second element of the intermediate layer and a fifth concentration of the second element of the insulating layers. Hereinafter, description of content which is the same as in the first embodiment will be omitted.

0055<figref idref="DRAWINGS">FIG. 3</figref> is a schematic cross-sectional view of a memory cell of the storage device according to the second embodiment.

0056As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the memory cell MC includes a lower electrode <b>10</b> (an example of a first conductive layer), an upper electrode <b>20</b> (an example of a second conductive layer), a resistance-variable layer <b>30</b>, interlayer insulating layers <b>40</b> (an example of an insulating layer), first interface regions <b>50</b> (an example of a first region), a selector layer <b>60</b> (an example of an intermediate layer), and second interface regions <b>70</b> (an example of a second region).

0057The selector layer <b>60</b> is provided between the lower electrode <b>10</b> and the resistance-variable layer <b>30</b>.

0058The selector layer <b>60</b> includes a second chalcogenide. The second chalcogenide includes a second element which is either silicon (Si) or germanium (Ge).

0059The second chalcogenide included in the selector layer <b>60</b> is different from the first chalcogenide included in the resistance-variable layer <b>30</b>. The second element contained in the second chalcogenide may be either the same as or different from the first element contained in the first chalcogenide.

0060The second chalcogenide is, for example, a chalcogenide containing silicon (Si) and tellurium (Te). The second chalcogenide is, for example, a chalcogenide containing germanium (Ge) and tellurium (Te). The second chalcogenide is, for example, a chalcogenide containing aluminum (Al) and tellurium (Te). The second chalcogenide is, for example, a chalcogenide containing antimony (Sb) and tellurium (Te). The second element is, for example, silicon.

0061The selector layer <b>60</b> has non-linear voltage-current characteristic. A large difference occurs in a current flowing through the selector layer <b>60</b> between when a low voltage is applied to the selector layer <b>60</b> and when a high voltage is applied to the selector layer <b>60</b>. Providing the selector layers <b>60</b>, for example, reduces a current flowing through memory cells MC other than a selected memory cell MC, and prevents incorrect writing of data and incorrect reading of data.

0062The chemical formulation of the second chalcogenide is not limited as long as it is a chalcogenide having non-linear voltage-current characteristic.

0063The second interface regions <b>70</b> are provided between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b>. The second interface regions <b>70</b> are provided on side surfaces of the selector layer <b>60</b>. The second interface regions <b>70</b> have a sixth concentration of the second element higher than both a fourth concentration of the second element of the selector layer <b>60</b> and a fifth concentration of the second element of the interlayer insulating layers <b>40</b>.

0064For example, when the second element is silicon, the concentration of silicon of the second interface regions (i.e., the sixth concentration) is higher than both the concentration of silicon of the selector layer <b>60</b> (i.e., the fourth concentration) and the concentration of silicon of the interlayer insulating layers <b>40</b> (i.e., the fifth concentration).

0065The second interface regions <b>70</b> are regions formed by segregation of the second element at the interfaces between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b>. The width in the second direction of the second interface regions <b>70</b> is, for example, less than 0.5 nm or less than 0.4 nm.

0066For example, when the second chalcogenide included in the selector layer <b>60</b> is a chalcogenide containing silicon (Si) and tellurium (Te), and the interlayer insulating layers <b>40</b> are silicon oxide, the second interface regions <b>70</b> are, for example, silicon oxide having a high silicon concentration.

0067Next, an example of a method of manufacturing the memory cell MC according to the second embodiment will be described.

0068For example, when the selector layer <b>60</b> is formed on the lower electrode <b>10</b> by the ALD method, the second chalcogenide is formed to contain the surplus second element compared with the second element that can be stably contained in the second chalcogenide.

0069For example, when the second chalcogenide included in the selector layer <b>60</b> is a chalcogenide containing silicon (Si) and tellurium (Te), the chemical formulation of Si₂Te₃is stable. Therefore, for example, the second chalcogenide is formed to contain surplus silicon compared with the chemical formulation.

0070Then, the resistance-variable layer <b>30</b>, the upper electrode <b>20</b>, and the interlayer insulating layers <b>40</b> are formed. The interlayer insulating layers <b>40</b> are formed in contact with the side surfaces of the resistance-variable layer <b>30</b> and the selector layer <b>60</b>.

0071Next, annealing is performed at, for example, a temperature of 500° C. or higher and 900° C. or lower. The annealing is performed for, for example, 1 second to 3 seconds. Through such annealing, the surplus second element segregates at the interfaces between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b>, and the second interface regions <b>70</b> are formed.

0072The phase change memory according to the second embodiment has the second interface regions <b>70</b> having a high concentration of the second element between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b>. The second interface regions <b>70</b> having the high concentration of the second element improves adhesion between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b>.

0073For example, when the second chalcogenide included in the selector layer <b>60</b> is a chalcogenide containing silicon (Si) and tellurium (Te), and the interlayer insulating layers <b>40</b> are silicon oxide, the second interface regions <b>70</b> are, for example, silicon oxide containing silicon at a high concentration. The second element is silicon.

0074By compounding silicon oxide containing silicon at the high concentration and the second chalcogenide containing silicon, adhesion between the selector layer <b>60</b> and the interlayer insulating layers <b>40</b> is improved.

0075A metal layer may be provided between the resistance-variable layer <b>30</b> and the selector layer <b>60</b>.

0076As described above, according to the storage device according to the second embodiment, in addition to the adhesion between the resistance-variable layer and the insulating layers, the adhesion between the selector layer and the insulating layers increases as well. Therefore, film peeling between the resistance-variable layer and the insulating layers and film peeling between the selector layer and the insulating layers are unlikely to occur during manufacture. Thereby, a storage device that can be stably manufactured is achieved.

Third Embodiment

0077A storage device of a third embodiment is the same as that of the first embodiment except that a memory cell array has a three-dimensional structure. Therefore, description of content that is the same as in the first embodiment will be omitted.

0078<figref idref="DRAWINGS">FIG. 4</figref> shows a block diagram of the storage device according to the third embodiment. <figref idref="DRAWINGS">FIG. 5</figref> is an equivalent circuit diagram of the memory cell array of the storage device according to the third embodiment. <figref idref="DRAWINGS">FIG. 6</figref> is a schematic cross-sectional view of the memory cell array of the storage device according to the third embodiment.

0079The memory cell array according to the third embodiment has a three-dimensional structure in which memory cells MC are arranged three-dimensionally.

0080As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the storage device according to the third embodiment includes a memory cell array <b>210</b>, a word line driver circuit <b>212</b>, a row decoder circuit <b>214</b>, a sense amplifier circuit <b>215</b>, a column decoder circuit <b>217</b>, and a control circuit <b>221</b>.

0081As shown in <figref idref="DRAWINGS">FIG. 5</figref>, a plurality of memory cells MC are arranged three-dimensionally in the memory cell array <b>210</b>. In <figref idref="DRAWINGS">FIG. 5</figref>, a region surrounded by a broken line corresponds to one memory cell MC.

0082The memory cell array <b>210</b> includes, for example, a plurality of word lines WL (WL<b>11</b>, WL<b>12</b>, WL<b>13</b>, WL<b>21</b>, WL<b>22</b>, WL<b>23</b>) and a plurality of bit lines BL (BL<b>11</b>, BL<b>12</b>, BL<b>21</b>, BL<b>22</b>). The word lines WL extend in an x direction. The word lines WL are arranged in a y direction (an example of a first direction). The bit lines BL extend in a z direction (an example of a second direction). The word lines WL and the bit lines BL intersect one another perpendicularly. The memory cells MC are arranged at intersections of the word lines WL and the bit lines BL.

0083The plurality of word lines WL are electrically connected to the row decoder circuit <b>214</b>. The plurality of bit lines BL are connected to the sense amplifier circuit <b>215</b>. Select transistors ST (ST<b>11</b>, ST<b>21</b>, ST<b>12</b>, and ST<b>22</b>) and global bit lines GBL (GBL<b>1</b> and GBL<b>2</b>) are provided between the plurality of bit lines BL and the sense amplifier circuit <b>215</b>.

0084The row decoder circuit <b>214</b> has a function of selecting a word line WL in accordance with an input row address signal. The word line driver circuit <b>212</b> has a function of applying a predetermined voltage to the word line WL selected by the row decoder circuit <b>214</b>.

0085The column decoder circuit <b>217</b> has a function of selecting a bit line BL in accordance with an input column address signal. The sense amplifier circuit <b>215</b> has a function of applying a predetermined voltage to the bit line BL selected by the column decoder circuit <b>217</b>. Moreover, the sense amplifier circuit <b>215</b> has a function of detecting and amplifying a current flowing between the selected word line WL and the selected bit line BL.

0086The control circuit <b>221</b> has a function of controlling the word line driver circuit <b>212</b>, the row decoder circuit <b>214</b>, the sense amplifier circuit <b>215</b>, the column decoder circuit <b>217</b>, and other circuits (not shown).

0087Circuits such as the word line driver circuit <b>212</b>, the row decoder circuit <b>214</b>, the sense amplifier circuit <b>215</b>, the column decoder circuit <b>217</b>, and the control circuit <b>221</b> are configured with, for example, a transistor or a wiring layer using a semiconductor layer (not shown).

0088<figref idref="DRAWINGS">FIG. 6</figref> shows a schematic cross-sectional view of the memory cell array <b>210</b> of the storage device according to the third embodiment. <figref idref="DRAWINGS">FIG. 6</figref> is a yz cross-sectional view of the memory cell array <b>210</b>. In <figref idref="DRAWINGS">FIG. 6</figref>, a region surrounded by a broken line is one memory cell MC.

0089The memory cell array <b>210</b> includes the word line WL<b>11</b> (an example of a first conductive layer), the word line WL<b>12</b>, the word line WL<b>21</b>, the word line WL<b>22</b>, and the bit line BL<b>11</b> (an example of a second conductive layer). The memory cell array <b>210</b> further includes the resistance-variable layer <b>30</b>, the interlayer insulating layers <b>40</b> (an example of an insulating layer), and the first interface regions <b>50</b> (an example of a first region).

0090As described above, according to the storage device according to the third embodiment, similarly to the first embodiment, adhesion between the resistance-variable layer and the insulating layers increases. Therefore, film peeling between the resistance-variable layer and the insulating layers is unlikely to occur during manufacture. Thereby, a storage device that can be stably manufactured is achieved. Further, in addition to the advantageous effects of the first embodiment, the three-dimensional structure improves the integration degree of the storage device.

0091A selector layer similar to that of the second embodiment may be provided to the memory cell MC of the storage device according to the third embodiment.

0092While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. An element of an embodiment may be substituted by an element of another embodiment or may be changed. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.