Electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is a continuation from U.S. application Ser. No. 15/660,317, filed Jul. 26, 2017, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-149611, filed Jul. 29, 2016, the entire contents of which are incorporated herein by reference.

FIELD

0002Embodiments described herein relate generally to an electric device and method for manufacturing the same.

BACKGROUND

0003In electronic devices, a demand for high efficiency and low cost of wiring mounting has been further increased. For example, a technique that relates to a display device which is an example of an electronic device and electrically connects a wiring portion having an in-hole connector provided inside a hole penetrating an inner surface and an outer surface of a first substrate formed of a resin and a wiring portion provided on an inner surface of a second substrate formed of a resin by an inter-substrate connector is disclosed (for example, JP 2002-40465 A).

SUMMARY

0004The present disclosure relates generally to an electric device and method for manufacturing the same. According to one embodiment, an electronic device includes a first substrate, a second substrate and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement having a first hole a second conductive layer having a second hole. The first surface of the second basement opposes the first conductive layer and is spaced therefrom. The second surface opposite to the first surface includes a first flat portion exposed from the second conductive layer. The connecting material is filled into the first hole electrically connect the first conductive layer and the second conductive layer to each other. Additional features and advantages are described herein, and will be apparent from the following Detailed Description and the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

0005<figref idref="DRAWINGS">FIG. 1</figref> is a plan view illustrating a configuration example of a display device DSP of a first embodiment;

0006<figref idref="DRAWINGS">FIG. 2</figref> is a plan view schematically illustrating a basic configuration and an equivalent circuit of the display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 1</figref>;

0007<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view illustrating a structure of a display area DA of the display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 1</figref>;

0008<figref idref="DRAWINGS">FIG. 4</figref> is a plan view illustrating a configuration example of a sensor SS according to the first embodiment;

0009<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view taken along line F<b>5</b>-F<b>5</b> in <figref idref="DRAWINGS">FIG. 1</figref>;

0010<figref idref="DRAWINGS">FIG. 6</figref> is a view illustrating an example of melting points of materials of first and second conductive layers L<b>1</b> and L<b>2</b> and first and second basements <b>10</b> and <b>20</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref>;

0011<figref idref="DRAWINGS">FIG. 7</figref> is a plan view of a contact hole V illustrated in <figref idref="DRAWINGS">FIG. 5</figref> when viewed from a second substrate SUB<b>2</b> side;

0012<figref idref="DRAWINGS">FIG. 8</figref> is an enlarged cross-sectional view of a second hole VB illustrated in <figref idref="DRAWINGS">FIG. 5</figref>;

0013<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view for describing a method for manufacturing a display device DSP of the first embodiment;

0014<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 9</figref>;

0015<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 10</figref>;

0016<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 11</figref>;

0017<figref idref="DRAWINGS">FIG. 13</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 12</figref>;

0018<figref idref="DRAWINGS">FIG. 14</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 13</figref>;

0019<figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 14</figref>;

0020<figref idref="DRAWINGS">FIG. 16</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 15</figref>;

0021<figref idref="DRAWINGS">FIG. 17</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 16</figref>;

0022<figref idref="DRAWINGS">FIG. 18</figref> is a cross-sectional view for describing the method for manufacturing a display device DSP subsequent to <figref idref="DRAWINGS">FIG. 17</figref>; and

0023<figref idref="DRAWINGS">FIG. 19</figref> is a plan view of a display device DSP of a second embodiment when viewed from a second substrate SUB<b>2</b> side.

DETAILED DESCRIPTION

0024In general, according to one embodiment, an electronic device includes a first substrate, a second substrate, and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement having a first hole and a second conductive layer having a second hole larger than the first hole. A first main surface of the second basement is opposed to the first conductive layer and is spaced apart from the first conductive layer. The second main surface opposite to the first main surface has a first flat portion exposed from the second conductive layer between an edge of the first hole and an edge of the second hole. The connecting material is filled in the first hole and electrically connects the first conductive layer and the second conductive layer via the first hole.

0025In addition, according to one embodiment, a method of manufacturing an electronic device, includes preparing a display panel, forming a first hole and placing a connecting material. Preparing a display panel including a first basement on which a first conductive layer is formed, and a second basement including a first main surface opposing the first conductive layer and a second main surface opposite to the first main surface, adhered to each other, and further including a second conductive layer over the second main surface, which covers the second main surface and a first flat portion which expose the second main surface via the second conductive layer. Forming a first hole penetrating from the second main surface to the first main surface in the first flat portion. Placing a connecting material in the first hole to electrically connect the first conductive layer and the second conductive layer to each other.

0026Embodiments will be described hereinafter with reference to the accompanying drawings. Incidentally, the disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, and the like of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Besides, in the specification and drawings, the structural elements having functions, which are identical or similar to the functions of the structural elements described in connection with preceding drawings, are denoted by like reference numerals, and an overlapping detailed description is omitted unless otherwise necessary.

0027In each embodiment, a display device is disclosed as an example of an electronic device. The display device can be used for various devices such as a smart phone, a tablet terminal, a mobile phone terminal, a notebook type personal computer, and a game machine. Main components disclosed in each embodiment can be applied to a liquid crystal display device, a self-luminous display device such as an organic electroluminescence display device, an electronic paper type display device having an electrophoretic element and the like, a display device to which micro electro mechanical systems (MEMS) is applied, or a display device to which electrochromism is applied, and the like.

0028Further, the electronic device is not limited to the display device, and may be, for example, an external type touch panel substrate that is overlaid and attached on the display device. The present invention can be applied to various electronic devices including an inter-substrate conducting structure in which a first basement and a second basement are disposed to be spaced apart from each other, the second basement has a first hole, a first conductive layer located over the first basement and a second conductive layer located on the second substrate are electrically connected to each other via the first hole.

First Embodiment

0029<figref idref="DRAWINGS">FIG. 1</figref> is a plan view illustrating an example of a display device DSP of a first embodiment. A first direction X, a second direction Y, and a third direction Z are orthogonal to each other, but may intersect with each other at an angle other than 90°. The first direction X and the second direction Y correspond to a direction parallel to a main surface of a substrate configuring a display device DSP and the third direction Z corresponds to a thickness direction of the display device DSP. Here, as an example of the display device DSP, a liquid crystal display device equipped with a sensor SS will be described.

0030The display device DSP includes a display panel PNL, an IC chip I<b>1</b>, a wiring substrate SUB<b>3</b> or the like. The display panel PNL is a liquid crystal panel, and includes a first substrate SUB<b>1</b>, a second substrate SUB<b>2</b>, a seal SE, and a liquid crystal layer LC. The second substrate SUB<b>2</b> is opposed to the first substrate SUB<b>1</b> in the third direction Z. The seal SE corresponds to a portion indicated diagonally upward right in <figref idref="DRAWINGS">FIG. 1</figref> and adheres the first substrate SUB<b>1</b> to the second substrate SUB<b>2</b>. The liquid crystal layer LC is disposed between the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b> at an inner side of the seal SE.

0031In the following description, a direction from the first substrate SUB<b>1</b> toward the second substrate SUB<b>2</b> is referred to as an upward direction and a direction from the second substrate SUB<b>2</b> toward the first substrate SUB<b>1</b> is referred to as a downward direction. In addition, what is viewed from the second substrate SUB<b>2</b> toward the first substrate SUB<b>1</b> is referred to as a plan view.

0032The display panel PNL includes a display area DA that displays an image and a frame-like non-display area NDA surrounding the display area DA. The display area DA is an example of a first area and is located inside an area surrounded by the seal SE. The non-display area NDA is an example of a second area and is adjacent to the display area DA. The seal SE is located in the non-display area NDA.

0033The wiring substrate SUB<b>3</b> is mounted on the first substrate SUB<b>1</b>. The wiring substrate SUB<b>3</b> is, for example, a flexible substrate having flexibility. It should be noted that the flexible substrate applicable in the present embodiment may include a flexible portion formed of a bendable material formed in at least a part thereof. In other words, the wiring substrate SUB<b>3</b> may be a flexible substrate the whole of which is configured as a flexible portion, and may be a rigid flexible substrate including a rigid portion formed of hard materials such as glass epoxy and a flexible portion formed of bendable materials such as polyimide.

0034The IC chip I<b>1</b> is mounted over the wiring substrate SUB<b>3</b>. The IC chip I<b>1</b> is not limited to the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, but the IC chip I<b>1</b> may be mounted over the first substrate SUB<b>1</b> extending outwardly of the second substrate SUB<b>2</b>, or may be mounted over an external circuit board connected to the wiring substrate SUB<b>3</b>. The IC chip I<b>1</b> includes, for example, a display driver DD that outputs a signal necessary for displaying an image. The display driver DD includes, for example, at least one of a signal line drive circuit SD, a scanning line drive circuit GD, and a common electrode drive circuit CD which will be described below. In addition, in the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the IC chip I<b>1</b> includes a detection circuit RC that serves as a touch panel controller or the like. The detection circuit RC may be built in another IC chip different from the IC chip I<b>1</b>.

0035The display panel PNL may be, for example, a transmissive type having a transmissive display function of selectively transmitting light from a lower side of the first substrate SUB<b>1</b> to display an image, or may be a reflective type having a reflective display function of selectively reflecting light from an upper side of the second substrate SUB<b>2</b> to display an image. Alternatively, the display panel PNL may be a transflective type having the transmissive display function and the reflective display function.

0036The sensor SS performs sensing for detecting a contact or approach of an object to the display device DSP. The sensor SS is provided with a plurality of detection electrodes Rx (Rx<b>1</b>, Rx<b>2</b>, Rx<b>3</b>, Rx<b>4</b>, . . . ). The detection electrode Rx is provided on the second substrate SUB<b>2</b>. Each detection electrode Rx extends in the first direction X and is arranged at intervals in the second direction Y. The detection electrode Rx includes a detector RS and a connector CN. In addition, each detection electrode Rx has a terminal RT (RT<b>1</b>, RT<b>2</b>, RT<b>3</b>, RT<b>4</b>, . . . ).

0037The detector RS is located in the display area DA and extends in the first direction X. In the detection electrode Rx, the detector RS is mainly used for sensing. As an example, the detector RS can be formed into a stripe shape by an aggregate of fine metal wires. In addition, in the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, one detection electrode Rx includes two detectors RS, but three or more detectors RS may be provided, or one detector RS may be provided.

0038The terminal RT is located on one end side of the non-display area NDA along the first direction X and is connected to the detector RS. The connector CN is located on one end side and the other end side of the non-display area NDA along the first direction X, and connects the plurality of detectors RS to each other, and at the same time, is connected to the terminal RT. In <figref idref="DRAWINGS">FIG. 1</figref>, one end side corresponds to a left side of the display area DA and the other end side corresponds to a right side of the display area DA. A part of the terminal RT is formed at a location overlaying the seal SE in planar view.

0039The first substrate SUB<b>1</b> includes pads P (P<b>1</b>, P<b>2</b>, P<b>3</b>, P<b>4</b>, . . . ) and wiring lines W (W<b>1</b>, W<b>2</b>, W<b>3</b>, W<b>4</b>, . . . ). The pad P and the wiring line W are located at one end side or the other end side of the non-display area NDA and overlay the seal SE in planar view. The pad P is formed at a location overlaying the terminal RT in planar view. The wiring line W is connected to the pad P, extends along the second direction Y, and is electrically connected to the detection circuit RC of the IC chip I<b>1</b> via the wiring substrate SUB<b>3</b>.

0040The contact hole V (V<b>1</b>, V<b>2</b>, V<b>3</b>, V<b>4</b>, . . . ) is formed at a location where the terminal RT and the pad P are opposed to each other. In addition, the contact hole V may penetrate through the pad P, simultaneously with penetrating the second substrate SUB<b>2</b> including the terminal RT and the seal SE. In the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the contact hole V has a circular shape in planar view, but it is not limited thereto, and may have other shapes such as an ellipse. The terminal RT is formed slightly larger than the contact hole V. In the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the terminal RT has a circular shape, but it is not limited thereto, and may have other shapes such as an octagon.

0041The contact hole V is provided with a connecting material C to be described below, and the terminal RT of the detection electrode Rx and the pad P are electrically connected to each other via the connecting material C. The detection electrode Rx is an example of the second conductive layer L<b>2</b> provided on the second substrate SUB<b>2</b> that is spaced apart from the first substrate SUB<b>1</b>, and the pad P and the wiring line W are an example of the first conductive layer L<b>1</b> provided on the first substrate SUB<b>1</b>.

0042The detection electrode Rx connected to the pad P is electrically connected to the detection circuit RC via the wiring substrate SUB<b>3</b> connected to the first substrate SUB<b>1</b>. The detection circuit RC reads a sensor signal output from the detection electrode Rx and detects the presence or absence of the contact or approach of the object, the location coordinate of the object or the like.

0043In the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, all of the terminal RT (RT<b>1</b>, RT<b>3</b>, . . . ), the pad P (P<b>1</b>, P<b>3</b>, . . . ), the wiring line W (W<b>1</b>, W<b>3</b>, . . . ), and the contact hole V (V<b>1</b>, V<b>3</b>, . . . ) of each of the odd-numbered detection electrodes Rx (Rx<b>1</b>, Rx<b>3</b>, . . . ) are located on one end side of the non-display area NDA. In contrast, all of the terminal RT (RT<b>2</b>, RT<b>4</b>, . . . ), the pad P (P<b>2</b>, P<b>4</b>, . . . ), the wiring line W (W<b>2</b>, W<b>4</b>, . . . ), and the contact hole V (V<b>2</b>, V<b>4</b>, . . . ) of each of the even-numbered detection electrodes Rx (Rx<b>2</b>, Rx<b>4</b>, . . . ) are located on the other end side opposite to the one end side of the non-display area NDA. According to the layout, a width of the one end side and a width of the other end side in the non-display area NDA can be uniform, which is suitable for narrowing the frame.

0044As illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, in the layout in which the pad P<b>3</b> is closer to the wiring substrate SUB<b>3</b> than the pad P<b>1</b>, the wiring line W<b>1</b> bypasses an inner side of the pad P<b>3</b>, that is, a side close to the display area DA, and are disposed in parallel inside the wiring line W<b>3</b> between the pad P<b>3</b> and the wiring substrate SUB<b>3</b>. Likewise, the wiring line W<b>2</b> bypasses an inner side of the pad P<b>4</b> and is disposed in parallel inside the wiring line W<b>4</b> between the pad P<b>4</b> and the wiring substrate SUB<b>3</b>.

0045<figref idref="DRAWINGS">FIG. 2</figref> is a plan view schematically illustrating a basic configuration and an equivalent circuit of the display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 1</figref>.

0046The display panel PNL includes a plurality of pixels PX in the display area DA. Here, a pixel indicates a minimum unit that can be individually controlled according to a pixel signal, and exists in, for example, a region including a switching element disposed at a location where a scanning line and a signal line to be described below intersect each other. The pixels PX are arrayed in a matrix in the first direction X and the second direction Y. In addition, the display panel PNL includes a plurality of scanning lines G (G<b>1</b> to Gn), a plurality of signal lines S (S<b>1</b> to Sm), a common electrode CE or the like in the display area DA.

0047Each scanning line G extends in the first direction X and is arranged in the second direction Y. Each signal line S extends in the second direction Y and is arranged in the first direction X. It should be noted that the scanning line G and the signal line S may not necessarily extend linearly, and a part thereof may be bent. The common electrode CE is arranged over the pixels PX.

0048The scanning line G, the signal line S, and the common electrode CE are each led out to the non-display area NDA. In the non-display area NDA, the scanning line G is connected to the scanning line drive circuit GD, the signal line S is connected to the signal line drive circuit SD, and the common electrode CE is connected to the common electrode drive circuit CD. The signal line drive circuit SD, the scanning line drive circuit GD, and the common electrode drive circuit CD may be formed on the first substrate SUB<b>1</b>, and a part or all of them are built in the IC chip I<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>

0049Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC or the like. The switching element SW is formed of, for example, a thin film transistor (TFT) and is electrically connected to the scanning line G and the signal line S. More specifically, the switching element SW includes a gate electrode WG, a source electrode WS, and a drain electrode WD. The gate electrode WG is electrically connected to the scanning line G. In the example illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, the electrode electrically connected to the signal line S is the source electrode WS, and the electrode electrically connected to the pixel electrode PE is the drain electrode WD.

0050The scanning line G is connected to the switching element SW in each of the pixels PX arranged in the first direction X. The signal line S is connected to the switching element SW in each of the pixels PX arranged in the second direction Y. Each of the pixel electrodes PE is opposed to the common electrode CE and drives the liquid crystal layer LC by an electric field generated between the pixel electrode PE and the common electrode CE. A storage capacitor CS is formed, for example, between the common electrode CE and the pixel electrode PE.

0051<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of the display device DSP taken along the first direction X in the display area DA. In the example illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the display panel PNL mainly has a configuration corresponding to a display mode using a horizontal electric field substantially parallel to an X-Y plane. It should be noted that the display panel PNL may have a configuration corresponding to a vertical electric field perpendicular to the X-Y plane, an inclined electric field to the X-Y plane, or a display mode that uses a combination of the electric fields.

0052In the display mode using the horizontal electric field, for example, a configuration in which either the first substrate SUB<b>1</b> or the second substrate SUB<b>2</b> is provided with both of the pixel electrode PE and the common electrode CE can be applied. In the display mode using the vertical electric field or the inclined electric field, for example, a configuration in which the first substrate SUB<b>1</b> is provided with any one of the pixel electrode PE and the common electrode CE and the second substrate SUB<b>2</b> is provided with the other of the pixel electrode PE and the common electrode CE can be applied.

0053The first substrate SUB<b>1</b> includes the first basement <b>10</b>, the signal line S, the common electrode CE, a metal layer M, the pixel electrode PE, a first insulating layer <b>11</b>, a second insulating layer <b>12</b>, a third insulating layer <b>13</b>, a first alignment film AL<b>1</b> or the like. The first basement <b>10</b> has a third main surface <b>10</b>A that is opposed to the second substrate SUB<b>2</b> and a fourth main surface <b>10</b>B opposite to the third main surface <b>10</b>A. In <figref idref="DRAWINGS">FIG. 3</figref>, the switching elements, the scanning lines, various insulating layers interposed therebetween or the like are omitted.

0054The first insulating layer <b>11</b> is located over the third main surface <b>10</b>A of the first basement <b>10</b>. The scanning line or a semiconductor layer of a switching element that is not shown is located between the first basement <b>10</b> and the first insulating layer <b>11</b>. The signal line S is located over the first insulating layer <b>11</b>. The second insulating layer <b>12</b> is located over the signal line S and the first insulating layer <b>11</b>. The common electrode CE is located over the second insulating layer <b>12</b>.

0055The metal layer M comes into contact with the common electrode CE directly above the signal line S. In the example illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the metal layer M is located over the common electrode CE, but it may be located between the common electrode CE and the second insulating layer <b>12</b>. The third insulating layer <b>13</b> is located over the common electrode CE and the metal layer M. The pixel electrode PE is located over the third insulating layer <b>13</b>. The pixel electrode PE is opposed to the common electrode CE via the third insulating layer <b>13</b>. In addition, the pixel electrode PE has a slit SL at a location where the pixel electrode PE is opposed to the common electrode CE. The first alignment film AL<b>1</b> covers the pixel electrode PE and the third insulating layer <b>13</b>.

0056The scanning line G, the signal line S, and the metal layer M are formed of metal materials such as molybdenum, tungsten, titanium, and aluminum. It should be noted that the scanning line G, the signal line S, and the metal layer M may have a single layer structure or a multilayer structure. The common electrode CE and the pixel electrode PE are formed of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first insulating layer <b>11</b> and the third insulating layer <b>13</b> are inorganic insulating layers and the second insulating layer <b>12</b> is an organic insulating layer.

0057It should be noted that the configuration of the first substrate SUB<b>1</b> is not limited to the example illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, and the pixel electrode PE may be located between the second insulating layer <b>12</b> and the third insulating layer <b>13</b> and the common electrode CE may be located between the third insulating layer <b>13</b> and the first alignment film AL<b>1</b>. In such a case, the pixel electrode PE is formed in a flat plate shape without a slit, and the common electrode CE has a slit opposed to the pixel electrode PE. In addition, both the pixel electrode PE and the common electrode CE may be formed in a comb shape and may be disposed so as to be engaged with each other.

0058The second substrate SUB<b>2</b> includes a second basement <b>20</b>, a light-shielding layer BM, a color filter CF, an overcoat layer OC, a second alignment film AL<b>2</b> or the like. The second basement <b>20</b> has a first main surface <b>20</b>A opposed to the first substrate SUB<b>1</b> and a second main surface <b>20</b>B opposite to the first main surface <b>20</b>A.

0059The light-shielding layer BM and the color filter CF are located over the first main surface <b>20</b>A of the second basement <b>20</b>. The light-shielding layer BM partitions each pixel and is located directly above the signal line S. The color filter CF is opposed to the pixel electrode PE, and a part thereof overlays the light-shielding layer BM. The color filter CF includes a red color filter, a green color filter, a blue color filter or the like. The overcoat layer OC covers the color filter CF. The second alignment film AL<b>2</b> covers the overcoat layer OC.

0060It should be noted that the color filter CF may be disposed on the first substrate SUB<b>1</b>. The color filter CF may include color filters for four or more colors. A pixel displaying white may be provided with a white color filter, provided with an uncolored resin material, or provided with the overcoat layer OC without being provided with the color filter.

0061A first polarizer PL<b>1</b> is located between the first basement <b>10</b> and an illumination device BL. A second polarizer PL<b>2</b> is located over the detection electrode Rx that is provided over the second main surface <b>20</b>B of the second basement <b>20</b>. It should be noted that the first polarizer PL<b>1</b> and the second polarizer PL<b>2</b> may be additionally provided with a retardation film or the like, if necessary.

0062A configuration example of the sensor SS mounted on the display device DSP of the present embodiment will be described with reference to <figref idref="DRAWINGS">FIG. 4</figref>. The sensor SS illustrated in <figref idref="DRAWINGS">FIG. 4</figref> is, for example, a mutual-capacitive electrostatic capacitance type, and can detect a contact or an approach of an object based on a change in electrostatic capacitance between a pair of electrodes opposed to each other via a dielectric. The sensor SS is, for example, an in-cell type touch panel.

0063The sensor SS includes a sensor driving electrode Tx and the detection electrode Rx. In the example illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the sensor driving electrode Tx corresponds to a portion indicated diagonally downward right and is provided on the first substrate SUB<b>1</b>. In addition, the detection electrode Rx corresponds to a portion indicated diagonally upward right and is provided on the second substrate SUB<b>2</b>. The sensor driving electrode Tx and the detection electrode Rx intersect with each other in the X-Y plane. The detection electrode Rx is opposed to the sensor driving electrode Tx in the third direction Z.

0064The sensor driving electrode Tx and the detection electrode Rx are located in the display area DA, and a part of the sensor driving electrode Tx and the detection electrode Rx extends to the non-display area NDA. In the example illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, each of the sensor driving electrodes Tx has a stripe shape extending in the second direction Y, and the sensor driving electrodes Tx are arranged at intervals in the first direction X. Each of the detection electrodes Rx extends in the first direction X and the detection electrodes Rx are arranged at intervals in the second direction Y. The detection electrode Rx is electrically connected to the pad P by the inter-substrate conducting structure and is connected to the detection circuit RC via the wiring line W.

0065Each of the sensor driving electrodes Tx is electrically connected to the common electrode drive circuit CD via the wiring line W. It should be noted that the number, size and shape of the sensor driving electrodes Tx and the detection electrodes Rx are not particularly limited, and can be variously changed. The sensor driving electrode Tx includes the above-mentioned common electrode CE and serves to generate an electric field between the sensor driving electrode Tx and the pixel electrode PE and generate capacitance between the sensor driving electrode Tx and the detection electrode Rx to detect a location of an object.

0066The common electrode drive circuit CD supplies a common drive signal to the sensor driving electrode Tx including the common electrode CE during display driving for displaying an image in the display area DA. In addition, the common electrode drive circuit CD supplies a sensor drive signal to the sensor driving electrode Tx during sensing driving for sensing. As the sensor drive signal is supplied to the sensor driving electrode Tx, the detection electrode Rx outputs a sensor signal necessary for sensing, in other words, a signal based on a change in inter-electrode capacitance between the sensor driving electrode Tx and the detection electrode Rx. The detection signal output from the detection electrode Rx is input to the detection circuit RC illustrated in <figref idref="DRAWINGS">FIG. 1</figref>.

0067It should be noted that the sensor SS is not limited to the mutual capacitive type of detecting an object based on the electrostatic capacitance between the pair of electrodes, that is, the change in the electrostatic capacitance between the sensor driving electrode Tx and the detection electrode Rx, and may be a self-capacitive type that detects an object based on a change in capacitance of the detection electrode Rx itself.

0068Next, the above-mentioned contact hole V (V<b>1</b>, V<b>2</b>, V<b>3</b>, V<b>4</b>, . . . ) will be described. <figref idref="DRAWINGS">FIG. 5</figref> is a schematic cross-sectional view of the display device DSP taken along the line F<b>5</b>-F<b>5</b> in <figref idref="DRAWINGS">FIG. 1</figref>.

0069In the example illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, in the inter-substrate conducting structure provided in the non-display area NDA, the display device DSP includes the first substrate SUB<b>1</b>, the second substrate SUB<b>2</b>, an organic insulating layer OI, a protective film PF, the connecting material C, the first polarizer PL<b>1</b>, and the second polarizer PL<b>2</b>. The first polarizer PL<b>1</b> adheres to the first substrate SUB<b>1</b> by an adhesive layer AD<b>1</b>. The second polarizer PL<b>2</b> adheres to the second substrate SUB<b>2</b> by an adhesive layer AD<b>2</b>.

0070The first substrate SUB<b>1</b> includes the above-mentioned first basement <b>10</b> and the first conductive layer L<b>1</b>. The first conductive layer L<b>1</b> includes the pad P (P<b>1</b>, P<b>2</b>, P<b>3</b>, P<b>4</b>, . . . ) or the wiring line W (W<b>1</b>, W<b>2</b>, W<b>3</b>, W<b>4</b>, . . . ) that are described above and is located over the third main surface <b>10</b>A side opposed to the second substrate SUB<b>2</b>. The first insulating layer <b>11</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, another insulating layer, or another conductive layer may be disposed between the first basement <b>10</b> and the pad P and between the first basement <b>10</b> and the second insulating layer <b>12</b>.

0071The second substrate SUB<b>2</b> includes the second basement <b>20</b> and the second conductive layer L<b>2</b> described above. The first main surface <b>20</b>A of the second basement <b>20</b> is opposed to the first conductive layer L<b>1</b> and is spaced apart from the first conductive layer L<b>1</b> in the third direction Z. The second conductive layer L<b>2</b> includes the above-mentioned detection electrode Rx, that is, the terminal RT (RT<b>1</b>, RT<b>2</b>, RT<b>3</b>, RT<b>4</b>, . . . ) or the connector CN. The second conductive layer L<b>2</b> is located over the second main surface <b>20</b>B side and is covered with the protective film PF. In other words, the first basement <b>10</b>, the first conductive layer L<b>1</b>, the second basement <b>20</b>, the second conductive layer L<b>2</b>, and the protective film PF are arranged in the third direction Z in this order.

0072The organic insulating layer OI is located between the first conductive layer L<b>1</b> and the second basement <b>20</b>. Instead of the organic insulating layer OI, an inorganic insulating layer or another conductive layer may be located, or an air layer may be located. It should be noted that various insulating layers and various conductive layers may be disposed between the second basement <b>20</b> and the second conductive layer L<b>2</b> or over the second conductive layer L<b>2</b>.

0073For example, the organic insulating layer OI includes the seal SE for bonding the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b>, the second insulating layer <b>12</b> of the first substrate SUB<b>1</b>, the light-shielding layer BM and the overcoat layer OC of the second substrate SUB<b>2</b>, or the like. The seal SE is located between the second insulating layer <b>12</b> and the overcoat layer OC. The liquid crystal layer LC is located in a gap between the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b> and is surrounded by the seal SE.

0074It should be noted that the metal layer M, the third insulating layer <b>13</b>, and the first alignment film AL<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> may be interposed between the second insulating layer <b>12</b> and the seal SE. The second alignment film AL<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> may be interposed between the overcoat layer OC and the seal SE.

0075The material of the first and second basements <b>10</b> and <b>20</b> is, for example, glass, or more specifically, alkali-free glass. Note that the material may be a flexible resin such as polyimide. The protective film PF is formed of, for example, organic insulating materials such as an acrylic resin. The first and second conductive layers L<b>1</b> and L<b>2</b> are formed of, for example, metal materials such as molybdenum, tungsten, titanium, aluminum, silver, copper, and chromium, an alloy in which these metal materials are combined, or transparent conductive materials such as ITO or IZO. The first and second conductive layers L<b>1</b> and L<b>2</b> may also have a single layer structure or a multilayer structure.

0076As illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the second basement <b>20</b> has a first hole VA penetrating from the second main surface <b>20</b>B to the first main surface <b>20</b>A. The second conductive layer L<b>2</b> has a second hole VB that penetrates the second conductive layer L<b>2</b> and is formed to be slightly larger than the first hole VA. The protective film PF has a third hole VC that penetrates the protective film PF and formed to be slightly larger than the first and second holes VA and VB.

0077In addition to the first to third holes VA, VB, and VC, the display device DSP has a fourth hole VD penetrating the first conductive layer L<b>1</b>, a fifth hole VE penetrating each organic insulating layer OI, and a concavity CC formed in the first basement <b>10</b>. The first to fifth holes VA, VB, VC, VD, and VE and the concavity CC communicate with each other and configure the above-mentioned contact hole V.

0078The fourth hole VD penetrates the first conductive layer L<b>1</b> at the pad P and is opposed to the first hole VA in the third direction Z. In the example illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the fifth hole VE includes a hole penetrating the second insulating layer <b>12</b>, a hole penetrating the seal SE, a hole penetrating a light-shielding layer BM and the overcoat layer OC or the like.

0079The fifth hole VE is extended in the second direction Y as compared with the first and fourth holes VA and VD. It should be noted that the fifth hole VE extends beyond the first and fourth holes VA and VD over all directions on the X-Y plane as well as in the second direction Y. In addition, an inner surface LS<b>1</b> of the first conductive layer L<b>1</b> is formed to be approximately flush with an edge of the concavity CC of the first basement <b>10</b>. For this reason, the first conductive layer L<b>1</b> has an upper surface LT<b>1</b> that is not covered with the organic insulating layer OI in the vicinity of the fourth hole VD.

0080The concavity CC is formed from the third main surface <b>10</b>A toward the fourth main surface <b>10</b>B of the first basement <b>10</b> and does not penetrate up to the fourth main surface <b>10</b>B. The concavity CC is opposed to the third hole VC in the third direction Z. In one example, the depth of the concavity CC along the third direction Z is about ⅕ to about ½ of a thickness of the first basement <b>10</b> in the third direction Z.

0081All of the fourth and fifth holes VD and VE and the concavity CC are located directly under the first to third holes VA, VB, and VC, and the third hole VC, the second hole VB, the first hole VA, the fifth hole VE, the fourth hole VD, and the concavity CC are arranged in the third direction Z in order. The contact hole V can be formed by irradiating laser light or etching from above the second substrate SUB<b>2</b>. Various organic insulating layers OI on which the fourth hole VD is provided are formed from, for example, materials having a melting point lower than that of the second basement <b>20</b> on which the first hole VA is provided and the first conductive layer L<b>1</b> on which the third hole VC is provided. Alternatively, various organic insulating layers OI are formed from materials that are easily etched.

0082As illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the connecting material C is disposed in the contact hole V. For example, it is preferable that the connecting material C contains metal materials such as silver, and the metal material includes fine particles having a particle diameter of the order of several nanometers to several tens of nanometers. The connecting material C electrically connects the first conductive layer L<b>1</b> and the second conductive layer L<b>2</b> via the contact hole V. In the example illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the connecting material C comes into contact with an inner circumferential surface LS<b>2</b>, an upper surface LT<b>2</b>, and an outer circumferential surface LU<b>2</b> of the terminal RT in the second conductive layer L<b>2</b>, respectively, and comes into contact with an inner surface LS<b>1</b> and an upper surface LT<b>1</b> of the pad P in the first conductive layer L<b>1</b>, respectively.

0083In the example illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the connecting material C is provided on the inner surfaces of the first to fifth holes VA, VB, VC, VD, and VE and the concavity CC, respectively, but the connecting material C is not filled in the vicinity of centers thereof. For this reason, the connecting material C has a hollow. The connecting material C having the shape is formed by injecting the connecting material C into the contact hole V under a barometric pressure or under the environment of atmospheric pressure lower than the barometric pressure and removing a solvent contained in the connecting material C.

0084The hollow of the connecting material C is filled up with a filling material FI. The filling material FI is formed of, for example, the same material as the protective film PF. It should be noted that the connecting material C may be formed so as not to have the hollow.

0085The connecting material C is continuously formed between the first conductive layer L<b>1</b> and the second conductive layer L<b>2</b> without being interrupted. By doing so, the second conductive layer L<b>2</b> is electrically connected to the above-mentioned wiring substrate SUB<b>3</b> via the connecting material C and the first conductive layer L<b>1</b>. For this reason, a control circuit that writes a signal into the second conductive layer L<b>2</b> or reads a signal output from the second conductive layer L<b>2</b> can be connected to the second conductive layer L<b>2</b> via the wiring substrate SUB<b>3</b>. Therefore, in order to connect the second conductive layer L<b>2</b> and the control circuit, there is no need to separately provide a wiring substrate for the second substrate SUB<b>2</b>.

0086Here, main materials usable for the first and second basements <b>10</b> and <b>20</b> or the first and second conductive layers L<b>1</b>, L<b>2</b> and their melting points are illustrated in <figref idref="DRAWINGS">FIG. 6</figref>.

0087In <figref idref="DRAWINGS">FIG. 6</figref>, as the metal materials, indium, aluminum, titanium, niobium, molybdenum, and tungsten are exemplified. In addition, as the glass material, silicon and quartz glass are exemplified.

0088It is preferable that a difference between the melting point of the material of the pad P of the first conductive layer L<b>1</b> on which the contact hole V is formed and the melting point of the material of the first basement <b>10</b> is within 300° C., for example. An example of the pad P may include a metal film containing titanium.

0089If the melting point of the material of the pad P is higher than that of the material of the first basement <b>10</b> by more than 300° C., the first basement <b>10</b> is excessively heated by a laser light for melting the pad P<b>1</b>, such that the molten first basement <b>10</b> is scattered into the contact hole V. Since the first basement <b>10</b> has a large electric resistance, conduction is hindered at a location to which the scattered material is attached.

0090In contrast, if the melting point of the material of the pad P is lower than that of the material of the first basement <b>10</b> by more than 300° C., the pad P is excessively heated by the laser light for melting the first basement <b>10</b> to be greatly lost. If the pad P becomes smaller, a contact area between the pad P and the connecting material C becomes smaller, such that connection reliability between the pad P and the connecting material C becomes lower.

0091For the same reasons, it is preferable that even a difference between a melting point of the material of the terminal RT of the second conductive layer L<b>2</b> in which the contact hole V is formed and a melting point of the material of the second basement <b>20</b> is within 300° C.

0092<figref idref="DRAWINGS">FIG. 7</figref> is a plan view of the contact hole V viewed from the second substrate SUB<b>2</b> side. <figref idref="DRAWINGS">FIG. 8</figref> is an enlarged cross-sectional view of the second hole VB illustrated in <figref idref="DRAWINGS">FIG. 5</figref>. As illustrated in <figref idref="DRAWINGS">FIGS. 7 and 8</figref>, the second main surface <b>20</b>B of the second basement <b>20</b> has a first flat portion FP<b>1</b> exposed from the second conductive layer L<b>2</b> between an edge E<b>1</b> of the first hole VA opened to the second basement <b>20</b> and an edge E<b>2</b> of the second hole VB opened to the detection electrode Rx. In the example illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, an inner surface <b>20</b>S of the first hole VA has a curved shape in the vicinity of a boundary between the first hole VA and the second hole VB. For example, the edge E<b>1</b> of the first hole VA corresponds to a boundary between the curved inner surface <b>20</b>S and the second main surface <b>20</b>B in parallel with the X-Y plane.

0093If the second main surface <b>20</b>B has a mortar-shaped cavity and the first hole VA is formed at a bottom of the cavity, if the second main surface <b>20</b>B has a protrusion rising to surround the first hole VA or the like, even the case where a part of the second main surface <b>20</b>B in the vicinity of the first hole VA is not necessarily parallel to the X-Y plane may be considered. However, in even the case where the second main surface <b>20</b>B is not flat in the vicinity of the first hole VA, the second main surface <b>20</b>B (for example, first flat portion FP<b>1</b>) of the second basement <b>20</b> remains inside the second hole VB opened to the second conductive layer L<b>2</b>. For this reason, the first flat portion FP<b>1</b> of the second main surface <b>20</b>B exposed from the second hole VB may be referred to as a main surface remaining portion FP<b>1</b>.

0094If the second main surface <b>20</b>B is parallel to the X-Y plane, the edge E<b>1</b> of the first hole VA can also be regarded as a starting point at which an angle of the second basement <b>20</b> cut on the Y-Z plane changes. The edge E<b>2</b> of the second hole VB can also be regarded as a starting point at which the angle of the second conductive layer L<b>2</b> cut on the Y-Z plane changes. Even in the case, a diameter of the second hole VB is larger than that of the first hole VA. In other words, the edge E<b>2</b> of the second hole VB is located outside the edge E<b>1</b> of the first hole VA in a radial direction. In addition, if the second main surface <b>20</b>B is parallel to the X-Y plane, the first flat portion FP<b>1</b> can be said to be a region parallel to the X-Y plane.

0095Furthermore, the second main surface <b>20</b>B has a second flat portion FP<b>2</b> exposed from the detection electrode Rx between the outer edge E<b>3</b> of the terminal RT of the detection electrode Rx and the edge E<b>4</b> of the third hole VC opened to the protective film PF. A difference in level G (illustrated in <figref idref="DRAWINGS">FIG. 13</figref>) is formed between the second flat portion FP<b>2</b> where the second main surface <b>20</b>B is exposed and an upper surface of the protective film PF.

0096In the example illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the first to third holes VA, VB, and VC are arranged so that their central axes coincide with each other. The first flat portion FP<b>1</b> is formed in an annular shape surrounding the first hole VA. The second flat portion FP<b>2</b> is formed in an annular shape surrounding the first hole VA except for a portion where the connector CN of the detection electrode Rx is disposed. In the example illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, widths of the first and second flat portions FP<b>1</b> and FP<b>2</b> are constant. It should be noted that the widths of the first and second flat portions FP<b>1</b> and FP<b>2</b> do not need to be constant over the entire circumference and may be partially different.

0097Next, an example of a method for manufacturing a display device DSP will be described with reference to <figref idref="DRAWINGS">FIGS. 9 to 18</figref>.

0098First, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, a display panel PNL is prepared. The display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 9</figref> includes the first substrate SUB<b>1</b> including at least the first basement <b>10</b> and the first conductive layer L<b>1</b> and the second substrate SUB<b>2</b> including at least the second basement <b>20</b> and the second conductive layer L<b>2</b>. In the display panel PNL, the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b> adhere to each other by the seal SE in the state where the second basement <b>20</b> is opposed to the first conductive layer L<b>1</b> and the second basement <b>20</b> is spaced apart from the first conductive layer L<b>1</b>. The second conductive layer L<b>2</b> is provided with the second hole VB in advance and the surface thereof is covered with the protective film PF.

0099Describing an example of the method for manufacturing a display panel PNL, the first substrate SUB<b>1</b> having the first conductive layer L<b>1</b> or the second insulating layer <b>12</b> or the like formed over the third main surface <b>10</b>A of the first basement <b>10</b> is prepared. The second substrate SUB<b>2</b> having the light-shielding layer BM, the overcoat layer OC or the like formed over the first main surface <b>20</b>A of the second basement <b>20</b> is prepared.

0100At this point, the second conductive layer L<b>2</b> is not formed over the second main surface <b>20</b>B of the second substrate SUB<b>2</b>. A loop-shaped seal SE is formed on any one of the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b>, and a liquid crystal material drops into the seal SE. Thereafter, the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b> are bonded to each other, and the seal SE is cured so that the first substrate SUB<b>1</b> adheres to the second substrate SUB<b>2</b>.

0101Thereafter, the first basement <b>10</b> and the second basement <b>20</b> are each etched with an etchant such as hydrofluoric acid (HF) to make the first basement <b>10</b> and the second basement <b>20</b> thin. Thereafter, the second conductive layer L<b>2</b> is formed over the second main surface <b>20</b>B of the second basement <b>20</b>. At this point, the second hole VB can be patterned at the same time. Note that the second conductive layer L<b>2</b> may be formed first, and then the second hole VB may be formed. By doing so, the display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 9</figref> is manufactured.

0102Another example of the method for manufacturing a display panel PNL will be described. That is, similarly to the above example, while the first substrate SUB<b>1</b> is prepared, the light-shielding layer BM, the overcoat layer OC or the like are formed over the first main surface <b>20</b>A of the second basement <b>20</b> and the second substrate SUB<b>2</b> on which the second conductive layer L<b>2</b> having the second hole VB patterned over the second main surface <b>20</b>B of the second basement <b>20</b> is formed is prepared. Thereafter, the seal SE is formed, the liquid crystal material drops, and then the first substrate SUB<b>1</b> and the second substrate SUB<b>2</b> adhere to each other. By doing so, the display panel PNL illustrated in <figref idref="DRAWINGS">FIG. 9</figref> is manufactured.

0103Subsequently, as illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the second substrate SUB<b>2</b> is irradiated with first laser light LSR<b>1</b>. In the example illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the first laser light LSR<b>1</b> is irradiated from above the second conductive layer L<b>2</b>. As a laser light source, for example, a carbon dioxide gas laser device or the like can be applied, but any device that can perform a drilling process on a glass material and an organic material can be used, and an excimer laser device or the like can also be applied.

0104As illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, the protective film PF is removed by irradiating the first laser light LSR<b>1</b> to form the third hole VC. In the third hole VC, the second main surface <b>20</b>B of the second basement <b>20</b> is exposed from the previously formed second hole VB. The first laser light LSR<b>1</b> is laser light having intensity at which the second conductive layer L<b>2</b> and the second basement <b>20</b> are not melted. Therefore, the second conductive layer L<b>2</b> and the second basement <b>20</b> are not damaged even when irradiated with the first laser light LSR<b>1</b>.

0105Further, as illustrated in <figref idref="DRAWINGS">FIG. 12</figref>, the second basement <b>20</b> is irradiated with second laser light LSR<b>2</b> via the second hole VB. The second laser light LSR<b>2</b> has a smaller diameter than the first laser light LSR<b>1</b>. In addition, the second laser light LSR<b>2</b> is laser light having intensity at which the first and second basements <b>10</b> and <b>20</b> and the first conductive layer L<b>1</b> can be melted or sublimed. For example, if an optical axis of the first laser light LSR<b>1</b> coincides with that of the second laser light LSR<b>2</b>, the laser light can be irradiated continuously without moving the laser light source. Since the second laser light LSR<b>2</b> is irradiated to the second hole VB that is an area where the second conductive layer L<b>2</b> is not formed, the second conductive layer L<b>2</b> is not damaged. That is, it is understood that the second laser light LSR<b>2</b> is higher in intensity than the first laser light LSR<b>1</b>.

0106As illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, the first hole VA penetrating the second basement <b>20</b> is formed by the second laser light LSR<b>2</b>. In addition, in the example illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, when the first laser light LSR<b>1</b> is irradiated, the fifth hole VE penetrating the organic insulating layer OI (light-shielding layer BM, overcoat layer OC, seal SE, second insulating layer <b>12</b> or the like), the fourth hole VD penetrating the first conductive layer L<b>1</b>, and the concavity CC of the first basement <b>10</b> are also formed at the same time. By doing so, the contact hole V for connecting the first conductive layer L<b>1</b> and the second conductive layer L<b>2</b> is formed.

0107The difference between the melting point of the material of the first conductive layer L<b>1</b> and the melting point of the material of the first basement <b>10</b> is within 300° C., and the fourth hole VD of the first conductive layer L<b>1</b> and the concavity CC of the first basement <b>10</b> are formed substantially at the same time. As a result, the inner surface LS<b>1</b> of the fourth hole VD and the edge of the concavity CC are formed to be approximately flush with each other.

0108Subsequently, the connecting material C for electrically connecting the first conductive layer L<b>1</b> and the second conductive layer L<b>2</b> is formed. First, as illustrated in <figref idref="DRAWINGS">FIG. 14</figref>, after the display panel PNL is provided inside a chamber CB, air inside the chamber CB is discharged to inject the connecting material C into the contact hole V under vacuum (under the environment in which a pressure is lower than the barometric pressure), for example. An injection device may be an ink jet or a dispenser.

0109At this point, the difference in level G is formed between the second flat portion FP<b>2</b> and the protective film PF. Even if the connecting material C is injected in an amount greatly exceeding the thickness of the second conductive layer L<b>2</b>, the protective film PF having the difference in level G serves as a levee to prevent the connecting material C from being leaked. As a result, the injected connecting material C can come into contact with not only the inner circumferential surface LS<b>2</b> and the upper surface LT<b>2</b> of the second conductive layer L<b>2</b> but also the outer circumferential surface LU<b>2</b> thereof in a wrap around manner.

0110It should be noted that the injected connecting material C may not flow to the first conductive layer L<b>1</b> and an internal space may be formed between the connecting material C and the first conductive layer L<b>1</b>. However, the internal space of the contact hole V becomes vacuum. For this reason, if gases such as air or inert gas are introduced into the chamber CB to reduce a degree of vacuum, as illustrated in <figref idref="DRAWINGS">FIG. 15</figref>, the connecting material C flows from the first hole VA into the fourth and fifth holes VD and VE and the concavity CC due to a difference in pressure around the internal space and the display panel PNL. By doing so, the connecting material C comes into contact with the first conductive layer L<b>1</b>.

0111Thereafter, as illustrated in <figref idref="DRAWINGS">FIG. 16</figref>, a solvent contained in the connecting material C is removed, such that a volume of the connecting material C is reduced. The connecting material C thus formed comes into contact with the second basement <b>20</b> in the first hole VA, comes into contact with the second conductive layer L<b>2</b> in the second hole VB, comes into contact with the light-shielding layer BM, the overcoat layer OC, the seal SE, and the second insulating layer <b>12</b>, respectively, in the fifth hole VE, comes into contact with the first conductive layer L<b>1</b> in the fourth hole VD, and comes into contact with the first basement <b>10</b> in the concavity CC.

0112It should be noted that the method for forming a connecting material C described with reference to <figref idref="DRAWINGS">FIGS. 15 and 16</figref> is merely an example and is not limited thereto. For example, even in the method for removing a solvent contained in the connecting material C after injecting the connecting material C into the fourth and fifth holes VD and VE and the concavity CC from the first hole VA under the barometric pressure, the connecting material C as described above may be formed.

0113Subsequently, as illustrated in <figref idref="DRAWINGS">FIG. 17</figref>, the filling material FI is filled in the hollow. The filling material FI is formed of, for example, the same material as the protective film PF. In the example illustrated in <figref idref="DRAWINGS">FIG. 17</figref>, the filling material FI is filled in the hollow of the connecting material C, and at the same time, covers the second conductive layer L<b>2</b> and the connecting material C. By doing so, the surface of the second substrate SUB<b>2</b> is substantially planarized, and the difference in level of the portion overlaying the contact hole V can be alleviated.

0114Subsequently, as illustrated in <figref idref="DRAWINGS">FIG. 18</figref>, the first polarizer PL<b>1</b> adheres to the first basement <b>10</b> and the second polarizer PL<b>2</b> adheres to the protective film PF. It should be noted that although the adhesive layers AD<b>1</b> and AD<b>2</b> are interposed between the first polarizer PL<b>1</b> and the first basement <b>10</b> and between the second polarizer PL<b>2</b> and the protective film PF, the illustration thereof is omitted here.

0115In the example illustrated in <figref idref="DRAWINGS">FIG. 18</figref>, the second polarizer PL<b>2</b> also extends to the portion overlaying the contact hole V. Since the difference in level caused by the contact hole V is alleviated by the protective film PF, it is possible to suppress the second polarizer PL<b>2</b> from being peeled due to a difference in level of a base portion of the second polarizer PL<b>2</b> at the time of the adhesion of the second polarizer PL<b>2</b>.

0116According to the display device DSP described above, the detection electrode Rx provided on the second substrate SUB<b>2</b> is connected to the pad P provided on the first substrate SUB<b>1</b> by the connecting material C provided in the contact hole V. For this reason, there is no need to mount the wiring substrate for connecting the detection electrode Rx and the detection circuit RC on the second substrate SUB<b>2</b>. In other words, the wiring substrate SUB<b>3</b> mounted on the first substrate SUB<b>1</b> forms a transmission path for transmitting a signal necessary for displaying an image on the display panel PNL, and at the same time, forms a transmission path for transmitting a signal between the detection electrode Rx and the detection circuit RC.

0117Therefore, the number of wiring substrates can be reduced and the cost can be reduced, as compared with the configuration example requiring a separate wiring substrate in addition to the wiring substrate SUB<b>3</b>. In addition, since a space for connecting the wiring substrate to the second substrate SUB<b>2</b> is unnecessary, a width of a non-display area of the display panel PNL, in particular, a width of a side edge on which the wiring substrate SUB<b>3</b> is mounted can be reduced. This makes it possible to narrow the frame and reduce the cost.

0118Alternatively, since the connecting material C comes into contact with not only the inner circumferential surface LS<b>2</b> of the second conductive layer L<b>2</b> in the second hole VB but also the upper surface LT<b>2</b> of the second conductive layer L<b>2</b>, the contact area between the connecting material C and the second conductive layer L<b>2</b> may be expanded, and the poor connection between the connecting material C and the second conductive layer L<b>2</b> can be suppressed.

0119In addition, since the connecting material C comes into contact with not only the inner surface LS<b>1</b> of the first conductive layer L<b>1</b> in the fourth hole VD but also the upper surface LT<b>1</b> of the first conductive layer L<b>1</b>, the contact area between the connecting material C and the first conductive layer L<b>1</b> may be expanded, and the poor connection between the connecting material C and the first conductive layer L<b>1</b> can be suppressed.

0120In addition, it is possible to alleviate the difference in level in the third direction Z due to the formation of the hollow in the connecting material C by filling the hollow of the connecting material C with the filling material FI. In addition, since the protective film PF covers the connecting material C and the second conductive layer L<b>2</b>, the protective film PF can protect the connecting material C and the second conductive layer L<b>2</b>.

0121In the present embodiment, the second main surface <b>20</b>B has a first flat portion FP<b>1</b> between the edge E<b>1</b> of the first hole VA and the edge E<b>2</b> of the second hole VB. At least a part of the first flat portion FP<b>1</b> and the first hole VA penetrating the second basement <b>20</b> are formed inside the second hole VB.

0122The second conductive layer L<b>2</b> and the second basement <b>20</b> have different expansion and contraction due to a change in temperature. However, according to the present embodiment, the second laser light LSR<b>2</b> for forming the first hole VA is irradiated and even if the second basement <b>20</b> is expanded or contracted due to heat, the location to which the second laser light LSR<b>2</b> is irradiated is provided with the second hole VB and is not covered with the second conductive layer L<b>2</b>. Therefore, a load applied to the second basement <b>20</b> can be suppressed to the minimum to form the first hole VA.

0123Furthermore, according to the present embodiment, it is possible to prevent the poor conduction between the connecting material C and the second conductive layer L<b>2</b> in advance.

0124The case where there is no second hole VB and the first hole VA penetrating the second conductive layer L<b>2</b> and the second basement <b>20</b> is formed can be considered. At this point, if the material of the second conductive layer L<b>2</b> has the melting point higher than that of the material of the second basement <b>20</b>, it is conceivable that the second basement <b>20</b> is excessively heated and scattered. If the scattered material of the second basement <b>20</b> adheres to the upper surface LT<b>2</b> of the second conductive layer L<b>2</b>, the conduction is hindered and therefore the connection reliability between the connecting material C and the second conductive layer L<b>2</b> may be reduced. In contrast, if the second hole VB of the second conductive layer L<b>2</b> and the first hole VA of the second basement <b>20</b> are separately formed as in the present embodiment, it is possible to prevent the second basement <b>20</b> from being scattered.

0125The display device DSP has the second flat portion FP<b>2</b> outside the second conductive layer L<b>2</b>. Due to the difference in level G between the second flat portion FP<b>2</b> and the protective film PF, the protective film PF serves as a levee at the time of filling the connecting material C. Since even the outer circumferential surface LU<b>2</b> of the second conductive layer L<b>2</b> is filled with the connecting material C in a wrap around manner, according to the present embodiment, it is possible to increase the contact area between the second conductive layer L<b>2</b> and the connecting material C and improve the connection reliability.

0126In the present embodiment, an example of the material of the first conductive layer L<b>1</b> is a metal film containing titanium, and the difference between the melting point of the material of the first conductive layer L<b>1</b> and the melting point of the material of the first basement <b>10</b> is within 300° C. For this reason, when the second laser light LSR<b>2</b> is irradiated, the fourth hole VD and the concavity CC are formed substantially at the same time, and any one of the first conductive layer L<b>1</b> and the first basement <b>10</b> is not excessively heated. By doing so, the first basement <b>10</b> or the like are not scattered, such that the connection reliability can be secured without hindering the conduction between the connecting material C and the first conductive layer L<b>1</b>.

Second Embodiment

0127Subsequently, a display device DSP of the second embodiment will be described with reference to <figref idref="DRAWINGS">FIG. 19</figref>. It should be noted that components having functions similar to those of the display device DSP of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. In the display device DSP of the second embodiment, the configuration of a third hole VC formed in a protective film PF is different from that of the first embodiment. Other components are the same as those of the first embodiment.

0128The third hole of the second embodiment includes a first portion VCA and a second portion VCB. The first portion VCA exposes a first flat portion FP<b>1</b> from the protective film PF. The second portion VCB exposes a second conductive layer L<b>2</b> (end portion RT) from the protective film PF.

0129The first portion VCA is formed in a circular shape having a diameter smaller than that of a second hole VB and is disposed so that a center axis thereof coincides with the first and second holes VA and VB, for example. The second portion VCB is disposed to be connected to the first portion VCA. The number of second portions VCB may be one or more than two. In the example illustrated in <figref idref="DRAWINGS">FIG. 19</figref>, the second portion VCB is formed in a circular shape having a diameter smaller than that of the first portion VCA, and eight second portions VCB are arranged at regular intervals.

0130Like the third hole VC in the first embodiment, the first portion VCA and the second portion VCB can be formed by the laser light. For example, after the first laser light is irradiated to form the first portion VCA, the second laser light having a diameter smaller than that of the first laser light may be irradiated plural times by moving a laser device along the circumferential direction of the first portion VCA to form the second portion VCB. Alternatively, the second portion VCB is first formed, and then the first portion VCA having a size connected to the second portion VCB can be formed.

0131In the example illustrated in <figref idref="DRAWINGS">FIG. 19</figref>, an edge E<b>4</b>A of the first portion VCA is located between the edge E<b>1</b> of the first hole VA and the edge E<b>2</b> of the second hole VB. An edge E<b>4</b>B of the second portion VCB is connected to the edge E<b>4</b>A of the first portion VCA. A second flat portion FP<b>2</b> in which the second main surface <b>20</b>B is exposed from the terminal RT is formed between the edge E<b>4</b>B and the outer edge E<b>3</b> of the terminal RT.

0132The above-mentioned connecting material C covers the first flat portion FP<b>1</b>, the terminal RT exposed from the second flat portion FP<b>2</b>, and the second flat portion FP<b>2</b>. Further, the above-mentioned filling material FI fills the inside of the first and second portions VCA and VCB of the third hole VC.

0133In the second embodiment, the second portion VCB that partially exposes the terminal RT is formed, instead of the third hole VC (see <figref idref="DRAWINGS">FIG. 7</figref>) that completely exposes the terminal RT. For this reason, the damage of the terminal RT caused by the radiation of the laser light can be suppressed to the minimum.

0134In the example illustrated in <figref idref="DRAWINGS">FIG. 19</figref>, the display device DSP has the plurality of second portions VCB. By doing so, since the connecting material C and the terminal RT come into contact with each other at a plurality of locations, the connection reliability can be secured even when all the terminals RT are not exposed.

0135As described above, according to the present embodiment, it is possible to provide an electronic device capable of narrowing the frame and reducing cost, and a method for manufacturing the same.

0136It should be noted that change of design may be arbitrarily added to the present invention, based on the display device described as one of the embodiments. The accompanying claims and their equivalents are intended to cover display devices modified as would fall within the scope and spirit of the inventions.

0137An example of the display device obtained from the structure disclosed in this specification will be appended.

0138(1) An electronic device, comprising:

0139a first substrate including a first basement and a first conductive layer;

0140a second substrate including a second basement and a second conductive layer; and

0141a connecting material electrically connecting the first conductive layer and the second conductive layer,

0142wherein the second basement includes a first surface, a second surface opposite to the first surface, and a first hole penetrating the second basement,

0143the first surface is opposed to the first conductive layer and spaced apart from the first conductive layer,

0144the second surface is provided with the second conductive layer,

0145the second conductive layer includes a second hole penetrating the second conductive layer and having a size larger than that of the first hole,

0146the second surface includes a first flat portion exposed from the second conductive layer between an edge of the first hole and an edge of the second hole, and

0147the connecting material contacts with the first conductive layer and the second conductive layer via the first hole.

0148(2) An electronic device, comprising:

0149a first substrate including a first basement and a first conductive layer;

0150a second substrate including a second basement and a second conductive layer; and

0151a connecting material electrically connects the first conductive layer and the second conductive layer,

0152wherein the second basement includes a first surface, a second surface opposite to the first surface, and a first hole penetrating the second basement,

0153the first surface is opposed to the first conductive layer and spaced apart from the first conductive layer,

0154the second surface is provided with the second conductive layer,

0155the second conductive layer includes a second hole penetrating the second conductive layer,

0156an edge of the second hole is located outside an edge of the first hole in a radial direction of the first hole, and

0157the connecting material contacts the first conductive layer and the second conductive layer via the first hole.

0158(3) The electronic device of item (1) or (2), wherein central axes of the first hole and the second hole coincide with each other.

0159(4) The electronic device of item (1), wherein

0160the second substrate further includes a protective film covering the second conductive layer,

0161the protective film includes a third hole,

0162the third hole penetrates the protective film and exposes the first flat portion and the second conductive layer around the first hole, and

0163the second surface includes a second flat portion exposed from the second conductive layer,

0164the second flat portion is located between an edge of the third hole and the second conductive layer, and is exposed from the protective film.

0165(5) The electronic device of item (4), wherein

0166the third hole includes a first portion and a second portion,

0167the first portion exposes the first flat portion from the protective film around the first hole,

0168the second portion partially exposes the second conductive layer from the protective film around the first portion.

0169(6) The electronic device of item (5), wherein

0170the third hole includes a plurality of second portions having a diameter smaller than that of the first portion.

0171(7) The electronic device of item (5), wherein in the first portion, central axes of the first hole and the second hole coincide with each other.

0172(8) The electronic device of any one of items (1) to (7), wherein

0173the second conductive layer includes:

0174a detector configured to be disposed in a first area and detect an object contacting or approaching the first area; and

0175a terminal configured to be disposed in a second area adjacent to the first area and connected to the detector, and

0176the first hole is formed in the terminal.

0177(9) A method of manufacturing an electronic device, comprising:

0178preparing a display panel, the display panel including a first basement

0179a first conductive layer over the first basement, and

0180a second basement comprising a first surface opposing the first conductive layer and a second surface opposite to the first surface,

0181wherein the first and second basements are adhered to each other, conductive layer over the second surface, which covers the second surface, and

0182a first flat portion which expose the second surface via the second conductive layer;

0183forming a first hole penetrating from the second surface to the first surface in the first flat portion; and

0184forming a connecting material in the first hole to electrically connect the first conductive layer and the second conductive layer to each other.

0185(10) The method of (9) further comprising:

0186forming a protective film to cover the second surface on which the second conductive layer and the first flat portion are already formed, prior to the forming of the first hole;

0187forming a third hole in the protective film to partially expose the first flap portion and the second conductive layer; and

0188irradiating second laser light to the first flat portion via the third hole, thereby forming the first hole.

0189(11) The method of (10), further comprising:

0190irradiating first laser light to the protective film, thereby forming the third hole.