Method for forming semiconductor device structure

BACKGROUND

0001The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

0002In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.

0003However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

0004Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0005<figref idref="DRAWINGS">FIGS. 1A-1F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

0006<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments.

0007<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments.

0008<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a variation of the stages of <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, in accordance with some embodiments.

0009<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments.

0010<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1C</figref>, in accordance with some embodiments.

0011<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of a variation of the stages of <figref idref="DRAWINGS">FIGS. 1E and 1F</figref>, in accordance with some embodiments.

0012<figref idref="DRAWINGS">FIGS. 8A-8F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

0013<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 8B</figref>, in accordance with some embodiments.

0014<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 8B</figref>, in accordance with some embodiments.

0015<figref idref="DRAWINGS">FIGS. 11A-11F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

0016<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 11B</figref>, in accordance with some embodiments.

0017<figref idref="DRAWINGS">FIG. 13</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 11B</figref>, in accordance with some embodiments.

0018<figref idref="DRAWINGS">FIGS. 14A-14Q</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

DETAILED DESCRIPTION

0019The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

0020Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

0021<figref idref="DRAWINGS">FIGS. 1A-1F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure <b>100</b>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments.

0022<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a variation of the stages of <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1B</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 1C</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of a variation of the stages of <figref idref="DRAWINGS">FIGS. 1E and 1F</figref>, in accordance with some embodiments.

0023As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, a semiconductor substrate <b>110</b> is provided. The semiconductor substrate <b>110</b> includes a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the semiconductor substrate <b>110</b> is made of an elementary semiconductor material including silicon or germanium in a single crystal, polycrystal, or amorphous structure.

0024In some other embodiments, the semiconductor substrate <b>110</b> is made of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe, or GaAsP, or a combination thereof. In some embodiments, the semiconductor substrate <b>110</b> includes multi-layer semiconductors, semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

0025As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, a first process <b>120</b> is performed over a top surface <b>112</b> of the semiconductor substrate <b>110</b>, in accordance with some embodiments. The first process <b>120</b> includes an etching process, a deposition process, a cleaning process, an implantation process, an oxidation process, a surface treatment process, or another suitable process.

0026The first process <b>120</b> may form a feature structure over (or in) the semiconductor substrate <b>110</b>. The feature structure includes an element over the semiconductor substrate <b>110</b>, a recess, a doped region in the semiconductor substrate <b>110</b>, or another suitable structure. For the sake of simplicity, the feature structure is not shown in <figref idref="DRAWINGS">FIG. 1A</figref>, and detailed description of exemplary embodiments relating to the feature structure is described below.

0027As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, after the first process <b>120</b>, a protective layer <b>130</b> is formed over the top surface <b>112</b> of the semiconductor substrate <b>110</b> in a first chamber <b>140</b>, in accordance with some embodiments. The protective layer <b>130</b> is configured to protect the top surface <b>112</b> of the semiconductor substrate <b>110</b> from being contaminated during a subsequent queue time, in accordance with some embodiments. In some embodiments, the protective layer <b>130</b> is configured to remove outgassing from the semiconductor substrate <b>110</b> during the subsequent queue time.

0028The protective layer <b>130</b> covers the substantially entire top surface <b>112</b>, in accordance with some embodiments. In another embodiment, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, the protective layer <b>130</b> covers only a portion of the top surface <b>112</b>, in accordance with some embodiments. In still another embodiment, as shown in <figref idref="DRAWINGS">FIG. 3</figref>, the protective layer <b>130</b> covers the top surface <b>112</b>, sidewalls <b>114</b> and <b>116</b>, and a bottom surface <b>118</b> of the semiconductor substrate <b>110</b>, in accordance with some embodiments.

0029The protective layer <b>130</b> includes an insulating material, in accordance with some embodiments. The protective layer <b>130</b> includes an organic material, a sulfide material, a porous material, an oxide material, or a nitride material, in accordance with some embodiments. The organic material includes hexamethyldisilazane (HMDS), a polymer material (e.g., a photoresist material), or another suitable organic material. The sulfide material includes hydrogen sulfide (H₂S), in accordance with some embodiments. The porous material includes a carbon material (e.g., activated carbon), in accordance with some embodiments. The protective layer <b>130</b> formed of the porous material serves as a getter layer to remove outgassing from the semiconductor substrate <b>110</b>, in accordance with some embodiments.

0030The protective layer <b>130</b> is formed using a coating process (e.g., a spin coating process), a deposition process (e.g., a chemical vapor deposition process or a physical vapor deposition process), an oxidation process, a dipping process, or another suitable process. The protective layer <b>130</b> is conformally formed over the top surface <b>112</b>, in accordance with some embodiments.

0031In some embodiments, the protective layer <b>130</b> is a planar layer. In some embodiments, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, the first process <b>120</b> is also performed in the first chamber <b>140</b>. For example, the first process <b>120</b> includes a deposition process, and the first chamber <b>140</b> is a deposition chamber.

0032In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the protective layer <b>130</b> has a first film <b>132</b> and a second film <b>134</b>. The first film <b>132</b> is between the second film <b>134</b> and the semiconductor substrate <b>110</b>, in accordance with some embodiments. The materials of the first film <b>132</b> and the second film <b>134</b> are different, in accordance with some embodiments.

0033The first film <b>132</b> includes a porous material (e.g., a carbon material) to remove outgassing from the semiconductor substrate <b>110</b>, in accordance with some embodiments. The second film <b>134</b> includes an organic material, a sulfide material, an oxide material, or a nitride material, in accordance with some embodiments.

0034As shown in <figref idref="DRAWINGS">FIG. 1C</figref>, a first transferring process is performed to transfer the semiconductor substrate <b>110</b> and the protective layer <b>130</b> from the first chamber <b>140</b> into a substrate carrier <b>150</b>, in accordance with some embodiments. The substrate carrier <b>150</b> includes a wafer carrier, in accordance with some embodiments. The substrate carrier <b>150</b> includes a front opening unified pod (FOUP), in accordance with some embodiments. In some embodiments, nitrogen or inert gas (e.g., argon or helium) is filled in the substrate carrier <b>150</b>.

0035As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the substrate carrier <b>150</b> may contain many substrates <b>110</b>. For the sake of simplicity, <figref idref="DRAWINGS">FIG. 1C</figref> shows only one semiconductor substrate <b>110</b>. Thereafter, the semiconductor substrate <b>110</b> and the protective layer <b>130</b> are kept in the substrate carrier <b>150</b> for a queue time to wait until a chamber (or a tool) for performing the next process is available, in accordance with some embodiments.

0036As shown in <figref idref="DRAWINGS">FIG. 1D</figref>, after the queue time, a second transferring process is performed to transfer the semiconductor substrate <b>110</b> and the protective layer <b>130</b> from the substrate carrier <b>150</b> into a second chamber <b>160</b>, in accordance with some embodiments. The semiconductor substrate <b>110</b> and the protective layer <b>130</b> are located in the substrate carrier <b>150</b> during a substantially entire first time interval between the first transferring process and the second transferring process, in accordance with some embodiments.

0037That is, in the substantially entire first time interval, the semiconductor substrate <b>110</b> and the protective layer <b>130</b> are kept in the substrate carrier <b>150</b>, and there is no treatment process performed over the semiconductor substrate <b>110</b> and the protective layer <b>130</b>, in accordance with some embodiments.

0038As shown in <figref idref="DRAWINGS">FIG. 1E</figref>, the substantially entire protective layer <b>130</b> is removed in the second chamber <b>160</b>, in accordance with some embodiments. A negligible portion of the protective layer <b>130</b> may be left after the removal process. The removal process includes a dry etching process, a wet etching process, a chemical mechanical polishing process, a cleaning process, or another suitable process.

0039The dry etching process includes an ashing process (e.g., an oxygen plasma ashing process), in accordance with some embodiments. The cleaning process uses a cleaning solution including an ozone in deionized water (O₃/DI) cleaning solution or a SPM cleaning solution, in accordance with some embodiments. The SPM cleaning solution includes a mixture of sulfuric acid, a hydrogen peroxide solution, and pure water, in accordance with some embodiments.

0040The protective layer <b>130</b> is an outermost layer of the semiconductor device structure <b>100</b> during a substantially entire second time interval between the formation of the protective layer <b>130</b> and the removal of the protective layer <b>130</b>, in accordance with some embodiments. That is, there is no layer or element formed over the protective layer <b>130</b> during the substantially entire second time interval, in accordance with some embodiments.

0041Since the protective layer <b>130</b> is removed, the contamination formed over the protective layer <b>130</b> during the queue time is removed as well. Therefore, the top surface <b>112</b> is kept clean after the queue time. As a result, the acceptable queue time is prolonged, which eases queue time constraints. Therefore, the second process is more manufacturable and the yield of the second process is improved.

0042In some embodiments, the first chamber <b>140</b> and the second chamber <b>160</b> are the same chamber. For example, the first chamber <b>140</b> (or the second chamber <b>160</b>) is a plasma chamber for performing a plasma deposition process and a plasma etching process.

0043As shown in <figref idref="DRAWINGS">FIG. 1F</figref>, after the removal of the protective layer <b>130</b>, a second process <b>170</b> is performed over the top surface <b>112</b> of the semiconductor substrate <b>110</b>, in accordance with some embodiments. The second process <b>170</b> includes a cleaning process, an etching process, a deposition process, an implantation process, an oxidation process, a surface treatment process, or another suitable process.

0044In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the second process <b>170</b> is performed in the second chamber <b>160</b>, and the second process <b>170</b> includes a cleaning process, an etching process, a chemical mechanical polishing process, a plasma process, or another suitable process. In some embodiments, the removal of the protective layer <b>130</b> and the second process are the same process (e.g., a cleaning process, an etching process, or a chemical mechanical polishing process).

0045<figref idref="DRAWINGS">FIGS. 8A-8F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure <b>800</b>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 8B</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 8B</figref>, in accordance with some embodiments.

0046It should be noted that the embodiment of <figref idref="DRAWINGS">FIGS. 8A-8F</figref> is a detailed embodiment of <figref idref="DRAWINGS">FIGS. 1A-1F</figref>, and <figref idref="DRAWINGS">FIGS. 8A-8F</figref> show a feature structure formed over the semiconductor substrate <b>110</b>. As shown in <figref idref="DRAWINGS">FIG. 8A</figref>, the first process <b>120</b> is performed over the top surface <b>112</b> of the semiconductor substrate <b>110</b> to form a feature structure <b>810</b>, in accordance with some embodiments. The feature structure <b>810</b> includes an element <b>812</b>, in accordance with some embodiments.

0047The element <b>812</b> includes a gate, a capacitor, a film, an active element, a passive element, an optical element, or another element suitable for being formed over the semiconductor substrate <b>110</b>. The element <b>812</b> includes a conductive structure or a semiconductor structure, in accordance with some embodiments. The first process <b>120</b> includes a deposition process (and an etching process) or another suitable process, in accordance with some embodiments.

0048As shown in <figref idref="DRAWINGS">FIG. 8B</figref>, after the first process <b>120</b>, the protective layer <b>130</b> is formed over the feature structure <b>810</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b> in the first chamber <b>140</b>, in accordance with some embodiments. In some embodiments, the protective layer <b>130</b> covers a top surface <b>812</b><i>a </i>and sidewalls <b>812</b><i>b </i>and <b>812</b><i>c </i>of the element <b>812</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b>.

0049The protective layer <b>130</b> is configured to protect the top surface <b>112</b> of the semiconductor substrate <b>110</b> and the feature structure <b>810</b> from being contaminated during a subsequent queue time, in accordance with some embodiments. In some embodiments, the protective layer <b>130</b> is configured to remove outgassing from the semiconductor substrate <b>110</b> and the feature structure <b>810</b> during the subsequent queue time.

0050In some embodiments, the protective layer <b>130</b> covers the substantially entire top surface <b>812</b><i>a </i>and the substantially entire sidewalls <b>812</b><i>b </i>and <b>812</b><i>c </i>of the element <b>812</b> and the substantially entire top surface <b>112</b>. In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, the protective layer <b>130</b> covers the element <b>812</b> (e.g., a conductive structure or a semiconductor structure) and a portion of the top surface <b>112</b>.

0051That is, the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 9</figref> exposes another portion of the top surface <b>112</b>. The exposed top surface <b>112</b> may be a passive surface formed by a passive material (e.g., an oxide material, a nitride material, or a dielectric material), which prevents the exposed top surface <b>112</b> from being undesirably affected during the subsequent queue time.

0052The formation of the protective layer <b>130</b> includes an oxidation process, a selective deposition process (e.g., a selective chemical vapor deposition process), a photolithography process, a printing process, or another suitable process. In some embodiments, the protective layer <b>130</b> is formed using the oxidation process, and the protective layer <b>130</b> includes metal oxide or semiconductor oxide.

0053As shown in <figref idref="DRAWINGS">FIG. 8B</figref>, the protective layer <b>130</b> conformally covers the top surface <b>812</b><i>a </i>and the sidewalls <b>812</b><i>b </i>and <b>812</b><i>c </i>of the element <b>812</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b>, in accordance with some embodiments. In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 10</figref>, the protective layer <b>130</b> is a planar layer.

0054In some embodiments, materials of the element <b>812</b> and the protective layer <b>130</b> are different, which raises the etching selectivity of the protective layer <b>130</b> to the element <b>812</b>. In some embodiments, the material of the protective layer <b>130</b> is different from the materials of the element <b>812</b> and the semiconductor substrate <b>110</b>, which raises the etching selectivity of the protective layer <b>130</b> to the element <b>812</b> and the semiconductor substrate <b>110</b>.

0055As shown in <figref idref="DRAWINGS">FIG. 8C</figref>, the first transferring process is performed to transfer the semiconductor substrate <b>110</b>, the protective layer <b>130</b>, and the feature structure <b>810</b> from the first chamber <b>140</b> into the substrate carrier <b>150</b>, in accordance with some embodiments. Thereafter, the semiconductor substrate <b>110</b>, the protective layer <b>130</b>, and the feature structure <b>810</b> are kept in the substrate carrier <b>150</b> for a queue time to wait until a chamber (or a tool) for performing the next process is available, in accordance with some embodiments.

0056As shown in <figref idref="DRAWINGS">FIG. 8D</figref>, after the queue time, the second transferring process is performed to transfer the semiconductor substrate <b>110</b>, the protective layer <b>130</b>, and the feature structure <b>810</b> from the substrate carrier <b>150</b> into the second chamber <b>160</b>, in accordance with some embodiments. The semiconductor substrate <b>110</b>, the protective layer <b>130</b>, and the feature structure <b>810</b> are kept in the substrate carrier <b>150</b> during the substantially entire first time interval between the first transferring process and the second transferring process, in accordance with some embodiments.

0057As shown in <figref idref="DRAWINGS">FIG. 8E</figref>, the substantially entire protective layer <b>130</b> is removed in the second chamber <b>160</b>, in accordance with some embodiments. A negligible portion of the protective layer <b>130</b> may be left after the removal process. As shown in <figref idref="DRAWINGS">FIG. 8F</figref>, after the removal of the protective layer <b>130</b>, the second process <b>170</b> is performed over the top surface <b>112</b> of the semiconductor substrate <b>110</b> and/or the feature structure <b>810</b>, in accordance with some embodiments.

0058The protective layer <b>130</b> is an outermost layer of the semiconductor device structure <b>800</b> during the substantially entire second time interval between the formation of the protective layer <b>130</b> and the removal of the protective layer <b>130</b>, in accordance with some embodiments. That is, there is no layer or element formed over the protective layer <b>130</b> during the substantially entire second time interval, in accordance with some embodiments.

0059Since the protective layer <b>130</b> is removed, the contamination formed over the protective layer <b>130</b> during the queue time is removed as well. Therefore, the top surface <b>112</b> and the feature structure <b>810</b> are kept clean after the queue time. As a result, the acceptable queue time is prolonged, which makes the second process more manufacturable and improves the yield of the second process and the performance of the semiconductor device structure <b>800</b>.

0060<figref idref="DRAWINGS">FIGS. 11A-11F</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure <b>1100</b>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 11B</figref>, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 13</figref> is a cross-sectional view of a variation of the stage of <figref idref="DRAWINGS">FIG. 11B</figref>, in accordance with some embodiments.

0061It should be noted that the embodiment of <figref idref="DRAWINGS">FIGS. 11A-11F</figref> is a detailed embodiment of <figref idref="DRAWINGS">FIGS. 1A-1F</figref>, and <figref idref="DRAWINGS">FIGS. 11A-11F</figref> show a feature structure formed in the semiconductor substrate <b>110</b>. As shown in <figref idref="DRAWINGS">FIG. 11A</figref>, the first process <b>120</b> is performed over the top surface <b>112</b> of the semiconductor substrate <b>110</b> to form a feature structure <b>1110</b>, in accordance with some embodiments. The feature structure <b>1110</b> includes a recess <b>114</b>, in accordance with some embodiments. The first process <b>120</b> includes a photolithography process and an etching process or another suitable process.

0062As shown in <figref idref="DRAWINGS">FIG. 11B</figref>, after the first process <b>120</b>, the protective layer <b>130</b> is formed over the feature structure <b>1110</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b> in the first chamber <b>140</b>, in accordance with some embodiments. In some embodiments, the protective layer <b>130</b> covers a bottom surface <b>114</b><i>a </i>and inner walls <b>114</b><i>b </i>and <b>114</b><i>c </i>of the recess <b>114</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b>.

0063The protective layer <b>130</b> is configured to protect the top surface <b>112</b> of the semiconductor substrate <b>110</b> and the recess <b>114</b> from being contaminated during a subsequent queue time, in accordance with some embodiments. In some embodiments, the protective layer <b>130</b> is configured to remove outgassing from the semiconductor substrate <b>110</b> during the subsequent queue time.

0064In some embodiments, the protective layer <b>130</b> covers the substantially entire bottom surface <b>114</b><i>a </i>and the substantially entire inner walls <b>114</b><i>b </i>and <b>114</b><i>c </i>of the recess <b>114</b> and the substantially entire top surface <b>112</b>. In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 12</figref>, the protective layer <b>130</b> covers the recess <b>114</b> and a portion of the top surface <b>112</b>. That is, the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 12</figref> exposes another portion of the top surface <b>112</b>.

0065The exposed top surface <b>112</b> may be a passive surface formed by a passive material (e.g., an oxide material, a nitride material, or a dielectric material), which prevents the exposed top surface <b>112</b> from being oxidized during the subsequent queue time. The formation of the protective layer <b>130</b> includes an oxidation process, a selective deposition process (e.g., a selective chemical vapor deposition process), a photolithography process, a printing process, or another suitable process.

0066As shown in <figref idref="DRAWINGS">FIG. 11B</figref>, the protective layer <b>130</b> conformally covers the bottom surface <b>114</b><i>a </i>and the inner walls <b>114</b><i>b </i>and <b>114</b><i>c </i>of the recess <b>114</b> and the top surface <b>112</b> of the semiconductor substrate <b>110</b>, in accordance with some embodiments. In some other embodiments, as shown in <figref idref="DRAWINGS">FIG. 13</figref>, the protective layer <b>130</b> is a planar layer.

0067As shown in <figref idref="DRAWINGS">FIG. 11C</figref>, the first transferring process is performed to transfer the semiconductor substrate <b>110</b> and the protective layer <b>130</b> from the first chamber <b>140</b> into the substrate carrier <b>150</b>, in accordance with some embodiments. Thereafter, the semiconductor substrate <b>110</b> and the protective layer <b>130</b> are kept in the substrate carrier <b>150</b> for a queue time to wait until a chamber (or a tool) for performing the next process is available, in accordance with some embodiments.

0068As shown in <figref idref="DRAWINGS">FIG. 11D</figref>, after the queue time, the second transferring process is performed to transfer the semiconductor substrate <b>110</b> and the protective layer <b>130</b> from the substrate carrier <b>150</b> into the second chamber <b>160</b>, in accordance with some embodiments. The semiconductor substrate <b>110</b> and the protective layer <b>130</b> are kept in the substrate carrier <b>150</b> during the substantially entire first time interval between the first transferring process and the second transferring process, in accordance with some embodiments.

0069As shown in <figref idref="DRAWINGS">FIG. 11E</figref>, the substantially entire protective layer <b>130</b> is removed in the second chamber <b>160</b>, in accordance with some embodiments. A negligible portion of the protective layer <b>130</b> may be left after the removal process. As shown in <figref idref="DRAWINGS">FIG. 11F</figref>, after the removal of the protective layer <b>130</b>, the second process <b>170</b> is performed over the top surface <b>112</b> of the semiconductor substrate <b>110</b> and/or the feature structure <b>1110</b>, in accordance with some embodiments.

0070The protective layer <b>130</b> is an outermost layer of the semiconductor device structure <b>1100</b> during the substantially entire second time interval between the formation of the protective layer <b>130</b> and the removal of the protective layer <b>130</b>, in accordance with some embodiments. That is, there is no layer or element formed over the protective layer <b>130</b> during the substantially entire second time interval, in accordance with some embodiments.

0071Since the protective layer <b>130</b> is removed, the contamination formed over the protective layer <b>130</b> during the queue time is removed as well. Therefore, the top surface <b>112</b> and the feature structure <b>1110</b> are kept clean after the queue time. As a result, the acceptable queue time is prolonged, which makes the second process more manufacturable and improves the yield of the second process and the performance of the semiconductor device structure <b>1100</b>.

0072<figref idref="DRAWINGS">FIGS. 14A-14Q</figref> are cross-sectional views of various stages of a process for forming a semiconductor device structure <b>1400</b>, in accordance with some embodiments. The embodiment of <figref idref="DRAWINGS">FIGS. 14A-14Q</figref> is an exemplary embodiment applying the protective layer mentioned above in a process for forming a transistor.

0073As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, a semiconductor substrate <b>1410</b> is provided. The semiconductor substrate <b>1410</b> is the same as or similar to the semiconductor substrate <b>110</b>. As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, an isolation structure <b>1420</b> is formed in the semiconductor substrate <b>1410</b>, in accordance with some embodiments. The isolation structure <b>1420</b> is configured to define and electrically isolate various device elements (not shown) formed in the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0074Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, another suitable element, or a combination thereof. Various processes are performed to form the various device elements, such as deposition, etching, implantation, photolithography, annealing, planarization, another applicable process, or a combination thereof.

0075The isolation structure <b>1420</b> is made of a dielectric material, in accordance with some embodiments. The dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, other suitable materials, or combinations thereof, in accordance with some embodiments. The isolation structure <b>1420</b> is formed by using an isolation technology, such as local oxidation of semiconductor (LOCOS), shallow trench isolation (STI), or the like, in accordance with some embodiments.

0076In some embodiments, the formation of the isolation structure <b>1420</b> includes patterning the semiconductor substrate <b>1410</b> by performing a photolithography process and an etching process to the semiconductor substrate <b>1410</b> so as to form a trench in the semiconductor substrate <b>1410</b>; and filling the trench with the dielectric material.

0077The etching process for forming the trench includes a dry etching process, a wet etching process, a plasma etching process, or a combination thereof, in accordance with some embodiments. The filling of the trench includes a chemical vapor deposition process, in accordance with some embodiments. In some embodiments, the filled trench has a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

0078As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, a gate dielectric material layer <b>1430</b><i>a </i>is deposited over the semiconductor substrate <b>1410</b>, in accordance with some embodiments. The gate dielectric material layer <b>1430</b><i>a </i>is made of silicon oxide, in accordance with some embodiments. The gate dielectric material layer <b>1430</b><i>a </i>is deposited using a chemical vapor deposition process (CVD process), in accordance with some embodiments.

0079As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, a dummy gate material layer <b>1440</b><i>a </i>is deposited over the gate dielectric material layer <b>1430</b><i>a</i>, in accordance with some embodiments. The dummy gate material layer <b>1440</b><i>a </i>is made of polysilicon, in accordance with some embodiments. The dummy gate material layer <b>1440</b><i>a </i>is deposited using a chemical vapor deposition process, in accordance with some embodiments.

0080As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, a mask layer <b>1450</b> is formed over the dummy gate material layer <b>1440</b><i>a</i>, in accordance with some embodiments. The mask layer <b>1450</b> exposes a portion of the dummy gate material layer <b>1440</b><i>a</i>, in accordance with some embodiments. In some embodiments, the mask layer <b>1450</b> includes oxide or nitride, such as silicon oxide, silicon oxynitride, silicon nitride, or the like. The mask layer <b>1450</b> is formed by a depositing process (such as a chemical vapor deposition process), a photolithography process, and an etching process, in accordance with some embodiments.

0081As shown in <figref idref="DRAWINGS">FIG. 14B</figref>, the dummy gate material layer <b>1440</b><i>a </i>exposed by the mask layer <b>1450</b> is removed, and the gate dielectric material layer <b>1430</b><i>a </i>under the removed dummy gate material layer <b>1440</b><i>a </i>is also removed, in accordance with some embodiments. The dummy gate material layer <b>1440</b><i>a </i>remaining under the mask layer <b>1450</b> forms a dummy gate <b>1440</b>, in accordance with some embodiments. The gate dielectric material layer <b>1430</b><i>a </i>remaining under the dummy gate <b>1440</b> forms a gate dielectric layer <b>1430</b>, in accordance with some embodiments. The removal process includes a dry etching process, in accordance with some embodiments.

0082After the removal process, the next stage is a cleaning process to remove the residues formed from the removal process of <figref idref="DRAWINGS">FIG. 14B</figref>. However, before the cleaning process, the semiconductor substrate <b>1410</b> needs to be kept in the substrate carrier <b>150</b> (as shown in <figref idref="DRAWINGS">FIG. 1C</figref>) for a queue time to wait until a cleaning chamber (or a cleaning tool) is available, in accordance with some embodiments.

0083For preventing the contamination of the semiconductor substrate <b>1410</b> during the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are performed to form a protective layer P<b>1</b> covering the semiconductor substrate <b>1410</b>, the mask layer <b>1450</b>, the dummy gate <b>1440</b>, and the gate dielectric layer <b>1430</b>, in accordance with some embodiments.

0084The materials and the formation methods of the protective layer P<b>1</b> and the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 1B</figref> are the same, in accordance with some embodiments. For the sake of simplicity, <figref idref="DRAWINGS">FIG. 14B</figref> does not show the first chamber <b>140</b> of <figref idref="DRAWINGS">FIG. 1B</figref> and the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref>.

0085As shown in <figref idref="DRAWINGS">FIG. 14C</figref>, after keeping the semiconductor substrate <b>1410</b> in the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref> for the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1D to 1F</figref> are performed to remove the protective layers P<b>1</b> and perform a cleaning process (i.e., the second process <b>170</b> of <figref idref="DRAWINGS">FIG. 1F</figref>) over the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0086As shown in <figref idref="DRAWINGS">FIG. 14C</figref>, a liner layer <b>1460</b> is formed over the semiconductor substrate <b>1410</b> to cover the mask layer <b>1450</b>, the dummy gate <b>1440</b>, and the gate dielectric layer <b>1430</b>, in accordance with some embodiments. The liner layer <b>1460</b> is configured to protect spacers formed subsequently from damage during a dummy-gate removal process, in accordance with some embodiments. The liner layer <b>1460</b> includes oxide, in accordance with some embodiments.

0087The liner layer <b>1460</b> is formed by an atomic layer deposition (ALD) process, a chemical vapor deposition process, or a physical vapor deposition (PVD) process, in accordance with some embodiments. The liner layer <b>1460</b> conformally covers the mask layer <b>1450</b>, the dummy gate <b>1440</b>, and the gate dielectric layer <b>1430</b>, in accordance with some embodiments.

0088As shown in <figref idref="DRAWINGS">FIG. 14D</figref>, a spacer layer <b>1480</b><i>a </i>is formed over the liner layer <b>1460</b> to cover the mask layer <b>1450</b>, the dummy gate <b>1440</b>, and the gate dielectric layer <b>1430</b>, in accordance with some embodiments. The spacer layer <b>1480</b><i>a </i>includes an insulating material, such as silicon oxide or silicon nitride. The spacer layer <b>1480</b><i>a </i>is formed using a chemical vapor deposition process, in accordance with some embodiments.

0089As shown in <figref idref="DRAWINGS">FIGS. 14D and 14E</figref>, an anisotropic etching process is performed to remove a portion of the spacer layer <b>1480</b><i>a</i>, in accordance with some embodiments. The spacer layer <b>1480</b><i>a </i>remaining over the sidewalls of the mask layer <b>1450</b>, the dummy gate <b>1440</b>, and the gate dielectric layer <b>1430</b> forms spacers <b>1480</b>, in accordance with some embodiments.

0090The spacers <b>1480</b> are configured to electrically isolate a gate formed subsequently from other devices and configured to act as a mask layer in a subsequent ion implantation process, in accordance with some embodiments. The anisotropic etching process includes a dry etching process, in accordance with some embodiments.

0091As shown in <figref idref="DRAWINGS">FIG. 14E</figref>, the stages of <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are performed to form a protective layer P<b>2</b> covering the semiconductor substrate <b>1410</b>, the mask layer <b>1450</b>, the dummy gate <b>1440</b>, the gate dielectric layer <b>1430</b>, the liner layer <b>1460</b>, and the spacers <b>1480</b>, in accordance with some embodiments. The materials and the formation methods of the protective layer P<b>2</b> and the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 1B</figref> are the same, in accordance with some embodiments.

0092As shown in <figref idref="DRAWINGS">FIG. 14F</figref>, after keeping the semiconductor substrate <b>1410</b> in the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref> for the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1D to 1F</figref> are performed to remove the protective layers P<b>2</b> and perform a cleaning process over the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0093As shown in <figref idref="DRAWINGS">FIG. 14F</figref>, heavily doped regions <b>1412</b> are formed in the semiconductor substrate <b>1410</b>, in accordance with some embodiments. The heavily doped regions <b>1412</b> are formed using an ion implantation process, in accordance with some embodiments. The ion implantation process is performed to introduce p-type impurities (e.g., boron) or n-type impurities (e.g., phosphorus) into the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0094The heavily doped regions <b>1412</b> are a heavily doped source region and a heavily doped drain region, in accordance with some embodiments. The heavily doped regions <b>1412</b> are located at the two opposite sides of the dummy gate <b>1440</b>, in accordance with some embodiments.

0095As shown in <figref idref="DRAWINGS">FIG. 14F</figref>, stressors <b>1490</b> are formed in the heavily doped regions <b>1412</b> by using suitable processes, in accordance with some embodiments. The suitable processes include, for example, an etching process for removing a portion of the semiconductor substrate <b>1410</b> and a selective epitaxial growth (SEG) process. Depending on the desired type of the resulting MOS device, either stressors applying a compressive stress to the channel region (such as SiGe stressors) or stressors applying a tensile stress to the channel region (such as SiC stressors) are formed.

0096As shown in <figref idref="DRAWINGS">FIG. 14G</figref>, a mask layer <b>210</b> is formed over the spacers <b>1480</b> and the semiconductor substrate <b>1410</b>, in accordance with some embodiments. The mask layer <b>210</b> is a photoresist layer, in accordance with some embodiments. The mask layer <b>210</b> has an opening <b>212</b> exposing the liner layer <b>1460</b> over the mask layer <b>1450</b>, in accordance with some embodiments.

0097As shown in <figref idref="DRAWINGS">FIG. 14H</figref>, the mask layer <b>1450</b> and the liner layer <b>1460</b> over the mask layer <b>1450</b> are removed through the opening <b>212</b>, in accordance with some embodiments. The removal process includes a dry etching process, in accordance with some embodiments. Thereafter, the mask layer <b>210</b> is removed.

0098As shown in <figref idref="DRAWINGS">FIG. 14I</figref>, spacer oxide layers <b>220</b> may be formed over the spacers <b>1480</b> and the stressors <b>1490</b> by using, for example, a chemical vapor deposition process. The spacer oxide layers <b>220</b> may fill the gaps between the spacers <b>1480</b> and the stressors <b>1490</b> to facilitate films, which are subsequently formed, to cover the spacers <b>1480</b> and the stressors <b>1490</b> smoothly. However, in some other embodiments, the spacer oxide layers <b>220</b> are not formed.

0099As shown in <figref idref="DRAWINGS">FIG. 14I</figref>, a contact etch stop layer <b>230</b> is formed over the semiconductor substrate <b>1410</b> to cover the stressors <b>1490</b>, in accordance with some embodiments. The contact etch stop layer <b>230</b> includes a dielectric material, in accordance with some embodiments.

0100The contact etch stop layer <b>230</b> includes silicon nitride, in accordance with some embodiments. The contact etch stop layer <b>230</b> is formed over the stressors <b>1490</b>, the spacers <b>1480</b>, the dummy gate <b>1440</b>, and the semiconductor substrate <b>1410</b>, in accordance with some embodiments. In some other embodiments, the contact etch stop layer <b>230</b> is not formed.

0101As shown in <figref idref="DRAWINGS">FIG. 14I</figref>, an insulating layer <b>240</b> is deposited over the contact etch stop layer <b>230</b>, in accordance with some embodiments. The insulating layer <b>240</b> includes silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, or combinations thereof, in accordance with some embodiments. The insulating layer <b>240</b> is deposited using a CVD process, a HDPCVD process, a spin-on process, a sputtering process, or a combination thereof, in accordance with some embodiments.

0102Afterwards, as shown in <figref idref="DRAWINGS">FIG. 14J</figref>, a planarization process is performed on the insulating layer <b>240</b> until a top surface of the dummy gate <b>1440</b> is exposed, in accordance with some embodiments. The planarization process includes a chemical mechanical polishing (CMP) process, in accordance with some embodiments. After the planarization process is performed, the insulating layer <b>240</b> has a substantially planar surface to facilitate subsequent process steps.

0103As shown in <figref idref="DRAWINGS">FIG. 14K</figref>, the dummy gate <b>1440</b> is removed, in accordance with some embodiments. The removal process for removing the dummy gate <b>1440</b> includes a wet etching process, a dry etching process, or a combination thereof, in accordance with some embodiments. In some embodiments, the gate dielectric layer <b>1430</b> is also removed. After the dummy gate <b>1440</b> and the gate dielectric layer <b>1430</b> are removed, an opening <b>1482</b> is formed between the spacers <b>1480</b>. The opening <b>1482</b> is a trench, in accordance with some embodiments.

0104As shown in <figref idref="DRAWINGS">FIG. 14K</figref>, the stages of <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are performed to form a protective layer P<b>3</b> covering the opening <b>1482</b>, the semiconductor substrate <b>1410</b>, the contact etch stop layer <b>230</b>, the insulating layer <b>240</b>, the liner layer <b>1460</b>, and the spacers <b>1480</b>, in accordance with some embodiments. The materials and the formation methods of the protective layer P<b>3</b> and the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 1B</figref> are the same, in accordance with some embodiments.

0105As shown in <figref idref="DRAWINGS">FIG. 14L</figref>, after keeping the semiconductor substrate <b>1410</b> in the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref> for the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1D to 1F</figref> are performed to remove the protective layers P<b>3</b> and perform a cleaning process over the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0106As shown in <figref idref="DRAWINGS">FIG. 14L</figref>, a gate dielectric layer <b>250</b> is formed to cover a bottom of the opening <b>1482</b>, in accordance with some embodiments. The gate dielectric layer <b>250</b> further covers the inner walls of the opening <b>1482</b>, top surfaces of the liner layer <b>1460</b>, the spacers <b>1480</b>, the contact etch stop layer <b>230</b>, and the insulating layer <b>240</b>, in accordance with some embodiments.

0107The gate dielectric layer <b>250</b> includes a dielectric material, such as a high dielectric constant (high-k) material. The high-k material includes hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high-k dielectric materials, or combinations thereof.

0108The high-k material is made of metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, other suitable materials, or combinations thereof, in accordance with some embodiments.

0109The gate dielectric layer <b>250</b> is deposited by any suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, other suitable processes, or combinations thereof, in accordance with some embodiments. In some embodiments, the gate dielectric layer <b>250</b> needs to be further annealed.

0110An intermediate dielectric layer (not shown) may be formed over the semiconductor substrate <b>1410</b> before the gate dielectric layer <b>250</b> is formed. The intermediate dielectric layer includes a suitable dielectric material, such as silicon oxide, hafnium silicate, silicon oxynitride, or combinations thereof.

0111As shown in <figref idref="DRAWINGS">FIG. 14L</figref>, a work function metal layer <b>260</b> is deposited over the gate dielectric layer <b>250</b>, in accordance with some embodiments. The work function metal layer <b>260</b> provides a desired work function for transistors to enhance device performance including improved threshold voltage.

0112In the embodiments of forming an NMOS transistor, the work function metal layer <b>260</b> can be an n-type metal capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV. The n-type metal includes metal, metal carbide, metal nitride, or combinations thereof, in accordance with some embodiments. For example, the n-type metal is made of tantalum, tantalum nitride, or combinations thereof.

0113On the other hand, in the embodiments of forming a PMOS transistor, the work function metal layer <b>260</b> can be a p-type metal capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV. The p-type metal includes metal, metal carbide, metal nitride, other suitable materials, or combinations thereof, in accordance with some embodiments. For example, the p-type metal is made of titanium, titanium nitride, other suitable materials, or combinations thereof.

0114The work function metal layer <b>260</b> is made of hafnium, zirconium, titanium, tantalum, aluminum, metal carbide (e.g., hafnium carbide, or zirconium carbide), aluminide, ruthenium or combinations thereof, in accordance with some embodiments. The work function metal layer <b>260</b> is deposited using a PVD process, CVD process, ALD process, plating process, another suitable method, or combinations thereof, in accordance with some embodiments.

0115As shown in <figref idref="DRAWINGS">FIG. 14L</figref>, a gate electrode layer <b>270</b> (also called a metal gate electrode layer) is deposited over the work function metal layer <b>260</b> to fill the opening <b>1482</b>, in accordance with some embodiments. The gate electrode layer <b>270</b> includes a suitable metal material, such as aluminum, tungsten, gold, platinum, cobalt, another suitable metal, an alloy thereof, or combinations thereof, in accordance with some embodiments. The gate electrode layer <b>270</b> is deposited using a PVD process, a CVD process, a plating process, the like, or combinations thereof, in accordance with some embodiments.

0116Afterwards, as shown in <figref idref="DRAWINGS">FIG. 14M</figref>, a planarization process is performed to remove the gate electrode layer <b>270</b>, the work function metal layer <b>260</b>, and the gate dielectric layer <b>250</b> outside of the opening <b>1482</b>, in accordance with some embodiments. The planarization process includes a chemical mechanical polishing (CMP) process or the like, in accordance with some embodiments.

0117The gate electrode layer <b>270</b>, the work function metal layer <b>260</b>, and the gate dielectric layer <b>250</b> together form a gate stack G (i.e., a metal gate stack), which is surrounded by the insulating layer <b>240</b>. The gate electrode layer <b>270</b> remaining in the opening <b>1482</b> serves as a metal gate electrode of the gate stack G, in accordance with some embodiments.

0118As shown in <figref idref="DRAWINGS">FIG. 14M</figref>, the stages of <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are performed to form a protective layer P<b>4</b> covering the gate electrode layer <b>270</b>, the work function metal layer <b>260</b>, the gate dielectric layer <b>250</b>, the semiconductor substrate <b>1410</b>, the contact etch stop layer <b>230</b>, the insulating layer <b>240</b>, the liner layer <b>1460</b>, and the spacers <b>1480</b>, in accordance with some embodiments. The materials and the formation methods of the protective layer P<b>4</b> and the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 1B</figref> are the same, in accordance with some embodiments.

0119As shown in <figref idref="DRAWINGS">FIG. 14N</figref>, after keeping the semiconductor substrate <b>1410</b> in the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref> for the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1D to 1F</figref> are performed to remove the protective layers P<b>4</b> and perform a cleaning process over the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0120As shown in <figref idref="DRAWINGS">FIG. 14N</figref>, an etching stop layer <b>280</b> (also called an insulating layer or a dielectric layer) is deposited over the top surfaces of the insulating layer <b>240</b>, the contact etch stop layer <b>230</b>, the spacers <b>1480</b>, the liner layer <b>1460</b>, the work function metal layer <b>260</b>, and the gate electrode layer <b>270</b>, in accordance with some embodiments. The etching stop layer <b>280</b> is made of silicon nitride, in accordance with some embodiments.

0121As shown in <figref idref="DRAWINGS">FIG. 14N</figref>, a protective layer <b>290</b> is formed on the etching stop layer <b>280</b>, in accordance with some embodiments. The protective layer <b>290</b> is configured to protect the etching stop layer <b>280</b> from damage during a subsequent pre-amorphized implantation (PAI) process, in accordance with some embodiments. The protective layer <b>290</b> includes a plasma-enhanced oxide (PEOX) layer, in accordance with some embodiments.

0122As shown in <figref idref="DRAWINGS">FIG. 14O</figref>, portions of the protective layer <b>290</b>, the etching stop layer <b>280</b>, and the insulating layer <b>240</b> are removed to form contact openings <b>312</b> passing through the protective layer <b>290</b>, the etching stop layer <b>280</b>, and the insulating layer <b>240</b>, in accordance with some embodiments. The openings <b>312</b> expose the stressors <b>1490</b>, in accordance with some embodiments. The removal process includes performing a photolithography process and an etching process, in accordance with some embodiments.

0123As shown in <figref idref="DRAWINGS">FIG. 14O</figref>, a dielectric spacer liner (DSL) layer <b>314</b> is conformally formed on the protective layer <b>290</b> and the sidewalls <b>312</b><i>a </i>of the contact openings <b>312</b>, in accordance with some embodiments. The DSL layer <b>314</b> is configured to protect the sidewalls <b>312</b><i>a </i>from being damaged by the subsequent PAI process. The DSL layer <b>314</b> is made of, for example, SiOC or other suitable materials.

0124A pre-amorphized implantation (PAI) process is performed to reduce the dopant channeling effect and enhance dopant activation, in accordance with some embodiments. In some embodiments, silicon, germanium or carbon is used. In some other embodiments, inert gases, such as neon, argon, krypton, xenon, and/or radon, are used.

0125The PAI process prevents subsequently doped impurities from channeling through spaces within the crystal lattice structure and reaching depths greater than desired. Portions of the stressors <b>1490</b> exposed and located at the bottoms <b>312</b><i>b </i>of the openings <b>312</b> are turned into an amorphous state as a result of the PAI process.

0126As shown in <figref idref="DRAWINGS">FIG. 14O</figref>, the stages of <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are performed to form a protective layer P<b>5</b> covering the DSL layer <b>314</b>, the etching stop layer <b>280</b>, the protective layer <b>290</b>, the gate electrode layer <b>270</b>, the work function metal layer <b>260</b>, the gate dielectric layer <b>250</b>, the semiconductor substrate <b>1410</b>, the contact etch stop layer <b>230</b>, the insulating layer <b>240</b>, the liner layer <b>1460</b>, and the spacers <b>1480</b>, in accordance with some embodiments. The materials and the formation methods of the protective layer P<b>5</b> and the protective layer <b>130</b> of <figref idref="DRAWINGS">FIG. 1B</figref> are the same, in accordance with some embodiments.

0127As shown in <figref idref="DRAWINGS">FIG. 14P</figref>, after keeping the semiconductor substrate <b>1410</b> in the substrate carrier <b>150</b> of <figref idref="DRAWINGS">FIG. 1C</figref> for the queue time, the stages of <figref idref="DRAWINGS">FIGS. 1D to 1F</figref> are performed to remove the protective layers P<b>5</b> and perform a cleaning process over the semiconductor substrate <b>1410</b>, in accordance with some embodiments.

0128As shown in <figref idref="DRAWINGS">FIG. 14P</figref>, a salicidation (self-aligned silicidation) process is performed to form metal silicide regions <b>1492</b> on/in the stressors <b>1490</b>, in accordance with some embodiments. The material of the metal silicide regions <b>1492</b> is made of nickel silicide, in accordance with some embodiments.

0129In some embodiments, the metal silicide regions <b>1492</b> are made of a silicide material of a suitable metal material. The suitable metal material includes cobalt (Co), platinum (Pt), titanium (Ti), ytterbium (Yb), molybdenum (Mo), erbium (Er), or combinations thereof, in accordance with some embodiments. In some embodiments, the salicidation process is not performed.

0130As shown in <figref idref="DRAWINGS">FIG. 14P</figref>, a conductive layer <b>320</b> is deposited on the protective layer <b>290</b> and is filled into the openings <b>312</b> to electrically contact the metal silicide regions <b>1492</b>, in accordance with some embodiments. The conductive layer <b>320</b> is formed by, for example, a PVD process or other suitable processes. The conductive layer <b>320</b> is made of, for example, tungsten or other suitable conductive materials.

0131As shown in <figref idref="DRAWINGS">FIG. 14Q</figref>, a planarization process is performed to remove the conductive layer <b>320</b> and the DSL layer <b>314</b> outside the openings <b>312</b>, and the protective layer <b>290</b>, in accordance with some embodiments. The planarization process includes a chemical mechanical polishing (CMP) process, in accordance with some embodiments. After the CMP process, the conductive layer <b>320</b> remaining in the openings <b>312</b> forms contact plugs <b>322</b> electrically connecting the metal silicide regions <b>1492</b> and the heavily doped regions <b>1412</b> (i.e. the S/D regions).

0132After the CMP process, top surfaces of the contact plugs <b>322</b>, the DSL layer <b>314</b>, and the etching stop layer <b>280</b> are coplanar with each other, in accordance with some embodiments. As shown in <figref idref="DRAWINGS">FIG. 14Q</figref>, a semiconductor device <b>1400</b> is formed. The semiconductor device <b>1400</b> is an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) or a p-type MOSFET, in accordance with some embodiments.

0133In accordance with some embodiments, methods for forming semiconductor device structures are provided. The methods form and remove a protective layer covering a semiconductor substrate at the start and end of a queue time between a first process and a second process. Since the protective layer is removed, the contamination formed over the protective layer during the queue time is removed as well. Therefore, the surface of the semiconductor substrate is kept clean after the queue time. As a result, the acceptable queue time is prolonged, which makes the second process more manufacturable and improves the yield of the second process and the performance of the semiconductor device structure.

0134In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate. The method includes forming a protective layer over the surface of the semiconductor substrate in a first chamber after the first process. The method includes performing a first transferring process to transfer the semiconductor substrate from the first chamber into a substrate carrier. The method includes performing a second transferring process to transfer the semiconductor substrate from the substrate carrier into a second chamber. The semiconductor substrate is located in the substrate carrier during a substantially entire first time interval between the first transferring process and the second transferring process. The method includes removing the substantially entire protective layer in the second chamber. The method includes performing a second process over the surface of the semiconductor substrate after the removal of the substantially entire protective layer.

0135In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate. The method includes forming a protective layer over the surface of the semiconductor substrate after the first process. The method includes removing the protective layer after a queue time. Before the removal of the protective layer, the protective layer is an outermost layer of the semiconductor device structure and covers the substantially entire surface. The method includes performing a second process over the surface of the semiconductor substrate after the removal of the protective layer.

0136In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a feature structure over a semiconductor substrate. The method includes forming a protective layer over the feature structure in a first chamber. The method includes performing a first transferring process to transfer the semiconductor substrate from the first chamber into a substrate carrier. The method includes performing a second transferring process to transfer the semiconductor substrate from the substrate carrier into a second chamber. The semiconductor substrate is located in the substrate carrier during a substantially entire first time interval between the first transferring process and the second transferring process. The method includes removing the protective layer in the second chamber. The method includes performing a second process over the semiconductor substrate and the feature structure after the removal of the protective layer.

0137The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.