Nova Patents
US10255232B2

Computer architecture with a hardware accumulator reset

Summary by NHIP

Hardware Accumulator Reset

The processor executes nested loops to scan image patches while resetting accumulators upon loop termination. This process avoids breaking pipelined execution by distinguishing zero overhead loop hardware from address generation units and sending break signals only at outermost loop ends.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.

US10255232B2, drawing sheet 1
Sheet 1 of 8

Term

5.8 yearsleft in the term

Expires 25 July 2032.

  1. Priority
  2. Filed
  3. Granted
  4. Today
  5. Expires

11 claims: 2 independent, 9 dependent

  1. 1
    Broadest claimClaim Score 37, narrow(NHIP)A method performable by a processor, the method comprising:executing by the processor multiple nested loops for scanning multiple dimensions of image patches;wherein the multiple nested loops comprises multiple innermost loops and outermost loops;wherein the processor comprises a flow control unit, multiple accumulators, multiple address generation units, and multiple zero overhead loop units;wherein an execution of each nested loop of the multiple nested loop comprises:checking, by a zero overhead loop hardware allocated to an execution of the nested loop, a fulfillment of an end of dimension condition that is indicative of an end of a scanning of a dimension of the multiple dimensions;wherein the zero overhead loop hardware differs from an address generation unit allocated to the execution of the nested loop;sending a break out of nested loop signal to the flow control unit only at an end of an outermost loop of the nested loop;andbreaking out of the nested loop, by the flow control unit, responsive to the break out of nested loop signal.
  2. 5
    A system comprising:a processor including multiple accumulators, a flow control unit, multiple address generation units, and multiple zero overhead loop units;wherein the processor is configured to execute multiple nested loops for scanning multiple dimensions of image patches;wherein the multiple nested loops comprises multiple innermost loops and outermost loops;wherein an execution, by the processor of each each nested loop of the multiple nested loop comprises:checking, by a zero overhead loop hardware allocated to an execution of the nested loop, a fulfillment of an end of dimension condition that is indicative of an end of a scanning of a dimension of the multiple dimensions;wherein the zero overhead loop hardware differs from an address generation unit allocated to the execution of the nested loop;sending a break out of nested loop signal to the flow control unit only at an end of an outermost loop of the nested loop;andbreaking out of the nested loop, by the flow control unit, responsive to the break out of nested loop signal.
Independent claims2