Semiconductor device including insulating films with different thicknesses and method for manufacturing the semiconductor device
Summary by NHIP
Thin Oxide Insulator Fabrication
The method forms a thin oxide insulating film over an oxide semiconductor using chemical vapor deposition with lower radio-frequency power than a subsequent thicker film. The first film measures less than or equal to 50 nm, exhibits spin densities below detection limits at a g-factor of 2.001, and forms at a higher temperature than the second film.
Claim Score by NHIP
Abstract
In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor device including an oxide semiconductor are improved. The semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and over the transistor, a first insulating film covering the gate insulating film, the oxide semiconductor film, and the pair of electrodes; and a second insulating film covering the first insulating film. An etching rate of the first insulating film is lower than or equal to 10 nm/min and lower than an etching rate of the second insulating film when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid.
Term
6.5 yearsleft in the term
Expires 15 March 2033.
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18 claims: 3 independent, 15 dependent
- 1Broadest claimClaim Score 49, average(NHIP)A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film over a substrate;forming a first oxide insulating film over and in contact with the oxide semiconductor film, in an apparatus and by chemical vapor deposition in a first atmosphere, and with a first radio-frequency power supplied to an electrode of the apparatus;and forming a second oxide insulating film over and in contact with the first oxide insulating film, in the apparatus and by chemical vapor deposition in a second atmosphere, and with a second radio-frequency power supplied to the electrode of the apparatus, wherein the first radio-frequency power is lower than the second radio-frequency power, wherein the first oxide insulating film is formed thinner than the second oxide insulating film, and a thickness of the first oxide insulating film is less than or equal to 50 nm, and wherein spin densities of the first oxide insulating film measured by electron spin resonance are less than or equal to a lower limit of detection at a g-factor of 2.001.
- 7A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film over a substrate;forming a first oxide insulating film over and in contact with the oxide semiconductor film, in an apparatus and by chemical vapor deposition in a first atmosphere, and with a first radio-frequency power supplied to an electrode of the apparatus;and forming a second oxide insulating film over and in contact with the first oxide insulating film, in the apparatus and by chemical vapor deposition in a second atmosphere, and with a second radio-frequency power supplied to the electrode of the apparatus, wherein the first radio-frequency power is lower than the second radio-frequency power, wherein the first oxide insulating film is formed thinner than the second oxide insulating film, and a thickness of the first oxide insulating film is less than or equal to 50 nm, wherein spin densities of the first oxide insulating film measured by electron spin resonance are less than or equal to a lower limit of detection at a q-factor of 2.001, and wherein the first oxide insulating film and the second oxide insulating film are a first silicon oxynitride film and a second silicon oxynitride film, respectively.
- 13A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film over a substrate;forming a first oxide insulating film over and in contact with the oxide semiconductor film, in an apparatus and by chemical vapor deposition in a first atmosphere, at a first temperature, and with a first radio-frequency power supplied to an electrode of the apparatus;forming a second oxide insulating film over and in contact with the first oxide insulating film, in the apparatus and by chemical vapor deposition in a second atmosphere, at a second temperature, and with a second radio-frequency power supplied to the electrode of the apparatus;and applying a heat treatment to the second oxide insulating film at a third temperature comprised between 250° C. and 450° C. in a nitrogen atmosphere, the third temperature being higher than the first temperature and the second temperature, wherein the first radio-frequency power is lower than the second radio-frequency power, wherein the first oxide insulating film is formed thinner than the second oxide insulating film, and a thickness of the first oxide insulating film is less than or equal to 50 nm, wherein spin densities of the first oxide insulating film measured by electron spin resonance are less than or equal to a lower limit of detection at a g-factor of 2.001, and wherein the first oxide insulating film and the second oxide insulating film are a first silicon oxynitride film and a second silicon oxynitride film, respectively.
Independent claims3
461 paragraphs in 5 sections, as filed
BACKGROUND OF THE INVENTION
00011. Field of the Invention
0002The present invention relates to a semiconductor device including a transistor.
00032. Description of the Related Art
0004Transistors used for most flat panel displays typified by a liquid crystal display device or a light-emitting display device are formed using a silicon semiconductor such as amorphous silicon, single crystal silicon, or polycrystalline silicon provided over a glass substrate. Further, transistors formed using such silicon semiconductors are used in integrated circuits (ICs) and the like.
0005In recent years, attention has been drawn to a technique in which, instead of a silicon semiconductor, a metal oxide exhibiting semiconductor characteristics is used for transistors. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.
0006For example, a technique is disclosed in which a transistor is manufactured using zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor and the transistor is used as a switching element or the like of a pixel of a display device (see Patent Documents 1 and 2).
REFERENCE
0000<ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0007">[Patent Document 1] Japanese Published Patent Application No. 2007-123861</li><li id="ul0001-0002" num="0008">[Patent Document 2] Japanese Published Patent Application No. 2007-096055</li></ul>
SUMMARY OF THE INVENTION
0009In a transistor including an oxide semiconductor, oxygen vacancies in an oxide semiconductor film cause the transistor to have poor electrical characteristics. For example, the threshold voltage of a transistor including an oxide semiconductor film which includes oxygen vacancies tends to shift in the negative direction, and thus the transistor tends to have normally-on characteristics. This is because charge is generated owing to the oxygen vacancies in the oxide semiconductor film, resulting in reduction of the resistance of the oxide semiconductor film. The transistor having normally-on characteristics causes various problems in that malfunction is likely to be caused when in operation and that power consumption is increased when not in operation.
0010Further, when the oxide semiconductor film includes an oxygen vacancy, as a problem, the amount of change in electrical characteristics, typically, the threshold voltage of the transistor is increased due to change over time or a bias-temperature stress test (hereinafter also referred to as a BT stress test).
0011Thus, one object of one embodiment of the present invention is to reduce the amount of oxygen vacancies in a semiconductor device including an oxide semiconductor. Another object of one embodiment of the present invention is to improve electrical characteristics of a semiconductor device including an oxide semiconductor.
0012According to one embodiment of the present invention, a semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and over the transistor, a first oxide insulating film covering the gate insulating film, the oxide semiconductor film, and the pair of electrodes; and a second oxide insulating film covering the first oxide insulating film. In the semiconductor device, the first oxide insulating film is dense and hard, typically an etching rate of the first oxide insulating film is lower than or equal to 10 nm/min and lower than an etching rate of the second oxide insulating film when etching is performed at 25° C. with a solution of 0.5 weight % of hydrofluoric acid.
0013Note that similar to the first insulating film, the gate insulating film may be an insulating film which is dense and hard, typically an insulating film having an etching rate lower than or equal to 10 nm/min and lower than an etching rate of the second insulating film when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid.
0014According to another embodiment of the present invention, a semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and a first insulating film covering the transistor and a second insulating film over the first insulating film. In the semiconductor device, the first insulating film is an oxide insulating film into which and from which oxygen is diffused, and the second insulating film is an oxide insulating film which contains oxygen at a higher proportion than a stoichiometric composition.
0015According to another embodiment of the present invention, a semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and an oxide insulating film covering the transistor. In the semiconductor device, the transistor has electrical characteristics in which the threshold voltage does not change or changes in a positive direction by a bias-temperature stress test, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V.
0016Note that the bias-temperature stress test is a positive BT stress test for applying a higher potential to the gate electrode than the pair of electrodes.
0017The bias-temperature stress test is a negative BT stress test for applying a lower potential to the gate electrode than the pair of electrodes.
0018Note that the bias-temperature stress test is a positive BT photostress test for applying a higher potential to the gate electrode than the pair of electrodes while irradiating a transistor with light.
0019The bias-temperature stress test is a negative BT photostress test for applying a lower potential to the gate electrode than the pair of electrodes while irradiating a transistor with light.
0020According to another embodiment of the present invention, a gate electrode and a gate insulating film are formed over a substrate, an oxide semiconductor film overlapping with the gate electrode is formed with the gate insulating film provided therebetween, and a pair of electrodes which is in contact with the oxide semiconductor film is formed. Next, an exposed portion of the oxide semiconductor film is exposed to plasma generated in an atmosphere containing oxygen and then a first insulating film which is dense and hard is formed immediately over the oxide semiconductor film and the pair of electrodes after the oxide semiconductor film and the pair of electrode have been exposed to plasma. The first insulating film is formed under conditions where the substrate placed in a treatment chamber which is vacuum-evacuated is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., the pressure in the treatment chamber is greater than or equal to 100 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber, and a high-frequency power is supplied to an electrode provided in the treatment chamber.
0021Further, the second insulating film is formed over the first insulating film. The second insulating film may be an insulating film which contains oxygen at a higher proportion than a stoichiometric composition. The insulating film which contains oxygen at a higher proportion than the stoichiometric composition is formed under conditions where the substrate placed in a treatment chamber which is vacuum-evacuated is held at a temperature higher than or equal to 180° C. and lower than or equal to 250° C., the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber, and a high-frequency power higher than or equal to 0.17 W/cm<sup>2 </sup>and lower than or equal to 0.5 W/cm<sup>2 </sup>is supplied to an electrode provided in the treatment chamber.
0022The atmosphere containing oxygen for generating plasma is an atmosphere containing one or more of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and air.
0023A silicon oxide film or a silicon oxynitride film is formed as the first insulating film and the second insulating film with a deposition gas containing silicon and an oxidizing gas as a source gas.
0024A silicon oxynitride film is formed as the first insulating film and the second insulating film with silane and dinitrogen monoxide as a source gas.
0025An oxide semiconductor film is exposed to plasma generated in an oxidizing atmosphere to supply oxygen to the oxide semiconductor film, whereby the amount of oxygen vacancies in the oxide semiconductor film can be reduced. Further, when a first insulating film which is dense and hard is formed immediately after the plasma treatment is performed, the concentration of impurities at the interface between the oxide semiconductor film and the first insulating film can be reduced. Furthermore, with the formation of the first insulating film which is dense and hard, the oxide semiconductor film can be prevented from being exposed to plasma and plasma damage to the oxide semiconductor film can be reduced during later film formation of a second insulating film. Accordingly, according to one embodiment of the present invention, a semiconductor device having excellent electrical characteristics can be manufactured.
0026Moreover, when an oxide insulating film into which and from which oxygen is diffused is formed over the oxide semiconductor film and then an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition is formed over the oxide insulating film, oxygen of the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition can be diffused into the oxide semiconductor film. Consequently, the amount of oxygen vacancies in the oxide semiconductor film can be reduced. Thus, a semiconductor device having excellent electrical characteristics can be manufactured.
BRIEF DESCRIPTION OF THE DRAWINGS
0027<figref idref="DRAWINGS">FIGS. 1A to 1D</figref> are a top view and cross-sectional views illustrating one embodiment of a transistor, and a graph showing electrical characteristics of the transistor.
0028<figref idref="DRAWINGS">FIGS. 2A to 2D</figref> are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor.
0029<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view illustrating one embodiment of a transistor.
0030<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view illustrating one embodiment of a transistor.
0031<figref idref="DRAWINGS">FIGS. 5A to 5C</figref> are each a cross-sectional view illustrating one embodiment of a display device.
0032<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are cross-sectional views each illustrating one embodiment of a display device.
0033<figref idref="DRAWINGS">FIGS. 7A and 7B</figref> are a top view and a cross-sectional view illustrating one embodiment of a display device.
0034<figref idref="DRAWINGS">FIGS. 8A and 8B</figref> are a cross-sectional view and a top view illustrating a common connection portion of a display device.
0035<figref idref="DRAWINGS">FIGS. 9A and 9B</figref> are a cross-sectional view and a top view illustrating a common connection portion of a display device.
0036<figref idref="DRAWINGS">FIGS. 10A to 10C</figref> each illustrate one embodiment of an electronic device.
0037<figref idref="DRAWINGS">FIG. 11</figref> shows a threshold voltage (Vth) and a shift value (Shift) of a transistor.
0038<figref idref="DRAWINGS">FIG. 12</figref> shows a threshold voltage (Vth) and a shift value (Shift) of a transistor.
0039<figref idref="DRAWINGS">FIGS. 13A and 13B</figref> show the definition of a threshold voltage and a shift value.
0040<figref idref="DRAWINGS">FIGS. 14A to 14D</figref> each show Vg-Id characteristics of a transistor.
0041<figref idref="DRAWINGS">FIGS. 15A to 15D</figref> each show Vg-Id characteristics of a transistor.
0042<figref idref="DRAWINGS">FIGS. 16A and 16B</figref> each show results of SSDP-SIMS measurement.
0043<figref idref="DRAWINGS">FIGS. 17A to 17C</figref> are cross-sectional views each illustrating a structure of a sample.
0044<figref idref="DRAWINGS">FIGS. 18A to 18C</figref> each show results of ESR measurement
0045<figref idref="DRAWINGS">FIG. 19</figref> shows results of ESR measurement.
0046<figref idref="DRAWINGS">FIGS. 20A and 20B</figref> each show Vg-Id characteristics of a transistor.
0047<figref idref="DRAWINGS">FIGS. 21A to 21C</figref> show results of ESR measurement.
0048<figref idref="DRAWINGS">FIGS. 22A and 22B</figref> each show results of ESR measurement.
0049<figref idref="DRAWINGS">FIGS. 23A and 23B</figref> are cross-sectional views each illustrating a structure of a sample.
0050<figref idref="DRAWINGS">FIGS. 24A to 24E</figref> show results of TDS measurement.
0051<figref idref="DRAWINGS">FIGS. 25A to 25F</figref> show results of SIMS measurement.
0052<figref idref="DRAWINGS">FIG. 26</figref> shows the etching rates of silicon oxynitride films.
DETAILED DESCRIPTION OF THE INVENTION
0053Embodiments and examples of the present invention will be described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments and examples. In addition, in the following embodiments and examples, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatching patterns in different drawings, and description thereof will not be repeated.
0054Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is in some cases exaggerated for clarity. Therefore, the embodiments and the examples of the present invention are not limited to such scales.
0055Note that terms such as “first”, “second”, and “third” in this specification are used in order to avoid confusion among components, and the terms do not limit the components numerically. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate.
0056Functions of a “source” and a “drain” are sometimes replaced with each other when the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.
0057Note that a voltage refers to a difference between potentials of two points, and a potential refers to electrostatic energy (electric potential energy) of a unit charge at a given point in an electrostatic field. In general, a difference between a potential of one point and a reference potential (e.g., a ground potential) is merely called a potential or a voltage, and a potential and a voltage are used in many cases as synonymous words. Thus, in this specification, a potential may be rephrased as a voltage and a voltage may be rephrased as a potential unless otherwise specified.
0058In this specification, in the case where an etching step is performed after a photolithography process, a mask formed in the photolithography process is removed.
Embodiment 1
0059In this embodiment, a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described with reference to drawings.
0060<figref idref="DRAWINGS">FIGS. 1A to 1C</figref> are a top view and cross-sectional views of a transistor <b>50</b> of a semiconductor device. <figref idref="DRAWINGS">FIG. 1A</figref> is a top view of the transistor <b>50</b>, <figref idref="DRAWINGS">FIG. 1B</figref> is a cross-sectional view taken along dashed-dotted line A-B in <figref idref="DRAWINGS">FIG. 1A</figref>, and <figref idref="DRAWINGS">FIG. 1C</figref> is a cross-sectional view taken along dashed-dotted line C-D in <figref idref="DRAWINGS">FIG. 1A</figref>. Note that in <figref idref="DRAWINGS">FIG. 1A</figref>, some components of the transistor <b>50</b> (e.g., a gate insulating film <b>18</b>), a substrate <b>11</b>, a base insulating film <b>13</b>, an insulating film <b>23</b>, an insulating film <b>24</b>, and the like are omitted for simplicity.
0061The transistor <b>50</b> illustrated in <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> includes a gate electrode <b>15</b> over the base insulating film <b>13</b>. Moreover, the gate insulating film <b>18</b> over the base insulating film <b>13</b> and the gate electrode <b>15</b>, an oxide semiconductor film <b>20</b> overlapping with the gate electrode <b>15</b> with the gate insulating film <b>18</b> provided therebetween, and a pair of electrodes <b>21</b> in contact with the oxide semiconductor film <b>20</b> are included. A protective film <b>25</b> including the insulating film <b>23</b> and the insulating film <b>24</b> is over the gate insulating film <b>18</b>, the oxide semiconductor film <b>20</b>, and the pair of electrodes <b>21</b>.
0062In the transistor <b>50</b> of this embodiment, the oxide semiconductor film <b>20</b> may be exposed to plasma generated in an oxidizing atmosphere. Atmospheres of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples of oxidizing atmospheres. Further, in the plasma treatment, the oxide semiconductor film <b>20</b> is preferred to be exposed to plasma generated with no bias applied to the substrate <b>11</b> side. By exposure of an oxide semiconductor film to such plasma, the oxide semiconductor film can be supplied with oxygen without being damaged; accordingly, the amount of oxygen vacancies in the oxide semiconductor film <b>20</b> can be reduced.
0063Further, the insulating film <b>23</b> is formed to be in contact with the oxide semiconductor film <b>20</b>. The insulating film <b>23</b> is an insulating film which is dense and hard. Specifically, the insulating film <b>23</b> is a silicon oxide film or a silicon oxynitride film having an etching rate lower than or equal to 10 nm/min, preferably lower than or equal to 8 nm/min, and lower than an etching rate of the insulating film <b>24</b> when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid.
0064When the insulating film <b>23</b> is dense and hard, the oxide semiconductor film can be prevented from being exposed to plasma and plasma damage to the oxide semiconductor film can be reduced during later film formation of the insulating film <b>24</b>. Accordingly, generation of oxygen vacancies in the oxide semiconductor film can be suppressed.
0065In the insulating film <b>23</b>, spin densities of a signal detected by electron spin resonance (ESR), which appear at E′-center (g-factor is 2.001) that show dangling bonds of silicon, are preferably lower than or equal to 2×10<sup>15 </sup>spins/cm<sup>3</sup>, more preferably lower than or equal to the lower limit of detection (1×10<sup>15 </sup>spins/cm<sup>3</sup>). Such an insulating film <b>23</b> has extremely few silicon dangling bonds. Therefore, the amount of change in threshold voltage of the transistor <b>50</b> having the insulating film <b>23</b> over time or in a BT stress test is small, and thus the transistor <b>50</b> has excellent electrical characteristics.
0066Further, the insulating film <b>23</b> is formed to be in contact with the oxide semiconductor film <b>20</b> in the transistor <b>50</b>. The insulating film <b>23</b> is an oxide insulating film into which and from which oxygen is diffused. Note that here, diffusion of oxygen includes movement of oxygen remaining in the insulating film <b>23</b> as well as movement of oxygen to the oxide semiconductor film <b>20</b> through the insulating film <b>23</b>.
0067When an oxide insulating film into which and from which oxygen is diffused is formed as the insulating film <b>23</b>, oxygen diffused from the insulating film <b>24</b> provided over the insulating film <b>23</b> can be diffused into the oxide semiconductor film <b>20</b> through the insulating film <b>23</b>.
0068As the insulating film <b>23</b>, a silicon oxide film, a silicon oxynitride film, or the like having a thickness greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm can be used.
0069Note that in the case where the oxide semiconductor film <b>20</b> is formed using a metal oxide containing indium, the insulating film <b>23</b> in some cases contains indium at a concentration of greater than or equal to 1×10<sup>15 </sup>atoms/cm<sup>3 </sup>and less than or equal to 5×10<sup>17 </sup>atoms/cm<sup>3</sup>. This occurs because indium contained in the oxide semiconductor film <b>20</b> is diffused into the insulating film <b>23</b> at the formation of the insulating film <b>23</b>. Note that as a film formation temperature of the insulating film <b>23</b> gets higher (e.g., higher than or equal to 350° C.), the indium content of the insulating film <b>23</b> is increased.
0070Further, the insulating film <b>24</b> is formed to be in contact with the insulating film <b>23</b>. The insulating film <b>24</b> is an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition.
0071As the insulating film <b>24</b>, a silicon oxide film, a silicon oxynitride film, or the like having a thickness greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 150 nm and less than or equal to 400 nm can be used.
0072Part of oxygen is released by heat treatment from the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. Therefore, when the oxide insulating film from which part of oxygen is released by heat treatment is provided over the insulating film <b>23</b> as the insulating film <b>24</b>, oxygen can be diffused into the oxide semiconductor film <b>20</b> and oxygen vacancies in the oxide semiconductor film <b>20</b> can be compensated. Alternatively, when the insulating film <b>24</b> is formed over the insulating film <b>23</b> during heat treatment, oxygen can be diffused into the oxide semiconductor film <b>20</b> and oxygen vacancies in the oxide semiconductor film <b>20</b> can be compensated. Still alternatively, when the insulating film <b>24</b> is formed over the insulating film <b>23</b> and is then subjected to heat treatment, oxygen can be diffused into the oxide semiconductor film <b>20</b> and oxygen vacancies in the oxide semiconductor film <b>20</b> can be compensated. Consequently, the amount of oxygen vacancies in the oxide semiconductor film can be reduced.
0073When the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition is provided over a back channel of the oxide semiconductor film <b>20</b> (a surface of the oxide semiconductor film <b>20</b>, which is opposite to a surface facing the gate electrode <b>15</b>) through the oxide insulating film into which and from which oxygen is diffused, oxygen can be diffused on the back channel side of the oxide semiconductor film <b>20</b>, and oxygen vacancies on the back channel side can be reduced. The transistor <b>50</b> having such a structure has the following electrical characteristics: the threshold voltage does not change or changes in a positive direction due to a BT stress test and a BT photostress test, and the amount of change (ΔVth) is less than or equal to 3.0 V, preferably less than or equal to 2.5 V, more preferably greater than or equal to 0 V and less than or equal to 1.5 V.
0074Further, it is possible to prevent outward diffusion of oxygen from the oxide semiconductor film <b>20</b> and entry of hydrogen, water, or the like into the oxide semiconductor film <b>20</b> from the outside by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like over the insulating film <b>24</b>. As for the insulating film having a blocking effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given as examples.
0075Here, electrical characteristics of a transistor having a small amount of change in threshold voltage in a BT stress test and a BT photostress test are described with reference to <figref idref="DRAWINGS">FIG. 1D</figref>.
0076The BT stress test is one kind of accelerated test and can evaluate, in a short time, change in characteristics (i.e., change over time) of transistors, which is caused by long-term use. In particular, the amount of change in threshold voltage of the transistor between before and after the BT stress test is an important indicator when examining the reliability of the transistor. If the amount of change in the threshold voltage between before and after the BT stress test is small, the transistor has higher reliability.
0077Next, a specific method of the BT stress test is described. First, initial characteristics of the transistor are measured at an initial temperature. Next, the temperature of the substrate over which the transistor is formed (substrate temperature) is set at fixed temperature, the pair of electrodes serving as a source electrode and a drain electrode of the transistor are set at a same potential, and the gate electrode is supplied for a certain period with potential different from that of the pair of electrodes serving as a source electrode and a drain electrode. The substrate temperature may be determined as appropriate in accordance with the test purpose. Then, the substrate temperature is set at a temperature similar to that of the initial temperature, and electrical characteristics of the transistor are measured again. As a result, a difference between the threshold voltage in the initial characteristics and the threshold voltage in the electrical characteristics after the BT stress test can be obtained as the amount of change in the threshold voltage.
0078Note that the test in the case where the potential applied to the gate electrode is higher than the potentials of the source electrode and the drain electrode is referred to as a positive BT stress test, and the test in the case where the potential applied to the gate electrode is lower than the potential of the source electrode and the drain electrode is referred to as a negative BT stress test. A BT stress test with light irradiation is referred to as a BT photostress test. The test in the case where light irradiation is performed and the potential applied to the gate electrode is higher than the potential of the source electrode and the drain electrode is referred to as a positive BT photostress test, and the test in the case where light irradiation is performed and the potential applied to the gate electrode is lower than the potential of the source electrode and the drain electrode is referred to as a negative BT photostress test.
0079The stress conditions for the BT stress test can be determined by setting the substrate temperature, the electric field intensity applied to the gate insulating film, and the time period of application of an electric field. The intensity of the electric field applied to the gate insulating film is determined in accordance with a value obtained by dividing a potential difference between the gate electrode, and the source electrode and the drain electrode by the thickness of the gate insulating film. For example, in the case where the intensity of the electric field applied to the 100-nm-thick gate insulating film is to be 3 MV/cm, the potential difference between the gate electrode, and the source electrode and the drain electrode can be set to 30 V.
0080<figref idref="DRAWINGS">FIG. 1D</figref> shows electrical characteristics of the transistor, and the horizontal axis indicates the gate voltage and the vertical axis indicates the drain current. A dashed line <b>41</b> denotes the initial characteristics of the transistor, and a solid line <b>43</b> denotes the electrical characteristics of the transistor after the BT stress test. The transistor of this embodiment has the following electrical characteristics: the amount of change in the threshold voltage in the dashed line <b>41</b> and the solid line <b>43</b> is 0 V or the threshold voltage changes in a positive direction, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V, more preferably less than or equal to 1.5 V, further preferably much less. Therefore, in the transistor of this embodiment, the threshold voltage is not shifted in the negative direction in the electrical characteristics after the BT stress test. That is, a transistor having normally-off characteristics does not become a transistor having normally-on characteristics by long-term usage. As a result, it is apparent that the transistor <b>50</b> of this embodiment has high reliability.
0081Note that a transistor including an oxide semiconductor film is an n-channel transistor; therefore, in this specification, a transistor which can be regarded as having no drain current flowing therein when a gate voltage is 0 V is defined as a transistor having normally-off characteristics. In contrast, a transistor which can be regarded as having a drain current flowing therein when a gate voltage is 0 V is defined as a transistor having normally-on characteristics.
0082Other details of the transistor <b>50</b> are described below.
0083There is no particular limitation on the property of a material and the like of the substrate <b>11</b> as long as the material has heat resistance enough to withstand at least later heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate <b>11</b>. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like may be used as the substrate <b>11</b>. Furthermore, any of these substrates further provided with a semiconductor element may be used as the substrate <b>11</b>.
0084Still alternatively, a flexible substrate may be used as the substrate <b>11</b>, and the base insulating film <b>13</b> and the transistor <b>50</b> may be provided directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate <b>11</b> and the base insulating film <b>13</b>. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate <b>11</b> and transferred onto another substrate. In such a case, the transistor <b>50</b> can be transferred to a substrate having low heat resistance or a flexible substrate as well.
0085As the base insulating film <b>13</b>, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, a gallium oxide film, a hafnium oxide film, an yttrium oxide film, an aluminum oxide film, an aluminum oxynitride film, and the like can be given as examples. Note that when a silicon nitride film, a gallium oxide film, a hafnium oxide film, an yttrium oxide film, an aluminum oxide film, or the like is used as the base insulating film <b>13</b>, it is possible to suppress diffusion of impurities such as an alkali metal, water, and hydrogen into the oxide semiconductor film <b>20</b> from the substrate <b>11</b>. Note that in this specification, a “silicon oxynitride film” refers to a film that includes more oxygen than nitrogen, and a “silicon nitride oxide film” refers to a film that includes more nitrogen than oxygen.
0086The gate electrode <b>15</b> can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing these metal elements in combination; or the like. Further, one or more metal elements selected from manganese and zirconium may be used. Further, the gate electrode <b>15</b> may have a single-layer structure or a stacked-layer structure of two or more layers. A single-layer structure of an aluminum film containing silicon; a two-layer structure in which a titanium film is stacked over an aluminum film; a two-layer structure in which a titanium film is stacked over a titanium nitride film; a two-layer structure in which a tungsten film is stacked over a titanium nitride film; a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film; and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order can be given as examples. Alternatively, a film, an alloy film, or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
0087The gate electrode <b>15</b> can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal element.
0088Further, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, an In—Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a film of a metal nitride (such as InN or ZnN), or the like may be provided between the gate electrode <b>15</b> and the gate insulating film <b>18</b>. These films each have a work function higher than or equal to 5 eV, preferably higher than or equal to 5.5 eV, which is higher than the electron affinity of an oxide semiconductor; thus, the threshold voltage of a transistor including the oxide semiconductor can be shifted in the positive direction. Accordingly, a switching element having what is called normally-off characteristics can be obtained. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a higher nitrogen concentration than at least the oxide semiconductor film <b>20</b>, specifically, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration higher than or equal to 7 at. % is used.
0089The gate insulating film <b>18</b> can be formed to have a single-layer structure or a stacked-layer structure using, for example, one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a gallium oxide film, and a Ga—Zn-based metal oxide film. The gate insulating film <b>18</b> may be formed using an oxide insulator from which oxygen is released by heating. With the use of a film from which oxygen is released by heating as the gate insulating film <b>18</b>, interface states at the interface between the oxide semiconductor film <b>20</b> and the gate insulating film <b>18</b> can be reduced; accordingly, a transistor with less deterioration in electrical characteristics can be obtained. Further, it is possible to prevent outward diffusion of oxygen from the oxide semiconductor film <b>20</b> and entry of hydrogen, water, or the like into the oxide semiconductor film <b>20</b> from the outside by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like on the gate electrode <b>15</b> side of the gate insulating film <b>18</b>. As for the insulating film having a blocking effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given as examples.
0090The gate insulating film <b>18</b> may be formed using a high-k material such as hafnium silicate (HfSiO<sub>x</sub>), hafnium silicate to which nitrogen is added (HfSi<sub>x</sub>O<sub>y</sub>N<sub>z</sub>), hafnium aluminate to which nitrogen is added (HfAl<sub>x</sub>O<sub>y</sub>N<sub>z</sub>), hafnium oxide, or yttrium oxide, so that gate leakage current of the transistor can be reduced.
0091The thickness of the gate insulating film <b>18</b> is preferably greater than or equal to 5 nm and less than or equal to 400 nm, more preferably greater than or equal to 10 nm and less than or equal to 300 nm, still more preferably greater than or equal to 50 nm and less than or equal to 250 nm.
0092An oxide semiconductor included in the oxide semiconductor film <b>20</b> preferably contains at least indium (In) or zinc (Zn). Alternatively, the oxide semiconductor film <b>20</b> preferably contains both In and Zn. In order to reduce fluctuations in electrical characteristics of the transistors including the oxide semiconductor film, the oxide semiconductor preferably contains one or more of stabilizers in addition to In or Zn.
0093As for stabilizers, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like can be given as examples. As another stabilizer, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be given as examples.
0094As the oxide semiconductor, for example, the following can be used: a single component metal oxide such as indium oxide, tin oxide, or zinc oxide; a two-component metal oxide such as an In—Zn-based metal oxide, a Sn—Zn-based metal oxide, an Al—Zn-based metal oxide, a Zn—Mg-based metal oxide, a Sn—Mg-based metal oxide, an In—Mg-based metal oxide, an In—Ga-based metal oxide, or an In—W-based metal oxide; a three-component metal oxide such as an In—Ga—Zn-based metal oxide (also referred to as IGZO), an In—Al—Zn-based metal oxide, an In—Sn—Zn-based metal oxide, a Sn—Ga—Zn-based metal oxide, an Al—Ga—Zn-based metal oxide, a Sn—Al—Zn-based metal oxide, an In—Hf—Zn-based metal oxide, an In—La—Zn-based metal oxide, an In—Ce—Zn-based metal oxide, an In—Pr—Zn-based metal oxide, an In—Nd—Zn-based metal oxide, an In—Sm—Zn-based metal oxide, an In—Eu—Zn-based metal oxide, an In—Gd—Zn-based metal oxide, an In—Tb—Zn-based metal oxide, an In—Dy—Zn-based metal oxide, an In—Ho—Zn-based metal oxide, an In—Er—Zn-based metal oxide, an In—Tm—Zn-based metal oxide, an In—Yb—Zn-based metal oxide, or an In—Lu—Zn-based metal oxide; or a four-component metal oxide such as an In—Sn—Ga—Zn-based metal oxide, an In—Hf—Ga—Zn-based metal oxide, an In—Al—Ga—Zn-based metal oxide, an In—Sn—Al—Zn-based metal oxide, an In—Sn—Hf—Zn-based metal oxide, or an In—Hf—Al—Zn-based metal oxide.
0095Note that, for example, an In—Ga—Zn-based metal oxide means an oxide containing In, Ga, and Zn as its main components and there is no particular limitation on the ratio of In, Ga, and Zn. The In—Ga—Zn-based metal oxide may contain a metal element other than In, Ga, and Zn.
0096Alternatively, a material represented by InMO<sub>3</sub>(ZnO)<sub>m </sub>(m>0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Alternatively, as the oxide semiconductor, a material represented by In<sub>2</sub>SnO<sub>5</sub>(ZnO)<sub>n </sub>(n>0 is satisfied, n is an integer) may be used.
0097For example, it is possible to use an In—Ga—Zn-based metal oxide containing In, Ga, and Zn at an atomic ratio of 1:1:1 (=1/3:1/3:1/3), 2:2:1 (=2/5:2/5:1/5), or 3:1:2 (=1/2:1/6:1/3), or any of oxides whose composition is in the neighborhood of the above compositions. Alternatively, an In—Sn—Zn-based metal oxide containing In, Sn, and Zn at an atomic ratio of 1:1:1 (=1/3:1/3:1/3), 2:1:3 (=1/3:1/6:1/2), or 2:1:5 (=1/4:1/8:5/8), or any of oxides whose composition is in the neighborhood of the above compositions may be used. Note that in the atomic ratio of each metal oxide, there is a margin of error of ±20% of the above atomic ratios.
0098However, the composition is not limited to those described above, and a material having the appropriate composition may be used depending on needed semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage). In order to obtain needed semiconductor characteristics and electrical characteristics, it is preferred that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element and oxygen, the interatomic distance, the density, and the like be set to be appropriate.
0099For example, a high mobility can be obtained relatively easily in the case where the In—Sn—Zn-based metal oxide is used. However, the mobility can be increased by reducing the defect density in the bulk also in the case where the In—Ga—Zn-based metal oxide is used.
0100Further, the energy gap of a metal oxide that can form the oxide semiconductor film <b>20</b> is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV. In this manner, the off-state current of a transistor can be reduced by using an oxide semiconductor having a wide energy gap.
0101Note that the oxide semiconductor film <b>20</b> may have an amorphous structure, a single crystal structure, or a polycrystalline structure.
0102The oxide semiconductor film <b>20</b> may be in a non-single-crystal state, for example. The non-single-crystal state is, for example, structured by at least one of c-axis aligned crystal (CAAC), polycrystal, microcrystal, and an amorphous part. The density of defect states of an amorphous part is higher than those of microcrystal and CAAC. The density of defect states of microcrystal is higher than that of CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (c-axis aligned crystalline oxide semiconductor). For example, the oxide semiconductor film <b>20</b> may include a CAAC-OS. In the CAAC-OS, for example, c-axes are aligned, and a-axes and/or b-axes are not macroscopically aligned.
0103For example, the oxide semiconductor film <b>20</b> may include microcrystal.
0104Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. A microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.
0105For example, the oxide semiconductor film <b>20</b> may include an amorphous part. Note that an oxide semiconductor including an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film, for example, has disordered atomic arrangement and no crystalline component. Alternatively, an amorphous oxide semiconductor film is, for example, absolutely amorphous and has no crystal part.
0106Note that the oxide semiconductor film <b>20</b> may be a mixed film including any of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. The mixed film, for example, includes a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS. Further, the mixed film may have a stacked-layer structure including a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS, for example.
0107Note that the oxide semiconductor film <b>20</b> may be in a single-crystal state, for example.
0108An oxide semiconductor film is preferred to include a plurality of crystal parts. In each of the crystal parts, a c-axis is preferred to be aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film. Note that among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. An example of such an oxide semiconductor film is a CAAC-OS film.
0109Here, the details of the CAAC-OS film are described. Note that in most cases, a crystal part in the CAAC-OS film fits inside a cube whose one side is less than 100 nm. In an image obtained with a transmission electron microscope (TEM), a boundary between the crystal parts in the CAAC-OS film are not clearly detected. Further, with the TEM, a grain boundary in the CAAC-OS film is not clearly found. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is suppressed.
0110In each of the crystal parts included in the CAAC-OS film, for example, a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film. Further, in each of the crystal parts, metal atoms are arranged in a triangular or hexagonal configuration when seen from the direction perpendicular to the a-b plane, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. In this specification, a term “perpendicular” includes a range from 80° to 100°, preferably from 85° to 95°. In addition, a term “parallel” includes a range from −10° to 10°, preferably from −5° to 5°.
0111In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is in some cases higher than that in the vicinity of the surface where the oxide semiconductor film is formed. Further, when an impurity is added to the CAAC-OS film, crystallinity of the crystal part in a region to which the impurity is added is in some cases lowered.
0112Since the c-axes of the crystal parts included in the CAAC-OS film are aligned in the direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface where the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that the film deposition is accompanied with the formation of the crystal parts or followed by the formation of the crystal parts through crystallization treatment such as heat treatment. Hence, the c-axes of the crystal parts are aligned in the direction parallel to a normal vector of the surface where the CAAC-OS film is formed or a normal vector of the surface of the CAAC-OS film.
0113In a transistor using the CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.
0114Alternatively, the oxide semiconductor film <b>20</b> may have a stacked-layer structure of a plurality of oxide semiconductor films. For example, the oxide semiconductor film <b>20</b> may have a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film which are formed using metal oxides with different compositions. Alternatively, for example, the first oxide semiconductor film may be formed using any of two-component metal oxide, a three-component metal oxide, and a four-component metal oxide, and the second oxide semiconductor film may be formed using any of these which is different from the oxide for the first oxide semiconductor film.
0115Further, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be made the same and the composition of the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be made different. For example, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:1:1, and the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 3:1:2. Alternatively, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:3:2, and the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 2:1:3.
0116At this time, one of the first oxide semiconductor film and the second oxide semiconductor film, which is closer to the gate electrode (on the channel side), preferably contains In and Ga at a proportion of In>Ga. The other oxide semiconductor film, which is farther from the gate electrode (on the back channel side) preferably contains In and Ga at a proportion of In≤Ga.
0117Further, the oxide semiconductor film <b>20</b> may have a three-layer structure of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film, in which the constituent elements thereof is made the same and the composition of the constituent elements of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film is made different. For example, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:3:2, the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 3:1:2, and the third oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:1:1.
0118An oxide semiconductor film which contains less In than Ga and Zn at an atomic ratio, typically, the first oxide semiconductor film containing In, Ga, and Zn at an atomic ratio of 1:3:2, has a higher insulating property than an oxide semiconductor film containing more In than Ga and Zn at an atomic ratio, typically, the second oxide semiconductor film, and an oxide semiconductor film containing Ga, Zn, and In at the same atomic ratio, typically, the third oxide semiconductor film. Further, when the first oxide semiconductor film containing In, Ga, and Zn at an atomic ratio of 1:3:2 has an amorphous structure, the insulating property is further improved. Accordingly, the second oxide semiconductor film and the third oxide semiconductor film each serve as a channel region, and the first oxide semiconductor film serves as a gate insulating film.
0119Since the constituent elements of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film are the same, the first oxide semiconductor film has fewer trap levels at the interface with the second oxide semiconductor film. Therefore, when the oxide semiconductor film <b>20</b> has the above structure, the amount of change in the threshold voltage of the transistor due to a change over time or a BT photostress test can be reduced.
0120In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the In content in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide containing In and Ga at a proportion of In>Ga has higher mobility than an oxide containing In and Ga at a proportion of In≤Ga. Further, in Ga, the formation energy of an oxygen vacancy is larger and thus an oxygen vacancy is less likely to occur, than in In; therefore, the oxide containing In and Ga at a proportion of In≤Ga has more stable characteristics than the oxide containing In and Ga at a proportion of In>Ga.
0121An oxide semiconductor containing In and Ga at a proportion of In>Ga is used on the channel side, and an oxide semiconductor containing In and Ga at a proportion of In≤Ga is used on the back channel side; so that field-effect mobility and reliability of the transistor can be further improved.
0122Further, the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film may be formed using oxide semiconductors having different crystallinity. That is, the oxide semiconductor film <b>20</b> may be formed using any of a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, and a CAAC-OS, as appropriate. When an amorphous oxide semiconductor is applied to any of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film, internal stress or external stress of the oxide semiconductor film <b>20</b> is relieved, change in characteristics of the transistor is reduced, and reliability of the transistor can be further improved.
0123The thickness of the oxide semiconductor film <b>20</b> is preferably greater than or equal to 1 nm and less than or equal to 100 nm, more preferably greater than or equal to 1 nm and less than or equal to 50 nm, still more preferably greater than or equal to 1 nm and less than or equal to 30 nm, further preferably greater than or equal to 3 nm and less than or equal to 20 nm.
0124The concentration of alkali metals or alkaline earth metals in the oxide semiconductor film <b>20</b> is preferably lower than or equal to 1×10<sup>18 </sup>atoms/cm<sup>3</sup>, more preferably lower than or equal to 2×10<sup>16 </sup>atoms/cm<sup>3</sup>. This is because, when alkali metals or alkaline earth metals are bonded to an oxide semiconductor, some of the alkali metals or the alkaline earth metals generate carriers and cause an increase in the off-state current of the transistor.
0125The oxide semiconductor film <b>20</b> may contain nitrogen at a concentration lower than or equal to 5×10<sup>18 </sup>atoms/cm<sup>3</sup>.
0126The pair of electrodes <b>21</b> is formed to have a single-layer structure or a stacked-layer structure including, as a conductive material, any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten or an alloy containing any of these metals as its main component. A single-layer structure of an aluminum film containing silicon; a two-layer structure in which a titanium film is stacked over an aluminum film; a two-layer structure in which a titanium film is stacked over a tungsten film; a two-layer structure in which a copper film is formed over a copper-magnesium-aluminum alloy film; a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order; and a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order can be given as examples. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
0127Next, a method for manufacturing the transistor <b>50</b> illustrated in <figref idref="DRAWINGS">FIGS. 1A to 1D</figref> is described with reference to <figref idref="DRAWINGS">FIGS. 2A to 2D</figref>.
0128As illustrated in <figref idref="DRAWINGS">FIG. 2A</figref>, the base insulating film <b>13</b> and the gate electrode <b>15</b> are formed over the substrate <b>11</b>, and the gate insulating film <b>18</b> is formed over the gate electrode <b>15</b>.
0129The base insulating film <b>13</b> is formed by a sputtering method, a CVD method or the like. Here, a 100-nm-thick silicon oxynitride film is formed by a CVD method.
0130A formation method of the gate electrode <b>15</b> is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like and then a mask is formed over the conductive film by a photolithography process. Then, part of the conductive film is etched using the mask to form the gate electrode <b>15</b>. After that, the mask is removed.
0131Note that instead of the above formation method, the gate electrode <b>15</b> may be formed by an electrolytic plating method, a printing method, an ink-jet method, or the like.
0132Here, a 100-nm-thick tungsten film is formed by a sputtering method. Then, a mask is formed by a photolithography process and the tungsten film is dry-etched using the mask to form the gate electrode <b>15</b>.
0133The gate insulating film <b>18</b> is formed by a sputtering method, a CVD method, an evaporation method, or the like.
0134In the case where the gate insulating film <b>18</b> is formed using a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film, a deposition gas containing silicon and an oxidizing gas are preferred to be used as a source gas. As typical examples of the deposition gas containing silicon, silane, disilane, and trisilane can be cited. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples.
0135In the case where a silicon nitride film is formed as the gate insulating film <b>18</b>, it is preferred to use a two-step formation method. First, a first silicon nitride film with few defects is formed by a plasma CVD method in which a mixed gas of silane, nitrogen, and ammonia is used as a source gas. Then, a second silicon nitride film in which the hydrogen concentration is low and hydrogen can be blocked is formed by switching the source gas to a mixed gas of silane and nitrogen. With such a formation method, a silicon nitride film having few defects and a blocking property against hydrogen can be formed as the gate insulating film <b>18</b>.
0136Moreover, in the case where a gallium oxide film is formed as the gate insulating film <b>18</b>, a metal organic chemical vapor deposition (MOCVD) method can be used.
0137Next, as illustrated in <figref idref="DRAWINGS">FIG. 2B</figref>, an oxide semiconductor film <b>19</b> is formed over the gate insulating film <b>18</b>.
0138A formation method of the oxide semiconductor film <b>19</b> is described below. An oxide semiconductor film is formed over the gate insulating film <b>18</b> by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like. Then, after a mask is formed over the oxide semiconductor film by a photolithography process, the oxide semiconductor film is partly etched using the mask. Accordingly, the oxide semiconductor film <b>19</b> which is over the gate insulating film <b>18</b> and subjected to element isolation so as to partly overlap with the gate electrode <b>15</b> is formed as illustrated in <figref idref="DRAWINGS">FIG. 2B</figref>. After that, the mask is removed.
0139A CAAC-OS film is formed by, for example, a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target might be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) might be separated from the sputtering target. In that case, the flat-plate-like sputtered particle reaches a substrate while maintaining their crystal state, whereby the CAAC-OS film can be deposited.
0140For the deposition of the CAAC-OS film, the following conditions are preferred to be used.
0141By reducing the amount of impurities entering the CAAC-OS film during the deposition, the crystal state can be prevented from being broken by the impurities. For example, reducing the concentration of impurities (e.g., hydrogen, water, carbon dioxide, and nitrogen) which exist in the deposition chamber is favorable. Furthermore, the concentration of impurities in a deposition gas can be reduced. Specifically, a deposition gas whose dew point is lower than or equal to −80° C., preferably lower than or equal to −100° C., can be used.
0142By increasing the substrate heating temperature during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches a substrate surface. Specifically, the substrate heating temperature during the deposition is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C. By increasing the substrate heating temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate surface, so that a flat plane of the flat-plate-like sputtered particle is attached to the substrate.
0143Furthermore, it is preferred that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is higher than or equal to 30 vol %, preferably 100 vol %.
0144As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.
0145The In—Ga—Zn—O compound target, which is polycrystalline, is made by mixing InO<sub>X </sub>powder, GaO<sub>Y </sub>powder, and ZnO<sub>Z </sub>powder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000° C. and lower than or equal to 1500° C. Note that X, Y, and Z are each a given positive number. Here, the predetermined molar ratio of InO<sub>x </sub>powder to GaO<sub>Y </sub>powder and ZnO<sub>Z </sub>powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target.
0146Alternatively, by using a printing method for forming the oxide semiconductor film <b>19</b>, the oxide semiconductor film <b>19</b> subjected to element isolation can be formed directly.
0147As a power supply device for generating plasma in the case where the oxide semiconductor film is formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate.
0148As a sputtering gas, an atmosphere of a rare gas (typically argon), an oxygen gas, or a mixed gas of a rare gas and oxygen is used as appropriate. In the case where the mixed atmosphere of a rare gas and oxygen is used, the proportion of oxygen is preferred to be higher than that of a rare gas.
0149Note that the target may be selected as appropriate depending on the composition of the oxide semiconductor film to be formed.
0150For example, in the case where the oxide semiconductor film is formed by a sputtering method at a substrate temperature higher than or equal to 150° C. and lower than or equal to 750° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C., more preferably higher than or equal to 200° C. and lower than or equal to 350° C., the oxide semiconductor film can be a CAAC-OS film.
0151Here, a 35-nm-thick oxide semiconductor film is formed by a sputtering method, a mask is formed over the oxide semiconductor film, and then part of the oxide semiconductor film is selectively etched. Accordingly, the oxide semiconductor film <b>19</b> is formed. After that, the mask is removed.
0152Next, as illustrated in <figref idref="DRAWINGS">FIG. 2C</figref>, the pair of electrodes <b>21</b> is formed.
0153A formation method of the pair of electrodes <b>21</b> is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like. Then, a mask is formed over the conductive film by a photolithography process. After that, part of the conductive film is etched using the mask to form the pair of electrodes <b>21</b>. Then, the mask is removed.
0154Here, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are sequentially stacked by a sputtering method. Then, a mask is formed over the titanium film by a photolithography process and the tungsten film, the aluminum film, and the titanium film are dry-etched using the mask to form the pair of electrodes <b>21</b>.
0155After the pair of electrodes <b>21</b> is formed, cleaning treatment is preferred to be performed to remove an etching residue. A short circuit of the pair of electrodes <b>21</b> can be suppressed by this cleaning treatment. The cleaning treatment can be performed using an alkaline solution such as a tetramethylammonium hydroxide (TMAH) solution; an acidic solution such as a diluted hydrofluoric acid solution, an oxalic acid solution, or a phosphoric acid solution; or water.
0156Next, the oxide semiconductor film <b>20</b> illustrated in <figref idref="DRAWINGS">FIG. 2D</figref> may be formed in such a manner that the oxide semiconductor film <b>19</b> is exposed to plasma generated in an oxidizing atmosphere to be supplied with oxygen <b>22</b> as illustrated in <figref idref="DRAWINGS">FIG. 2C</figref>. As an oxidizing atmosphere, atmospheres of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples. Further, in the plasma treatment, the oxide semiconductor film <b>19</b> is preferred to be exposed to plasma generated with no bias applied to a lower electrode on which the substrate <b>11</b> is mounted. Consequently, the oxide semiconductor film <b>19</b> can be supplied with oxygen without being damaged; accordingly, the amount of oxygen vacancies in the oxide semiconductor film <b>20</b> can be reduced.
0157Here, the oxide semiconductor film <b>20</b> is formed by exposing the oxide semiconductor film <b>19</b> to oxygen plasma which is generated in such a manner that dinitrogen monoxide is introduced into a treatment chamber of a plasma CVD apparatus, and an upper electrode provided in the treatment chamber is supplied with high-frequency power of 150 W with the use of a 27.12 MHz high-frequency power source.
0158The surface of the oxide semiconductor film <b>19</b> is exposed to plasma generated in an oxidizing atmosphere to be able to be supply oxygen to the oxide semiconductor film <b>19</b>, whereby the amount of oxygen vacancies in the oxide semiconductor film can be reduced. Moreover, impurities remaining on the surface of the oxide semiconductor film <b>19</b> due to the etching treatment, for example, a halogen such as fluorine or chlorine, can be removed.
0159Next, the insulating film <b>23</b> is formed over the oxide semiconductor film <b>20</b> and the pair of electrodes <b>21</b>. Then, the insulating film <b>24</b> is formed over the insulating film <b>23</b>. At this time, the insulating film <b>23</b> is formed without exposure to the atmosphere after the oxide semiconductor film <b>20</b> is formed by the above plasma treatment, whereby the concentration of impurities at the interface between the oxide semiconductor film <b>20</b> and the insulating film <b>23</b> can be reduced.
0160Further, it is preferred to form the insulating film <b>24</b> without exposure to the atmosphere, directly after the insulating film <b>23</b> is formed. After the insulating film <b>23</b> is formed, the insulating film <b>24</b> is formed directly by adjusting at least one of the flow rate of the source gas, the pressure, the high-frequency power, and the substrate temperature without exposure to the atmosphere, whereby the concentration of impurities attributed to the atmosphere at the interface between the insulating film <b>23</b> and the insulating film <b>24</b> can be reduced and further oxygen contained in the insulating film <b>24</b> can be diffused into the oxide semiconductor film <b>20</b>; accordingly, the amount of oxygen vacancies in the oxide semiconductor film <b>20</b> can be reduced.
0161As the insulating film <b>23</b>, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., the pressure in the treatment chamber is greater than or equal to 30 Pa and less than or equal to 250 Pa, preferably greater than or equal to 40 Pa and less than or equal to 250 Pa, more preferably greater than or equal to 100 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber, and high-frequency power is supplied to an electrode provided in the treatment chamber.
0162A deposition gas containing silicon and an oxidizing gas are preferred to be used as the source gas of the insulating film <b>23</b>. As typical examples of the deposition gas containing silicon, silane, disilane, and trisilane can be cited. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples.
0163Under the above conditions, the oxide insulating film into which and from which oxygen is diffused can be formed as the insulating film <b>23</b>. With the insulating film <b>23</b>, damage to the oxide semiconductor film <b>20</b> can be reduced during a later formation process of the insulating film <b>24</b>. Further, when the pressure in the treatment chamber, which is one of the film formation conditions of the insulating film <b>23</b>, is greater than or equal to 100 Pa and less than or equal to 250 Pa, damage to the oxide semiconductor film <b>20</b> can be reduced.
0164Note that when the ratio of the amount of the oxidizing gas to the amount of the deposition gas containing silicon is 100 or higher, the hydrogen content in the insulating film <b>23</b> can be reduced. Consequently, the amount of hydrogen entering the oxide semiconductor film <b>20</b> can be reduced; thus, the negative shift in the threshold voltage of the transistor can be suppressed.
0165Further, as the insulating film <b>23</b>, a silicon oxide film or a silicon oxynitride film can be formed under the following conditions: the substrate placed in a treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 300° C. and lower than or equal to 400° C., preferably higher than or equal to 320° C. and lower than or equal to 370° C., the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of the source gas into the treatment chamber, and high-frequency power is supplied to an electrode provided in the treatment chamber.
0166Under the above film formation conditions, the bonding strength of silicon and oxygen becomes strong in the above substrate temperature range. Consequently, as the insulating film <b>23</b>, a dense and hard oxide insulating film into which and from which oxygen is diffused, typically, a silicon oxide film or a silicon oxynitride film having an etching rate lower than or equal to 10 nm/min, preferably lower than or equal to 8 nm/min when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid can be formed.
0167Here, as the insulating film <b>23</b>, a 10-nm-thick silicon oxynitride film is formed by a plasma CVD method under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as the source gas, the pressure in the treatment chamber is 200 Pa, the substrate temperature is 220° C., and the high-frequency power of 100 W is supplied to an upper electrode of parallel plate electrodes with the use of a 27.12 MHz high-frequency power source. Under the above conditions, a silicon oxynitride film into which and from which oxygen is diffused can be formed.
0168As the insulating film <b>24</b>, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C., preferably higher than or equal to 180° C. and lower than or equal to 250° C., more preferably higher than or equal to 180° C. and lower than or equal to 230° C., the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber, and high-frequency power higher than or equal to 0.17 W/cm<sup>2 </sup>and lower than or equal to 0.5 W/cm<sup>2</sup>, preferably higher than or equal to 0.26 W/cm<sup>2 </sup>and lower than or equal to 0.35 W/cm<sup>2</sup>, more preferably higher than or equal to 0.25 W/cm<sup>2 </sup>and lower than or equal to 0.40 W/cm<sup>2 </sup>is supplied to an electrode provided in the treatment chamber.
0169As the film formation conditions of the insulating film <b>24</b>, the high-frequency power having the above power density is supplied to the treatment chamber having the above pressure, whereby the degradation efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas is promoted; therefore, the oxygen content of the insulating film <b>24</b> becomes higher than that in the stoichiometric composition. However, the bonding strength of silicon and oxygen is weak in the above substrate temperature range; therefore, part of oxygen is released by heating. Thus, it is possible to form an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating. Moreover, the insulating film <b>23</b> is provided over the oxide semiconductor film <b>20</b>. Accordingly, in the process for forming the insulating film <b>24</b>, the insulating film <b>23</b> serves as a protective film of the oxide semiconductor film <b>20</b>. Consequently, the insulating film <b>24</b> can be formed using the high-frequency power having a high power density while damage to the oxide semiconductor film <b>20</b> is reduced.
0170Here, as the insulating film <b>24</b>, a 400-nm-thick silicon oxynitride film is formed by a plasma CVD method under the following conditions: silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm are used as the source gas, the pressure in the treatment chamber is 200 Pa, the substrate temperature is 220° C., and the high-frequency power of 1500 W is supplied to an upper electrode of parallel plate electrodes with the use of a 27.12 MHz high-frequency power source. Note that the plasma CVD apparatus used in this embodiment is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm<sup>2</sup>, and the power per unit area (power density) into which the supplied power is converted is 0.25 W/cm<sup>2</sup>.
0171As described in this embodiment, the surface of the oxide semiconductor film <b>19</b> is exposed to plasma generated in an oxidizing atmosphere to be able to supply oxygen to the oxide semiconductor film <b>19</b>, whereby the amount of oxygen vacancies in the oxide semiconductor film can be reduced. Moreover, impurities remaining on the surface of the oxide semiconductor film <b>19</b> due to the etching treatment, for example, a halogen such as fluorine or chlorine can be removed. Further, when the substrate is carried out from the treatment chamber, impurities contained in the atmosphere, for example, boron is attached to the surface of the oxide semiconductor film. However, in the plasma CVD apparatus, after the surface of the oxide semiconductor film <b>19</b> is exposed to plasma generated in an oxidizing atmosphere, the insulating film <b>23</b> is formed in succession by introducing the source gas of the insulating film <b>23</b> into the treatment chamber and adjusting the pressure, the high-frequency power, and the substrate temperature without exposure to the atmosphere, whereby the concentration of impurities at the interface between the oxide semiconductor film <b>20</b> and the insulating film <b>23</b> can be reduced. Consequently, change in electrical characteristics of the transistor can be reduced. Further, after the insulating film <b>23</b> is formed, the insulating film <b>24</b> is formed in succession by adjusting the flow rate of the source gas, the pressure, the high-frequency power, and the substrate temperature without exposure to the atmosphere, whereby the concentration of impurities at the interface between the insulating film <b>23</b> and the insulating film <b>24</b> can be reduced.
0172Next, heat treatment is performed. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.
0173An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. With the use of the RTA apparatus, the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened.
0174The heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air in which a water content is less than or equal to 20 ppm, preferably less than or equal to 1 ppm, more preferably less than or equal to 10 ppb), or a rare gas (e.g., argon or helium). The atmosphere of nitrogen, oxygen, ultra-dry air, or a rare gas is preferred not to contain hydrogen, water, and the like.
0175Here, the heat treatment is performed at 250° C. under a mixed atmosphere of nitrogen and oxygen for one hour.
0176The heat treatment is performed, whereby oxygen contained in the insulating film <b>24</b> is diffused into the oxide semiconductor film <b>20</b> to compensate oxygen vacancies in the oxide semiconductor film <b>20</b>. Thus, the amount of oxygen vacancies in the oxide semiconductor film <b>20</b> can be reduced.
0177Note that when the temperature in the heat treatment is higher than the film formation temperature of the insulating film <b>23</b>, more oxygen contained in the insulating film <b>23</b> can be diffused into the oxide semiconductor film <b>20</b>; thus, oxygen vacancies in the oxide semiconductor film <b>20</b> can be compensated more. The temperature of the heat treatment at this time can be higher than or equal to 250° C. and lower than the strain point of the substrate, preferably higher than or equal to 250° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.
0178Through the above process, a transistor having excellent electrical characteristics in which the negative shift in the threshold voltage can be suppressed can be manufactured. Moreover, a highly reliable transistor having the following electrical characteristics can be manufactured: the amount of change in electrical characteristics due to change over time or a BT photostress test is small, typically the threshold voltage does not change or changes in a positive direction, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V.
0179Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.
Embodiment 2
0180In this embodiment, a structure and a method for manufacturing a transistor whose gate insulating film is different from that of the transistor shown in Embodiment 1 will be described with reference to <figref idref="DRAWINGS">FIGS. 1A to 1C</figref> and <figref idref="DRAWINGS">FIG. 3</figref>.
0181As the gate insulating film <b>18</b> illustrated in <figref idref="DRAWINGS">FIGS. 1A to 1C</figref>, in a transistor of this embodiment, a dense and hard oxide insulating film into which and from which oxygen is diffused, typically, a silicon oxide film or a silicon oxynitride film having an etching rate lower than or equal to 10 nm/min, preferably lower than or equal to 8 nm/min when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid is formed.
0182Note that in the case where the dense and hard oxide insulating film into which and from which oxygen is diffused is formed as the gate insulating film <b>18</b>, a silicon oxide film or a silicon oxynitride film is formed under the following conditions in a manner similar to that of the insulating film <b>23</b> of Embodiment 1: the substrate placed in a treatment chamber of a plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 300° C. and lower than or equal to 400° C., more preferably higher than or equal to 320° C. and lower than or equal to 370° C., the pressure is greater than or equal to 30 Pa and less than or equal to 250 Pa, preferably greater than or equal to 40 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber, and high-frequency power is supplied to an electrode provided in the treatment chamber.
0183Note that when the ratio of the amount of the oxidizing gas to the amount of the deposition gas containing silicon is 100 or higher, the hydrogen content in the gate insulating film <b>18</b> can be reduced. Consequently, the amount of hydrogen entering the oxide semiconductor film <b>20</b> can be reduced; thus, the negative shift in the threshold voltage of the transistor can be suppressed.
0184Under the film formation conditions of the gate insulating film <b>18</b>, the bonding strength of silicon and oxygen becomes strong in the above substrate temperature range. Consequently, the dense and hard oxide insulating film can be formed as the gate insulating film <b>18</b>. Moreover, when the film formation pressure is made lower than the above range, the amount of defects, typically, dangling bonds of silicon in the gate insulating film <b>18</b> can be reduced. Consequently, a transistor in which the amount of change in threshold voltage is small and whose electrical characteristics are excellent can be manufactured.
0185Here, as the gate insulating film <b>18</b>, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as the source gas, the pressure in the treatment chamber is 40 Pa, the substrate temperature is 350° C., and the high-frequency power of 100 W is supplied to an upper electrode of parallel plate electrodes with the use of a 27.12 MHz high-frequency power source. Under the above conditions, a dense and hard silicon oxynitride film into which and from which oxygen is diffused can be formed.
0186A transistor in which negative shift in the threshold voltage is suppressed and whose electrical characteristics are excellent can be manufactured in such a manner that the other components of the transistor are formed by using structures and formation methods similar to those of the transistor <b>50</b> illustrated in <figref idref="DRAWINGS">FIGS. 1A to 1C</figref>. Moreover, a highly reliable transistor having the following electrical characteristics can be manufactured: the amount of change in electrical characteristics due to change over time or a BT photostress test is small, typically the threshold voltage does not change or changes in a positive direction, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V.
0187Further, as in a transistor <b>60</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the gate insulating film <b>18</b> may have a two-layer structure of an insulating film <b>16</b> in contact with the gate electrode <b>15</b> and an insulating film <b>17</b> which is formed over the insulating film <b>16</b> and is in contact with the oxide semiconductor film <b>20</b>.
0188In that case, the insulating film <b>16</b> can be formed to have a single-layer structure or a stacked-layer structure using, for example, one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a gallium oxide film, and a Ga—Zn-based metal oxide film. Further, it is possible to prevent outward diffusion of oxygen from the oxide semiconductor film <b>20</b> and entry of oxygen into the oxide semiconductor film <b>20</b> from the outside by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like as the insulating film <b>16</b>. As the insulating film having a blocking effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given as examples.
0189The insulating film <b>16</b> may be formed using a high-k material such as hafnium silicate (HfSiO<sub>x</sub>), hafnium silicate to which nitrogen is added (HfSi<sub>x</sub>O<sub>y</sub>N<sub>z</sub>), hafnium aluminate to which nitrogen is added (HfAl<sub>x</sub>O<sub>y</sub>N<sub>z</sub>), hafnium oxide, or yttrium oxide, so that gate leakage current of the transistor can be reduced.
0190As the insulating film <b>17</b>, an oxide insulating film into which and from which oxygen is diffused can be used in a manner similar to that of the insulating film <b>23</b> of Embodiment 1. Alternatively, a dense and hard oxide insulating film into which and from which oxygen is diffused, typically, a silicon oxide film or a silicon oxynitride film having an etching rate lower than or equal to 10 nm/min, preferably lower than or equal to 8 nm/min, and lower than an etching rate of the insulating film <b>24</b> when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid can be formed.
0191The thickness of each of the insulating films <b>16</b> and <b>17</b> is greater than or equal to 5 nm and less than or equal to 400 nm. Note that the thicknesses of the insulating film <b>16</b> and the insulating film <b>17</b> may be determined so that the sum of the thicknesses of the two insulating films is within the range of the thickness of the gate insulating film <b>18</b> of the transistor <b>50</b> illustrated in <figref idref="DRAWINGS">FIGS. 1A to 1C</figref>.
0192The gate insulating film <b>18</b> is formed here to have a large thickness and is preferred to have a stacked-layer structure of a silicon nitride film with resistivity higher than or equal to 5×10<sup>13 </sup>Ω·cm and lower than or equal to 1×10<sup>15 </sup>Ω·cm and a silicon oxynitride film, whereby in a transistor formed later, electrostatic breakdown caused between the gate electrode <b>15</b> and the oxide semiconductor film <b>20</b> or between the gate electrode <b>15</b> and the pair of electrodes <b>21</b> can be suppressed.
0193Here, as the insulating film <b>16</b>, a 50-nm-thick silicon nitride film is formed by a plasma CVD method under the following conditions: silane with a flow rate of 50 sccm and nitrogen with a flow rate of 5000 sccm are used as a source gas, the pressure in a treatment chamber is 60 Pa, the substrate temperature is 350° C., and the high-frequency power of 1500 W is supplied to an upper electrode of parallel plate electrodes.
0194Here, as the insulating film <b>17</b>, a 200-nm-thick silicon oxide film is formed by a plasma CVD method under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as a source gas, the pressure in a treatment chamber is 40 Pa, the substrate temperature is 350° C., and the high-frequency power of 100 W is supplied to an upper electrode of parallel plate electrodes. Under the above conditions, a dense and hard silicon oxide film into which and from which oxygen is diffused can be formed.
0195Through the above process, a transistor in which negative shift in the threshold voltage is suppressed and whose electrical characteristics are excellent can be manufactured in such a manner that a gate insulating film is partly or entirely formed by using a dense and hard oxide insulating film into which and from which oxygen is diffused. Moreover, a highly reliable transistor having the following electrical characteristics can be manufactured: the amount of change in electrical characteristics due to change over time or a BT photostress test is small, typically the threshold voltage does not change or changes in a positive direction, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V.
Embodiment 3
0196In this embodiment, a transistor having a structure different from that of Embodiment 1 and Embodiment 2 will be described with reference to <figref idref="DRAWINGS">FIG. 4</figref>. A transistor <b>70</b> of this embodiment includes a plurality of gate electrodes facing each other with an oxide semiconductor film provided therebetween.
0197A transistor <b>70</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref> includes the base insulating film <b>13</b> over the substrate <b>11</b> and the gate electrode <b>15</b> over the base insulating film <b>13</b>. Moreover, the gate insulating film <b>18</b> over the base insulating film <b>13</b> and the gate electrode <b>15</b>, the oxide semiconductor film <b>20</b> overlapping with the gate electrode <b>15</b> with the gate insulating film <b>18</b> provided therebetween, and the pair of electrodes <b>21</b> in contact with the oxide semiconductor film <b>20</b> are included. The protective film <b>25</b> including the insulating film <b>23</b> and the insulating film <b>24</b> is over the gate insulating film <b>18</b>, the oxide semiconductor film <b>20</b>, and the pair of electrodes <b>21</b>. Further, a gate electrode <b>61</b> overlapping with the oxide semiconductor film <b>20</b> with the protective insulating film <b>25</b> provided therebetween is included.
0198The gate electrode <b>61</b> can be formed in a manner similar to that of the gate electrode <b>15</b> of Embodiment 1.
0199The transistor <b>70</b> of this embodiment has the gate electrode <b>15</b> and the gate electrode <b>61</b> facing each other with the oxide semiconductor film <b>20</b> provided therebetween. By application of different potentials to the gate electrode <b>15</b> and the gate electrode <b>61</b>, the threshold voltage of the transistor <b>70</b> can be controlled, in a preferable manner, the negative shift in the threshold voltage can be suppressed. Moreover, the oxide semiconductor film <b>20</b> whose surface is exposed to plasma generated in an oxidizing atmosphere and the insulating film <b>23</b> which is formed in succession after the plasma treatment are included, whereby impurities between the oxide semiconductor film <b>20</b> and the gate electrode <b>61</b> can be reduced, and change in the threshold voltage of the transistor <b>70</b> can be reduced. Further, with the use of the oxide semiconductor film <b>20</b> in which the amount of oxygen vacancies is reduced, the negative shift in the threshold voltage of the transistor <b>70</b> can be suppressed. Further, the transistor <b>70</b> has the following excellent electrical characteristics: the amount of change in the threshold voltage due to change over time or a BT photostress test is small, typically the threshold voltage does not change or changes in a positive direction, and the amount of change is less than or equal to 3.0 V, preferably less than or equal to 2.5 V.
Embodiment 4
0200In this embodiment, a method for manufacturing a transistor in which the concentration of hydrogen in an oxide semiconductor film is reduced will be described. Such a transistor is any of the transistors described in Embodiments 1 to 3. Note that at least one of steps described in this embodiment may be combined with the process of manufacturing the transistor described in any of Embodiments 1 to 3; it is not necessary to combine all steps therewith.
0201The concentration of hydrogen in the oxide semiconductor film <b>20</b> of Embodiment 1 is preferably lower than 5×10<sup>19 </sup>atoms/cm<sup>3</sup>, more preferably lower than 5×10<sup>18 </sup>atoms/cm<sup>3</sup>, still more preferably lower than or equal to 1×10<sup>18 </sup>atoms/cm<sup>3</sup>, further preferably lower than or equal to 5×10<sup>17 </sup>atoms/cm<sup>3</sup>, still further preferably lower than or equal to 1×10<sup>16 </sup>atoms/cm<sup>3</sup>.
0202Hydrogen contained in the oxide semiconductor film <b>20</b> reacts with oxygen bonded to a metal atom to produce water, and a defect is formed in a lattice from which oxygen is released (or a portion from which oxygen is removed). In addition, a bond of hydrogen and oxygen causes generation of electrons serving as carriers. Thus, the impurities containing hydrogen are reduced as much as possible in the formation process of the oxide semiconductor film, whereby the concentration of hydrogen in the oxide semiconductor film can be reduced. Therefore, when a channel region is formed in an oxide semiconductor film that is highly purified by removing hydrogen as much as possible, the negative shift in the threshold voltage can be reduced and leakage current between a source electrode and a drain electrode of a transistor, typically, the off-state current per channel width can be reduced to several yA/μm to several zA/μm; thus, electrical characteristics of the transistor can be improved.
0203As a first method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, there is a method in which hydrogen or water contained in the substrate <b>11</b>, the base insulating film <b>13</b>, the gate electrode <b>15</b>, and the gate insulating film <b>18</b> is released by heat treatment or plasma treatment before the oxide semiconductor film <b>20</b> is formed. This method allows hydrogen or water attached to the substrate <b>11</b>, the base insulating film <b>13</b>, the gate electrode <b>15</b>, and the gate insulating film <b>18</b> to be prevented from diffusing into the oxide semiconductor film <b>20</b> in later heat treatment. The heat treatment is performed at a temperature higher than or equal to 100° C. and lower than the strain point of the substrate under an inert atmosphere, a reduced-pressure atmosphere, or a dry air atmosphere. Further, for the plasma treatment, rare gas, oxygen, nitrogen, or nitrogen oxide (e.g., nitrous oxide, nitrogen monoxide, or nitrogen dioxide) is used.
0204As a second method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, there is a method in which before the oxide semiconductor film is formed by a sputtering apparatus, a dummy substrate is put into the sputtering apparatus, and an oxide semiconductor film is formed over the dummy substrate, so that hydrogen, water, or the like attached to the target surface or a deposition shield are removed. This method allows reduction of entry of hydrogen, water, or the like into the oxide semiconductor film.
0205As a third method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, for example, in the case where a sputtering method is employed in the formation of the oxide semiconductor film, there is a method in which the substrate temperature is set to higher than or equal to 150° C. and lower than or equal to 750° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C., further preferably higher than or equal to 200° C. and lower than or equal to 350° C. and the oxide semiconductor film is formed. By this method, entry of hydrogen, water, or the like into the oxide semiconductor film can be reduced.
0206Here, a sputtering apparatus which can reduce the concentration of hydrogen in the oxide semiconductor film <b>20</b> is described in detail below.
0207The leakage rate of a treatment chamber in which the oxide semiconductor film is formed is preferred to be lower than or equal to 1×10<sup>−10 </sup>Pa·m<sup>3</sup>/sec., whereby entry of impurities such as hydrogen or water into the film formed by a sputtering method can be reduced.
0208Evacuation of a treatment chamber in a sputtering apparatus is preferred to be performed with a rough vacuum pump such as a dry pump and a high vacuum pump such as a sputter ion pump, a turbo molecular pump, or a cryopump in appropriate combination. The turbo molecular pump has an outstanding capability in evacuating a large-sized molecule, whereas it has a low capability in evacuating hydrogen and water. Further, a combination with a sputter ion pump having a high capability in evacuating hydrogen or a cryopump having a high capability in evacuating water is effective.
0209An adsorbate present at the inner wall of the treatment chamber does not affect the pressure in the treatment chamber because it is adsorbed on the inner wall, but the adsorbate leads to release of a gas at the time of the evacuation of the treatment chamber. Therefore, although the leakage rate and the evacuation rate do not have a correlation, it is important that the adsorbate present in the treatment chamber be desorbed as much as possible and evacuation be performed in advance with the use of a pump having high evacuation capability. Note that the treatment chamber may be subjected to baking for promotion of desorption of the adsorbate. By the baking, the rate of desorption of the adsorbate can be increased about tenfold. The baking should be performed at a temperature higher than or equal to 100° C. and lower than or equal to 450° C. At this time, when the adsorbate is removed while an inert gas is introduced, the rate of desorption of water or the like, which is difficult to be desorbed only by evacuation, can be further increased.
0210As described above, in the process for forming the oxide semiconductor film, entry of impurities is suppressed as much as possible through control of the pressure in the treatment chamber, leakage rate of the treatment chamber, and the like, whereby entry of hydrogen, water, or the like into the oxide semiconductor film can be reduced.
0211As a fourth method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, there is a method in which a high-purity gas which is a source gas from which impurities containing hydrogen are removed is used. This method allows reduction of entry of hydrogen, water, or the like into the oxide semiconductor film.
0212As a fifth method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, there is a method in which the oxide semiconductor film is formed and is then subjected to heat treatment. By the heat treatment, the oxide semiconductor film can be dehydrated or dehydrogenated.
0213The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 250° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.
0214The heat treatment is performed under atmosphere of an inert gas including nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, the heat treatment may be performed under an atmosphere of an inert gas first, and then under an oxygen atmosphere. It is preferred that the above atmosphere of an inert gas and oxygen atmosphere do not contain hydrogen, water, and the like. The treatment time is 3 minutes to 24 hours.
0215Note that as illustrated in <figref idref="DRAWINGS">FIG. 2B</figref>, the oxide semiconductor film <b>20</b> that is subjected to element isolation is formed and then the heat treatment for dehydration or dehydrogenation may be performed. Through the above process, hydrogen, water, or the like contained in the gate insulating film <b>18</b> can be efficiently released in the heat treatment for dehydration or dehydrogenation.
0216The heat treatment for dehydration or dehydrogenation may be performed more than once, and may also serve as another heat treatment.
0217As the fifth method for reducing the concentration of hydrogen in the oxide semiconductor film <b>20</b>, the substrate is preferred to be heated in a heating chamber of a plasma CVD apparatus before the oxide semiconductor film <b>19</b> is exposed to plasma in an oxidizing atmosphere illustrated in <figref idref="DRAWINGS">FIG. 2C</figref> of Embodiment 3. After the heat treatment, the oxide semiconductor film <b>19</b> is exposed to plasma in an oxidizing atmosphere of the treatment chamber of the plasma CVD apparatus in succession without exposure to the atmosphere and further the insulating film <b>23</b> is formed in succession without exposure to the atmosphere, whereby the amount of impurities such as boron at the interface between the oxide semiconductor film <b>20</b> and the insulating film <b>23</b> can be reduced while impurities such as hydrogen and water are released from the oxide semiconductor film <b>20</b>.
0218By combination of at least one of the first to fifth methods for reducing the concentration of hydrogen in the oxide semiconductor film and any of the methods for manufacturing a transistor, which are described in Embodiments 1 to 3, a transistor whose channel region is formed in an oxide semiconductor film which is highly purified by removing hydrogen, water, or the like as much as possible can be manufactured. Thus, the negative shift in the threshold voltage can be reduced and leakage current between a source electrode and a drain electrode of a transistor, typically, the off-state current per channel width can be reduced to several yA/μm to several zA/μm; thus, electrical characteristics of the transistor can be improved. From the above, according to this embodiment, a transistor in which the negative shift in the threshold voltage is reduced and the leakage current is reduced, and whose electrical characteristics are excellent can be manufactured.
Embodiment 5
0219A semiconductor device (also referred to as a display device) having a display function can be manufactured using the transistor examples of which are shown in the above embodiments. Moreover, some or all of the driver circuits which include the transistor can be formed over a substrate where the pixel portion is formed, whereby a system-on-panel can be obtained. In this embodiment, an example of a display device using the transistor examples of which are shown in the above embodiments is described with reference to <figref idref="DRAWINGS">FIGS. 5A to 5C</figref> and <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>. <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are cross-sectional views illustrating cross-sectional structures taken along chain line M-N in <figref idref="DRAWINGS">FIG. 5B</figref>.
0220In <figref idref="DRAWINGS">FIG. 5A</figref>, a sealant <b>905</b> is provided so as to surround a pixel portion <b>902</b> provided over a first substrate <b>901</b>, and the pixel portion <b>902</b> is sealed with a second substrate <b>906</b>. In <figref idref="DRAWINGS">FIG. 5A</figref>, a signal line driver circuit <b>903</b> and a scan line driver circuit <b>904</b> each are formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate prepared separately, and mounted in a region different from the region surrounded by the sealant <b>905</b> over the first substrate <b>901</b>. Further, various signals and potentials are supplied to the signal line driver circuit <b>903</b>, the scan line driver circuit <b>904</b>, and the pixel portion <b>902</b> from flexible printed circuits (FPCs) <b>918</b><i>a </i>and <b>918</b><i>b. </i>
0221In <figref idref="DRAWINGS">FIGS. 5B and 5C</figref>, the sealant <b>905</b> is provided so as to surround the pixel portion <b>902</b> and the scan line driver circuit <b>904</b> which are provided over the first substrate <b>901</b>. The second substrate <b>906</b> is provided over the pixel portion <b>902</b> and the scan line driver circuit <b>904</b>. Thus, the pixel portion <b>902</b> and the scan line driver circuit <b>904</b> are sealed together with a display element by the first substrate <b>901</b>, the sealant <b>905</b>, and the second substrate <b>906</b>. In <figref idref="DRAWINGS">FIGS. 5B and 5C</figref>, a signal line driver circuit <b>903</b> which is formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant <b>905</b> over the first substrate <b>901</b>. In <figref idref="DRAWINGS">FIGS. 5B and 5C</figref>, various signals and potentials are supplied to the signal line driver circuit <b>903</b> which is separately formed, the scan line driver circuit <b>904</b>, and the pixel portion <b>902</b> from an FPC <b>918</b>.
0222Although <figref idref="DRAWINGS">FIGS. 5B and 5C</figref> each show an example in which the signal line driver circuit <b>903</b> is formed separately and mounted on the first substrate <b>901</b>, one embodiment of the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.
0223Note that a connection method of a separately formed driver circuit is not particularly limited, and a chip on glass (COG) method, a wire bonding method, a tape automated bonding (TAB) method, or the like can be used. <figref idref="DRAWINGS">FIG. 5A</figref> shows an example in which the signal line driver circuit <b>903</b> and the scan line driver circuit <b>904</b> are mounted by a COG method. <figref idref="DRAWINGS">FIG. 5B</figref> shows an example in which the signal line driver circuit <b>903</b> is mounted by a COG method. <figref idref="DRAWINGS">FIG. 5C</figref> shows an example in which the signal line driver circuit <b>903</b> is mounted by a TAB method.
0224The display device includes in its category a panel in which a display element is sealed and a module in which an IC including a controller or the like is mounted on the panel.
0225A display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, the display device also includes the following modules in its category: a module to which a connector such as an FPC or a TCP is attached; a module having a TCP at the tip of which a printed wiring board is provided; and a module in which an integrated circuit (IC) is directly mounted on a display element by a COG method.
0226The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors and any of the transistors which are described in the above embodiments can be used.
0227As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. A light emitting element includes, in its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.
0228As illustrated in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, the semiconductor device includes a connection terminal electrode <b>915</b> and a terminal electrode <b>916</b>. The connection terminal electrode <b>915</b> and the terminal electrode <b>916</b> are electrically connected to a terminal included in the FPC <b>918</b> through an anisotropic conductive agent <b>919</b>.
0229The connection terminal electrode <b>915</b> is formed using the same conductive film as a first electrode <b>930</b>, and the terminal electrode <b>916</b> is formed using the same conductive film as a pair of electrodes in each of a transistor <b>910</b> and a transistor <b>911</b>.
0230Each of the pixel portion <b>902</b> and the scan line driver circuit <b>904</b> which are provided over the first substrate <b>901</b> includes a plurality of transistors. <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> illustrate the transistor <b>910</b> included in the pixel portion <b>902</b> and the transistor <b>911</b> included in the scan line driver circuit <b>904</b>. In <figref idref="DRAWINGS">FIG. 6A</figref>, the protective film <b>25</b> described in any of Embodiments 1 to 3 or an insulating film <b>924</b> corresponding to a stacked film of the protective film <b>25</b> and a silicon nitride film is provided over the transistor <b>910</b> and the transistor <b>911</b>. In <figref idref="DRAWINGS">FIG. 6B</figref>, a planarization film <b>921</b> is further provided over the insulating film <b>924</b>. Note that an insulating film <b>923</b> serves as a base film.
0231In this embodiment, any of the transistors described in the above embodiments can be used as the transistor <b>910</b> and the transistor <b>911</b>.
0232Moreover, <figref idref="DRAWINGS">FIG. 6B</figref> shows an example in which a conductive film <b>917</b> is provided over the insulating film <b>924</b> so as to overlap with a channel region of the oxide semiconductor film of the transistor <b>911</b> for the driver circuit. In this embodiment, the conductive film <b>917</b> is formed using the same conductive film as the first electrode <b>930</b>. By providing the conductive film <b>917</b> so as to overlap with the channel region of the oxide semiconductor film, the amount of change in the threshold voltage of the transistor <b>911</b> between before and after a BT stress test can be further reduced. The conductive film <b>917</b> may have the same potential as or a potential different from that of the gate electrode of the transistor <b>911</b>, and the conductive film <b>917</b> can serve as a second gate electrode. The potential of the conductive film <b>917</b> may be GND, 0 V or in a floating state.
0233In addition, the conductive film <b>917</b> has a function of blocking an external electric field. In other words, the conductive film <b>917</b> has a function of preventing an external electric field (particularly, a function of preventing static electricity) from affecting the inside (a circuit portion including the transistor). Such a blocking function of the conductive film <b>917</b> can prevent change in electrical characteristics of the transistor due to the influence of an external electric field such as static electricity. The conductive film <b>917</b> can be used for any of the transistors described in the above embodiments.
0234In the display panel, the transistor <b>910</b> included in the pixel portion <b>902</b> is electrically connected to a display element. There is no particular limitation on the kind of the display element as long as display can be performed, and various kinds of display elements can be used.
0235An example of a liquid crystal display device using a liquid crystal element as the display element is shown in <figref idref="DRAWINGS">FIG. 6A</figref>. In <figref idref="DRAWINGS">FIG. 6A</figref>, a liquid crystal element <b>913</b> which is a display element includes the first electrode <b>930</b>, a second electrode <b>931</b>, and a liquid crystal layer <b>908</b>. Note that an insulating film <b>932</b> and an insulating film <b>933</b> which serve as alignment films are provided so that the liquid crystal layer <b>908</b> is provided therebetween. The second electrode <b>931</b> is provided on the second substrate <b>906</b> side. The second electrode <b>931</b> overlaps with the first electrode <b>930</b> with the liquid crystal layer <b>908</b> provided therebetween.
0236The first electrode <b>930</b> and the second electrode <b>931</b> can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
0237Alternatively, the first electrode <b>930</b> and the second electrode <b>931</b> can be formed using one or more materials selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); an alloy of any of these metals; and a nitride of any of these metals.
0238The first electrode <b>930</b> and the second electrode <b>931</b> can be formed using a conductive composition including a conductive macromolecule (also referred to as a conductive polymer). The conductive macromolecule, known as a π-electron conjugated conductive macromolecule, can be used. Polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given as examples.
0239A spacer <b>935</b> is a columnar spacer obtained by selective etching of an insulating film and is provided in order to control the distance between the first electrode <b>930</b> and the second electrode <b>931</b> (a cell gap). Alternatively, a spherical spacer may be used.
0240In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on a condition.
0241Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition which includes a liquid crystal showing a blue phase and a chiral agent has a short response time of 1 msec or less, and has optical isotropy, which makes the alignment process unneeded and viewing angle dependence small. In addition, since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Thus, the productivity of the liquid crystal display device can be increased.
0242The first substrate <b>901</b> and the second substrate <b>906</b> are fixed in place by the sealant <b>905</b>. As the sealant <b>905</b>, an organic resin such as a thermosetting resin or a photocurable resin can be used.
0243The amount of change in the threshold voltage of any of the transistor including an oxide semiconductor film used in the above embodiments is small. Moreover, such a transistor can operate at a high speed because a relatively high field-effect mobility can be obtained. Thus, when the above transistor is used in a pixel portion of a semiconductor device having a display function, high-quality images can be obtained. Since a driver circuit portion and the pixel portion can be formed separately over one substrate, the number of components of the semiconductor device can be reduced.
0244The size of storage capacitor formed in the liquid crystal display device is set considering the leakage current of the transistor provided in the pixel portion or the like so that charge can be held for a predetermined period. By using the transistor including the highly-purified oxide semiconductor film, it is enough to provide a storage capacitor having a capacitance that is ⅓ or less, preferably ⅕ or less of a liquid crystal capacitance of each pixel; therefore, the aperture ratio of a pixel can be increased.
0245In the display device, a black matrix (a light-blocking film), an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like are provided as appropriate. For example, circular polarization may be obtained by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source.
0246As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, R, G, B, and W (W corresponds to white), or R, G, B, and one or more of yellow, cyan, magenta, and the like can be used. Further, the sizes of display regions may be different between respective dots of color elements. The present invention is not limited to the application to a display device for color display but can also be applied to a display device for monochrome display.
0247Here, a structure of a periphery portion of the liquid crystal display device is described with reference to <figref idref="DRAWINGS">FIGS. 7A and 7B</figref>, <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>, and <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>.
0248In the liquid crystal display device, a liquid crystal element can be an element in which a liquid crystal is provided between a counter electrode and a pixel electrode electrically connected to a switching element. In many cases, the counter electrodes have the same potential in the entire pixel portion. Therefore, the counter electrode is also referred to as a connection terminal or a common electrode. Note that the potential of the counter electrode is controlled by a peripheral circuit such as a driver circuit. The potential of the counter electrode is adjusted in accordance with a potential of a signal line which is actually applied to the pixel electrode. When the potential of the signal line which is actually applied to the pixel electrode is changed, a defect might occur in a display screen; therefore, the potential of the counter electrode is preferred to be optimized so as to correspond to the center of potential amplitude of the pixel electrode. Next, a liquid crystal display device including a first counter electrode provided in a driver circuit portion (a scan line driver circuit and a signal line driver circuit) and a second counter electrode provided in a pixel portion, which can be supplied with different potentials, is described.
0249<figref idref="DRAWINGS">FIG. 7A</figref> is a top view of the liquid crystal display device. The top view of <figref idref="DRAWINGS">FIG. 7A</figref> illustrates any of the display devices illustrated in <figref idref="DRAWINGS">FIGS. 5A to 5C</figref> in which an FPC has not been attached to a first substrate <b>1210</b>. <figref idref="DRAWINGS">FIG. 7B</figref> is a cross-sectional view taken along chain line E-F of <figref idref="DRAWINGS">FIG. 7A</figref>, which illustrates a connection region of a conductive particle and a connection wiring.
0250In the liquid crystal display device, the first substrate <b>1210</b> which is provided with pixel electrodes each electrically connected to a switching element, and a second substrate <b>1204</b> provided with a first counter electrode <b>1291</b> and a second counter electrode <b>1292</b> are attached to each other with a sealant <b>1205</b>, and the interior space surrounded by the sealant <b>1205</b> is filled with a liquid crystal <b>1280</b>. A signal line driver circuit <b>1200</b>, a scan line driver circuit <b>1201</b>, and a pixel portion <b>1202</b> in which the pixel electrodes are formed in a matrix form are provided over the first substrate <b>1210</b>.
0251The second counter electrode <b>1292</b> provided over the driver circuit portion has a potential which is different from that of the first counter electrode <b>1291</b>. Different potentials can be supplied to the first counter electrode <b>1291</b> provided in the pixel portion <b>1202</b> and the second counter electrode <b>1292</b> provided in the driver circuit portion.
0252A potential difference (voltage) is applied to the pixel electrode through the switching element. Therefore, there is a possibility that the voltage applied to the pixel electrode is smaller by the voltage which is actually applied to a wiring connected to the switching element several volts, which is several volts. Thus, it is preferred that a potential difference (voltage) applied to the first counter electrode <b>1291</b> be set in consideration of the difference.
0253The second counter electrode <b>1292</b> provided in the driver circuit portion has a flat shape and may be processed into a pattern having an opening. By processing the second counter electrode <b>1292</b> into the pattern having an opening, parasitic capacitance formed between the second counter electrode <b>1292</b> and a conductive film included in a transistor provided in the driver circuit portion can be reduced. Accordingly, low power consumption of the liquid crystal display device can be achieved.
0254In this specification, a pattern having an opening (a slit) of the second counter electrode <b>1292</b> in the driver circuit portion includes patterns which are partly opened, such as a bend portion and a branching comb-like portion as well as a pattern which is opened in a closed space.
0255Further, a terminal portion <b>1240</b> is formed in an edge portion of the first substrate <b>1210</b>. <figref idref="DRAWINGS">FIG. 7B</figref> shows an example of a cross-sectional structure of the terminal portion <b>1240</b>.
0256<figref idref="DRAWINGS">FIG. 7B</figref> is a cross-sectional view of a region where an upper wiring and a lower wiring are electrically connected to each other with conductive particles <b>1270</b> contained in a resin layer <b>1235</b>. A connection wiring <b>1208</b> is formed over the first substrate <b>1210</b>. A connection terminal <b>1241</b> which is formed at the same time as the pixel electrode is formed over the connection wiring <b>1208</b>. The connection terminal <b>1241</b> is electrically connected to the first counter electrode <b>1291</b> through the connection wiring <b>1208</b> and the conductive particles <b>1270</b>. Further, the connection terminal <b>1241</b> is connected to an FPC (not illustrated). Note that in <figref idref="DRAWINGS">FIG. 7B</figref>, the conductive particles <b>1270</b> are fixed by the resin layer <b>1235</b>. The resin layer <b>1235</b> can be formed using an organic resin or a fitted glass like that used for the sealant <b>1205</b>.
0257As the conductive particle <b>1270</b>, a conductive particle in which an insulating sphere is covered with a thin metal film can be used. The insulating sphere is formed using silica glass, hard resin, or the like. The thin metal film can be formed to have a single-layer structure or a stacked-layer structure using one or more of gold, silver, palladium, nickel, indium tin oxide, and indium zinc oxide. For example, as each metal thin film, a gold thin film, a stack of a nickel thin film and a gold thin film, or the like can be used. By using the conductive particle <b>1270</b> in which the insulating sphere is contained at the center, elasticity can be improved so that destruction due to external pressure can be reduced.
0258The space around the conductive particles <b>1270</b> may be provided with a conductive resin layer formed with a conductive polymer instead of an insulating resin layer. As typical examples of the conductive polymer, conductive polyaniline, conductive polypyrrole, conductive polythiophene, a complex of polyethylenedioxythiophene (PEDOT) and poly(styrenesulfonic acid) (PSS), and the like can be cited. That is, when the conductive polymer is in contact with the counter electrode or the connection wiring, the conductive particle <b>1270</b> and the conductive polymer are in contact with the counter electrode and the connection wiring, so that connection resistance between the counter electrode and the connection wiring can be reduced.
0259Note that the connection wiring <b>1208</b> and the first counter electrode <b>1291</b> formed on the second substrate <b>1204</b> are electrically connected to each other through the conductive particles <b>1270</b>. Further, a connection wiring <b>1209</b> and the second counter electrode <b>1292</b> formed on the second substrate <b>1204</b> are electrically connected to each other through a conductive particle <b>1271</b> (see <figref idref="DRAWINGS">FIG. 7A</figref>). The connection wiring <b>1209</b> and the connection wiring <b>1208</b> have different potentials.
0260Here, cross-sectional views of a common connection portion (also referred to as a common contact portion) for electrically connecting the counter electrodes (the first counter electrode <b>1291</b> and the second counter electrode <b>1292</b>) provided on the second substrate <b>1204</b> to the terminal portion <b>1240</b> and top views of the common connection portion are shown in <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> and <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>. Note that an example in which the common connection portion is formed over the first substrate <b>1210</b> is shown. In <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> and <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, a transistor <b>1211</b> included in the pixel portion <b>1202</b> is formed over the first substrate <b>1210</b>, in addition to the common connection portion. The common connection portion is formed through the same process as the transistor <b>1211</b> of the pixel portion <b>1202</b>, whereby the common connection portion can be formed without complicating the process. Moreover, over the first substrate <b>1210</b>, not only the pixel portion <b>1202</b> but also a driver circuit (the scan line driver circuit <b>1201</b>) may be formed in addition to the common connection portion, or the common connection portion may be formed through the same process as the transistors <b>910</b> and <b>911</b> included in the driver circuit (the scan line driver circuit <b>1201</b>) (see <figref idref="DRAWINGS">FIG. 6A</figref>).
0261In this embodiment, the common connection portion is provided in a position which does not overlap with the sealant (except for the pixel portion) and a paste including conductive particles is provided separately from the sealant so as to overlap with the common connection portion, whereby the common connection portion can be electrically connected to the counter electrodes. Note that the common connection portion is provided in a position overlapping with the sealant <b>1205</b> for bonding the first substrate <b>1210</b> and the second substrate <b>1204</b> and may be electrically connected to the counter electrodes through the conductive particles <b>1270</b> contained in the sealant <b>1205</b>.
0262In <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>, a common connection portion in which a connection wiring <b>1251</b> is formed with a wiring formed using the same material and through the same process as a wiring (gate wiring) processed into a gate electrode is illustrated.
0263In <figref idref="DRAWINGS">FIG. 8A</figref>, the transistor <b>1211</b> which is electrically connected to a pixel electrode <b>1250</b> is a channel-etched transistor. Any of the transistors described in the above embodiments can be used as appropriate as the transistor <b>1211</b>.
0264<figref idref="DRAWINGS">FIG. 8B</figref> shows an example of the top view of the common connection portion, and chain line I-J in <figref idref="DRAWINGS">FIG. 8B</figref> corresponds to a cross section of the common connection portion of <figref idref="DRAWINGS">FIG. 8A</figref>. Note that in <figref idref="DRAWINGS">FIG. 8B</figref>, portions the same as those in <figref idref="DRAWINGS">FIG. 8A</figref> are denoted by the same reference numerals. Here, the connection terminal <b>1241</b> is not illustrated in a hatching pattern but indicated by a broken line in order to avoid complexity of the drawing.
0265The connection wiring <b>1251</b> is provided over a gate insulating film <b>1253</b> and is formed using the same material and through the same process as a source electrode <b>1259</b> and a drain electrode <b>1261</b> of the transistor <b>1211</b>.
0266The connection wiring <b>1251</b> is covered with a protective film <b>1255</b>. The protective film <b>1255</b> has a plurality of openings in positions overlapping with the connection wiring <b>1251</b>. These openings are formed through the same process as a contact hole that connects the drain electrode <b>1261</b> of the transistor <b>1211</b> and the pixel electrode <b>1250</b>.
0267Note that the contact hole in the pixel portion and the openings in the common connection portion are distinctively described because their sizes differ considerably. In <figref idref="DRAWINGS">FIG. 8A</figref>, the pixel portion <b>1202</b> and the common connection portion are not illustrated on the same scale. For example, the length of the chain line I-J in the common connection portion is about 500 μm, whereas the size of the transistor of the pixel portion <b>1202</b> is less than 50 μm; thus, the area of the common connection portion is ten times or more as large as that of the transistor. However, the scales of the pixel portion <b>1202</b> and the common connection portion are changed in <figref idref="DRAWINGS">FIG. 8A</figref> for simplification.
0268Moreover, the connection terminal <b>1241</b> is provided over the protective film <b>1255</b> and is formed using the same material and through the same process as the pixel electrode <b>1250</b> in the pixel portion <b>1202</b>.
0269In this manner, the common connection portion is manufactured through the same process as the transistor <b>1211</b> in the pixel portion <b>1202</b>. The connection wiring <b>1251</b> is preferred to have a structure with which wiring resistance as a metal wiring can be reduced.
0270Then, the first substrate <b>1210</b> provided with the pixel portion <b>1202</b> and the common connection portion is fixed to the second substrate <b>1204</b> provided with the counter electrodes with the sealant <b>1205</b>.
0271Note that the connection terminal <b>1241</b> is electrically connected to the counter electrodes on the second substrate <b>1204</b> through the conductive particles <b>1270</b> illustrated in <figref idref="DRAWINGS">FIG. 7B</figref>.
0272Next, a common connection portion whose structure is partly different from that of the common connection portion illustrated in <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> will be described with reference to <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>. In <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, a common connection portion in which a connection electrode <b>1267</b> formed using the same material and through the same process as a gate wiring is provided, and in which a wiring formed using the same material and through the same process as the source electrode <b>1259</b> and the drain electrode <b>1261</b> (a source wiring and a drain wiring) is provided as a connection wiring <b>1263</b> connected to the connection electrode <b>1267</b> will be illustrated in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>.
0273<figref idref="DRAWINGS">FIG. 9B</figref> shows an example of the top view of the common connection portion, and chain line L-M in <figref idref="DRAWINGS">FIG. 9B</figref> corresponds to a cross section of the common connection portion of <figref idref="DRAWINGS">FIG. 9A</figref>. Here, a connection terminal <b>1265</b> is not illustrated in a hatching pattern but indicated by a broken line in order to avoid complexity of the drawing.
0274The connection electrode <b>1267</b> is provided over the first substrate <b>1210</b> and is formed using the same material and through the same process as the gate electrode of the transistor <b>1211</b>.
0275The connection electrode <b>1267</b> is covered with the gate insulating film <b>1253</b> and the protective film <b>1255</b>. The gate insulating film <b>1253</b> and the protective film <b>1255</b> have an opening <b>1260</b> at a position overlapping with the connection electrode <b>1267</b>. Note that this opening <b>1260</b> is formed by etching through the same process as the contact hole that connects the drain electrode <b>1261</b> and the pixel electrode <b>1250</b>, and then further by etching the gate insulating film <b>1253</b> selectively.
0276A connection wiring <b>1263</b> is provided over the gate insulating film <b>1253</b> and is formed using the same material and through the same process as the source electrode <b>1259</b> and the drain electrode <b>1261</b>.
0277The connection wiring <b>1263</b> is covered with the protective film <b>1255</b>. The protective film <b>1255</b> has a plurality of openings <b>1262</b> in positions overlapping with the connection wiring <b>1263</b>. These openings <b>1262</b> are formed through the same process as the contact hole that connects the drain electrode <b>1261</b> and the pixel electrode <b>1250</b>.
0278Moreover, the connection terminal <b>1265</b> is provided over the protective film <b>1255</b> and is formed using the same material and through the same process as the pixel electrode <b>1250</b> in the pixel portion <b>1202</b>.
0279In this manner, the common connection portion is formed through the same process as the transistor <b>1211</b> of the pixel portion <b>1202</b>.
0280Further, in the common connection portion illustrated in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, a plurality of conductive particles are selectively disposed only in the opening <b>1260</b> of the gate insulating film <b>1253</b>. That is, the plurality of conductive particles are disposed in a region where the connection terminal <b>1265</b> and the connection electrode <b>1267</b> are in contact with each other. The connection terminal <b>1265</b> in contact with both the connection electrode <b>1267</b> and the connection wiring <b>1263</b> is an electrode which is in contact with the conductive particles and is electrically connected to the counter electrodes of the second substrate <b>1204</b>.
0281Although an example of the common connection portion electrically connected to the counter electrodes is shown here, such a common connection portion can be used as a connection portion connected to another wiring or a connection portion connected to an external connection terminal or the like without being limited to the above example. Note that the structure of the common connection portion illustrated in FIGS. <b>8</b>A and <b>8</b>B and the structure of the common connection portion illustrated in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref> can be combined freely.
0282Next, as the display element included in the display device, a light-emitting element utilizing electroluminescence can be used. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.
0283In the organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.
0284The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. The dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an example of an organic EL element as a light-emitting element is described here.
0285In order to extract light emitted from the light-emitting element, it is acceptable as long as at least one of a pair of electrodes is transparent. A transistor and a light-emitting element are formed over a substrate. The light-emitting element can have a top emission structure in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure in which light emission is extracted through the surface on the substrate side; or a dual emission structure in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side, and a light-emitting element having any of these emission structures can be used.
0286An example of a light-emitting device using a light-emitting element as the display element is shown in <figref idref="DRAWINGS">FIG. 6B</figref>. A light-emitting element <b>963</b> which is a display element is electrically connected to the transistor <b>910</b> provided in the pixel portion <b>902</b>. Note that although the structure of the light-emitting element <b>963</b> is a stacked-layer structure of the first electrode <b>930</b>, a light-emitting layer <b>961</b>, and the second electrode <b>931</b>, the structure is not limited thereto. The structure of the light-emitting element <b>963</b> can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element <b>963</b>, or the like.
0287A partition wall <b>960</b> can be formed using an organic insulating material or an inorganic insulating material. It is particularly preferred that the partition wall <b>960</b> be formed using a photosensitive resin material to have an opening over the first electrode <b>930</b> so that a sidewall of the opening has an inclined surface with a continuous curvature.
0288The light-emitting layer <b>961</b> may be formed to have a single-layer structure or a stacked-layer structure including a plurality of layers.
0289A protective layer may be formed over the second electrode <b>931</b> and the partition wall <b>960</b> in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element <b>963</b>. As the protective layer, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a DLC film, or the like can be formed. In addition, in a space which is sealed with the first substrate <b>901</b>, the second substrate <b>906</b>, and a sealant <b>936</b>, a filler <b>964</b> is provided and sealed. It is preferred that, in this manner, the light-emitting element be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air.
0290As the sealant <b>936</b>, an organic resin such as a thermosetting resin or a photocurable resin, fritted glass including low-melting glass, or the like can be used. The fritted glass is preferred because of its high barrier property against impurities such as water and oxygen. When the fitted glass is used for the sealant <b>936</b>, the fritted glass is preferred to be provided over the insulating film <b>924</b> as illustrated in <figref idref="DRAWINGS">FIG. 6B</figref>. Since the insulating film <b>924</b> is any of the protective films <b>25</b> described in Embodiments 1 to 3 or an inorganic insulating film corresponding to a stacked film of the protective film <b>25</b> and a silicon nitride film, the insulating film <b>924</b> can have higher adhesion to the fritted glass.
0291As the filler <b>964</b>, as well as an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used: polyvinyl chloride (PVC), an acrylic resin, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), ethylene vinyl acetate (EVA), or the like can be used. For example, nitrogen is used for the filler.
0292If necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate for a light-emitting surface of the light-emitting element. Further, a polarizing plate or a circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.
0293The first electrode and the second electrode (each of which are also referred to as a pixel electrode, a connection terminal, a counter electrode layer, or the like) for applying voltage to the display element can have light-transmitting properties or light-reflecting properties, which depends on the direction in which light is extracted, the position where the electrodes are provided, and the pattern structure of the electrodes.
0294Since the transistor is easily broken owing to static electricity or the like, a protective circuit for protecting the driver circuit is preferred to be provided. The protection circuit is preferred to be formed using a nonlinear element.
0295As described above, by using any of the transistors described in the above embodiments, a highly reliable semiconductor device having a display function can be provided.
0296This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.
Embodiment 6
0297A semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of the electronic devices include television sets (also referred to as televisions or television receivers), monitors of computers or the like, cameras such as digital cameras or digital video cameras, digital photo frames, cellular phones (also referred to as mobile phones or cellular phone sets), portable game consoles, portable information terminals, audio reproducing devices, large-sized game machines such as pachinko machines, electronic paper, and the like. The electronic paper can be used for electronic devices for displaying information in a variety of fields. For example, the electronic paper can be applied to an electronic book (e-book) reader, a poster, an advertisement in a vehicle such as a train, a digital signage, a public information display (PID), displays of various cards such as a credit card, and the like. The portable information terminal which is an example of electronic devices is described with reference to <figref idref="DRAWINGS">FIGS. 10A to 10C</figref>.
0298<figref idref="DRAWINGS">FIGS. 10A and 10B</figref> illustrate a foldable tablet terminal. <figref idref="DRAWINGS">FIG. 10A</figref> illustrates the tablet terminal which is unfolded. The tablet terminal includes a housing <b>9630</b>, a display portion <b>9631</b><i>a</i>, a display portion <b>9631</b><i>b</i>, a display mode switch <b>9034</b>, a power switch <b>9035</b>, a power-saving mode switch <b>9036</b>, a clasp <b>9033</b>, and an operation switch <b>9038</b>.
0299Part of the display portion <b>9631</b><i>a </i>can be a touch panel region <b>9632</b><i>a</i>, and data can be input by touching operation keys <b>9638</b> that are displayed. Although a structure in which a half region in the display portion <b>9631</b><i>a </i>has only a display function and the other half region has a touch panel function is shown as an example, the display portion <b>9631</b><i>a </i>is not limited to this structure. The whole region in the display portion <b>9631</b><i>a </i>may have a touch panel function. For example, the display portion <b>9631</b><i>a </i>can display keyboard buttons in the whole region to be a touch panel, and the display portion <b>9631</b><i>b </i>can be used as a display screen.
0300In a manner similar to that of the display portion <b>9631</b><i>a</i>, part of the display portion <b>9631</b><i>b </i>can be a touch panel region <b>9632</b><i>b</i>. When a keyboard display switching button <b>9639</b> displayed on the touch panel is touched with a finger, a stylus, or the like, a keyboard can be displayed on the display portion <b>9631</b><i>b. </i>
0301Touch input can be performed in the touch panel region <b>9632</b><i>a </i>and the touch panel region <b>9632</b><i>b </i>at the same time.
0302The display mode switch <b>9034</b> can switch the display between a portrait mode and a landscape mode, and between monochrome display and color display, for example. The power-saving mode switch <b>9036</b> can control display luminance to be optimal in accordance with the amount of external light in use of the tablet terminal which is detected by an optical sensor incorporated in the tablet terminal. Another detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, may be incorporated in the tablet terminal, in addition to the optical sensor.
0303Although the display portion <b>9631</b><i>a </i>and the display portion <b>9631</b><i>b </i>have the same display area in <figref idref="DRAWINGS">FIG. 10A</figref> as an example, one embodiment of the present invention is not particularly limited to this example. The display portion <b>9631</b><i>a </i>and the display portion <b>9631</b><i>b </i>may have different areas or different display quality. For example, higher definition images may be displayed on one of the display portion <b>9631</b><i>a </i>and the display portion <b>9631</b><i>b. </i>
0304<figref idref="DRAWINGS">FIG. 10B</figref> illustrates the tablet terminal which is folded. The tablet terminal includes the housing <b>9630</b>, a solar battery <b>9633</b>, a charge and discharge control circuit <b>9634</b>, a battery <b>9635</b>, and a DC-DC converter <b>9636</b>. As an example, <figref idref="DRAWINGS">FIG. 10B</figref> illustrates the charge and discharge control circuit <b>9634</b> including the battery <b>9635</b> and the DC-DC converter <b>9636</b>.
0305Since the tablet terminal can be folded, the housing <b>9630</b> can be closed when not in use. Thus, the display portion <b>9631</b><i>a </i>and the display portion <b>9631</b><i>b </i>can be protected, which makes it possible to provide a tablet terminal with high durability and improved reliability for long-term use.
0306The tablet terminal illustrated in <figref idref="DRAWINGS">FIGS. 10A and 10B</figref> can also have a function of displaying various kinds of data (e.g., a still image, a moving image, and a text image), a function of displaying a calendar, the date, the time, or the like on the display portion, a touch-input function of operating or editing data displayed on the display portion by touch input, a function of controlling processing by various kinds of software (programs), and the like.
0307The solar battery <b>9633</b>, which is attached on a surface of the tablet terminal, can supply electric power to a touch panel, a display portion, an image signal processor, and the like. Note that the solar battery <b>9633</b> can be provided on one or both surfaces of the housing <b>9630</b>, so that the battery <b>9635</b> can be charged efficiently.
0308The structure and operation of the charge and discharge control circuit <b>9634</b> illustrated in <figref idref="DRAWINGS">FIG. 10B</figref> is described with reference to a block diagram in <figref idref="DRAWINGS">FIG. 10C</figref>. <figref idref="DRAWINGS">FIG. 10C</figref> illustrates the solar battery <b>9633</b>, the battery <b>9635</b>, the DC-DC converter <b>9636</b>, a converter <b>9637</b>, switches SW<b>1</b> to SW<b>3</b>, and the display portion <b>9631</b>. The battery <b>9635</b>, the DC-DC converter <b>9636</b>, the converter <b>9637</b>, and the switches SW<b>1</b> to SW<b>3</b> correspond to the charge and discharge control circuit <b>9634</b> illustrated in <figref idref="DRAWINGS">FIG. 10B</figref>.
0309First, an example of operation in the case where power is generated by the solar battery <b>9633</b> using external light is described. The voltage of power generated by the solar battery <b>9633</b> is raised or lowered by the DC-DC converter <b>9636</b> so that a voltage for charging the battery <b>9635</b> is obtained. When the display portion <b>9631</b> is operated with the power from the solar battery <b>9633</b>, the switch SW<b>1</b> is turned on and the voltage of the power is raised or lowered by the converter <b>9637</b> to a voltage needed for operating the display portion <b>9631</b>. In addition, when display on the display portion <b>9631</b> is not performed, the switch SW<b>1</b> is turned off and the switch SW<b>2</b> is turned on so that charge of the battery <b>9635</b> may be performed.
0310Although the solar battery <b>9633</b> is shown as an example of a power generation means, there is no particular limitation on the power generation means and the battery <b>9635</b> may be charged with another power generation means such as a piezoelectric element or a thermoelectric conversion element (Peltier element). For example, the battery <b>9635</b> may be charged with a non-contact power transmission module which is capable of charging by transmitting and receiving power by wireless (without contact), or another charge means used in combination.
0311This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.
Example 1
0312In this example, measurement results of a BT stress test and a BT photostress test of a transistor included in a semiconductor device of one embodiment of the present invention will be described. Specifically, the amounts of change in the threshold voltage and shift value of the transistor of one embodiment of the present invention will be described.
0313First of all, a manufacturing process of a transistor included in each of a sample A<b>1</b>, a sample A<b>2</b>, a sample A<b>3</b>, and a sample A<b>4</b> is described. Description in this example is made with reference to <figref idref="DRAWINGS">FIGS. 2A to 2D</figref> and <figref idref="DRAWINGS">FIG. 3</figref>.
0314First, a glass substrate was used as the substrate <b>11</b>, and the gate electrode <b>15</b> was formed over the substrate <b>11</b>.
0315The gate electrode <b>15</b> was formed as follows: a 100-nm-thick tungsten film was formed by a sputtering method, a mask was formed over the tungsten film by a photolithography process, and the tungsten film was partly etched using the mask.
0316Next, the gate insulating film <b>18</b> including the insulating film <b>16</b> and the insulating film <b>17</b> (see <figref idref="DRAWINGS">FIG. 3</figref>) was formed over the gate electrode <b>15</b>.
0317A 50-nm-thick silicon nitride film was formed as the insulating film <b>16</b>, and a 200-nm-thick silicon oxynitride film was formed as the insulating film <b>17</b>. The silicon nitride film was formed under the following conditions: silane with a flow rate of 50 sccm and nitrogen with a flow rate of 5000 sccm were supplied to a treatment chamber of a plasma CVD apparatus, the pressure in the treatment chamber was controlled to 60 Pa, and the power of 150 W was supplied with the use of a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm were supplied to a treatment chamber of the plasma CVD apparatus, the pressure in the treatment chamber was controlled to 40 Pa, and the power of 100 W was supplied with the use of a 27.12 MHz high-frequency power source. Note that each of the silicon nitride film and the silicon oxynitride film was formed at a substrate temperature of 350° C.
0318<figref idref="DRAWINGS">FIG. 2A</figref> can be referred to for the structure obtained through the steps up to here. Note that although the base insulating film <b>13</b> is illustrated in <figref idref="DRAWINGS">FIG. 2A</figref>, the base insulating film <b>13</b> was not formed in this example.
0319Next, the oxide semiconductor film <b>19</b> overlapping with the gate electrode <b>15</b> with the gate insulating film <b>18</b> provided therebetween was formed.
0320Here, an IGZO film which was a CAAC-OS film was formed over the gate insulating film <b>18</b> by a sputtering method, a mask is formed over the IGZO film by a photolithography process, and the IGZO film was partly etched using the mask. Then, the etched IGZO film was subjected to heat treatment, so that the oxide semiconductor film <b>19</b> was formed. In this example, a 35-nm-thick IGZO film was formed.
0321The IGZO film was formed under the following conditions: a sputtering target containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used, argon with a flow rate of 50 sccm and oxygen with a flow rate of 50 sccm were supplied as a sputtering gas to a treatment chamber of a sputtering apparatus, the pressure in the treatment chamber was controlled to be 0.6 Pa, and the direct current power of 5 kW was supplied. Note that the IGZO film was formed at a substrate temperature of 170° C.
0322As the heat treatment, heat treatment at 450° C. under a nitrogen atmosphere for one hour and then heat treatment at 450° C. under a mixed atmosphere of nitrogen and oxygen for one hour were performed.
0323<figref idref="DRAWINGS">FIG. 2B</figref> can be referred to for the structure obtained through the steps up to here.
0324Next, the pair of electrodes <b>21</b> which was in contact with the oxide semiconductor film <b>19</b> was formed.
0325A conductive film was formed over the gate insulating film <b>18</b> and the oxide semiconductor film <b>19</b>, a mask was formed over the conductive film by a photolithography process, and the conductive film was partly etched using the mask, so that the pair of electrodes <b>21</b> was formed. Note that as the conductive film, a 400-nm-thick aluminum film was formed over a 50-nm-thick tungsten film, and a 100-nm-thick titanium film was formed over the aluminum film.
0326Next, the substrate was moved to a treatment chamber filled with dinitrogen monoxide. Then, the oxide semiconductor film <b>20</b> illustrated in <figref idref="DRAWINGS">FIG. 2D</figref> was formed by exposing the oxide semiconductor film <b>19</b> to oxygen plasma which was generated in such a manner that an upper electrode provided in the treatment chamber was supplied with high-frequency power of 150 W with the use of a 27.12 MHz high-frequency power source.
0327Next, the insulating film <b>23</b> was formed in succession over the oxide semiconductor film <b>20</b> and the pair of electrodes <b>21</b> without exposure to the atmosphere after the above plasma treatment. As the insulating film <b>23</b>, a silicon oxynitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 30 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as a source gas, the pressure in a treatment chamber was 40 Pa, the substrate temperature was 220° C., and the high-frequency power of 150 W was supplied to an upper electrode of parallel plate electrodes. A sample in which the thickness of the insulating film <b>23</b> is 20 nm is referred to as the sample A<b>1</b>, a sample in which the thickness of the insulating film <b>23</b> is 50 nm is referred to as the sample A<b>2</b>, and a sample in which the thickness of the insulating film <b>23</b> is 100 nm is referred to as the sample A<b>3</b>. Note that since the substrate temperature in this process is 220° C. which is relatively low, the silicon oxynitride film in some cases resulted in a silicon oxide film not containing nitrogen. Moreover since the substrate temperature in this process is 220° C. which is relatively low, the amount of released hydrogen in the film formation process is small compared with that in the film formation process at 350° C.; therefore, the silicon oxynitride film (silicon oxide film) contain hydrogen in some cases.
0328Next, the insulating film <b>24</b> was formed over the insulating film <b>23</b>. As the insulating film <b>24</b>, a 400-nm-thick silicon oxynitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as a source gas, the pressure in a treatment chamber was 200 Pa, the substrate temperature was 220° C., and the high-frequency power of 1500 W was supplied to an upper electrode of parallel plate electrodes. Under the above conditions, it is possible to form a silicon oxynitride film which contains oxygen at a higher proportion than the stoichiometric composition. In other words, a silicon oxynitride film from which part of oxygen is released by heating can be formed.
0329Next, heat treatment was performed. The heat treatment was performed at 350° C. under a mixed atmosphere of oxygen and nitrogen for one hour.
0330Next, an insulating film was formed over the insulating film <b>24</b>. Here, a 1.5-μm-thick acrylic resin was formed as the insulating film. After that, heat treatment was performed. The heat treatment was performed at 250° C. under an atmosphere of nitrogen for one hour.
0331Through the above process, the transistor included in each of the samples A<b>1</b> to A<b>3</b> was manufactured.
0332Note that a sample in which insulating films are formed under the following conditions instead of the insulating film <b>23</b> and the insulating film <b>24</b> of the samples A<b>1</b> to A<b>3</b> is referred to as the sample A<b>4</b>. A formation method of the insulating film <b>23</b> and the insulating film <b>24</b> of the sample A<b>4</b> is described below.
0333The insulating film <b>23</b> was formed in succession over the oxide semiconductor film <b>20</b> and the pair of electrodes <b>21</b> without exposure to the atmosphere after the above plasma treatment. As the insulating film <b>23</b>, a 20-nm-thick silicon oxynitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm were used as a source gas, the pressure in the treatment chamber was 200 Pa, the substrate temperature was 350° C., and the high-frequency power of 100 W was supplied to an upper electrode of parallel plate electrodes.
0334Next, the insulating film <b>24</b> was formed over the insulating film <b>23</b>. As the insulating film <b>24</b>, a 380-nm-thick silicon oxynitride film was formed under the conditions similar to those of the insulating film <b>24</b> of the samples A<b>1</b> to A<b>3</b>.
0335The other processes were performed in a manner similar to that of the processes in the samples A<b>1</b> to A<b>3</b>, whereby the transistor included in the sample A<b>4</b> was manufactured.
0336A sample which was formed as follows is referred to as a sample A<b>5</b>: after the insulating film <b>24</b> was formed under the same conditions as the sample A<b>2</b>, a silicon nitride film was formed in succession without the above heat treatment at 350° C. for one hour and was then subjected to heat treatment at 350° C. under a mixed atmosphere of nitrogen and oxygen, and after that, an acrylic resin was formed over the silicon nitride film.
0337Further, a sample which was formed as follows is referred to as a sample A<b>6</b>: after the insulating film <b>24</b> was formed under the same conditions as the sample A<b>2</b> and the above heat treatment at 350° C. for one hour was performed, a silicon nitride film was formed and was then subjected to heat treatment at 300° C. under a mixed atmosphere of nitrogen and oxygen, and after that, an acrylic resin was formed over the silicon nitride film.
0338As the silicon nitride film of each of the sample A<b>5</b> and the sample A<b>6</b>, the 50-nm-thick silicon nitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm were used as a source gas, the pressure in the treatment chamber was 200 Pa, the substrate temperature was 220° C., and the high-frequency power of 1000 W was supplied to an upper electrode of parallel plate electrodes.
0339In addition, a manufacturing process of a transistor included in a comparative sample A<b>1</b> is described. The structure and the method for manufacturing the transistor included in the comparative sample A<b>1</b> are similar to those of the samples A<b>1</b> to A<b>3</b> except that the insulating film <b>23</b> is not formed.
0340Next, a BT stress test and a BT photostress test were performed on each of the samples A<b>1</b> to A<b>6</b> and the comparative sample A<b>1</b>. Here, the BT stress test in which voltage was applied to the gate electrode was performed under the following conditions: the substrate temperature was 80° C., the intensity of an electric field applied to the gate insulating film was 1.28 MV/cm, and the application time was 2000 seconds.
0341Under conditions similar to those of the above BT stress test, the BT photostress test in which the transistor is irradiated with white LED light of 3000 l× to apply voltage to the gate electrode was performed.
0342Here, a measurement method of the BT stress test is described. To measure initial characteristics of the transistor subjected to the BT stress test, a change in characteristics of current flowing between the source and the drain electrode (hereinafter referred to as the drain current), that is, Vg-Id characteristics were measured under the following conditions: the substrate temperature was 25° C., the voltage between the source electrode and the drain electrode (hereinafter the drain voltage) was 1 V or 10 V, and the voltages between the source electrode and the gate electrode (hereinafter the gate voltage) was changed from −30 V to +30 V.
0343Next, the substrate temperature was raised to 80° C., and then, the potentials of the source electrode and the drain electrode of the transistor were set to 0 V. Then, voltage was kept being applied to the gate electrode for 2000 seconds so that the intensity of the electric field applied to the gate insulating film was 1.28 MV/cm.
0344Note that in a negative BT stress test, a voltage of −30 V was applied to the gate electrode, and in a positive BT stress test, a voltage of 30 V was applied to the gate electrode. In a negative BT photostress test, a voltage of −30 V was applied to the gate electrode while irradiation with white LED light of 3000 l× was performed, and in a positive BT photostress test, a voltage of 30 V was applied to the gate electrode while irradiation with white LED light of 3000 l× was performed.
0345Next, the substrate temperature was lowered to 25° C. while voltage was continuously applied to the gate electrode, and the source electrode and the drain electrode. After the substrate temperature was reached to 25° C., the application of voltage to the gate electrode, and the source electrode and the drain electrode was stopped.
0346Next, Vg-Id characteristics were measured under the same conditions as the measurement of the initial characteristics, and Vg-Id characteristics after the BT stress test and the BT photostress test were obtained. <figref idref="DRAWINGS">FIG. 11</figref> shows, in each of the samples A<b>1</b> to A<b>4</b> and the comparative sample A<b>1</b>, a difference between a threshold voltage in the initial characteristics and a threshold voltage after BT stress tests (i.e., the amount of change in threshold voltage (ΔVth)) and a difference in shift values (i.e., the amount of change in shift value (ΔShift)). <figref idref="DRAWINGS">FIG. 12</figref> shows, in each of the samples A<b>5</b> and A<b>6</b>, the amount of change in threshold voltage (ΔVth)) and the amount of change in shift value (ΔShift)). In <figref idref="DRAWINGS">FIG. 11</figref> and <figref idref="DRAWINGS">FIG. 12</figref>, the vertical axis indicates the ΔVth and ΔShift.
0347Here, a threshold voltage and a shift value in this specification are described with reference to <figref idref="DRAWINGS">FIGS. 13A and 13B</figref>.
0348In this specification, in a curve <b>312</b> where the horizontal axis indicates the gate voltage (Vg [V]) and the vertical axis indicates the square root of drain current (Id<sup>1/2 </sup>[A]), the threshold voltage (Vth) is defined as a gate voltage at a point of intersection of an extrapolated tangent line <b>314</b> of Id<sup>1/2 </sup>having the highest inclination with the Vg axis (i.e., d<sup>1/2 </sup>of 0 A) (see <figref idref="DRAWINGS">FIG. 13A</figref>). Note that in this specification, threshold voltage is calculated with a drain voltage Vd of 10 V.
0349In this specification, in a curve <b>316</b> where the horizontal axis indicates the gate voltage (Vg [V]) and the vertical axis indicates the logarithm of drain current (Id [A]), the shift value (Shift) is defined as a gate voltage at a point of intersection of an extrapolated tangent line <b>318</b> of Id having the highest inclination with a straight line of Id=1.0×10<sup>−12 </sup>[A] (see <figref idref="DRAWINGS">FIG. 13B</figref>). Note that in this specification, a shift value is calculated with a drain voltage Vd of 10 V.
0350As shown in <figref idref="DRAWINGS">FIG. 11</figref>, after the negative BT photostress test in the comparative sample A<b>1</b>, both the threshold voltage and the shift value were shifted in the negative direction and the amount of change in threshold voltage (ΔVth) and the amount of change in shift value (ΔShift) were large. However, after the BT stress test and the BT photostress test in the samples A<b>1</b> to A<b>6</b>, as shown in <figref idref="DRAWINGS">FIG. 11</figref> and <figref idref="DRAWINGS">FIG. 12</figref>, both the amount of change in threshold voltage (ΔVth) and the amount of change in shift value (ΔShift) were small. Further, in the samples A<b>1</b> to A<b>6</b>, both the threshold voltage and the shift value were shifted in the positive direction, and the amount of change in threshold voltage (ΔVth) and the amount of change in shift value (ΔShift) tended to become small, less than or equal to 3.0 V, preferably less than or equal to 2.5 V. Accordingly, it is found that, when an oxide insulating film into which and from which oxygen is diffused and an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition are stacked as a protective film of a transistor, a transistor having small amounts of change in threshold voltage and shift value in the BT stress test and the BT photostress test can be manufactured.
0351Next, samples in each of which a silicon nitride film was formed over the insulating film <b>24</b> were subjected to accelerated life test to evaluate moisture resistance. Here, the accelerated life test for evaluating moisture resistance was performed using the samples A<b>5</b> and A<b>6</b>, and as comparative samples, a comparative sample A<b>2</b> and a comparative sample A<b>3</b>.
0352Here, a manufacturing process of a transistor included in each of the comparative samples A<b>2</b> and A<b>3</b> is described. In the transistor included in each of the comparative samples A<b>2</b> and A<b>3</b>, instead of the silicon nitride films in the sample A<b>5</b> and the sample A<b>6</b>, a 200-nm-thick silicon nitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 50 sccm and nitrogen with a flow rate of 5000 sccm were used as a source gas, the pressure in a treatment chamber was 200 Pa, the substrate temperature was 220° C., and the high-frequency power of 1000 W was supplied to an upper electrode of parallel plate electrodes.
0353Next, a pressure cooker test (PCT) was performed as the accelerated life test to evaluate moisture resistance. In the PCT in this example, the samples A<b>5</b> and A<b>6</b> and the comparative samples A<b>2</b> and A<b>3</b> were held for 15 hours under the following conditions: the temperature was 130° C., the humidity was 85%, and the pressure was 0.23 MPa.
0354<figref idref="DRAWINGS">FIG. 14A</figref> shows Vg-Id initial characteristics of the transistors included in the comparative sample A<b>2</b>, and <figref idref="DRAWINGS">FIG. 14B</figref> shows Vg-Id initial characteristics of the transistors included in the sample A<b>5</b>. <figref idref="DRAWINGS">FIG. 14C</figref> shows Vg-Id initial characteristics of the transistors included in the comparative sample A<b>2</b> after the pressure cooker test, and <figref idref="DRAWINGS">FIG. 14D</figref> shows Vg-Id initial characteristics of the transistors included in the sample A<b>5</b> after the pressure cooker test.
0355<figref idref="DRAWINGS">FIG. 15A</figref> shows Vg-Id initial characteristics of the transistors included in the comparative sample A<b>3</b>, and <figref idref="DRAWINGS">FIG. 15B</figref> shows Vg-Id initial characteristics of the transistors included in the sample A<b>6</b>. <figref idref="DRAWINGS">FIG. 15C</figref> shows Vg-Id initial characteristics of the transistors included in the comparative sample A<b>3</b> after the pressure cooker test, and <figref idref="DRAWINGS">FIG. 15D</figref> shows Vg-Id initial characteristics of the transistors included in the sample A<b>6</b> after the pressure cooker test.
0356In each of <figref idref="DRAWINGS">FIGS. 14A to 14D</figref> and <figref idref="DRAWINGS">FIGS. 15A to 15D</figref>, the horizontal axis indicates the gate voltage (Vg), the left vertical axis indicates the drain current (Id) flowing between the pair of electrodes <b>21</b>, and the right vertical axis indicates the field-effect mobility (μFE). Further, the solid line indicates the initial characteristics of current-voltage characteristics at a drain voltage (Vd) of 1 V or 10V, and the dashed line indicates the field-effect mobility with respect to the gate voltage at a drain voltage of 10 V. Note that the field-effect mobility was obtained by operation of each sample in a saturation region. In each sample, electrical characteristics of 20 transistors were measured.
0357As shown in <figref idref="DRAWINGS">FIGS. 14A to 14D</figref> and <figref idref="DRAWINGS">FIGS. 15A to 15D</figref>, after the pressure cooker test in each of the comparative samples A<b>2</b> and A<b>3</b>, the threshold voltage is shifted in the negative direction, whereas, after the pressure cooker test in each of the samples A<b>5</b> and A<b>6</b>, the amount of change in threshold voltage is extremely small. Accordingly, by forming the silicon nitride film over the insulating film <b>24</b> under the above conditions, a transistor with less deterioration can be manufactured even under an environment having high humidity.
Example 2
0358In this example, diffusion of oxygen into and from the insulating film <b>23</b> described in Embodiment 1 will be described. In this example, the diffusion of oxygen will be described by measuring the concentration of oxygen by substrate side depth profile secondary ion mass spectrometry (SSDP-SIMS) (SIMS from the back side).
0359First, a method for forming a sample B<b>1</b> and a sample B<b>2</b> is described.
0360A 100-nm-thick silicon oxynitride (SiON) film was formed over a silicon wafer under the conditions of the insulating film <b>23</b>, which is described in Embodiment 1. Here, the silicon oxynitride film was formed under the following conditions: the silicon wafer was placed in a treatment chamber of a plasma CVD apparatus, silane with a flow rate of 30 sccm and dinitrogen monoxide with a flow rate of 4000 sccm which were used as a source gas were supplied to the treatment chamber, the pressure in the treatment chamber was controlled to 200 Pa, and the power of 150 W was supplied with the use of a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed at a temperature of the silicon wafer being 220° C. Note that the plasma CVD apparatus used in this example is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm<sup>2</sup>, and the power per unit area (power density) into which the supplied power is converted is 0.025 W/cm<sup>2</sup>.
0361Next, a 100-nm-thick silicon oxide (SiO<sub>x</sub>) film was formed over the silicon oxynitride film by a sputtering method. Here, the silicon oxide film containing <sup>18</sup>O was formed under the following conditions: the silicon wafer was placed in a treatment chamber of a sputtering apparatus, <sup>18</sup>O (an isotope of <sup>16</sup>O) with a flow rate of 300 sccm which was used as a source gas was supplied to the treatment chamber, the pressure in the treatment chamber was controlled to 0.7 Pa, and the power of 8000 W was supplied with the use of a high-frequency power source. This sample is referred to as the sample B<b>1</b>.
0362Next, the sample B<b>1</b> was heated at 350° C. for one hour. This sample is referred to as the sample B<b>2</b>.
0363Next, the concentration profiles of <sup>18</sup>O contained in each of the samples B<b>1</b> and B<b>2</b> were measured by SSDP-SIMS (measurement from the back side, here from the silicon wafer side).
0364Other than <sup>16</sup>O which is a main nuclide in oxygen, isotopes such as <sup>17</sup>O and <sup>18</sup>O exist. It is known that the proportions of <sup>17</sup>O and <sup>18</sup>O in all of the oxygen atoms in nature are about 0.038% and about 0.201%, respectively. That is, the concentrations of <sup>17</sup>O and <sup>18</sup>O can be estimated by measuring the concentration of <sup>16</sup>O in the silicon oxynitride film by SIMS. Here, the concentration of <sup>18</sup>O in the silicon oxynitride film and the concentration of <sup>18</sup>O estimated from its proportion to <sup>16</sup>O are compared, whereby whether <sup>18</sup>O is diffused or not into the silicon oxynitride (SiON) film from the silicon oxide (SiO<sub>x</sub>) film can be judged.
0365Here, the concentrations of <sup>16</sup>O and <sup>18</sup>O in the silicon oxynitride film were measured. Note that a cesium primary ion (Cs<sup>+</sup>) was used as a primary ion species.
0366<figref idref="DRAWINGS">FIGS. 16A and 16B</figref> each show the concentration profiles of <sup>18</sup>O which were obtained by the SSDP-SIMS measurement.
0367<figref idref="DRAWINGS">FIG. 16A</figref> shows the measurement result of the sample B<b>1</b>. A curve <b>801</b> is the concentration profile of <sup>18</sup>O which was calculated on the basis of the concentration profile of <sup>16</sup>O measured by SSDP-SIMS with the assumption of a natural proportion of <sup>18</sup>O, and a curve <b>803</b> is the concentration profile of <sup>18</sup>O measured by SSDP-SIMS.
0368<figref idref="DRAWINGS">FIG. 16B</figref> shows the measurement result of the sample B<b>2</b>. A curve <b>811</b> is the concentration profile of <sup>18</sup>O which was calculated on the basis of the concentration profile of <sup>16</sup>O measured by SSDP-SIMS, and a curve <b>813</b> is the concentration profile of <sup>18</sup>O measured by SSDP-SIMS.
0369In the SiON in <figref idref="DRAWINGS">FIG. 16A</figref>, the curve <b>801</b> and the curve <b>803</b> coincide with each other. That is, it is found that <sup>18</sup>O contained in the SiO<sub>x </sub>is not diffused into the SiON in the sample B<b>1</b>.
0370On the other hand, the concentration shown by the curve <b>813</b> is raised more than that shown by the curve <b>811</b> in the SiON in <figref idref="DRAWINGS">FIG. 16B</figref>. That is, it is found that <sup>18</sup>O contained in the SiO<sub>x </sub>is diffused into the SiON by the heat treatment and the concentration of <sup>18</sup>O in the SiON is increased.
0371As described above, oxygen is diffused into the silicon oxynitride film formed under the conditions of the insulating film <b>23</b>, which is described in Embodiment 1. That is, excess oxygen contained in an insulating film in contact with the silicon oxynitride film can be diffused into the silicon oxynitride film.
Example 3
0372In this example, change in defects of the oxide semiconductor film which is caused at the same time as the formation of the insulating film <b>23</b> and the insulating film <b>24</b> described in Embodiment 1 will be described. In this example, results of electron spin resonance (ESR) by which the amount of oxygen vacancies in the oxide semiconductor film was measured will be described.
0373First, a method for forming samples C<b>1</b>, samples C<b>2</b>, and samples C<b>3</b> which are illustrated in <figref idref="DRAWINGS">FIGS. 17A to 17C</figref> is described.
0374A method for forming the sample C<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 17A</figref> is described.
0375A 100-nm-thick IGZO film <b>973</b><i>a </i>which was a CAAC-OS film was formed by a sputtering method over a quartz substrate <b>971</b>. Here, the IGZO film was formed under the following conditions: a sputtering target containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used, argon with a flow rate of 50 sccm and oxygen with a flow rate of 50 sccm were supplied as a sputtering gas to a treatment chamber of a sputtering apparatus, the pressure in the treatment chamber was controlled to 0.6 Pa, and the direct current power of 5 kW was supplied. Note that the IGZO film was formed at a substrate temperature of 170° C.
0376Next, a silicon oxynitride film <b>975</b> was formed over the IGZO film <b>973</b><i>a </i>under the conditions of the insulating film <b>23</b>, which is described in Embodiment 1. Here, the silicon oxynitride film was formed under the following conditions: the quartz substrate was placed in a treatment chamber of a plasma CVD apparatus, silane with a flow rate of 30 sccm and dinitrogen monoxide with a flow rate of 4000 sccm which were used as a source gas were supplied to the treatment chamber, and the power of 150 W was supplied with the use of a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed at a temperature of the quartz substrate being 220° C. Note that the plasma CVD apparatus used in this example is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm<sup>2</sup>, and the power per unit area (power density) into which the supplied power is converted is 0.025 W/cm<sup>2</sup>.
0377A plurality of samples C<b>1</b> were formed in such a manner that the pressure in the treatment chamber during the formation of the insulating film <b>23</b> was controlled to 40 Pa, 120 Pa, and 200 Pa and the silicon oxynitride films <b>975</b> were formed to thicknesses of 20 nm, 50 nm, and 100 nm.
0378Next, a method for forming samples C<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 17B</figref> is described.
0379A silicon oxynitride film <b>977</b> was formed over a sample C<b>1</b> under the conditions of the insulating film <b>24</b> formation, which is described in Embodiment 1. Here, the 400-nm-thick silicon oxynitride film was formed by a plasma CVD method under the following conditions: the quartz substrate was placed in a treatment chamber of the plasma CVD apparatus, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm which were used as a source gas were supplied to the treatment chamber, the pressure in the treatment chamber was 200 Pa, the substrate temperature was 220° C., and the high-frequency power of 1500 W was supplied to an upper electrode of parallel plate electrodes.
0380Note that here, the IGZO film which was a CAAC-OS film is an IGZO film <b>973</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 17B</figref>.
0381Through the above process, the samples C<b>2</b> were formed.
0382Next, a method for forming the samples C<b>3</b> illustrated in <figref idref="DRAWINGS">FIG. 17C</figref> is described.
0383The samples C<b>3</b> were formed by heating samples C<b>2</b> at 350° C. for one hour. Note that here, the IGZO film which was a CAAC-OS film is an IGZO film <b>973</b><i>c </i>illustrated in <figref idref="DRAWINGS">FIG. 17C</figref>.
0384Next, ESR measurement was performed on the samples C<b>1</b> to C<b>3</b>. In the ESR measurement performed at a predetermined temperature, a value of a magnetic field (H<sub>0</sub>) where a microwave is absorbed is used for an equation g=hν/βH<sub>0</sub>, so that a parameter of a g-factor can be obtained. Note that the frequency of the microwave is denoted by ν, and the Planck constant and the Bohr magneton are denoted by, respectively, h and β which are both constants.
0385Here, the ESR measurement was performed under the following conditions. The measurement temperature was room temperature (25° C.), the high-frequency power (power of microwaves) of 9.4 GHz was 20 mW, and the direction of a magnetic field was parallel to a surface of each of the IGZO films in the samples. Note that the lower limit of the detection of the spin densities of a signal due to oxygen vacancies in the IGZO film, which appeared when g (g-factor) was 1.93, was 2.2×10<sup>16 </sup>spins/cm<sup>3</sup>.
0386<figref idref="DRAWINGS">FIGS. 18A to 18C</figref> each show spin densities of signals that appear when g (g-factor) is 1.93. <figref idref="DRAWINGS">FIG. 18A</figref> shows spin densities in the samples C<b>1</b>, <figref idref="DRAWINGS">FIG. 18B</figref> shows spin densities in the samples C<b>2</b>, and <figref idref="DRAWINGS">FIG. 18C</figref> shows spin densities in the samples C<b>3</b>. Note that in each of <figref idref="DRAWINGS">FIGS. 18A to 18C</figref>, a 1<sup>st</sup>-SiON indicates the silicon oxynitride film <b>975</b>.
0387Moreover, the IGZO films included in one of the samples C<b>2</b> and one of the samples C<b>3</b> shown in <figref idref="DRAWINGS">FIGS. 18B and 18C</figref> were evaluated by ESR and their first derivative curves are shown in <figref idref="DRAWINGS">FIG. 19</figref>. A curve <b>981</b> is a first derivative curve of a sample C<b>2</b> in which a 50-nm-thick silicon oxynitride film <b>975</b> was formed under the film formation conditions of the pressure of 40 Pa.
0388A curve <b>983</b> is a first derivative curve of a sample C<b>3</b> in which a 50-nm-thick silicon oxynitride film <b>975</b> was formed under the film formation conditions of the pressure of 40 Pa.
0389It is found from <figref idref="DRAWINGS">FIG. 19</figref> that, in the sample C<b>2</b>, a signal having symmetry due to an oxygen vacancy is detected at a g-factor of 1.93, which means that the IGZO film contains an oxygen vacancy. On the other hand, it is found that, in the sample C<b>3</b>, a signal having symmetry due to an oxygen vacancy is not detected (i.e., the amount of oxygen vacancies was less than or equal to the lower limit of detection) and that the amount of oxygen vacancies in the IGZO film cannot be detected.
0390It is found from <figref idref="DRAWINGS">FIG. 18A</figref> that as the thickness of the silicon oxynitride film <b>975</b> is larger or the film formation pressure is lower, the amount of oxygen vacancies in the IGZO film <b>973</b><i>a </i>increases. This is because it will be more difficult for the excess oxygen contained in the silicon oxynitride film <b>977</b> to diffuse into the IGZO film as the thickness of the silicon oxynitride film <b>975</b> formed under the conditions of the insulating film <b>24</b> described in Embodiment 1 increases. Further, the oxide semiconductor film is damaged as the film formation pressure is lower and thus the amount of oxygen vacancies increases under such film formation conditions of the silicon oxynitride film <b>975</b>.
0391It is found from <figref idref="DRAWINGS">FIG. 18B</figref> that, in most of the samples where the silicon oxynitride film <b>977</b> is formed over the silicon oxynitride film <b>975</b>, the amount of oxygen vacancies in the IGZO film <b>973</b><i>b </i>is less than or equal to the lower limit of detection, though the amount of oxygen vacancies increases in some samples.
0392This is because oxygen vacancies in the IGZO film <b>973</b><i>b </i>are reduced as follows: the silicon oxynitride film <b>977</b> which is an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition is formed over the silicon oxynitride film <b>975</b>, so that excess oxygen contained in the silicon oxynitride film <b>977</b> is diffused into the IGZO film <b>973</b><i>b </i>through the silicon oxynitride film <b>975</b> to compensate the oxygen vacancies.
0393It is found from <figref idref="DRAWINGS">FIG. 18C</figref> that the amount of oxygen vacancies in the IGZO film <b>973</b><i>c </i>is less than or equal to the lower limit of detection by the heat treatment performed after the silicon oxynitride film <b>977</b> is formed over the silicon oxynitride film <b>975</b>.
0394This is because oxygen vacancies in the IGZO film <b>973</b><i>c </i>are reduced as follows: the silicon oxynitride film <b>977</b> which is an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition is formed over the silicon oxynitride film <b>975</b>, so that excess oxygen contained in the silicon oxynitride film <b>977</b> is diffused into the IGZO film <b>973</b><i>c </i>through the silicon oxynitride film <b>975</b> to compensate the oxygen vacancies.
0395As described above, the amount of oxygen vacancies in an oxide semiconductor film can be reduced by stacking a silicon oxynitride film over the oxide semiconductor film. Moreover, with application of the structure to a transistor, as shown in Example 1, the transistor in which the threshold voltage is shifted in the positive direction and the amount of change in threshold voltage is less than or equal to 3.0 V, preferably less than or equal to 2.5 V, can be manufactured.
Example 4
0396In this example, the insulating film <b>23</b> formed over a transistor and the Vg-Id characteristics of the transistor will be described with reference to <figref idref="DRAWINGS">FIGS. 20A and 20B</figref>, <figref idref="DRAWINGS">FIGS. 21A to 21C</figref>, <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>, <figref idref="DRAWINGS">FIGS. 23A and 23B</figref>, and <figref idref="DRAWINGS">FIGS. 24A to 24E</figref>.
0397First, a manufacturing process of transistors included in each of a sample D<b>1</b> and a sample D<b>2</b> is described. Note that the samples D<b>1</b> and D<b>2</b> differ only in the flow rate of the source gas used for forming the insulating film <b>23</b> described in Embodiment 1.
0398The sample D<b>1</b> is similar to the sample A<b>2</b>, and as the insulating film <b>23</b>, a 50-nm-thick silicon oxynitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 30 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as a source gas, the pressure in a treatment chamber of a plasma CVD apparatus was 40 Pa, the substrate temperature was 220° C., and the high-frequency power of 150 W was supplied to an upper electrode of parallel plate electrodes. Here, the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was 133.
0399The sample D<b>2</b> is also similar to the sample A<b>2</b>, and as the insulating film <b>23</b>, a 50-nm-thick silicon oxynitride film was formed by a plasma CVD method under the following conditions: silane with a flow rate of 80 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as a source gas, the pressure in a treatment chamber was 40 Pa, the substrate temperature was 220° C., and the high-frequency power of 150 W was supplied to an upper electrode of parallel plate electrodes. Here, the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was 50.
0400Next, the Vg-Id characteristics of the samples D<b>1</b> and D<b>2</b> were measured. <figref idref="DRAWINGS">FIG. 20A</figref> shows the Vg-Id characteristics of the samples D<b>1</b>, and <figref idref="DRAWINGS">FIG. 20B</figref> shows the Vg-Id characteristics of the samples D<b>2</b>. In each of <figref idref="DRAWINGS">FIGS. 20A and 20B</figref>, the horizontal axis indicates the gate voltage (Vg), and the vertical axis indicates the drain current (Id) flowing between the pair of electrodes <b>21</b>. The Vg-Id characteristics were measured at drain voltages (Vd) of 1 V and 10 V. Further, the field-effect mobility with respect to the gate voltage at the drain voltage of 10 V is shown. Note that the field-effect mobility was obtained by operation of each sample in a saturation region. Note that here, the Vg-Id characteristics of 24 transistors are shown.
0401Although the samples D<b>2</b> fluctuate in threshold voltage as shown in <figref idref="DRAWINGS">FIG. 20B</figref>, the samples D<b>1</b> fluctuate less in threshold voltage as shown in <figref idref="DRAWINGS">FIG. 20A</figref>. Accordingly, it is found that, when the ratio of the flow ratio of dinitrogen monoxide to silane is 100 or higher as the film formation conditions of the insulating film <b>23</b>, favorable Vg-Id characteristics can be obtained.
0402Next, the flow rate of the source gas used for forming the insulating film <b>23</b> and the amount of oxygen vacancies in the oxide semiconductor film were measured by ESR.
0403First, a method for forming samples is described.
0404A 100-nm-thick IGZO film which was a CAAC-OS film was formed by a sputtering method over a quartz substrate. The IGZO film was formed under conditions similar to those of the samples C<b>1</b> to C<b>3</b>.
0405Next, a 400-nm-thick silicon oxynitride film was formed over the IGZO film under the conditions of the insulating film <b>23</b> formed in the above samples D<b>1</b> and D<b>2</b>. A sample in which the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was 100 or higher (<b>133</b>) in a manner similar to that of a sample D<b>1</b> is referred to as a sample D<b>3</b>. A sample in which the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was less than 100 (<b>50</b>) in a manner similar to that of a sample D<b>2</b> is referred to as a sample D<b>4</b>.
0406Next, a samples D<b>3</b> and D<b>4</b> were heated at 350° C. A sample obtained by heating a sample D<b>3</b> is referred to as a sample D<b>5</b>. A sample obtained by heating a sample D<b>4</b> is referred to as a sample D<b>6</b>.
0407Next, the samples D<b>3</b> to D<b>6</b> were measured by ESR. The ESR measurement was performed under conditions similar to those of the ESR measurement performed in Example 3.
0408<figref idref="DRAWINGS">FIG. 21A</figref> shows spin densities of signals that appear when g (g-factor) is 1.93. In <figref idref="DRAWINGS">FIG. 21A</figref>, the vertical axis indicates the spin density.
0409Moreover, <figref idref="DRAWINGS">FIG. 21B</figref> shows first derivative curves which were obtained by measuring the samples D<b>3</b> and D<b>5</b> by ESR, and <figref idref="DRAWINGS">FIG. 21C</figref> shows first derivative curves which were obtained by measuring the samples D<b>4</b> and D<b>6</b> by ESR.
0410It is found from <figref idref="DRAWINGS">FIG. 21A</figref> that in the samples D<b>3</b>, D<b>4</b>, and D<b>6</b>, the spin densities are high, and from <figref idref="DRAWINGS">FIGS. 21B and 21C</figref> that in each of the samples D<b>3</b>, D<b>4</b>, and D<b>6</b>, a signal having symmetry due to an oxygen vacancy is detected at a g-factor of 1.93, which means that the IGZO film contains an oxygen vacancy. On the other hand, it is found from <figref idref="DRAWINGS">FIG. 21B</figref> that in the sample D<b>5</b>, a signal having symmetry due to an oxygen vacancy is not detected (i.e., the amount of oxygen vacancies was less than or equal to the lower limit of detection) and, as shown in <figref idref="DRAWINGS">FIG. 21A</figref>, that the amount of oxygen vacancies in the IGZO film cannot be detected.
0411It is found from <figref idref="DRAWINGS">FIGS. 21A to 21C</figref> that the amount of oxygen vacancies in the IGZO film can be reduced by performing the heat treatment after the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane is 100 or higher.
0412Next, the flow rate of the source gas used for forming the insulating film <b>23</b> and the amount of oxygen vacancies in the insulating film <b>23</b> were measured by ESR.
0413First, samples which were formed are described. In formed samples, a 400-nm-thick silicon oxynitride film was formed over a quartz substrate under the conditions of the insulating film <b>23</b> formed in the above samples D<b>1</b> and D<b>2</b>. A sample in which the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane is 100 or higher (<b>133</b>) in a manner similar to that of the sample D<b>1</b> is referred to as a sample D<b>7</b>. A sample in which the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane is lower than 100 (<b>55</b>) in a manner similar to that of the sample D<b>2</b> is referred to as a sample D<b>8</b>.
0414Next, the samples D<b>7</b> to D<b>8</b> were measured by ESR. The ESR measurement was performed under the following conditions: the measurement temperature was room temperature (25° C.), the high-frequency power (power of microwaves) of 9.2 GHz was 20 mW, and the direction of a magnetic field was parallel to a surface of each of the silicon oxynitride films in the samples. The lower limit of the detection of the spin densities of a signal due to dangling bonds of silicon contained in the silicon oxynitride film, which appear when g is 2.001, is 1.0×10<sup>15 </sup>spins/cm<sup>3</sup>. It can be said that, as the spin densities are lower, there are a few defects due to dangling bonds of silicon contained in the silicon oxynitride film.
0415Results of the ESR measurement are shown in <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>. <figref idref="DRAWINGS">FIG. 22A</figref> shows a first derivative curve of the silicon oxynitride film in the sample D<b>7</b>, and <figref idref="DRAWINGS">FIG. 22B</figref> shows a first derivative curve of the silicon oxynitride film in the sample D<b>8</b>. As shown in <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>, although, in the sample D<b>8</b>, a signal having symmetry due to a dangling bond is detected at a g-factor of 2.001, in the sample D<b>7</b>, a signal having symmetry due to a dangling bond is not detected at a g-factor of 2.001. That is, it is found that the amount of dangling bonds of silicon contained in the silicon oxynitride film is small in the sample D<b>7</b>.
0416It is found from <figref idref="DRAWINGS">FIGS. 22A and 22B</figref> that the amount of dangling bonds in the silicon oxynitride film can be reduced by forming the silicon oxynitride film under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane is 100 or higher.
0417Next, thermal desorption spectroscopy (TDS) analysis was performed on the amount of released oxygen in the case where the insulating film <b>23</b> into which and from which oxygen is diffused and the insulating film <b>24</b> which contains oxygen at a higher proportion than the stoichiometric composition are stacked and results thereof are shown.
0418First, samples which were formed are described with reference to <figref idref="DRAWINGS">FIGS. 23A and 23B</figref>. The formed samples each have a structure <b>1</b> or a structure <b>2</b>.
0419In the structure <b>1</b>, as illustrated in <figref idref="DRAWINGS">FIG. 23A</figref>, an insulating film <b>993</b> was formed over a silicon wafer <b>991</b> under conditions similar to those of the insulating film <b>24</b>, and then an insulating film <b>995</b> was formed over the insulating film <b>993</b> under conditions similar to those of the insulating film <b>23</b>.
0420In the structure <b>2</b>, as illustrated in <figref idref="DRAWINGS">FIG. 23B</figref>, the insulating film <b>995</b> was formed over the silicon wafer <b>991</b> under conditions similar to those of the insulating film <b>23</b>, and then the insulating film <b>993</b> was formed over the insulating film <b>995</b> under conditions similar to those of the insulating film <b>24</b>.
0421As the insulating film <b>993</b>, a 400-nm-thick silicon oxynitride film was formed under the conditions similar to those of the insulating film <b>24</b> of the samples A<b>1</b> to A<b>3</b>.
0422As the insulating film <b>995</b>, a 50-nm-thick silicon oxynitride film was formed under the conditions similar to those of the insulating film <b>23</b> of the samples D<b>1</b> and D<b>2</b>.
0423A sample of the structure <b>1</b> in which, as the insulating film <b>995</b>, the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was 100 or higher (<b>133</b>) in a manner similar to that of the sample D<b>1</b> is referred to as a sample E<b>1</b>.
0424A sample of the structure <b>1</b> in which, as the insulating film <b>995</b>, the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was lower than 100 (<b>50</b>) in a manner similar to that of the sample D<b>2</b> is referred to as a sample E<b>2</b>.
0425A sample of the structure <b>2</b> in which, as the insulating film <b>995</b>, the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was 100 or higher (<b>133</b>) in a manner similar to that of the sample D<b>1</b> is referred to as a sample E<b>3</b>.
0426A sample of the structure <b>2</b> in which, as the insulating film <b>995</b>, the silicon oxynitride film was formed under a condition where the ratio of the flow rate of dinitrogen monoxide to the flow rate of silane was lower than 100 (<b>55</b>) in a manner similar to that of the sample D<b>2</b> is referred to as a sample E<b>4</b>.
0427Note that as shown in <figref idref="DRAWINGS">FIG. 22B</figref>, the insulating film <b>995</b> included in each of the samples E<b>2</b> and E<b>4</b> is a silicon oxynitride film having a dangling bond of silicon, similar to the silicon oxynitride film included in the sample D<b>8</b>.
0428Next, TDS analyses were performed on the samples E<b>1</b> to E<b>4</b>. Results of the TDS analyses are shown in <figref idref="DRAWINGS">FIGS. 24A to 24E</figref>. <figref idref="DRAWINGS">FIG. 24A</figref> shows TDS analysis result of the sample E<b>1</b>, <figref idref="DRAWINGS">FIG. 24B</figref> shows TDS analysis result of the sample E<b>2</b>, <figref idref="DRAWINGS">FIG. 24C</figref> shows TDS analysis result of the sample E<b>3</b>, and <figref idref="DRAWINGS">FIG. 24D</figref> shows TDS analysis result of the sample E<b>4</b>. In <figref idref="DRAWINGS">FIGS. 24A to 24D</figref>, the horizontal axis indicates the substrate temperature of the samples E<b>1</b> to E<b>4</b>, and the vertical axis indicates the peak intensity of a TDS spectrum.
0429Further, <figref idref="DRAWINGS">FIG. 24E</figref> shows the amount of released oxygen observed from the results of the TDS analyses shown in <figref idref="DRAWINGS">FIGS. 24A to 24D</figref>.
0430In the TDS analysis, a peak observed at a region where the substrate temperature is higher than or equal to 300° C. and lower than or equal to 400° C. is a peak derived from release of oxygen (specifically, an oxygen atom or an oxygen molecule) contained in the analyzed sample (in this example, the samples E<b>1</b> to E<b>4</b>) to the outside. The total amount of oxygen released to the outside corresponds to the integral value of the peak. In the case where the oxygen content of the silicon oxynitride film is higher than the content of oxygen which satisfies the stoichiometric composition, it is considered that excess oxygen is easily released to the outside. Thus, with the degree of the peak intensity, the amount of oxygen contained in the stacked silicon oxynitride films can be estimated.
0431It is found from <figref idref="DRAWINGS">FIGS. 24A to 24E</figref> that the amount of released oxygen is reduced in the sample where a silicon oxynitride film having a dangling bond of silicon is used as the insulating film <b>995</b> (the samples E<b>2</b> and E<b>4</b>). Accordingly, it is found that, when an insulating film into which and from which oxygen is diffused has a dangling bond of silicon, oxygen diffused from an insulating film which contains oxygen at a higher proportion than the stoichiometric composition is bonded to the dangling bond of silicon; therefore, the amount of released oxygen is reduced. That is, in the stack of the insulating film <b>23</b> and the insulating film <b>24</b> which is used as a protective film of a transistor, the insulating film <b>23</b> having a few dangling bonds of silicon is formed, whereby oxygen contained in the insulating film <b>24</b> which contains oxygen at a higher proportion than the stoichiometric composition can be efficiently diffused into an oxide semiconductor film of the transistor and oxygen vacancies in the oxide semiconductor film can be compensated. As a result, the fluctuations and negative shifts in the threshold voltage of the transistor can be suppressed as shown in <figref idref="DRAWINGS">FIGS. 20A and 20B</figref>.
Example 5
0432In this example, the concentrations of hydrogen, nitrogen, and fluorine in an insulating film formed over an oxide semiconductor film were measured by SIMS and results thereof will be shown.
0433First, a method for forming a sample F<b>1</b> and a sample F<b>2</b> is described.
0434The sample F<b>1</b> has a structure similar to that of the sample A<b>2</b>. Note that oxygen plasma treatment prior to the formation of the insulating film <b>23</b> is not performed.
0435In the sample F<b>2</b>, the oxygen plasma treatment prior to the formation of the insulating film <b>23</b> and the formation of the insulating film <b>23</b> which were performed in the sample A<b>2</b> were not performed, and the insulating film <b>24</b> was formed over the oxide semiconductor film <b>19</b>.
0436Next, the samples F<b>1</b> and F<b>2</b> were measured by SIMS. <figref idref="DRAWINGS">FIG. 25A</figref> shows the concentration of hydrogen, <figref idref="DRAWINGS">FIG. 25B</figref> shows the concentration of nitrogen, and <figref idref="DRAWINGS">FIG. 25C</figref> shows the concentration of fluorine in the insulating films <b>23</b> and <b>24</b> in the sample F<b>1</b>. <figref idref="DRAWINGS">FIG. 25D</figref> shows the concentration of hydrogen, <figref idref="DRAWINGS">FIG. 25E</figref> shows the concentration of nitrogen, and <figref idref="DRAWINGS">FIG. 25F</figref> shows the concentration of fluorine in the insulating film <b>24</b> in the sample F<b>2</b>. In <figref idref="DRAWINGS">FIGS. 25A to 25F</figref>, the horizontal axis indicates the depth from the surface of each sample and the vertical axis indicates the concentration of each element.
0437In the sample F<b>1</b>, the concentrations of hydrogen and nitrogen are not changed at the interface between the insulating film <b>23</b> and the insulating film <b>24</b>, whereas the concentration of fluorine has a peak at the interface between the insulating film <b>23</b> and the insulating film <b>24</b>. From the following description, the concentration of fluorine has a peak at the above interface. After the insulating film <b>23</b> was formed, the power of a plasma CVD apparatus was cut, the flow rate of a source gas introduced into a treatment chamber and the pressure in the treatment chamber were changed, and power was resupplied to the plasma CVD apparatus to form the insulating film <b>24</b>. Note that after the insulating film <b>23</b> was formed, the surface of the insulating film <b>23</b> was exposed to the atmosphere in the treatment chamber until the insulating film <b>24</b> was formed.
0438In the treatment chamber, fluorine or NF<sub>3 </sub>which was used in cleaning of the treatment chamber was attached to the inner wall of the treatment chamber, and the fluorine or NF<sub>3 </sub>released from the inner wall of the treatment chamber was attached to the surface of the insulating film <b>23</b> while the insulating film <b>24</b> was formed just after the insulating film <b>23</b> was formed. Therefore, the concentration of fluorine is increased at the interface between the insulating film <b>23</b> and the insulating film <b>24</b> and thus has a peak.
0439Note that since only a single layer of the insulating film <b>24</b> is provided over the oxide semiconductor film <b>19</b> in the sample F<b>2</b>, the concentration of fluorine in the insulating film <b>24</b> does not have a peak as shown in <figref idref="DRAWINGS">FIG. 25F</figref>.
Example 6
0440In this example, characteristics of a silicon oxynitride film formed using a method for forming an insulating film of one embodiment of the present invention will be described. Specifically, the etching rate of the silicon oxynitride film formed by the method will be described with reference to <figref idref="DRAWINGS">FIG. 26</figref>.
0441First, samples which were formed are described. The formed samples are a sample G<b>1</b>, a sample G<b>2</b>, and a comparative sample G<b>1</b> in each of which a 100-nm-thick silicon oxynitride film was formed over a glass substrate. Note that in the sample G<b>1</b>, the silicon oxynitride film was formed under the conditions of the insulating film <b>23</b>, which is described in Embodiment 1, and, in the comparative sample G<b>1</b>, the silicon oxynitride film was formed under the conditions of the insulating film <b>24</b>, which is described in Embodiment 1.
0442The silicon oxynitride film was formed under the following conditions: the glass substrate was placed in a treatment chamber of a plasma CVD apparatus, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm which were used as a source gas were supplied to the treatment chamber, the pressure in the treatment chamber was controlled to 200 Pa, and the power of 100 W was supplied with the use of a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed at a substrate temperature of 350° C. Note that the plasma CVD apparatus used here is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm<sup>2</sup>, and the power per unit area (power density) into which the supplied power is converted is 0.017 W/cm<sup>2</sup>.
0443A sample formed in the above manner is referred to as the sample G<b>1</b>.
0444A sample formed as follows is referred to as the sample G<b>2</b>: the silicon oxynitride film was formed under the film formation conditions of the sample G<b>1</b>, except for the pressure in a treatment chamber, which was 40 Pa.
0445Further, the silicon oxynitride film of another sample was formed under the following conditions: the glass substrate was placed in a treatment chamber of a plasma CVD apparatus, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm which were used as a source gas were supplied to the treatment chamber, the pressure in the treatment chamber was controlled to 200 Pa, and the power of 1500 W was supplied with the use of a 27.12 MHz high-frequency power source. The silicon oxynitride film was formed at a substrate temperature of 220° C. Note that the plasma CVD apparatus used here is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm<sup>2</sup>, and the power per unit area (power density) into which the supplied power is converted is 0.25 W/cm<sup>2</sup>.
0446The sample formed in the above manner is referred to as the comparative sample G<b>1</b>.
0447Next, the film thicknesses of the samples G<b>1</b> and G<b>2</b> and the comparative sample G<b>1</b> were measured. Then, the samples G<b>1</b> and G<b>2</b> and the comparative sample G<b>1</b> were immersed in 0.5 weight % of hydrofluoric acid for 45 seconds. Note that the temperature of the hydrofluoric acid at this time was room temperature. After that, the film thicknesses of the silicon oxynitride films of the samples were measured. From the results of the thicknesses, the etching rates of the silicon oxynitride films of the samples were calculated. The etching rates of the samples are shown in <figref idref="DRAWINGS">FIG. 26</figref>.
0448The etching rate of the sample G<b>1</b> was 8.5 nm/min, the etching rate of the sample G<b>2</b> was 7.8 nm/min, and the etching rate of the comparative sample G<b>1</b> was 13.5 nm/min.
0449As described above, under the conditions of the insulating film <b>23</b>, which is described in Embodiment 1, a silicon oxynitride film whose etching rate is lower than that of the silicon oxynitride film formed under the conditions of the insulating film <b>24</b>, which is described in Embodiment 1, and whose etching rate is 10 nm/min, preferably 8 nm/min, can be formed.
0450This application is based on Japanese Patent Application serial No. 2012-092324 filed with the Japan Patent Office on Apr. 13, 2012, Japanese Patent Application serial No. 2012-108840 filed with the Japan Patent Office on May 10, 2012, and Japanese Patent Application serial No. 2012-125447 filed with the Japan Patent Office on May 31, 2012, the entire contents of which are hereby incorporated by reference.
Contents5
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18 members in 3 offices
Priority claims7
| Document | Office | Kind | Date |
|---|---|---|---|
| 2012092324 | Japan | – | |
| 2012092324 | Japan | A | |
| 2012108840 | Japan | – | |
| 2012108840 | Japan | A | |
| 2012125447 | Japan | – | |
| 2012125447 | Japan | A | |
| 201313833389 | United States of America | A |
Members18
| Document | Office | Kind | |
|---|---|---|---|
| US2013270549A1 | United States of America | A1 | |
| KR20130116204A | Republic of Korea | A | |
| JP2014007381A | Japan | A | |
| US9337342B2 | United States of America | B2 | |
| US2016247903A1 | United States of America | A1 | |
| JP6059566B2 | Japan | B2 | |
| JP2017059851A | Japan | A | |
| JP6246307B2 | Japan | B2 | |
| JP2018061045A | Japan | A | |
| US10170599B2This record | United States of America | B2 | |
| JP6630334B2 | Japan | B2 | |
| JP2020053695A | Japan | A | |
| KR102108303B1 | Republic of Korea | B1 | |
| KR20200050921A | Republic of Korea | A | |
| JP6877519B2 | Japan | B2 | |
| JP2021122051A | Japan | A | |
| KR102355315B1 | Republic of Korea | B1 | |
| JP7095154B2 | Japan | B2 |
78 transactions on the USPTO file
Allowed after 2 non-final rejections, 1 final rejection and 1 RCE.
- Non-final rejections
- 2
- Final rejections
- 1
- RCEs
- 1
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 8th Year, Large EntityM1552 | M1552 | |
| Payment of Maintenance Fee, 4th Year, Large EntityM1551 | M1551 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Printer Rush- No mailingTCPB | TCPB | |
| Email NotificationEML_NTR | EML_NTR | |
| Mail Miscellaneous Communication to ApplicantMM327 | MM327 | |
| Miscellaneous Communication to Applicant - No Action CountM327 | M327 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Reasons for AllowanceEX.R | EX.R | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Request for Foreign Priority (Priority Papers May Be Included)RQPR | RQPR | |
| Priority document has successfully retrieved via PDX/DASPD.RECVD | PD.RECVD | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Dispatched from OIPEOIPE | OIPE | |
| FITF set to NO - revise initial settingFTFI | FTFI | |
| Application Is Now CompleteCOMP | COMP | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Preliminary AmendmentA.PE | A.PE | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Cleared by OIPE CSRL194 | L194 | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE | |
| Request from applicant for the USPTO to retrieve the Priority DocumentPDREQUST | PDREQUST | |
| PTO/SB/69-Authorize EPO Access to Search ResultsSREXR141 | SREXR141 | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
3 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF |
Numbers
- Publication
- 10170599
- Application
- 15147105
Titles
- English
- Semiconductor device including insulating films with different thicknesses and method for manufacturing the semiconductor device
Patent term adjustment
- Applicant delay
- −82 days
- Net adjustment
- 0 days
Classification
- CPC, 21
- H01L29/66969
- H10D30/6755
- H10D30/6704
- H10D99/00
- H01L21/0217
- H10D30/031
- H01L21/02271
- H01L21/02565
- H01L21/47573
- H01L27/1225
- H01L27/1259
- H10D30/6757
- H01L29/7869
- H10D86/021
- H01L29/78696
- H10D86/60
- H10D86/423
- H10P14/3434
- H10P14/6334
- H10P14/69433
- H10P50/282
- IPC, 16
- H01L29 78
- H01L21 16
- H01L21 00
- H01L29 24
- H01L21 47
- H01L29 66
- H01L27 12
- H01L21 02
- H01L29 786
- H01L21 4757
- H10P14 22
- H10P14 40
- H10P14 68
- H10P14 692
- H10P14 694
- H10P95 00