System and method for link based computing system having automatically adjustable bandwidth and corresponding power consumption

FIELD OF INVENTION

0001The field of invention relates to the computer sciences, generally, and, more specifically, to port circuitry for a link based computing system having automatically adjustable bandwidth and corresponding power consumption.

BACKGROUND

0002Computing systems have traditionally been designed with a “front-side bus” between their processors and memory controller(s). High end computing systems typically include more than one processor so as to effectively increase the processing power of the computing system as a whole. Unfortunately, in computing systems where a single front-side bus connects multiple processors and a memory controller together, if two components that are connected to the bus transfer data/instructions between one another, then, all the other components that are connected to the bus must be “quiet” so as to not interfere with the transfer.

0003For instance, if four processors and a memory controller are connected to the same front-side bus, and, if a first processor transfers data or instructions to a second processor on the bus, then, the other two processors and the memory controller are forbidden from engaging in any kind of transfer on the bus. Bus structures also tend to have high capacitive loading which limits the maximum speed at which such transfers can be made. For these reasons, a front-side bus tends to act as a bottleneck within various computing systems and in multi-processor computing systems in particular.

0004In recent years computing system designers have begun to embrace the notion of replacing the front-side bus with a network. <figref idref="DRAWINGS">FIG. 1</figref> shows an approach where the front-side bus is essentially replaced with a network <b>104</b><i>a </i>having point-to-point links between each one of processors <b>101</b>_<b>1</b> through <b>101</b>_N and memory controller <b>102</b>. The presence of the network <b>104</b><i>a </i>permits simultaneous data/instruction exchanges between different pairs of communicating components that are coupled to the network <b>104</b><i>a</i>. For example, processor <b>101</b>_<b>1</b> and memory controller <b>102</b> could be involved in a data/instruction transfer during the same time period in which processor <b>101</b>_<b>3</b> and processor <b>101</b>_<b>4</b> are involved in a data/instruction transfer. While providing a performance advantage, point-to-point link based systems typically are less power efficient than front-side bus systems.

0005Computing systems that embrace a network in lieu of a front-side bus may extend the network to include other regions of the computing system <b>104</b><i>b </i>such as one or more point-to-point links between the memory controller <b>102</b> and any of the computing system's I/O devices (e.g., network interface, hard-disk file, etc.).

BRIEF DESCRIPTION OF THE DRAWINGS

0006The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

0007<figref idref="DRAWINGS">FIG. 1</figref> (prior art) shows a computing system with a network that couples a processor to a memory controller;

0008<figref idref="DRAWINGS">FIG. 2</figref> shows a computing system having sockets interconnected by a network;

0009<figref idref="DRAWINGS">FIG. 3</figref> shows an embodiment of port circuitry;

0010<figref idref="DRAWINGS">FIG. 4<i>a </i></figref>shows various link bandwidths that the port circuitry of <figref idref="DRAWINGS">FIG. 3</figref> may need;

0011<figref idref="DRAWINGS">FIG. 4<i>b </i></figref>pertains to different states of operation that the port circuitry of <figref idref="DRAWINGS">FIG. 3</figref> is capable of effecting in light of various link bandwidth needs.

DETAILED DESCRIPTION

0012<figref idref="DRAWINGS">FIG. 2</figref> shows a more detailed depiction of a multi-processor computing system that embraces the placement of a network, rather than a bus, between components within the computing system. The components <b>210</b>_<b>1</b> through <b>210</b>_<b>4</b> that are coupled to the network <b>204</b> are referred to as “sockets” because they can be viewed as being plugged into the computing system's network <b>204</b>. One of these sockets, socket <b>210</b>_<b>1</b>, is depicted in detail.

0013According to the depiction observed in <figref idref="DRAWINGS">FIG. 2</figref>, socket <b>210</b>_<b>1</b> is coupled to network <b>204</b> through two bi-directional point-to-point links <b>213</b>, <b>214</b>. In an implementation, each bi-directional point-to-point link is made from a pair of uni-directional point-to-point links that transmit information in opposite directions. For instance, bi-directional point-to-point link <b>214</b> is made of a first uni-directional point-to-point link (e.g., a copper transmission line) whose direction of information flow is from socket <b>210</b>_<b>1</b> to socket <b>210</b>_<b>2</b> and a second uni-directional point-to-point link whose direction of information flow is from socket <b>210</b>_<b>2</b> to socket <b>210</b>_<b>1</b>.

0014Because two bi-directional links <b>213</b>, <b>214</b> are coupled to socket <b>210</b>_<b>1</b>, socket <b>210</b>_<b>1</b> includes two separate regions of data link layer and physical layer circuitry <b>212</b>_<b>1</b>, <b>212</b>_<b>2</b>. That is, circuitry region <b>212</b>_<b>1</b> corresponds to a region of data link layer and physical layer circuitry that services bi-directional link <b>213</b>; and, circuitry region <b>212</b>_<b>2</b> corresponds to a region of data link layer and physical layer circuitry that services bi-directional link <b>214</b>. As is understood in the art, the physical layer of a network typically forms parallel-to-serial conversion, encoding and transmission functions in the outbound direction and, reception, decoding and serial-to-parallel conversion in the inbound direction.

0015That data link layer of a network is typically used to ensure the integrity of information being transmitted between points over a point-to-point link (e.g., with CRC code generation on the transmit side and CRC code checking on the receive side). Data link layer circuitry typically includes logic circuitry while physical layer circuitry may include a mixture of digital and mixed-signal (and/or analog) circuitry. Note that the combination of data-link layer and physical layer circuitry may be referred to as a “port” or Media Access Control (MAC) layer. Thus circuitry region <b>212</b>_<b>1</b> may be referred to as a first port or MAC layer region and circuitry region <b>212</b>_<b>2</b> may be referred to as a second port or MAC layer circuitry region.

0016Socket <b>210</b>_<b>1</b> also includes a region of routing layer circuitry <b>211</b>. The routing layer of a network is typically responsible for forwarding an inbound packet toward its proper destination amongst a plurality of possible direction choices. For example, if socket <b>210</b>_<b>2</b> transmits a packet along link <b>214</b> that is destined for socket <b>210</b>_<b>4</b>, the routing layer <b>211</b> of socket <b>210</b>_<b>1</b> will receive the packet from port <b>212</b>_<b>2</b> and determine that the packet should be forwarded to port <b>212</b>_<b>1</b> as an outbound packet (so that it can be transmitted to socket <b>210</b>_<b>4</b> along link <b>213</b>).

0017By contrast, if socket <b>210</b>_<b>2</b> transmits a packet along link <b>214</b> that is destined for processor <b>201</b>_<b>1</b> within socket <b>210</b>_<b>1</b>, the routing layer <b>211</b> of socket <b>210</b>_<b>1</b> will receive the packet from port <b>212</b>_<b>2</b> and determine that the packet should be forwarded to processor <b>201</b>_<b>1</b>. Typically, the routing layer undertakes some analysis of header information within an inbound packet (e.g., destination node ID, connection ID) to “look up” which direction the packet should be forwarded. Routing layer circuitry <b>211</b> is typically implemented with logic circuitry and memory circuitry (the memory circuitry being used to implement a “look up table”).

0018The particular socket <b>210</b>_<b>1</b> depicted in detail in <figref idref="DRAWINGS">FIG. 2</figref> contains four processors <b>201</b>_<b>1</b> through <b>201</b>_<b>4</b>. Here, the term processor, processing core and the like may be construed to mean logic circuitry designed to execute program code instructions. Each processor may be integrated on the same semiconductor chip with other processor(s) and/or other circuitry regions (e.g., the routing layer circuitry region and/or one or more port circuitry region). It should be understood that more than two ports/bi-directional links may be instantiated per socket. Also, the computing system components within a socket that are “serviced by” the socket's underlying routing and MAC layer(s) may include a component other than a processor such as a memory controller or I/O hub.

0019A problem in link based computing systems involves the power consumption of the port circuitry. Specifically, because portions of the port circuitry may be designed to operate at some of the highest frequencies used by the entire system, the port circuitry may also possess some of the highest power consumption densities within the entire system. High energy consumption becomes particularly wasteful when the port circuitry's corresponding links are not being used at their maximum capacity. That is, the port circuitry may be consuming energy at its maximum power rate while the data flowing through the port circuitry is less than its maximum data rate.

0020<figref idref="DRAWINGS">FIGS. 3 and 4</figref> outline an embodiment of port circuitry designed to modulate its power consumption consistently with the amount of data that is presently flowing through it. A circuitry diagram is shown in <figref idref="DRAWINGS">FIG. 3</figref>, and, a bandwidth demand curve and state machine diagram are shown in <figref idref="DRAWINGS">FIGS. 4<i>a </i>and 4<i>b</i></figref>, respectively. According to the circuit diagram of <figref idref="DRAWINGS">FIG. 3</figref>, a single “logical” uni-directional link is actually constructed from a plurality of “physical” uni-directional links, where, the total bandwidth of the logical uni-directional link is viewed as the combined bandwidth of the physical uni-directional links. For instance, if there are eight 1.25 Gb/s physical uni-directional links connecting nodes A and B within the computing system's network, then, a 10.0 Gb/s logical link is viewed as connecting nodes A and B within the computing system's network. Each physical link may also be referred to as a “lane.”

0021Accordingly, <figref idref="DRAWINGS">FIG. 3</figref> shows a generic architecture for a single logical link having N lanes <b>302</b>_<b>1</b> through <b>302</b>_N in the transmit direction and N lanes <b>303</b>_<b>1</b> through <b>303</b>_N in the receive direction. In the transmit direction, each lane is driven by a respective transmitter <b>306</b>_<b>1</b> through <b>306</b>_N, and, each respective transmitter is preceded by a respective serializer <b>307</b>_<b>1</b> which converts a parallel “word” of data (e.g., a 10 bit wide word of data, a 16 bide word of data, etc.) into a serial bit stream. A shift register may be used as a serializer. A respective encoder for encoding the serialized bit stream (e.g., such as an 8b/10b encoder for minimizing data corruption errors during transmission) may be associated with each serializer. Each transmitter may be a “driver” circuit that drives electrical signals over its respective link (in which case each link may correspond to an electrically conductive transmission line (such as a 50 ohm or 75 ohm copper cable)), or, each transmitter may be an optical device such as a LED or LASER (in which case each link may correspond to a fiber optic cable).

0022Each logical link is presumed to be divided into a number of logical “channels” used by the higher layers of the computing system. For simplicity, the circuitry of <figref idref="DRAWINGS">FIG. 3</figref> only shows two channels “Channel_<b>1</b>” and “Channel_<b>2</b>.” Data to be transported over channel <b>1</b> is entered into queue <b>332</b>. Data to be transported over channel <b>2</b> is entered into queue <b>331</b>. A multiplexer <b>330</b> is used to control which channel is presently given use of the logical link. The output of multiplexer <b>330</b> feeds a queue <b>318</b> that packs words of data for transmission provided by either of queues <b>331</b> or <b>332</b>. Multiplexer <b>330</b> may also serve as a clock domain cross-over point as data entered into queues <b>331</b> or <b>332</b> may be timed according to a clock source having a different fundamental frequency than the clock source used to time the operation of the serializers <b>307</b> and drivers <b>306</b>. Outbound lane segregation circuitry <b>317</b> is a circuit that divides the data queued into streams of words for each lane, and, presents these streams to their respective serializer.

0023The inbound direction circuitry essentially operates in reverse order of the transmit direction circuitry. Respective electrical or optical receivers <b>308</b>_<b>1</b> through <b>308</b>_N receive serial data for each lane. Deserializers <b>309</b>_<b>1</b> through <b>309</b>_N convert the inbound serial bit streams into parallel words for each lane. An inbound lane aggregation circuit <b>318</b> packs the smaller words from the deserializers into larger words. These words may cross a clock domain boundary through queue <b>319</b>. From queue <b>319</b> outbound words are steered into one of channel queues <b>334</b>, <b>335</b>. Other pertinent parts of the circuitry of <figref idref="DRAWINGS">FIG. 3</figref> will be described in more detail further below.

0024<figref idref="DRAWINGS">FIG. 4<i>a </i></figref>demonstrates different combined inbound and outbound traffic intensities <b>401</b> through <b>404</b> that the port circuitry of <figref idref="DRAWINGS">FIG. 3</figref> may be asked to handle. <figref idref="DRAWINGS">FIG. 4<i>a </i></figref>also relates the specific traffic intensities to a specific state depicted in the state diagram of <figref idref="DRAWINGS">FIG. 4<i>b</i></figref>. Each state <b>405</b> through <b>408</b> in the state diagram corresponds to a specific mode of operation of the port circuit of <figref idref="DRAWINGS">FIG. 3</figref>. Thus, the port circuitry of <figref idref="DRAWINGS">FIG. 3</figref> has different operational modes, where, each mode is specially tailored for a specific traffic intensity. The port circuitry of <figref idref="DRAWINGS">FIG. 3</figref> includes a state machine <b>301</b> that: 1) detects the current traffic intensity environment that the port circuitry is being asked to handle; and, 2) places (or keeps) the port circuitry in a specific mode of operation that is appropriate for the detected traffic intensity.

0025Essentially, the spectrum of different traffic intensities that the port circuitry may be asked to handle are divided into multiple groups (e.g., the four groups depicted in <figref idref="DRAWINGS">FIG. 4<i>a</i></figref>: heavy <b>401</b>, moderate <b>402</b>, sporadic <b>403</b> and light <b>404</b>). Before describing the details of the state diagram, it may be helpful to understand more fully the nature of the traffic patterns that the port circuitry is apt to handle. Assuming the port circuitry is for a socket containing processing cores that communicate to a remote memory controller through the logical link, the outbound traffic intensity tends to be sporadic or light in nature (e.g., akin to traffic intensity <b>403</b> or <b>404</b>) because the CPU primarily asks the memory controller for data with a simple request (however in cases of high system performance demands even the request flow in the outbound direction can be heavy <b>401</b> or moderate <b>402</b>). Outbound traffic may consist data packets for writing to memory. The number of writes tends to be much smaller (for example, on-third to one-fourth) than the number of read requests to memory in a number of workloads which keeps the traffic on outbound link sporadic.

0026By contrast, in the inbound direction, the requested data is actually being received. A single request for data is typically responded to with multiple bytes of data (e.g., “a cache line's worth” of data such as 32 bytes, 64 bytes, etc.). Hence, the traffic intensity in the inbound direction, depending on the frequency at which the processing core(s) are asking for data through the transmit side, can vary any where between heavy <b>401</b> to light <b>404</b>. Accordingly, inbound traffic is burst-like in nature.

0027In the case of a logical link that connects two processing cores, the traffic flows are somewhat different than that described just above because the processing cores can snoop each other's caches. That is, referring to <figref idref="DRAWINGS">FIG. 3</figref>, a stream of requests for data can be received in the inbound direction (from the processing core to which the port circuit of <figref idref="DRAWINGS">FIG. 3</figref> is talking to) and a flow of data sent in response to these requests can flow out in the outbound direction.

0028According to one embodiment, the state machine <b>301</b> only concerns itself with the outbound circuitry regardless of where the port circuit is located in the system. In this case, only transmitters are turned on and off, so, the port circuitry essentially modulates the bandwidth in the outbound direction irregardless of the amount of traffic that is being received on its inbound side. Here, the state machine will receive some form of input signal from the outbound circuitry (such as a signal from circuitry associated with queue <b>318</b> that determines the state of the queue (i.e., how many entries are queued in the queue) and/or analyzes each request in the queue (e.g., to determine how much data is being asked for). Also, note that the port logic on the other side of the logical link will control the logical link bandwidth in the inbound direction.

0029In alternate embodiments, control packets may be sent between connected port circuits (i.e., port circuits that communicate to one another over the same logical link) so that both sides of a logical link are in the same state. For instance, according to one approach, referring to <figref idref="DRAWINGS">FIG. 3</figref>, if state machine <b>301</b> decides that the link needs to enter a specific state, a control packet is created and entered into outbound queue <b>318</b>. The packet is sent over the link in the outbound link direction and interpreted on the other side of the link which causes the port circuit on the other side of the link to enter the same state the state machine <b>301</b> just decided to enter.

0030According to one such approach, in the case of a logical link between a processing core and a memory controller, the state machine on the processing core side is the “master” and simply tells the memory controller side what state is the correct state. In this case, the state machine on the processing core side can determine the proper bandwidth and power consumption of the link simply by monitoring the requests for data flowing out in the outbound direction. In this case, the state machine will receive some form of input signal from the outbound circuitry (such as a signal from circuitry associated with queue <b>318</b>) that determines the state of the queue (i.e., how many entries are queued in the queue) and/or analyzes each request in the queue (e.g., to determine how much data is being asked for).

0031Even additional alternate embodiments exist (such as a memory controller side master that measures the requests on in its inbound side and/or the amount of data being sent on its outbound side). In the case of a logical link between two processing cores, again, one end of the link may act as the master, however, requests should be monitored in both the inbound and outbound directions so that the amount of requested data flowing through link can be measured in both directions. As such, the state machine should receive input signals from both the inbound and outbound circuitry (such as signals generated by circuitry associated with queue <b>318</b> and circuitry associated with queue <b>319</b>).

0032According to <figref idref="DRAWINGS">FIGS. 4<i>a </i>and 4<i>b</i></figref>, when the traffic intensity is heavy <b>404</b>, the port circuitry state machine <b>301</b> adjusts itself to be in the L0 state <b>405</b>. In the L0 state, all lanes are active (i.e., no lanes are turned off). In this case, the port circuitry has enabled the logical link for full bandwidth with corresponding full power consumption. When traffic intensity is moderate <b>404</b>, the port circuitry state machine <b>301</b> adjusts itself to be in the L0p or “L0 partial” state. In the L0p state, some of the lanes are turned “off” in both the inbound and outbound direction. As such, the logical link has less than full bandwidth, but, is also consuming less than full power as well.

0033For instance, according to one approach, N=8 and entry into the L0p state from the L0 state turns 4 lanes off (leaving four lanes on). Thus, the logical link is reduced to half bandwidth in the L0p state. In further embodiments there may also exist multiple sub-states of the L0p state to further granularize the bandwidth and/or power consumption adjustments that can be made. For instance, the L0p state could be divided into two sub-states, one that operates at half speed (e.g., four lanes are on for an N=8 system) and another that operates at a quarter speed (e.g., two lanes are on for an N=8 system).

0034When traffic intensity is sporadic <b>403</b>, the port circuitry state machine adjusts itself to be in the L0s state in which all lanes are turned off. Referring to <figref idref="DRAWINGS">FIG. 3</figref>, according to one embodiment, the manner in which lanes are turned off in the L0p and L0s states is of importance. Specifically, the transmitters of the respective lanes are turned “off” and the phase locked loop (PLL) and/or delay locked loop (DLL) circuits <b>312</b>, <b>313</b> that source the clock signal(s) <b>310</b> used by the transmitters <b>306</b>_<b>1</b> through <b>306</b>_N are left “on” (i.e., continue to operate). This, in turn, requires those transmitters that are turned off to be turned off according to some technique other than turning off the circuitry that generates their input clock signal. For instance, supply power could be removed (requiring some form of switch between each transmitter and/or receiver's input power node) or the input clock and/or input signals to the transmitter and/or receiver could be squelched (requiring a logic gate or some other circuit capable of voiding a thru signal to be placed in series with a clock signal line or in the signal channel flowing through the transmitter and/or receiver).

0035For simplicity, <figref idref="DRAWINGS">FIG. 3</figref> only shows individual “enable” lines <b>320</b>_<b>1</b> through <b>320</b>_N to achieve the turning off of the respective transmitters <b>306</b>_<b>1</b> through <b>306</b>_N (e.g., enable line <b>320</b>_<b>1</b> turns off transmitter <b>306</b>_<b>1</b>; enable line <b>320</b>_<b>2</b> turns off transmitter <b>306</b>_<b>2</b>; etc.). It should be understood that enable lines <b>320</b>_<b>1</b> through <b>320</b>_N can couple to any circuit that turns their respective transmitters off. Similarly, enable lines <b>320</b>_<b>1</b> through <b>320</b>_N individually turn off receivers <b>308</b>_<b>1</b> through <b>308</b>_N, respectively. Of course, a separate enable line for each transmitter and receiver may be used.

0036A motivation for leaving the phase locked loop (PLL) and/or delay locked loop (DLL) circuits <b>312</b>, <b>313</b> “on” is that the bring-up delay associated with the bringing up of these circuits back to full operation is avoided should the port circuit transition from the L0s state to a state in which bandwidth is needed. Here, phase locked loop and delay locked loop circuits are understood to require a “synch time” after they are first turned on before they reach their proper steady state frequency. By leaving these circuits <b>312</b>, <b>313</b> “on” in the L0s state, if the port circuit transitions back to a state in which working bandwidth is required, the port circuit need not wait for the synch time before traffic can begin to be transmitted over the logical link.

0037When traffic intensity is light <b>403</b>, the port circuitry state machine adjusts itself to be in the L1 state in which not only are all lanes are turned off but also the clock generation circuits <b>312</b>, <b>313</b> are turned off via clock control lines <b>315</b>, <b>316</b>. In this state, the traffic intensity is so small that the power savings benefit from turning off the clock generation circuit outweighs the penalty of having to endure the synch time delay when bringing up the port circuit out of the L1 state.

0038In a credit based flow control system, a port circuit can only send data if it has sufficient credits. Here, each time a packet is sent out, the credit count on the sending side is decremented. The credit(s) is/are effectively returned to the sending side by the receiving side only after the receiving side successfully receives the sent packet. Each credit typically represents an amount of data that is permitted to be sent over the link. In a design approach where the state machine <b>301</b> only concerns itself with modulating the bandwidth in the outbound direction, a problem may arise in the L0s and L1 states if the logical link imposes flow control through the use of credits. Specifically, because all outbound lanes are turned off in the L0s and L1 states, credits can not be returned to the sending side (i.e., traffic may be regularly flowing on the inbound side while the transmit side has no bandwidth).

0039According to one algorithm designed to prevent this situation, when the amount of credits that are waiting to be returned to the sending side have reached a threshold amount, a timer is started in which the outbound side will enter the L0 (or, alternatively, L0p) state if no transaction or other need to use the outbound direction naturally arises (i.e., no packet is presented in either of queues <b>331</b>, <b>332</b> for transport over the logical link that the returned credits can piggy back on). After reaching the L0 (or L0p) state, a control packet is then sent containing the credits that have stockpiled in the port circuit. Here, not shown in <figref idref="DRAWINGS">FIG. 3</figref>, is a counter that measures the number of credits waiting to be returned to the sending side. The state machine <b>301</b> has one or more inputs that indicate the value of this counter, and, the state machine <b>301</b> monitors these inputs in the L1 or L0s state. The state machine also has (or receives input from an associated) timer that indicates when the critical time period for triggering entry into a non-zero bandwidth state has elapsed.

0040Returning to <figref idref="DRAWINGS">FIG. 4<i>b</i></figref>, an embodiment of the state machine <b>301</b> operates as follows. According to one embodiment, the state machine <b>301</b> receives input signals from circuitry associated with one or more of the outbound queues (e.g., outbound queue <b>318</b> and/or both outbound queues <b>331</b>, <b>332</b>) that periodically determines the amount of data waiting to be transported and the average amount of data waiting to be transported between the sampling times. When the average amount of data falls below some critical threshold (e.g., within a range of 10 to 20% of the outbound direction's maximum bandwidth when all links are on (the L0 state)) over a period of time, the state machine <b>301</b> transitions <b>410</b> the port circuit into the L0p state <b>406</b>.

0041While in the L0p state <b>406</b>, the average amount of data waiting to be transported is still monitored, and, if it rises above some critical threshold (e.g., within a range of 60 to 80% of the outbound direction's maximum bandwidth when all links are on (the L0 state)) over a period of time (Tb) in which bandwidth is computed, the L0 state is re-entered <b>411</b>. Note that the threshold associated with transition <b>411</b> (L0p to L0) should be higher than the threshold of transition <b>410</b> (L0 to L0p) so that some form of hysteresis is built into the transitions between these two states. Recall that the L0p state may have multiple sub states that may be entered through different thresholds, where, each state has a corresponding outbound bandwidth. Specifically, a lower bandwidth sub-state is continually entered into as the average amount of data waiting to be transported continues to fall beneath lower and lower thresholds.

0042A transition <b>412</b> from the L0p state <b>406</b> to the L0s state <b>407</b> can be triggered if the average amount of data waiting to be transported falls to zero and remains there for a specific period of time (Ti). According to one approach, the time of inactivity is greater than the time period over which the average amount of data waiting to be transported is measured (in other words, Ti>Tb). A transition <b>413</b> from the L0s state to the L0 state (or, alternatively, transition <b>417</b> to the L0p state) occurs if one of the outbound channel queues <b>331</b>, <b>332</b> receives a packet for outbound transmission. As such, the state machine receives input signals from circuitry associated with these queues <b>331</b>, <b>332</b> that monitor their state and the amount of data they represent/contain. Transitioning from L0s based on the reception of a packet improves performance by minimizing the latency to reads (assuming that a read packet was received) whereas transitions from L0p to a high bandwidth state may use a bandwidth threshold metric. In systems where performance may not be as important as power savings (such as a mobile system), bandwidth metrics may be used to transition even from the L0s state. That is, in a desktop system, where higher performance is likely to be more important, transistion <b>413</b> may be utilized to minimize latency. In a mobile system, where the amount of power consumed is likely to be more important, transitions <b>413</b> and <b>411</b> (to go from L0s from L0p and L0) may be utilized. While in state L0s, the transition utilized may also be based on the transaction type of the arriving packet. For example, utilizing transition <b>413</b> for demand transactions to minimize latency and transition <b>417</b> for transactions where latency is not critical (for example, the latency associated with prefetch transactions is generally not critical).

0043A transition <b>415</b> into the L1 state occurs if the L0s state is maintained for a pre-determined time period. As such, the state machine maintains (or accepts input signals from) a timer that measures this time period. Transitions <b>418</b> and <b>416</b> from the L1 stat may use similar conditions as the transitions from L0s. For example, the conditions that apply to <b>413</b> and/or <b>417</b> may apply to transitions <b>418</b> and <b>416</b>.

0044Of course, other state machines only using a portion of the state machine described in <figref idref="DRAWINGS">FIG. 4<i>b </i></figref>may be utilized that employ the above described transitional techniques. For example, state machines utilizing just L0; L0 and L0s; L0 and L0p; or L0, L0s, and L0p; etc. may be used. Additionally, the state machine used for inbound and outbound traffic may be different.

0045Using L0s for inbound transactions typically provides the best power to performance tradeoff. L0p and L0p in combination with L0s does not quite have the same beneficial tradeoff (although the combination of L0s and L0p is better than L0p alone). For outbound transactions, the combination of L0p and L0s provides the best power to performance tradeoff. Additionally, the benefits of using L0s versus L0p, etc. differ based on the number of processing cores in the system.

0046The state machine <b>301</b> may be implemented with logic circuitry such as a dedicated logic circuit or with a microcontroller or other form of processing core that executes program code instructions. Thus processes taught by the discussion above may be performed with program code such as machine-executable instructions that cause a machine that executes these instructions to perform certain functions. In this context, a “machine” may be a machine that converts intermediate form (or “abstract”) instructions into processor specific instructions (e.g., an abstract execution environment such as a “virtual machine” (e.g., a Java Virtual Machine), an interpreter, a Common Language Runtime, a high-level language virtual machine, etc.)), and/or, electronic circuitry disposed on a semiconductor chip (e.g., “logic circuitry” implemented with transistors) designed to execute instructions such as a general-purpose processor and/or a special-purpose processor. Processes taught by the discussion above may also be performed by (in the alternative to a machine or in combination with a machine) electronic circuitry designed to perform the processes (or a portion thereof) without the execution of program code.

0047It is believed that processes taught by the discussion above may also be described in source level program code in various object-orientated or non-object-orientated computer programming languages (e.g., Java, C#, VB, Python, C, C++, J#, APL, Cobol, Fortran, Pascal, Perl, etc.) supported by various software development frameworks (e.g., Microsoft Corporation's .NET, Mono, Java, Oracle Corporation's Fusion, etc.). The source level program code may be converted into an intermediate form of program code (such as Java byte code, Microsoft Intermediate Language, etc.) that is understandable to an abstract execution environment (e.g., a Java Virtual Machine, a Common Language Runtime, a high-level language virtual machine, an interpreter, etc.), or a more specific form of program code that is targeted for a specific processor.

0048An article of manufacture may be used to store program code. An article of manufacture that stores program code may be embodied as, but is not limited to, one or more memories (e.g., one or more flash memories, random access memories (static, dynamic or other)), optical disks, CD-ROMs, DVD ROMs, EPROMs, EEPROMs, magnetic or optical cards or other type of machine-readable media suitable for storing electronic instructions. Program code may also be downloaded from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a propagation medium (e.g., via a communication link (e.g., a network connection)).

0049In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.