Feedback circuit and methods for negative charge pump

BACKGROUND

Field

This disclosure relates generally to semiconductor devices, and more specifically, to sensing voltages for circuits with reverse back biasing.

Related Art

Charge pumps are common blocks in modern microcontroller architectures; for instance, within FLASH memories blocks to generate program/erase voltages. In more advanced technological nodes, charge pumps can be employed to generate bulk/back biasing of logic gates. Biasing techniques are a key element to control the threshold voltage of logic devices to reduce leakage as well as increase speed.

Fully Depleted Silicon-On-Insulator (FDSOI) is a breakthrough technology that overcomes the limited back bias ranges of conventional bulk technologies. In order to generate the back bias voltage for PMOS devices, a regulated charge pump is necessary.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of an embodiment of a semiconductor device for a charge pump with reverse back biasing in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates a schematic diagram of an embodiment of a sense circuit that can be used in the semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a block diagram of an embodiment of a sense circuit that can be used in the semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a block diagram of another embodiment of a sense circuit that can be used in the semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates graphs of feedback voltage versus negative voltage for the sense circuits shown in <figref idref="DRAWINGS">FIGS. 3 and 4</figref>.

DETAILED DESCRIPTION

Embodiments of devices disclosed herein include regulated charge pumps to support extended forward back biasing (FBB) for PMOS devices. Sense circuitry is used to regulate a charge pump by providing a level-shifted positive feedback voltage that is proportional to the negative voltage output by the charge pump. Calibration is not required for the sense circuitry because the feedback path does not require a reference current or voltage. Moreover, there are no switches to control in the feedback path.

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of an embodiment of a semiconductor device <b>100</b> for a charge pump with reverse back biasing in accordance with the present invention that includes bandgap circuitry <b>102</b>, comparator <b>104</b>, clock oscillator <b>106</b>, logic gate <b>108</b>, charge pump <b>110</b>, load <b>112</b> and sense circuit <b>114</b>. Bandgap circuit <b>102</b> is coupled to supply voltage VDD and is configured to supply a reference voltage VREF to a negating input of comparator <b>104</b>. Sense circuit <b>114</b> provides a feedback voltage signal VFBK to a non-negating input of comparator <b>104</b>. Output of comparator <b>104</b> is provided to a first input of logic gate <b>108</b>, which is implemented as an AND gate in the example shown. Another input of logic gate <b>108</b> is coupled to receive the clock signal CLK from oscillator <b>106</b>. Output from logic gate <b>108</b> is provided to charge pump <b>110</b>, and output from charge pump (VNEG) <b>110</b> is provided to load <b>112</b>, and to sense circuit <b>114</b>. Sense circuit <b>114</b> is also coupled to supply voltage VSS.

Semiconductor device <b>100</b> provides a regulated charge pump <b>110</b> that can support FBB in Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology. FBB can be used to maximize battery lifetime but may also be applied to compensate for die-to-die and within-die process variations. Charge pump <b>110</b> can be implemented using two voltage-boosting cells in cascade and can be based on digital pulse skipping as disclosed in U.S. Pat. No. 6,819,162 issued to Pelliconi on Nov. 16, 2004. Other suitable configurations for charge pump <b>110</b> can be used. Sense circuit <b>114</b> receives a negative voltage VNEG from charge pump <b>110</b> and translates negative voltage VNEG to a positive feedback voltage VFBK (i.e., between VSS and VDD). Positive feedback voltage VFBK is compared to a positive reference voltage provided by bandgap circuit <b>102</b>. Under these conditions, sense circuit <b>114</b> can be exposed to voltages higher than supply voltage VDD. Thus, a configuration for sense circuit <b>114</b> that is capable of handling voltage higher than supply voltage VDD is disclosed herein.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates a schematic diagram of an embodiment of a sense circuit <b>114</b> that can be used in the semiconductor device <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> that includes a voltage to current (V2I) converter <b>200</b> with resistors <b>202</b>, <b>212</b>, <b>214</b>, PMOS transistors <b>204</b>, <b>208</b>, <b>220</b>, and NMOS transistors <b>206</b>, <b>210</b>, <b>218</b>, and a current mirror <b>201</b> with PMOS transistors <b>216</b>, <b>220</b> and resistor <b>222</b>. Resistor <b>202</b> includes a first terminal coupled to input voltage VIN, and a second terminal coupled to a source electrode of NMOS transistor <b>206</b> and a first terminal of resistor <b>212</b>. A second terminal of resistor <b>212</b> is coupled to negative voltage VNEG (from charge pump <b>110</b>). NMOS transistor <b>206</b> includes a source electrode coupled to the first terminal of resistor <b>212</b> and the second terminal of resistor <b>202</b>, a gate electrode coupled to gate electrodes of NMOS transistors <b>210</b>, <b>218</b>, and a drain electrode coupled to the gate electrode of NMOS transistor <b>206</b> and a drain electrode of PMOS transistor <b>204</b>. PMOS transistor <b>204</b> further includes a source electrode coupled to input voltage VIN, a source electrode of PMOS transistor <b>208</b>, and the first terminal of resistor <b>202</b>, and a gate electrode coupled to the gate electrode of PMOS transistor <b>208</b>. PMOS transistor <b>208</b> further includes a drain electrode coupled to the drain electrode of NMOS transistor <b>210</b> and a gate electrode coupled to the drain electrode of PMOS transistor <b>208</b>. NMOS transistor <b>210</b> further includes a gate electrode coupled to the gate electrodes of NMOS transistors <b>206</b>, <b>218</b>, and a source electrode coupled a first terminal of resistor <b>214</b> and to a source electrode of NMOS transistor <b>218</b>. Resistor <b>214</b> includes a first terminal coupled to the source electrodes of NMOS transistors <b>210</b>, <b>218</b> and a second terminal coupled to the second terminal of resistor <b>212</b> and negative voltage VNEG. NMOS transistor <b>218</b> further includes a gate electrode coupled to the gate electrodes of NMOS transistors <b>206</b>, <b>210</b> and a drain electrode coupled to the drain and gate electrodes of PMOS transistor <b>216</b>. PMOS transistor <b>216</b> further includes a gate electrode coupled to the gate electrode of PMOS transistor <b>220</b> and the drain electrode of PMOS transistor <b>216</b>, and a source electrode coupled to supply voltage VDD and a source electrode of PMOS transistor <b>220</b>. PMOS transistor <b>220</b> further includes a gate electrode coupled to the gate electrode of PMOS transistor <b>216</b> and a drain electrode coupled to a first terminal of resistor <b>222</b>. A second terminal of resistor <b>222</b> is coupled to supply voltage VSS, which may be ground. Feedback voltage VFBK is provided at node A between the drain electrode of PMOS transistor <b>220</b> and the first terminal of resistor <b>222</b>.

If transistors <b>206</b>, <b>210</b>, <b>218</b> and resistors <b>212</b> and <b>214</b> are matched, V2I converter <b>200</b> generates a current (IREF) that is proportional to the negative voltage VNEG output by charge pump <b>110</b> according to the following equation: <br /><i>I</i>REF=(<i>V</i>IN−<i>V</i>NEG)/(<i>R</i>1+2<i>R</i>2).

In current mirror <b>201</b>, reference current IREF is converted to positive feedback voltage VFBK at node A. If resistor <b>222</b> matches resistors <b>212</b>, <b>214</b>, output voltage mismatch caused by differences in the temperature coefficient of resistors <b>212</b>, <b>214</b> and <b>222</b> cancels out, eliminating the need to trim sense circuit <b>114</b>. Sense circuit <b>114</b> does not require an amplifier to convert voltage to current, saving space, reducing power consumption, and eliminating the need for amplifier compensation. In addition, the source electrodes of NMOS transistors <b>206</b>, <b>210</b> are degenerated, allowing sense circuit <b>114</b> to operate on lower supply voltage.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a block diagram of an embodiment of sense circuit <b>114</b> that can be used in the semiconductor device <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> with an example of voltages that can be used. Sense circuit <b>114</b> includes voltage to current converter <b>200</b> and current mirror <b>201</b> that may be coupled to one another as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Input voltage VIN is at zero (0) Volts, negative voltage VNEG is at −1.8 Volts, supply voltage VDD is at 1.8 Volts, and the value of feedback voltage VFBK is approximately 1.2 Volts. <figref idref="DRAWINGS">FIG. 5</figref> shows a graph (VFBK-<b>3</b>) of feedback voltage versus negative voltage for the voltages applied to sense circuit <b>114</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>. Notice that the VFBK-<b>3</b> curve has a linear negative slope until the feedback voltage reaches the threshold voltage VTH of transistors <b>216</b>/<b>220</b> in current mirror <b>201</b>. At VTH, the slope of the VFBK-<b>3</b> curve increases sharply and becomes substantially vertical, indicating a limited range of response for feedback voltage VFBK to comparator <b>104</b> (<figref idref="DRAWINGS">FIG. 1</figref>).

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a block diagram of an embodiment of sense circuit <b>114</b> that can be used in the semiconductor device <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> with another example of voltages that can be used to increase the range of response for feedback voltage VFBK. Sense circuit <b>114</b> includes voltage to current converter <b>200</b> and current mirror <b>201</b> that may be coupled to one another as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Input voltage VIN is at 1.8 Volts, negative voltage VNEG is at −1.8 Volts, supply voltage VDD is at 1.8 Volts, and the value of feedback voltage VFBK is approximately 1.2 Volts. <figref idref="DRAWINGS">FIG. 5</figref> shows a graph (VFBK-<b>4</b>) of feedback voltage versus negative voltage for the voltages applied to sense circuit <b>114</b> shown in <figref idref="DRAWINGS">FIG. 4</figref>. Notice that the feedback voltage (VFBK-<b>4</b>) has a constant linear negative slope through the entire range of negative voltage (VNEG), indicating a full range of response for feedback voltage VFBK to comparator <b>104</b> (<figref idref="DRAWINGS">FIG. 1</figref>). One tradeoff to having a full range of feedback voltage response is that power consumption is higher with input voltage (VIN) set to 1.8 Volts as shown in <figref idref="DRAWINGS">FIG. 4</figref> than at zero Volts as shown in <figref idref="DRAWINGS">FIG. 3</figref>.

By now it should be appreciated that in selected embodiments there has been provided a circuit (<b>114</b>) for converting a negative voltage to a positive proportional voltage that can comprise a first power supply terminal (VIN), a second power supply terminal (VDD), a third power supply terminal (Vss), an input node coupled to receive the negative voltage (VNEG), an output node (VFBK) coupled to provide the positive proportional voltage, a voltage-to-current converter (<b>200</b>) coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node, and a current mirror (<b>201</b>, <b>216</b>/<b>220</b>) coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor (R<b>4</b>) to provide the positive proportional voltage.

In another aspect, the current mirror can comprise a first transistor (<b>216</b>) of a first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the voltage-to-current converter to receive the intermediate current, and a control electrode coupled to the second current electrode, a second transistor (<b>220</b>) of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to a first terminal of the first resistor, and a control electrode coupled to the control electrode of the first transistor. The first terminal of the first resistor can provide the positive proportional voltage.

In another aspect, the voltage to current converter can comprise a first transistor (<b>204</b>) of a first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode, and a second current electrode; a second transistor (<b>208</b>) of the first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the control electrode of the first transistor, and second current electrode coupled to the control electrode of the second transistor; a third transistor (<b>206</b>) of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the third transistor, and a second current electrode coupled to the input node; and a fourth transistor (<b>210</b>) of the second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the input node.

In another aspect, the voltage to current converter can further comprise a second resistor (R<b>2</b><b>212</b>) coupled between the second current electrode of the third transistor and the input node; and a third resistor (R<b>3</b><b>214</b>) coupled between the second current electrode of the fourth transistor and the input node.

In another aspect, the voltage to current converter can further comprise a fifth transistor (<b>218</b>) of the second conductivity type having a first current electrode which provides the intermediate current, a control electrode coupled to the control electrode of the fourth transistor, and a second current electrode coupled to the second current electrode of the fourth transistor.

In another aspect, the second resistor and the third resistor have a same resistance value.

In another aspect, the voltage to current converter can further comprise a fourth resistor (R<b>1</b><b>202</b>) coupled between the second current electrode of the third transistor and the first power supply terminal.

In another aspect, the current mirror can comprise a sixth transistor (<b>216</b>) of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the first current electrode of the fifth transistor, and a control electrode coupled to the second current electrode of the seventh transistor; and a seventh transistor (<b>220</b>) of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to a first terminal of the first resistor, and a control electrode coupled to the control electrode of the sixth transistor. The first terminal of the first resistor can provide the positive proportional voltage.

In another aspect, the first, second, and third resistors can be a same type of resistor.

In another aspect, a supply voltage at the second power supply terminal (VDD) can be greater than a supply voltage at the first power supply terminal (VIN) and the supply voltage at the first power supply terminal (VIN) can be greater than the negative voltage (VNEG).

In another aspect, the circuit can further comprise a negative charge pump (<b>108</b>) coupled to provide the negative voltage to the input node.

In another aspect, the circuit can further comprise a comparator (<b>104</b>) coupled to receive the positive proportional voltage and a reference voltage (vref); and a logic circuit (<b>106</b>) coupled to receive an output of the comparator and a clock signal (<b>105</b>), and coupled to provide a control signal to the negative charge pump in response to the output of the comparator and clock signal.

In other embodiments, a circuit for converting a negative voltage to a positive proportional voltage can comprise a first power supply terminal (Vin); a second power supply terminal (Vdd); a third power supply terminal (Vss); an input node coupled to receive the negative voltage (Vneg) from a negative charge pump; an output node (Vfbk) coupled to provide the positive proportional voltage; a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node; a first resistor (R<b>4</b>); a first transistor (<b>216</b>) of a first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the voltage-to-current converter to receive the intermediate current, and a control electrode coupled to the second current electrode; and a second transistor (<b>220</b>) of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to a first terminal of the first resistor, and a control electrode coupled to the control electrode of the first transistor. The first terminal of the first resistor can provide the positive proportional voltage.

In another aspect, the voltage to current converter can comprise a third transistor (<b>204</b>) of a first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode, and a second current electrode; a fourth transistor (<b>208</b>) of the first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the control electrode of the third transistor, and second current electrode coupled to the control electrode of the fourth transistor; a fifth transistor (<b>206</b>) of a second conductivity type having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the first current electrode of the fifth transistor, and a second current electrode coupled to the input node; and a sixth transistor (<b>210</b>) of the second conductivity type having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to the input node.

In another aspect, the voltage to current converter can further comprise a second resistor (R<b>2</b><b>212</b>) coupled between the second current electrode of the fifth transistor and the input node; a third resistor (R<b>3</b><b>214</b>) coupled between the second current electrode of the sixth transistor and the input node; and a fourth resistor (R<b>1</b><b>202</b>) coupled between the second current electrode of the fifth transistor and the first power supply terminal.

In another aspect, the voltage to current converter can further comprise a seventh transistor (<b>218</b>) of the second conductivity type having a first current electrode which provides the intermediate current, a control electrode coupled to the control electrode of the sixth transistor, and a second current electrode coupled to the second current electrode of the sixth transistor.

In another aspect, the second resistor and the third resistor have a same resistance value.

In still further selected embodiments, in a circuit having a first power supply terminal (Vin), a second power supply terminal (Vdd), and a third power supply terminal (Vss), a method can comprise providing a negative voltage to an input node of a voltage-to-current converter powered by the first power supply terminal; generating an intermediate current proportional to the negative voltage at the input node of the voltage-to-current converter; and using a current mirror powered by the second supply power terminal to mirror the intermediate current at the output node of the voltage-to-current converter through a resistor to the third power supply terminal to provide a positive proportional voltage at a first terminal of the resistor that is proportional to the negative voltage.

In another aspect, the current mirror can comprise a first transistor (<b>216</b>) of a first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the voltage-to-current converter to receive the intermediate current, and a control electrode coupled to the second current electrode; and a second transistor (<b>220</b>) of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to a first terminal of the first resistor, and a control electrode coupled to the control electrode of the first transistor. The first terminal of the first resistor can provide the positive proportional voltage.

In another aspect, the voltage to current converter can comprise a first transistor (<b>204</b>) of a first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode, and a second current electrode; a second transistor (<b>208</b>) of the first conductivity type having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the control electrode of the first transistor, and second current electrode coupled to the control electrode of the second transistor; a third transistor (<b>206</b>) of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the third transistor, and a second current electrode coupled to the input node; a fourth transistor (<b>210</b>) of the second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the input node; a second resistor (R<b>2</b><b>212</b>) coupled between the second current electrode of the fifth transistor and the input node; a third resistor (R<b>3</b><b>214</b>) coupled between the second current electrode of the sixth transistor and the input node; and a fourth resistor (R<b>1</b><b>202</b>) coupled between the second current electrode of the fifth transistor and the first power supply terminal.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

Although the disclosure is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.