Reconfigurable circuit with crossbar switches including non-volatile resistive switches

TECHNICAL FIELD

0001This invention is about a reconfigurable circuit using non-volatile resistive switches.

BACKGROUND ART

0002Semiconductor integrated circuit (IC) is constructed by transistors built on a semiconductor substrate and upper layer wires used to connect transistors. The patterns of the transistors and wires are determined in the IC design stage. The interconnections between the transistors cannot be changed after fabrication.

0003In reconfigurable circuits such as FPGAs (Field-Programmable Gate Arrays), configuration data including operation and interconnection information is stored in memories, so that different logic operations and interconnections can be realized by configuring the memories after fabrication according to requirements of end users. In most of commercial FPGAs, SRAM (Static Random Access Memory) is used to store the configuration data.

0004Typically, each SRAM is composed of 6 transistors and each modern FPGA chip has more than 10M SRAMs, which causes extremely large area overhead and cost. Data routing is realized by a large number of CMOS switches (each composed of one SRAM and one nMOS transistor), which causes low logic density, large power consumption and large delay.

0005To overcome the problems of SRAM-based FPGAs, non-volatile resistive switches (NVRSs) integrated between wires up on transistor layer have been proposed for small area overhead. Non-volatility also contributes to zero standby power consumption.

0006As an example, in the reconfigurable circuits shown in the non-patent document 1 and patent document 1, a non-volatile resistive atom switch (NVRAS) composed of a solid-electrolyte sandwiched between an active electrode (Cu) and an inert electrode (Ru) has high OFF/ON resistance ratio (>10⁵), therefore the NVRAS can replace the CMOS switch for small area overhead and high logic density. Moreover, lower capacitance of the NVRAS than nMOS transistor leads to low power consumption and high speed. The ON/OFF state of the NVRAS is hold even when not powered, therefore when power is turned on configuration data can be loaded immediately.

Problem to be Solved by the Invention

0007Reconfigurable circuits may contain redundant circuitry that can be used to repair a reconfigurable circuit that contains defective transistors and wires in manufacturing, thereby improving production yield. For example, in patent document 2 and patent document 3, if defects are detected prior to shipment, redundant circuitry will replace the defective circuit before shipping to customers. Customers can configure the repaired device to perform desired logic functions correctly. However, the redundant circuitry is wasted if there is no defect, which causes area, delay and power consumption overhead.

0008Moreover, for the NVRS-based FPGA, rewrite cycle count of the NVRSs is limited (typically 1000 for the NVRAS in patent document 1). Defects of NVRSs may occur when customers configure the device after shipment, because a few of the NVRSs may have less rewrite cycle count than guaranteed rewrite cycle count. The defective NVRSs may be fixed ON or OFF when reconfiguration is performed, so that customers cannot configure the device to implement desired logic functions correctly. As a result, the broken device should be recalled and a substitute device should be delivered, which causes large cost.

0009It is desired to relieve defective NVRSs automatically after shipment to make sure customers can perform desired logic function correctly even if defects of NVRSs occur. One of relief methods usually used in memory chip is replacement of defective row/column NVRSs by redundant row/column NVRSs as shown in patent document 4. In NVRS-based reconfigurable circuit, crossbar switch using NVRSs realizes data routing. The relief method may be used to relieve defective NVRSs. As an example shown in <figref idref="DRAWINGS">FIG. 1A</figref>, one-level crossbar switch <b>301</b> is used to realize 4 inputs and 4 outputs data routing, and redundant switches <b>302</b> are used to relieve a defective NVRS S₂₂. The box in <figref idref="DRAWINGS">FIG. 1A</figref> shows symbols that indicate the ON and OFF states in which a normal NVRS is set and a defective NVRS is fixed. The data routing from IN<b>2</b> to OUT<b>2</b> cannot be realized because of the fixed OFF S₂₂. As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, the redundant NVRSs S_R2and S_2Rcan be turned ON to relieve the data routing from IN<b>2</b> to OUT<b>2</b>. The fixed OFF S₂₂is successfully relieved by redundant switches <b>302</b>. However, as shown in <figref idref="DRAWINGS">FIG. 2A</figref>, if a fixed ON NVRS S₁₂defect occurs, both the IN<b>1</b> and IN<b>2</b> are shorted, even if the redundant NVRSs S_R2and S_2Rare turned ON shown in <figref idref="DRAWINGS">FIG. 2B</figref>, the fixed ON defect cannot be relieved. The fixed ON S₁₂is unsuccessfully relieved by redundant switches <b>302</b>.

0010The purpose of this patent is to provide a reconfigurable circuit to relieve both fixed ON and OFF defects of NVRSs automatically to make sure customer can perform desired logic function even if defects occur. <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0011">[Non-patent document 1] N. Banno et al., “Reliable Solid-Electrolyte Crossbar Switch for Programmable Logic Device”, Symposium on VLSI Technology, pp. 115-116, (2010).</li><li id="ul0001-0002" num="0012">[Patent document 1] U.S. Pat. No. 8,816,312</li><li id="ul0001-0003" num="0013">[Patent document 2] U.S. Pat. No. 4,899,067</li><li id="ul0001-0004" num="0014">[Patent document 3] U.S. Pat. No. 8,860,460</li><li id="ul0001-0005" num="0015">[Patent document 4] U.S. Pat. No. 8,837,242</li></ul>

SUMMARY OF THE INVENTION

0016The present invention provides a reconfigurable circuit comprises: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the plurality of third non-volatile resistive switches.

0017According to the reconfigurable circuit by the present invention, both fixed ON and OFF defects of NVRSs can be automatically relieved to make sure customer can perform desired logic function even if defects occur.

BRIEF DESCRIPTION OF DRAWINGS

0018<figref idref="DRAWINGS">FIG. 1A</figref> illustrates that a fixed OFF NVRS defect occurs in a conventional one-level crossbar switch with redundant switches.

0019<figref idref="DRAWINGS">FIG. 1B</figref> illustrates that the fixed OFF NVRS defect can be relieved by the redundant switches.

0020<figref idref="DRAWINGS">FIG. 2A</figref> illustrates that a fixed ON NVRS defect occurs in a conventional one-level crossbar switch with redundant switches.

0021<figref idref="DRAWINGS">FIG. 2B</figref> illustrates that the fixed OFF NVRS defect cannot be relieved by the redundant switches.

0022<figref idref="DRAWINGS">FIG. 3</figref> illustrates a two-level crossbar switch with a redundant column in a NVRS-based reconfigurable circuit according to embodiment 1.

0023<figref idref="DRAWINGS">FIG. 4A</figref> illustrates that a fixed OFF NVRS defect occurs in a two-level crossbar switch with a redundant column according to embodiment 1.

0024<figref idref="DRAWINGS">FIG. 4B</figref> illustrates that the fixed OFF NVRS defect can be relieved by the redundant column according to embodiment 1.

0025<figref idref="DRAWINGS">FIG. 5A</figref> illustrates that a fixed ON NVRS defect occurs in a two-level crossbar switch with a redundant column according to embodiment 1.

0026<figref idref="DRAWINGS">FIG. 5B</figref> illustrates that the fixed ON NVRS defect can be relieved by the redundant column according to embodiment 1.

0027<figref idref="DRAWINGS">FIG. 6</figref> illustrates structure of the NVRS-based reconfigurable circuit according to embodiment 1.

0028<figref idref="DRAWINGS">FIG. 7</figref> illustrates a write circuit of the NVRS in a two-level crossbar switch with a redundant column according to embodiment 1.

0029<figref idref="DRAWINGS">FIG. 8</figref> illustrates a read circuit of the NVRS in a two-level crossbar switch with a redundant column according to embodiment 1.

0030<figref idref="DRAWINGS">FIG. 9</figref> illustrates an address comparator in the NVRS-based reconfigurable circuit according to embodiment 1.

0031<figref idref="DRAWINGS">FIG. 10</figref> illustrates a pre-decoder in the NVRS-based reconfigurable circuit according to embodiment 1.

0032<figref idref="DRAWINGS">FIG. 11</figref> illustrates a controller in the NVRS-based reconfigurable circuit according to embodiment 1.

0033<figref idref="DRAWINGS">FIG. 12</figref> illustrates configuration flow chart of the NVRS-based reconfigurable circuit when a fixed OFF NVRS defect occurs according to embodiment 1.

0034<figref idref="DRAWINGS">FIG. 13</figref> illustrates configuration flow chart of the NVRS-based reconfigurable circuit when a fixed ON NVRS defect occurs according to embodiment 1.

0035<figref idref="DRAWINGS">FIG. 14</figref> illustrates a two-level crossbar switch with multiple redundant columns in a NVRS-based reconfigurable circuit according to embodiment 2.

0036<figref idref="DRAWINGS">FIG. 15</figref> illustrates structure of the NVRS-based reconfigurable circuit according to embodiment 2.

0037<figref idref="DRAWINGS">FIG. 16</figref> illustrates a pre-decoder in the NVRS-based reconfigurable circuit according to embodiment 2.

0038<figref idref="DRAWINGS">FIG. 17</figref> illustrates a write circuit of the NVRS in a two-level crossbar switch with multiple redundant columns according to embodiment 2.

0039<figref idref="DRAWINGS">FIG. 18</figref> illustrates a read circuit of the NVRS in a two-level crossbar switch with multiple redundant columns according to embodiment 2.

0040<figref idref="DRAWINGS">FIG. 19A</figref> illustrates that multiple fixed OFF NVRS defects occur in a two-level crossbar switch with multiple redundant columns according to embodiment 2.

0041<figref idref="DRAWINGS">FIG. 19B</figref> illustrates that the fixed OFF NVRS defects can be relieved by the redundant columns according to embodiment 2.

0042<figref idref="DRAWINGS">FIG. 20A</figref> illustrates that fixed ON NVRS defects occur in a two-level crossbar switch with multiple redundant columns according to embodiment 2.

0043<figref idref="DRAWINGS">FIG. 20B</figref> illustrates that the fixed ON NVRS defects can be relieved by the redundant column according to embodiment 2.

0044<figref idref="DRAWINGS">FIG. 21A</figref> illustrates a two-level crossbar switch in a NVRS-based reconfigurable circuit according to embodiment 3.

0045<figref idref="DRAWINGS">FIG. 21B</figref> illustrates a two-level crossbar switch in a NVRS-based reconfigurable circuit according to embodiment 3.

0046<figref idref="DRAWINGS">FIG. 21C</figref> illustrates a two-level crossbar switch in a NVRS-based reconfigurable circuit according to embodiment 3.

0047<figref idref="DRAWINGS">FIG. 21D</figref> illustrates a two-level crossbar switch in a NVRS-based reconfigurable circuit according to embodiment 3.

0048<figref idref="DRAWINGS">FIG. 22</figref> illustrates a write circuit of the NVRS in a two-level crossbar switch with multiple redundant columns according to embodiment 3.

0049<figref idref="DRAWINGS">FIG. 23</figref> illustrates a read circuit of the NVRS in a two-level crossbar switch with multiple redundant columns according to embodiment 3.

0050<figref idref="DRAWINGS">FIG. 24A</figref> illustrates a non-volatile switch cell using 1 NVRS.

0051<figref idref="DRAWINGS">FIG. 24B</figref> illustrates a non-volatile switch cell using 1 transistor <b>2</b> NVRSs.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiment 1

0052A first exemplary embodiment of the present invention will be described. <figref idref="DRAWINGS">FIG. 3</figref> illustrates a two-level crossbar switch with a redundant column in a NVRS-based reconfigurable circuit. A 4×4 crossbar switch is used as an example. First and second wires are disposed in a first direction, while third wires and a fourth wire are disposed in a second direction intersecting the first direction. Inputs IN<b>0</b>, IN<b>1</b>, IN<b>2</b> and IN<b>3</b> are coupled to the first wires one-to-one, and outputs OUT<b>0</b>, OUT<b>1</b>, OUT<b>2</b> and OUT<b>3</b> are coupled to the second wires one-to-one. The NVRS-based reconfigurable circuit comprises first level crossbar switch <b>10</b>, second level crossbar switch <b>11</b> and redundant column <b>12</b>. In first level crossbar switch <b>10</b>, first NVRSs through which the first wires are connected to the third wires. In second level crossbar switch <b>11</b>, second NVRSs through which the second wires are connected to the third wires. In redundant column <b>12</b>, third NVRSs through which the fourth wire are connected to the first and second wires. The third NVRSs in the redundant column should be kept OFF, if there is no defective NVRS in the two-level crossbar switch. <figref idref="DRAWINGS">FIG. 3</figref> only shows one kind of two-level crossbar switches. The present invention is available for the other kinds of two-level crossbar switches. For example, both the first NVRSs and second NVRSs may be sparsely arranged.

0053<figref idref="DRAWINGS">FIGS. 4A and 4B</figref> illustrate relief of a fixed OFF NVRS defect in the reconfigurable circuit according to embodiment 1. The box in <figref idref="DRAWINGS">FIG. 4A</figref> shows symbols that indicate the ON and OFF states in which a normal NVRS is set and a defective NVRS is fixed. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, to perform routing paths IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b>, NVRSs S₁₁, S₂₂, S₅₁and S₆₂should be turned on. However, the routing path IN<b>2</b>-to-OUT<b>2</b> cannot be successfully performed, because the NVRS S₆₂fails to be turned ON (fixed OFF defect). To relieve the fixed OFF S₆₂, redundant column <b>12</b> replaces the defective column VL<b>2</b>. The NVRSs R_s2and R_s6in redundant column <b>12</b> are turned ON as shown in <figref idref="DRAWINGS">FIG. 4B</figref>. As a result, the routing path IN<b>2</b>-to-OUT<b>2</b> is relieved.

0054<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> illustrate relief of a fixed ON NVRS defect in the reconfigurable circuit according to embodiment 1. As shown in <figref idref="DRAWINGS">FIG. 5A</figref>, to perform routing paths IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b>, NVRSs S₁₁, S₂₂, S₅₁and S₆₂should be turned on. However, the NVRS S₅₂fails to be turned OFF (fixed ON defect), which results in collision of IN<b>1</b> and IN<b>2</b>. As a result, both the routing paths IN<b>1</b>-to-OUT<b>1</b> and

0055IN<b>2</b>-to-OUT<b>2</b> cannot be successfully performed. To relieve the fixed ON S₅₂, redundant column <b>12</b> replaces the defective column VL<b>2</b>. The NVRSs R_s2and R_s6in redundant column <b>12</b> are turned ON, and S₂₂and S₆₂in defective column VL<b>2</b> are turned OFF shown in <figref idref="DRAWINGS">FIG. 5B</figref>. As a result, both the routing paths IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b> are relieved.

0056<figref idref="DRAWINGS">FIG. 6</figref> illustrates structure of the reconfigurable circuit according to embodiment 1. The reconfigurable circuit comprises controller <b>21</b>, programmable logic cell array (PLCA) <b>22</b>, row and column write drivers <b>23</b>, <b>24</b>, row and column address decoders <b>33</b>, <b>34</b>, sense amplifier (SA) <b>25</b>, non-volatile memory <b>26</b>, address comparator (CMP) <b>27</b>, pre-decoder <b>28</b>, a special-purpose input/output (SPIO) and a general-purpose input/output (GPIO). In PLCA <b>22</b>, many logic blocks are connected with each other using the two-level crossbar switches shown in <figref idref="DRAWINGS">FIG. 3</figref>. Any logic function can be performed according to configuration data from outside through the SPIO. Controller <b>21</b> receives configuration data and row/column addresses from outside, controls write and read operation of NVRSs, detect the defective column address by comparing actual configuration result of NVRSs with the configuration data. Row and column address decoders <b>33</b>, <b>34</b> receiving addresses from controller <b>21</b> select a NVRS to be written or read. Row and column write drivers <b>23</b>, <b>24</b> generate set/reset voltage to turn ON/OFF the selected NVRS. SA <b>25</b> reads the state of the selected NVRS. Non-volatile memory <b>26</b> stores defective column address detected by controller <b>21</b>. If a defect of a NVRS occurs, controller <b>21</b> will enable CMP <b>27</b> to compare a column address with the defective column address stored in non-volatile memory <b>26</b>. If same, a redundant column enable signal HIT will be activated to “HIGH”. Pre-decoder <b>28</b> will prevent the column address from entering column address decoder <b>34</b>, and enable redundant column <b>12</b>. As a result, the NVRSs in redundant column <b>12</b> will be configured instead of the NVRSs in the defective column. The redundant column enable signal HIT corresponds to a redundancy enable signal. A line, through which the HIT is transmitted, is referred to as a redundancy enable signal line.

0057<figref idref="DRAWINGS">FIG. 7</figref> illustrates a write circuit for the NVRSs in NVRS-based reconfigurable circuit according to embodiment 1. The first and second wires are connected to first transistors one-to-one. Row address decoder <b>33</b> controls the first transistors to select one of the first and second wires to be connected to a row write driver PV_X. The third wires are connected to second transistors one-to-one. Column address decoder <b>34</b> controls the second transistors to select one of the third wires to be connected to a column write driver PV_Y. The fourth wire is connected to the column write driver PV_Ythrough a third transistor controlled by redundant column <b>12</b> enable signal HIT. Let me explain how to write S₅₁as an example. We set row address X=5 and column address Y=1, PV_Xand PV_Yare connected to a NVRS S₅₁. In case S₅₁is a NVRAS, PV_Xis connected to an active electrode (Cu) and PV_Yis connected to an inert electrode (Ru). If we want to configure S₅₁as “ON” state, PV_Xshould supply a high voltage and PV_Yshould supply a low voltage. In another word, a positive voltage is applied to S₅₁. On the other hand, if we want to configure S₅₁as “OFF” state, PV_Xshould supply a low voltage and PV_Yshould supply a high voltage. In another word, a negative voltage is applied to S₅₁.

0058<figref idref="DRAWINGS">FIG. 8</figref> illustrates a read circuit for the NVRSs in NVRS-based reconfigurable circuit according to embodiment 1. The principle is to apply a relative small positive voltage to a target NVRS, and use SA <b>25</b> to detect the current flows through the target NVRS to read its state. It is different from <figref idref="DRAWINGS">FIG. 7</figref> that the first and second wires are connected to ground line GND through the first transistors, and the third wires and the fourth wire are connected to SA <b>25</b> through the second transistors and the third transistor, respectively. Let me explain how to read state of S₅₁as an example. We set row address X=5 and column address Y=1, S₅₁is connected to SA <b>25</b> and GND. SA <b>25</b> clamps a fixed voltage (typically lower than 1V) applied to S₅₁, and detects current flow through S₅₁. If large current flows, the state of S₅₁is ON, otherwise, if there is almost no current flow, the state is OFF.

0059<figref idref="DRAWINGS">FIG. 9</figref> illustrates the CMP in NVRS-based reconfigurable circuit according to embodiment 1. CMP <b>27</b> includes 4 XNOR gates that compare respective bits of a defective column address YDAdd with respective bits of the column address YAdd, and a 5-input AND gate that receives the enable bit EN and 4 output signals from these 4 XNOR gates. HIT is activated to “HIGH” on condition that all the bits of the defective column address YDAdd match the bits of the column address YAdd and that the enable bit EN is “HIGH”.

0060<figref idref="DRAWINGS">FIG. 10</figref> illustrates the pre-decoder in NVRS-based reconfigurable circuit according to embodiment 1. Pre-decoder <b>28</b> consists of 4 AND gates and a NOT gate. When HIT is activated to “HIGH”, the output pre-decoded column address bits YAddpr₀˜YAddpr₃become “LOW”. Otherwise, when HIT is “LOW”, the output pre-decoded column address bits YAddpr₀˜YAddpr₃are equal to the column address bits YAdd₀˜YAdd₃.

0061<figref idref="DRAWINGS">FIG. 11</figref> illustrates the controller in NVRS-based reconfigurable circuit according to embodiment 1. Controller <b>21</b> comprises external I/F circuit <b>41</b>, functional unit (FU) <b>42</b>, memory <b>43</b>, address buffer <b>44</b>, data buffer <b>45</b> and internal bus <b>46</b>. External I/F circuit <b>41</b> controls input/output data transfer of the SPIO. FU <b>42</b> is used to control write/read operation of NVRSs, and detect defective NVRSs according to the program stored in memory <b>43</b>. Address buffer <b>44</b> stores addresses from outside. Data buffer <b>45</b> stores configuration data from outside and configuration result read from PLCA <b>22</b>.

0062<figref idref="DRAWINGS">FIG. 12</figref> illustrates configuration flow chart of the NVRS-based reconfigurable circuit when a fixed OFF NVRS defect occurs according to embodiment 1. We assume initial status is that a NVRS-based reconfigurable circuit has been programmed to perform a logic circuit A, and no NVRS defect has occurred. Purpose is to reprogram the NVRS-based reconfigurable circuit to perform another logic circuit B. First step <b>101</b> is to reset (turn OFF) all the NVRSs except the NVRSs in a redundant column which are initially set to be “OFF” state prior to shipment. Second step <b>102</b> is to configure the NVRS-based reconfigurable circuit according to the configuration data of the circuit B. Third step is get actual configuration result by reading out state of NVRSs using the read circuit shown in <figref idref="DRAWINGS">FIG. 7</figref> (steps <b>103</b> and <b>104</b>). Fourth step <b>105</b> is to compare the actual configuration result with the configuration data. If they are matched at step <b>106</b>, the circuit B is successfully performed in the NVRS-based reconfigurable circuit. Otherwise, if a fixed OFF NVRS defect occurs, the corresponding defective column is replaced by the redundant column (step <b>107</b>). As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the NVRS S₂₂is not necessary to be turned OFF for the replacement. Therefore the process directly loops back to second step <b>102</b> to configure the redundant column. As a result, the defective column is automatically replaced by the redundant column.

0063<figref idref="DRAWINGS">FIG. 13</figref> illustrates configuration flow chart of the NVRS-based reconfigurable circuit when a fixed ON NVRS defect occurs according to embodiment 1. It is different from the <figref idref="DRAWINGS">FIG. 12</figref> that if a fixed ON NVRS defect occurs, the process loops back to first step <b>101</b> (reset all the NVRSs). As shown in <figref idref="DRAWINGS">FIG. 5</figref>, to replace of the defective column VL<b>2</b> by the redundant column VLR, it is necessary to turn OFF the S₂₂and S₆₂. If not, collision of the IN<b>1</b> and IN<b>2</b> still occurs even if replacement is done.

Embodiment 2

0064Next, a second embodiment according to the present invention will be presented. The present embodiment discloses a two-level crossbar switch with multiple redundant columns in a NVRS-based reconfigurable circuit according to embodiment 2. More than one defect column can be relieved.

0065<figref idref="DRAWINGS">FIG. 14</figref> illustrates a two-level crossbar switch with multiple redundant columns in a NVRS-based reconfigurable circuit. A 4×4 crossbar switch is used as an example. First and second wires are disposed in a first direction, while third and fourth wires are disposed in a second direction intersecting the first direction. Inputs IN<b>0</b>, IN<b>1</b>, IN<b>2</b> and IN<b>3</b> are coupled to the first wires one-to-one, and outputs OUT<b>0</b>, OUT<b>1</b>, OUT<b>2</b> and OUT<b>3</b> are coupled to the second wires one-to-one. The NVRS-based reconfigurable circuit comprises first level crossbar switch <b>10</b>, second level crossbar switch <b>11</b> and redundant columns <b>13</b>. In first level crossbar switch <b>10</b>, first NVRSs through which the first wires are connected to the third wires. In second level crossbar switch <b>11</b>, second NVRSs through which the second wires are connected to the third wires. In redundant columns <b>13</b>, third NVRSs through which the fourth wires are connected to the first and second wires. The third NVRSs in redundant columns <b>13</b> should be kept OFF, if there is no defective NVRS in the two-level crossbar switch. <figref idref="DRAWINGS">FIG. 14</figref> only shows one kind of two-level crossbar switches. The present invention is available for the other kinds of two-level crossbar switches. For example, both the first NVRSs and second NVRSs may be sparsely arranged.

0066<figref idref="DRAWINGS">FIG. 15</figref> illustrates structure of the reconfigurable circuit according to embodiment 2. Different parts of the reconfigurable circuit according to embodiment 2 from the reconfigurable circuit according to embodiment 1 are shown as follows. We use 4 redundant columns <b>13</b> as an example to explain the differences. 4 non-volatile memories <b>26</b> are used to store addresses of maximum 4 defective columns. 4 CMPs <b>27</b> are used to match the maximum 4 defective columns' addresses and a column address from controller <b>21</b>, and generate HIT₀˜HIT₃to control corresponding to 4 redundant columns <b>13</b> in PLCA <b>22</b>.

0067The pre-decoder shown in <figref idref="DRAWINGS">FIG. 16</figref> is different from that shown in <figref idref="DRAWINGS">FIG. 10</figref> of the reconfigurable circuit according to embodiment 1. Pre-decoder <b>38</b> according to embodiment 2 consists of 4 AND gates and a NOR gate. When at least one of the HIT₀˜HIT₃is activated to “HIGH”, the output pre-decoded column address bits YAddpr₀˜YAddpr₃become “LOW”. Otherwise, when all of HIT₀˜HIT₃are “LOW”, the output pre-decoded column address bits YAddpr₀˜YAddpr₃are equal to input column address bits YAdd₀˜YAdd₃.

0068<figref idref="DRAWINGS">FIG. 17</figref> and <figref idref="DRAWINGS">FIG. 18</figref> illustrate write and read circuits for the NVRSs in NVRS-based reconfigurable circuit according to embodiment 2, respectively. It is different from the write and read circuits according to embodiment 1 that HIT₀˜HIT₄are used to control third transistors of redundant columns <b>13</b>. For example, if the column VL<b>1</b> is defective and its address Y=1 is stored in a non-volatile memory MO shown in <figref idref="DRAWINGS">FIG. 15</figref>, when controller <b>21</b> sends an column address Y=1, HIT₀is active to “HIGH”, and the redundant column VLR<b>0</b> is written or read instead of the defective column VL<b>1</b>.

0069<figref idref="DRAWINGS">FIGS. 19A and 19B</figref> illustrate relief of multiple fixed OFF NVRS defects in the reconfigurable circuit according to embodiment 2. As shown in <figref idref="DRAWINGS">FIG. 19A</figref>, to perform routing paths IN<b>0</b>-to-OUT<b>0</b>, IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b>, NVRSs S₀₀, S₁₁, S₂₂, S₄₀, S₅₁and S₆₂should be turned on. However, the routing paths IN<b>0</b>-to-OUT<b>0</b> and IN<b>2</b>-to-OUT<b>2</b> cannot be successfully performed, because the NVRSs S₄₀and S₆₂fail to be turned ON (fixed OFF defect). To relieve the fixed OFF S₄₀and S₆₂, the redundant columns VLR<b>0</b> and VLR<b>1</b> replace the defective columns VL<b>0</b> and VL<b>2</b>, respectively. The NVRSs R₀₀, R₄₀, R₂₁and R₆₁in the redundant columns VLR<b>0</b> and VLR<b>1</b> are turned ON as shown in <figref idref="DRAWINGS">FIG. 19B</figref>. As a result, the routing paths IN<b>0</b>-to-OUT<b>0</b> and IN<b>2</b>-to-OUT<b>2</b> are relieved.

0070<figref idref="DRAWINGS">FIGS. 20A and 20B</figref> illustrate relief of multiple fixed ON NVRS defects in the reconfigurable circuit according to embodiment 2. As shown in <figref idref="DRAWINGS">FIG. 20A</figref>, to perform routing paths IN<b>0</b>-to-OUT<b>0</b>, IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b>, NVRSs S₀₀, S₁₁, S₂₂, S₄₀, S₅₁and S₆₂are turned on. However, the NVRSs S₄₁and S₅₂fail to be turned OFF (fixed ON defect), which results in collision of IN<b>0</b>, IN<b>1</b> and FN<b>2</b>. As a result, all the routing paths IN<b>0</b>-to-OUT<b>0</b>, IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b> cannot be successfully performed. To relieve the fixed ON S₄₁and S₅₂, the redundant columns VLR<b>0</b> and VLR<b>1</b> replace the defective column VL<b>1</b> and VL<b>2</b>, respectively. The NVRSs R₁₀, R₅₀, R₂₁and R₆₁in the redundant columns VLR<b>0</b> and VLR<b>1</b> are turned ON, and S₁₁, S₅₁, S₂₂and S₆₂in defective columns VL<b>1</b> and VL<b>2</b> are turned OFF shown in <figref idref="DRAWINGS">FIG. 20B</figref>. As a result, all the routing paths IN<b>0</b>-to-OUT<b>0</b>, IN<b>1</b>-to-OUT<b>1</b> and IN<b>2</b>-to-OUT<b>2</b> are relieved.

Embodiment 3

0071Next, a third embodiment according to the present invention will be presented. The present embodiment discloses low-power high-write-reliability NVRS-based reconfigurable circuit.

0072The present embodiment focuses on a particular kind of two-level crossbar switch, where NVRSs are arranged on the diagonal line of the first or second level crossbar switch. <figref idref="DRAWINGS">FIGS. 21A to 21D</figref> show some examples. As shown in <figref idref="DRAWINGS">FIGS. 21A and 21B</figref>, diagonally arranged NVRSs in each of first level crossbar switches <b>10</b>, <b>14</b> are used to control inputs IN<b>0</b>˜IN<b>3</b> connected to second level crossbar switch <b>11</b>, and second level crossbar switch <b>11</b> can be reconfigured to perform different routing paths. As shown in <figref idref="DRAWINGS">FIGS. 21C and 21D</figref>, first level crossbar switch <b>15</b> can be reconfigured to perform different routing paths, and diagonally arranged NVRSs in each of second level crossbar switches <b>16</b>, <b>17</b> are used to control outputs OUT<b>0</b>˜OUT<b>3</b>. The diagonally arranged NVRSs are used to enable the two-level crossbar switch, and are initially turned ON prior to shipment. Diagonally arranged NVRS in a first (second) level crossbar switch are turned OFF only when fixed “ON” NVRS defects occur in a second (first) level crossbar switch, which leads to high reliability of the diagonally arranged NVRSs.

0073<figref idref="DRAWINGS">FIG. 22</figref> and <figref idref="DRAWINGS">FIG. 23</figref> illustrates write and read circuits of the NVRS in a two-level crossbar switch with multiple redundant columns according to embodiment 3, respectively. The two-level crossbar switch shown in <figref idref="DRAWINGS">FIG. 21A</figref> is used as an example to show the difference between the write and read circuits according to embodiment 2 and those according to embodiment 3. First and second level row address decoders <b>33</b>-<b>1</b>, <b>33</b>-<b>2</b> are used for the first and second level crossbar switches <b>10</b>, <b>11</b>, respectively. A first switch is coupled between power supply VDD and first row address decoder <b>33</b>-<b>1</b>. A second switch is coupled between ground line GND and first row address decoder <b>33</b>-<b>1</b>. When the first and second switches are turned OFF, first row address decoder <b>33</b>-<b>1</b> loses power entirely. On the other hand, when the first and second switches are turned ON, first row address decoder <b>33</b>-<b>1</b> receives power. If the two-level crossbar switch shown in <figref idref="DRAWINGS">FIG. 21C or 21D</figref> is used, the first and second switches will be provided in second row address decoder <b>33</b>-<b>2</b> instead of first row address decoder <b>33</b>-<b>1</b>. Power gating technology is introduced in the first level row address decoder. Sleep signal is not active to “HIGH” until fixed ON NVRS defects occur in the second level crossbar switch, which leads low power consumption.

0074In the present invention, a circular symbol used to indicate a NVRS in embodiments 1 to 3 may include all kinds of switch cells composed of NVRSs. For example, not only the switch cell composed of one NVRS R<b>1</b> shown in <figref idref="DRAWINGS">FIG. 24A</figref> but also the switch cell composed of two NVRSs R<b>1</b>, R<b>2</b> and one transistor shown in <figref idref="DRAWINGS">FIG. 24B</figref> are included in the present invention. ON/OFF resistance ratio of each of the NVRSs in embodiments 1 to 3 is over 10⁴. Each of the NVRSs in embodiments 1 to 3 comprises a metal oxide resistance change device or a solid electrolyte resistance change device. A semiconductor device may comprise the reconfigurable circuit in embodiments 1 to 3.

0075The reconfigurable circuit in the present invention may be used in mobile phone, IoT (Internet of Things) devices, and so on.

0076It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.

Further Exemplary Embodiment 1

0077A reconfigurable circuit comprising: <ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0000"><ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0078">a first level crossbar switch that has first non-volatile resistive switches;</li><li id="ul0003-0002" num="0079">a second level crossbar switch that has second non-volatile resistive switches; and</li><li id="ul0003-0003" num="0080">a first wire and third non-volatile resistive switches that are used for redundancy, wherein</li><li id="ul0003-0004" num="0081">input wires of said second level crossbar switch are connected to output wires of said first level crossbar switch one-to-one, and</li><li id="ul0003-0005" num="0082">input wires of said first level crossbar switch and output wires of said second level crossbar switch are connected to said first wire through said plurality of third non-volatile resistive switches.</li></ul></li></ul>

Further Exemplary Embodiment 2

0083The reconfigurable circuit according to Further exemplary embodiment 1, wherein <ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0000"><ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0084">said third non-volatile resistive switches are fully arranged on said first wire.</li></ul></li></ul>

Further Exemplary Embodiment 3

0085The reconfigurable circuit according to Further exemplary embodiment 1, wherein <ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0000"><ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0086">more than two said first wires are provided; and</li><li id="ul0007-0002" num="0087">said first wires are connected to said input wires of said first level crossbar switch and said output wires of said second level crossbar switch through said third non-volatile resistive switches.</li></ul></li></ul>

Further Exemplary Embodiment 4

0088The reconfigurable circuit according to Further exemplary embodiment 3, wherein <ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0000"><ul id="ul0009" list-style="none"><li id="ul0009-0001" num="0089">said third non-volatile resistive switches are fully arranged on said first wires.</li></ul></li></ul>

Further Exemplary Embodiment 5

0090The reconfigurable circuit according to Further exemplary embodiment 1, wherein <ul id="ul0010" list-style="none"><li id="ul0010-0001" num="0000"><ul id="ul0011" list-style="none"><li id="ul0011-0001" num="0091">said first non-volatile resistive switches are diagonally arranged in said first level crossbar switch, and said second non-volatile resistive switches are fully or sparsely arranged in said second level crossbar switch.</li></ul></li></ul>

Further Exemplary Embodiment 6

0092The reconfigurable circuit according to Further exemplary embodiment 5, wherein <ul id="ul0012" list-style="none"><li id="ul0012-0001" num="0000"><ul id="ul0013" list-style="none"><li id="ul0013-0001" num="0093">said input wires of said first level crossbar switch are connected to source terminals of first transistors one-to-one, wherein</li><li id="ul0013-0002" num="0094">gate terminals of said first transistors are connected to a first row address decoder, and drain terminals of said first transistors are connected to a row write driver;</li><li id="ul0013-0003" num="0095">said output wires of said second level crossbar switch are connected to source terminals of second transistors one-to-one, wherein</li><li id="ul0013-0004" num="0096">gate terminals of said second transistors are connected to a second row address decoder, and drain terminals of said second transistors are connected to said row write driver.</li></ul></li></ul>

Further Exemplary Embodiment 7

0097The reconfigurable circuit according to Further exemplary embodiment 6, wherein <ul id="ul0014" list-style="none"><li id="ul0014-0001" num="0000"><ul id="ul0015" list-style="none"><li id="ul0015-0001" num="0098">a first switch is coupled between power supply and said first row address decoder, and a second switch is coupled between ground line and said first row address decoder, wherein</li><li id="ul0015-0002" num="0099">when said first and second switches are turned OFF, said first row address decoder loses power entirely, and when said first and second switches are turned ON, said first row address decoder receives power.</li></ul></li></ul>

Further Exemplary Embodiment 8

0100The reconfigurable circuit according to Further exemplary embodiment 1, wherein <ul id="ul0016" list-style="none"><li id="ul0016-0001" num="0000"><ul id="ul0017" list-style="none"><li id="ul0017-0001" num="0101">said first non-volatile resistive switches are fully or sparsely arranged in said first level crossbar switch, and said second non-volatile resistive switches are diagonally arranged in said second level crossbar switch.</li></ul></li></ul>

Further Exemplary Embodiment 9

0102The reconfigurable circuit according to Further exemplary embodiment 8, wherein <ul id="ul0018" list-style="none"><li id="ul0018-0001" num="0000"><ul id="ul0019" list-style="none"><li id="ul0019-0001" num="0103">said input wires of said first level crossbar switch are connected to source terminals of first transistors one-to-one, wherein</li><li id="ul0019-0002" num="0104">gate terminals of said first transistors are connected to a first row address decoder, and drain terminals of said first transistors are connected to a row write driver;</li><li id="ul0019-0003" num="0105">said output wires of said second level crossbar switch are connected to source terminals of second transistors one-to-one, wherein</li><li id="ul0019-0004" num="0106">gate terminals of said second transistors are connected to a second row address decoder, and drain terminals of said second transistors are connected to said row write driver.</li></ul></li></ul>

Further Exemplary Embodiment 10

0107The reconfigurable circuit according to Further exemplary embodiment 9, wherein <ul id="ul0020" list-style="none"><li id="ul0020-0001" num="0000"><ul id="ul0021" list-style="none"><li id="ul0021-0001" num="0108">a first switch is coupled between power supply and said second row address decoder, and a second switch is coupled between ground line and said second row address decoder, wherein</li><li id="ul0021-0002" num="0109">when said first and second switches are turned OFF, said second row address decoder loses power entirely, and when said first and second switches are turned ON, said second row address decoder receives power.</li></ul></li></ul>

Further Exemplary Embodiment 11

0110The reconfigurable circuit according to any one of Further exemplary embodiments 1 to 10, wherein <ul id="ul0022" list-style="none"><li id="ul0022-0001" num="0000"><ul id="ul0023" list-style="none"><li id="ul0023-0001" num="0111">ON/OFF resistance ratio of each of said first, second and third non-volatile resistive switches is over 10⁴.</li></ul></li></ul>

Further Exemplary Embodiment 12

0112The reconfigurable circuit according to any one of Further exemplary embodiments 1 to 10, wherein <ul id="ul0024" list-style="none"><li id="ul0024-0001" num="0000"><ul id="ul0025" list-style="none"><li id="ul0025-0001" num="0113">each of said first, second and third non-volatile resistive switches comprises a metal oxide resistance change device or a solid electrolyte resistance change device.</li></ul></li></ul>

Further Exemplary Embodiment 13

0114A semiconductor device comprising: <ul id="ul0026" list-style="none"><li id="ul0026-0001" num="0000"><ul id="ul0027" list-style="none"><li id="ul0027-0001" num="0115">the reconfigurable circuit according to any one of Further exemplary embodiments 1 to 12.</li></ul></li></ul>

Further Exemplary Embodiment 14

0116A method for utilizing the reconfigurable circuit according to Further exemplary embodiment 9; the method comprising: <ul id="ul0028" list-style="none"><li id="ul0028-0001" num="0000"><ul id="ul0029" list-style="none"><li id="ul0029-0001" num="0117">said first and second switches are turned ON when a fixed ON defect occurs in one switch from among said second non-volatile resistive switches.</li></ul></li></ul>

Further Exemplary Embodiment 15

0118A method for utilizing the reconfigurable circuit according to Further exemplary embodiment 10; the method comprising: <ul id="ul0030" list-style="none"><li id="ul0030-0001" num="0000"><ul id="ul0031" list-style="none"><li id="ul0031-0001" num="0119">said first and second switches are turned ON when a fixed ON defect occurs in one switch from among said first non-volatile resistive switches.</li></ul></li></ul>