Three dimensional integrated circuit

Three-dimensional integrated circuit

THREE DIMENSIONAL INTEGRATED CIRCUIT

The present disclosure generally relates to the manufacture of integrated circuit devices. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional devices using heterogeneous and non-uniform layers (such as fully fabricated integrated circuits). To illustrate by way of example, the integrated circuit may especially include a memory device, a processor device, a digital signal processing device, a special application device, a controller device, a communication device, and others.

Generally, a mechanical backgrinding process is used to thin the semiconductor substrate in the conventional wafer stack. Backgrinding imparts a high level of mechanical stress to these devices and can cause large thickness variations. Therefore, other processes for separating substrates are desirable.

One method of substrate thinning is described in US Patent No. 6,316,333 (hereinafter, "Bruel"). Bruel described implanting ions through a gate structure to form a split plane in a substrate, and removing part of the substrate by splitting along the split plane. Bruel admitted that ion implantation caused damage to the device structure (e.g., channel area), which could render the device inoperable. Bruel describes building structures on the exposed surface of the substrate to selectively block ion implantation, thereby reducing damage to structures directly under the blocking structure.

However, there are several restrictions on Bruel's proposal. The structure described by Bruel is relatively large, for example, a gate length of 0.5 microns. Current devices use much smaller structures, for example, a gate length of 30 nanometers or less, which is more than one less than the gate length described by Bruel Magnitude. In order to accumulate enough hydrogen ions to perform a splitting operation, ions must be implanted through most of the device surface. In addition, modern devices are becoming increasingly complex and include a higher number of sensitive structures. Some of these structures (such as vertical transistors) have vertical components that are longer than horizontal components, which presents a greater chance of damage from a vertically oriented ion passing through the structure.

In addition, larger structures are generally more robust to ion damage than smaller structures. Smaller structures will have fewer atoms and are more sensitive to the breaking of atoms within the structure. For example, a barrier layer having a characteristic size of 10 nm can have a thickness of one tens of atoms, so that the rupture of a single atom can have a significant effect on the barrier properties.

The embodiments of the present disclosure are related to semiconductor devices including ion splitting technology. Embodiments can be used to form a three-dimensional integrated circuit (3DIC) by implanting ions through a circuit layer to form a split plane, repairing damage caused by the implantation, and stacking semiconductor substrates. These substrates can be processed at wafer scale.

In one embodiment, the process of forming a 3DIC includes providing a first substrate having a circuit layer including a plurality of dielectric and conductive structures, and implanting ions through the circuit layer and implanting into the second substrate A split plane is formed in a substrate, and after the plasma is implanted through the circuit layer, the semiconductor substrate is exposed to a hydrogen mixture at a first temperature for a first time to repair the implanted ions damage. A first part of the first substrate on which the plurality of dielectric and conductive structures are disposed is separated from a second part of the first substrate by splitting at the split plane, and the first part of the substrate is bonded to A second substrate. At least a part of the conductive structures of the first substrate can be subsequently connected to the conductive structures of the second substrate. The first temperature can be from 300C to 500C, and the time can be at least half an hour. The conductive and dielectric structures may include high-K dielectric structures, which include at least one material with a K value of 10 or more.

The first substrate and the second substrate may be wafer-scale substrates, and ion implantation After and before separating the first part from the second part, the first substrate may not be exposed to a temperature higher than, for example, 300C, 400C, 450C, or 500C.

In one embodiment, the hydrogen mixture has at least 1% hydrogen, and the remainder of the gas mixture is one or more inert gases. For example, the gas mixture may be synthetic gas.

Ions can be implanted at a temperature lower than 100C and a proton energy that is sufficient to damage most recoil and place the split plane deeper than the thickness of the depletion layer of the operating transistor.

In one embodiment, a procedure for repairing damage caused by ion implantation into a semiconductor substrate through a circuit layer including a conductive and dielectric structure is performed by using the conductive and dielectric structures of the semiconductor substrate. After the dielectric structure is implanted with ions, the semiconductor substrate is exposed to a hydrogen mixture at a first temperature for a first time to perform. The conductive and dielectric structures may include high-K dielectric structures, including hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO₂), hafnium silicate (HfSiO₄), tantalum oxide (TaO₅), tungsten oxide (WO₃), cerium oxide (CeO₂), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), strontium titanate (SrTiO₃), lanthanum aluminate (LaAlO₃), niobium pentoxide (NiO₅), zirconium silicate (ZrSiO₄) And zirconia (ZrO₂) At least one of.

The hydrogen mixture may have at least 1% hydrogen, and the remainder of one or more inert gases, such as synthesis gas. The exposure time can be at least 30 minutes, and the first temperature can be, for example, from 300C to 500C or from 350C to 450C. In one embodiment, the first time is from half an hour to five hours, and the first temperature is from 350C to 450C.

In an embodiment, the dielectric structure may include at least one dielectric material with a K value of 20 or greater, the first temperature is from 300C to 500C, the hydrogen mixture includes at least 1% hydrogen, and the temperature is at least 30 Minutes, and the plasma is implanted to form a split plane under the circuit layer.

A method of forming a device includes: providing a first substrate; depositing a thickness range compensation material on a first surface of the first substrate; implanting ions into the first substrate, and the plasma travels through the range Compensating the material to define a split section in the first substrate, the split section including at least one contour corresponding to the thickness of the absorbent material; removing the absorbent material; and splitting the first substrate at the split section, This exposes the at least one contour. In one embodiment, the at least one profile is a coolant channel. The range compensation material can be a photoresist material.

The method of forming a device may include coating the exposed surface of the coolant channel with a coating after splitting the first substrate. The coating material can be a material that prevents a chemical reaction between a coolant fluid and the first substrate material. For example, the coating material can be a nitride material or an oxide material. The thermal conductivity of the coating material may be higher than the thermal conductivity of a bulk material of the first substrate. In some embodiments, the first substrate has a thermal conductivity greater than 130 W/mK at a temperature of 25 degrees Celsius. The first substrate may include carbon, for example, in an embodiment where the first substrate is a diamond or graphite material.

After splitting, the split surface of the first substrate can be bonded to a second substrate having a circuit layer. In this embodiment, the bonding can be formed by an oxide layer deposited on a surface of the second substrate. When the range compensation layer is removed, a bonding layer can be deposited on the first surface of the first substrate and used to bond a third substrate including a circuit layer to the first substrate on the first substrate. The bonding layer on the surface. The first substrate, the second substrate, and the third substrate may be wafer-scale substrates.

In some embodiments, hydrogen ions are implanted through one or more circuit layers including high-K dielectrics and conductive elements. In these embodiments, ion implantation can damage the dielectric and conductive components. It can be repaired by exposing the substrate to an atmosphere including hydrogen and inert gas at a temperature ranging from 350 degrees Celsius to 500 degrees Celsius for at least 30 minutes to repair the damage to the dielectric structures damage.

In one embodiment, a method for forming a stacked semiconductor device includes: implanting ions through the dielectric and conductive structure of a first substrate to define a split plane in the first substrate; Splitting the first substrate at a location to obtain a split layer including one of the dielectric and conductive structures; bonding at least one die to the first substrate, the at least one die having a width smaller than that of the first substrate A width; depositing a planarizing material on the at least one die; planarizing the planarizing material to form a planarized upper surface on the at least one die; and stacking a third on the planarized upper surface Substrate.

The plasma can be implanted at a temperature of 100 degrees Celsius or below 100 degrees. In one embodiment, the plasma is implanted at room temperature.

In some embodiments, the total thickness variation (TTV) of the material split from the substrate is 4% or less than 4%, 2% or less than 2% or 1% or less than 1%. The first substrate, the second substrate, and the third substrate may be wafer-scale substrates. In addition, after the first substrate is split, the first substrate can be annealed to repair the damage to the dielectric and conductive structures caused by the plasma.

In one embodiment, in an environment including hydrogen, an annealing process is performed to repair the damage of the dielectric and conductive structures at a temperature of 350 degrees Celsius or greater than 350 degrees Celsius. The conditions in a repair procedure should be sufficient to allow hydrogen to penetrate the surface of the device and bind to molecules damaged by an implantation process. In a specific embodiment, the repair annealing is performed at a temperature of 400 degrees Celsius in an atmosphere including from 2% to 5% hydrogen (the rest is one or more inert gases). In one embodiment, the repair annealing is performed enough to allow hydrogen to diffuse despite the passivation of the circuit structure in the device (which may include an interconnection network of metal and low-k dielectric material) and occupy the damaged dielectric junction A time period for the site. In one embodiment, annealing is performed at a temperature of 400 degrees Celsius for one hour.

An embodiment may include after bonding the at least one die to the first substrate And before combining the at least one die on the third substrate, depositing a dielectric material on the at least one die.

Before implanting the plasma, a range compensation layer can be formed on the first substrate.

After the first substrate is split, the first substrate can be bonded to a second substrate. In one embodiment, the second substrate has a second dielectric and conductive structure, and the second substrate is formed by implanting ions through the second dielectric and conductive structures. The first substrate, the second substrate, and the third substrate may be wafers.

The small die can be one of several types of devices, including amplifiers, RF tuners, radio tuners, light-emitting diodes, and optical sensors.

The plurality of conductive structures may be a plurality of transistors, which have respective plurality of conductive gates separated from respective channel regions by gate dielectrics.

In one embodiment, a method of forming a three-dimensional integrated circuit includes: providing a first semiconductor substrate having a first circuit layer including a conductive metal and a dielectric material; The plurality of conductive metals and dielectric materials of the layer implant ions to establish a first split plane in the first substrate; split the first substrate at the first split plane; provide a second semiconductor substrate, the The second semiconductor substrate has a second circuit layer including a conductive metal and a dielectric material; ions are implanted through the conductive metal and dielectric material of the second circuit layer to establish a second circuit layer in the second substrate Splitting the plane; splitting the second substrate at the second splitting plane; bonding the first substrate to the second substrate; stacking at least one die on the second substrate, the die having a smaller number of A width of a width of a circuit structure; depositing a planarizing material on the at least one die; planarizing the planarizing material to form a planarized upper surface on the at least one die; and on the planarized A third substrate is stacked on the surface.

In one embodiment, a method of forming a semiconductor device includes: a An ion range compensation layer is formed on a surface of a substrate; ions are implanted through the ion range compensation layer and the dielectric and conductive structure of the first substrate to define a split plane in the first substrate; in the split plane Splitting the first substrate at a location to obtain a split layer including one of the dielectric and conductive structures; bonding at least one die to the first substrate, the at least one die having a width smaller than that of the first substrate A width; depositing a planarizing material on the at least one die; planarizing the planarizing material to form a planarized upper surface on the at least one die; and stacking a third on the planarized upper surface Substrate.

According to the present disclosure, technologies generally related to the manufacture of integrated circuit devices are provided. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers (such as fully fabricated integrated circuits). By way of example, the integrated circuit may include, among other things, a memory device, a processor device, a special application device, a controller device, a communication device, and others.

One method includes providing a first substrate having a dielectric structure and a conductive structure. Ions are implanted into the first substrate, and the plasma travels through the dielectric structures and the conductive structures to define a split plane in the first substrate. The first substrate is split at the split plane to obtain a split layer having the dielectric structures and one of the conductive structures. The split layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, and the split layer is one of the stacked IC layers.

Provides three-dimensional stacking and interconnection of heterogeneous and non-uniform layers (such as fully fabricated integrated circuits). Including technologies used to significantly reduce the interlayer separation and increase the available interlayer connection density (resulting in increased signal bandwidth and system functionality) compared to existing chip stacking methods that use interposers and via silicon vias (TSV). This technology is extended for the use of high-energy proton implantation for segmentation and layer transfer developed for homogeneous materials, such as the manufacture of silicon-on-insulator (SOI) wafers, which are suitable for layer transfer of heterogeneous layers and for damage in device structures Modification of the considerations of effects.

In one example, the present disclosure provides techniques including methods for manufacturing an integrated circuit. The method includes: providing a semiconductor substrate including a surface area, a plurality of transistor devices formed overlying the surface area, an interlayer interconnection including a structured metal layer and a structured dielectric layer The connection area and the interlayer connection overlying the plurality of transistor devices, and the overlying interconnection area to provide a dielectric material of the bonding interface, but there may be variations. The method includes forming an unpatterned photoresist material overlying one of the bonding interfaces provided by the dielectric material. In one example, the unpatterned photoresist material is configured to shield one or more of the plurality of transistors from electromagnetic radiation in a wavelength range below 400 nm, and to selectively adjust a subsequent One of the depths of the implantation process. The method subjects the unpatterned photoresist material to the implantation process to introduce a plurality of hydrogen particles to a split region underlying the surface region of the semiconductor substrate through the unpatterned photoresist material The depth is selected to define a transfer device between the split region and a surface of the dielectric material to form a plurality of interconnected conductive metal layers and insulation having a total metal thickness of 3 to 5 microns or less than 3 to 5 microns The thickness of one of the multiple layers of the dielectric. The method removes the unpatterned photoresist material after the hydrogen implantation step. The method bonds the surface of the dielectric material covering the transfer device to a transfer substrate to temporarily bond the semiconductor substrate to the transfer substrate.

In one example, the method applies enough energy to a portion of the split region to remove an upper portion of the semiconductor substrate from the lower bulk of substrate material, while using the transfer substrate to hold the upper portion of the semiconductor substrate so that the upper portion Contains a hydrogen damaged area. Energy can be provided spatially or globally as described in US Patent No. 6,013,563 (the '563 patent), which is hereby incorporated by reference in its entirety. In one example, the method subjects the hydrogen-damaged area overlying the transfer device to a smoothing process to remove part or all of the hydrogen-damaged area and form a backside surface. In one example, the method forms a thickness of the dielectric material overlying the backside surface.

In one example, the backside surface is configured with one or more layouts for forming a bottom landing pad in the structured metal layer connected to the transfer device and for connecting to one of an adjacent device layer An interlayer conductive path of a landing pad that combines the conductive path.

In one example, the method further includes depositing a dielectric layer to form a suitable bonding interface on the structured metal layer, the structured metal layer including a layer formed on a densely patterned metal interconnection layer The 5 to 10 micron thick conductive layer is used to provide a device power signal, a ground signal and a frequency synchronization signal, and the dielectric layer has a plurality of conductive paths through the dielectric layer for communicating with an upper transfer device The interlayer conductors in the layers are combined.

In one example, the method further includes aligning the transfer device layer and the semiconductor substrate to permanently bond the interlayer conduction path. In one example, the method further includes removing the temporarily bonded semiconductor substrate from the transfer device. In one example, the method further includes forming an internal flow path to allow coolant to pass therethrough to cool the transfer device. The interlayer coolant channels can be formed by using a patterned photoresist layer added on the unpatterned photoresist layer. The thickness and/or position of the patterned photoresist layer can be selected to adjust the local penetration depth of the proton beam to form a non-flat split surface in the substrate on the top surface of the coolant channel, wherein the bottom surface is joined by the lower plane supply.

In one example, the plurality of transistor devices are selected from CMOS devices, bipolar transistors, logic devices, memory devices, digital signal processing devices, analog devices, light absorption and imaging devices, photovoltaic cells or microelectromechanical structures (MEMS) or at least one of any combination thereof.

In one example, in the implantation process, the proton energy ranges from 500 kV to 2 MeV. In one example, the split area is located 1 to 10 microns from the top surface of the dielectric material. In one example, an unpatterned photoresist material having a high absorptivity of electromagnetic radiation with a wavelength of less than 400 nm is selected. In one example, the semiconductor substrate includes a silicon or other suitable material for The formation of electrical, optical or electromechanical devices.

In one example, the implantation process is provided at a dose ranging from 5E16 to 5E17 particles/cm². In one example, a beamline implanter is used to provide the implantation process. In one example, the implantation process is provided by a linear accelerator (LINAC) or other variations.

In one example, the split region has a peak concentration at the edge of the implantation range. In one example, the split area includes a plurality of hydrogen-filled micro plates. In one example, the split region is characterized by a stress sufficient to induce propagation of a substantially flat split region. In an example, the split region is configured as a uniform implant region or a patterned implant region. In one example, the splitting area is patterned or graded to facilitate a controlled splitting action.

In one example, the method includes forming a plurality of interconnect structures between the backside surface and the plurality of transistors or interconnect regions. In one example, the method further includes: providing a second semiconductor substrate including a plurality of second transistor devices and an overlying second dielectric material; and combining the second semiconductor substrate configured with the second semiconductor substrate The dielectric material is used to form a stacked semiconductor structure. In one example, the method further includes forming a patterned photoresist material overlying the unpatterned photoresist material.

In an example, the plurality of transistor devices and the interconnection region are characterized by a thickness of three microns and less; wherein the implantation process is characterized by a range of five microns to ten microns, so that the plurality of transistor devices And a characteristic size of the interconnect area does not affect the implantation process. In an example, the plurality of transistor devices and the interconnection region are characterized by a thickness of three micrometers and less; wherein the implantation process is characterized by a range of five micrometers to ten micrometers, so that the range of the implantation A characteristic space dimension is not disturbed by the thickness of the plurality of transistor devices and the interconnection region. In one example, the plurality of transistor devices are provided for a memory array or a logic array.

In one example, the energy system is selected from thermal, mechanical, chemical, electrical or a combination thereof to provide a split inducing energy. In one example, the energy is provided to cause a controlled splitting action, Including the initiation of division and the spread of division. In one example, the energy is provided to form a plurality of tiny plate bubbles in the splitting area. A split surface can be connected to a network of tiny board bubbles.

The present disclosure achieves these benefits and others in the case of known process technologies. However, a further understanding of the essence and advantages of the present disclosure can be achieved by referring to the subsequent parts of this specification and the accompanying drawings.

<p>1000Program flow</p><p>1002Donor substrate</p><p>1004Split plane formation</p><p>1006Disposal of substrates</p><p>1008Plasma activation and bonding process</p><p>1010Transfer layer</p><p>1011Recycling</p><p>1012Epitaxial (EPI) smoothing and thickening</p><p>1014Separable substrate</p><p>1050Simplified procedures</p><p>1052IC processing</p><p>1054Thinning</p><p>1100General IC program flow</p><p>1102wafer</p><p>1104IC Floor "n+1"</p><p>1106Wafer Scale Processing (WSP) stacking (1 to n)</p><p>1108Floor</p><p>1200Simplified procedures</p><p>1202Split Plane</p><p>1203Substrate</p><p>1204Split</p><p>1206IC processing</p><p>1300Simplified procedures</p><p>1302Substrate</p><p>1304Etching</p><p>1400Program flow</p><p>1402Substrate</p><p>1500Simplified program flow</p><p>1502Silicone film</p><p>1504Releasable substrate</p><p>1506IC process</p><p>1508Processed layer</p><p>1702Device layer</p><p>2100A program used to form a 3DIC structure with one of different grain sizes</p><p>2102Program</p><p>2104Program</p><p>2106Program</p><p>2108Program</p><p>2110Program</p><p>2112Planarization process</p><p>2202Base device structure</p><p>2202AWafer level bonding semiconductor layer</p><p>2202BWafer-level bonding semiconductor layer</p><p>2204Metal connection layer between devices</p><p>2206Vertical through hole</p><p>2208Interconnect layer</p><p>2210grain</p><p>2212Dielectric materials</p><p>2214Packing material</p><p>2216Interconnect structure</p><p>2218Upper device layer</p><p>2702Base device structure</p><p>2710grain</p><p>2718Upper device structure</p><p>2720Cooling channel</p><p>2722Vertical through hole</p><p>2902Patterned range compensation layer</p>

Fig. 1 is a schematic diagram of an embodiment of the disclosure.

Figure 2 illustrates a heterostructure containing a transistor device layer and an upper network of metal and low-k material in an example, in which provision is provided by implantation through an additional patterned photoresist layer Coolant channels between layers.

2A-2B are simplified cross-sectional views showing the use of patterned oxide as an absorbent.

3 is a schematic diagram of the transferred device layer viewed at the uneven surface split point after the protons are implanted through the patterned double-layer photoresist (PR) layer in an example, which is after removing the PR layer and attaching Check after a temporarily combined transfer seat frame.

Figure 4 outlines the IC device to be transferred at the high-dose proton implantation site in an example, where a uniform PR layer is in place on the device metal interconnection layer.

5 is a simplified diagram of the transfer device layer after proton implantation, removal of the PR layer of the temporarily bonded transfer mount, and completion of the wafer-level splitting process in an example.

6 shows the main steps applied to the bottom area of the transferred device layer in an example, including forming an oxide layer suitable for bonding after removing the implanted damage layer and finally adjusting the thickness of the device layer substrate layer, and forming A dense array of interlayer metal connectors and bonding pads.

Figure 7 shows the split and prepared transferred device layer in one example at a point precisely aligned with the mating interconnect structure on the upper surface of the lower device layer in the developed 3D device stack.

Figure 8 shows a compact 3D stack completed by one of the transferred IC devices bonded to the lower device layer in an example, where the alignment interlevel metal lines are in place and along the oxide layer bonding interface bonded to the landing pad Place.

Figure 9 shows a schematic example of two device layers stacked with a thick metal interconnect layer in one example.

FIG. 10 shows an example of a process flow for preparing a separable substrate according to an embodiment.

FIG. 10A shows the IC processing and/or thinning steps performed downstream of the program flow shown in FIG. 10.

FIG. 11 shows a simplified diagram of a general IC program flow according to an embodiment.

Figures 12-15 show simplified processing flows according to various alternative embodiments.

Fig. 16 is a simplified cross-sectional view showing one of the patterned high-K layers in one of the appropriate positions incorporating coolant channels.

Figure 17A is a simplified cross-sectional view showing an example of a detached, unsupported device layer deforming a thin substrate layer into a concave shape on a thin substrate layer under net compressive stress after its manufacture.

Figure 17B is a simplified cross-sectional view of the effect of adding a stress compensation layer to the back side of a thin substrate containing a stressed device layer on the top side.

Figure 18 is a simplified diagram of bonding a high purity, single crystal transfer layer to a chemical or mechanical "weak" separation layer on a substrate.

Figure 19A shows a simplified cross-sectional view of a high-energy, high-dose proton implantation to form a hydrogen-rich layer placed several microns below the CMOS transistor layer.

19B is a simplified cross-sectional view of the CMOS device layer after the formation of the final gate stack and metal interconnection structure is completed, in which the hydrogen-rich layer is performed by one of the steps performed before the "replacement gate" manufacturing step High-energy, high-dose proton implantation is formed.

Figure 20 shows a simplified cross-sectional view of the "top-to-top" metal layer combination of a transfer device layer and a lower device layer in a 3DIC stack.

Fig. 21 illustrates a procedure for forming a 3DIC structure having a different crystal grain size.

Fig. 22 is a simplified cross-sectional view showing one example of the structure of the lower device.

Figure 23 is a simplified cross-sectional view showing an example of a stacked device structure.

Figure 24 is a simplified cross-sectional view showing an example of a smaller grain size device bonded on a 3DIC.

Figure 25 is a simplified cross-sectional view showing an example of a material deposited on a smaller grain size device bonded on a 3DIC.

Figure 26 is a simplified cross-sectional view showing an example of a 3DIC structure with different crystal grain sizes.

Figure 27 is a simplified cross-sectional view showing another example of a 3DIC structure with different crystal grain sizes.

Figure 28 is a simplified cross-sectional view showing one example of proton implantation.

Figure 29 is a simplified cross-sectional view showing an example of proton implantation via a range compensation layer.

Figure 30 illustrates the thermal conductivity of a silicon substrate at various phosphorus-containing dopant concentrations and temperatures.

Figure 31 illustrates the thermal conductivity of a silicon substrate at various boron dopant concentrations and temperatures.

Figure 32 illustrates the temperature-dependent thermal conductivity for 6H-SiC at various temperatures and dopant concentrations.

Figure 33 illustrates the thermal conductivity of various carbon materials.

Figure 34 illustrates a bonding step for a transfer layer.

Figure 35 illustrates the formation of a buried hydrogen profile below the partially completed device layer.

Figure 36 illustrates a complete device layer on the hydrogen profile.

Figure 37 illustrates a 1 MeV proton implanted in a 3μm thick multilayer containing Cu metal and SiO on a Si substrate₂The dielectric layer, one of the CMOS device layers is located immediately below the metal/oxide multilayer.

38A and 38B respectively illustrate a recoil section and an ionization section for the implantation of FIG. 37.

According to the present disclosure, technologies generally related to the manufacture of integrated circuit devices are provided. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers (such as fully fabricated integrated circuits). To illustrate by way of example, the integrated circuit may especially include a memory device, a processor device, a digital signal processing device, a special application device, a controller device, a communication device, and others.

One embodiment establishes and expands the technical capabilities of two large regions, a layer transfer method for forming a homogeneous layer by a bonded stack (such as forming a silicon-on-insulator (SOI) wafer), and is complicated in current use and development. The sparse arrays of interposer layers and metal vias are used for device-to-device connections to form a variety of methods of 3-D stacking of electrical devices.

An embodiment provides the stacking and interconnection of a variety of electrical and electromechanical layers by simplifying the combination and having a physical-scale interconnect structure of a factor of 10 or more than the currently available insert/TSV method, and provides a great increase The number of electrical connection paths between devices (thus resulting in a greatly expanded data transmission bandwidth and 3-D device functionality). The present disclosure also provides for the protection of sensitive device layers from harmful ultraviolet radiation associated with the use of high-energy proton beams, and the construction of inter-level networks for coolant flow channels for self-functioning 3-D device stacking The volume removes heat. Additional details of the present disclosure can be found throughout this specification and more specifically below.

The embodiment can use such as H-cut separation and plasma to achieve room temperature transfer procedure The combination of activation bonding and Si separation using MeV proton technology combines a silicon-on-insulator (SOI) wafer formation method to achieve sufficient CMOS 3D stacking.

This layer transfer (LT) applied to 3D wafer scale packaging (WSP) can allow a large number of benefits due to its high parallel connectivity and ability to different processes. The embedded RAM/cache layer is a natural application.

The conventional WSP method can experience difficulties in one or more of the various regions: bonding, layer alignment, layer thinning, and layer interconnection. For example, thinning of the layer to less than 10 μm can desirably result in vias with a smaller aspect ratio.

The use of plasma fusion combination allows for advantageous alignment. Also, the embodiments as described herein can make layer alignment and interconnection practically achievable.

Embodiments using LT technology involving cold processing allow the processing of wafers with interlayer dielectric (ILD)/metal interconnections. The fusion bonding of plasma activation gives bonding strength, ultra-thin bonding, and no glue layer. As described below, rapid thinning operations are possible and do not necessarily require chemical mechanical polishing (CMP), polishing, or lapping operations.

The embodiments are compatible with a variety of IC manufacturing processes, including manufacturing processes for complementary metal oxide semiconductor (CMOS) and random access memory (RAM) devices.

The use of implantation under MeV energy allows thicker implantation through the entire device layer (10 μm). Therefore, a complete CMOS device layer can be transferred instead of a partial layer.

Implant scanning technology can be used. Examples may include improving channel performance through "jitter".

According to an embodiment, the use of MeV protons for full CMOS stacking can provide certain benefits. Embodiments may allow avoiding shadows due to CMOS layers including transistor, dielectric, and/or metal layer structures.

1 MeV proton beam is sufficient to perform through 8 Cu metal interconnection layers and a full deep H-cut implantation of CMOS microprocessor (MPU), with<img file="TWM588362U_D0001.tif" />10μm Si penetration.

For a 1 MeV proton beam passing through a model 8-layer Cu interconnect array and the connected CMOS transistor layer, this 10 μm depth in Si is large enough to separate the damage peak from the CMOS device area. The desired minimum separation under the bonded oxide surface of the CMOS transistor layer in the proton-damaged area and the substrate layer of the transferred layer is of merit to the depletion of the substrate material of a biased, energized bulk CMOS array The depth, for a 1V supply voltage and a 10 ohm-cm substrate material, is about 1 micron. Depending on the device design and supply voltage, the CMOS transistor layer including bulk "finFET" and "fully depleted SOI" devices may have a slightly thinner substrate depletion thickness. The relative accuracy (disambiguation/range) of 1 MeV proton profile is better than that of standard SOI wafer manufacturing implants (in<img file="TWM588362U_D0002.tif" />40 keV) is much more accurate.

It should be further noted that the H peak depth can be reduced by spin-coating the resist absorption layer. This aspect is further described in conjunction with FIG. 1 to FIG. 9 discussed later below.

FIG. 10 shows an example of a process flow 1000 for preparing a separable substrate according to an embodiment. Here, the donor substrate 1002 is subjected to split plane formation 1004, for example, by implantation of hydrogen ions.

Next, the donor substrate including the split plane is bonded to a processing substrate 1006, for example, by a plasma activation bonding process 1008. Next, by executing the room temperature controlled splitting process (rT-CCP^TM) LT occurs so that a part of the donor remains together with the processing substrate. Alternatively, a part of the donor can be kept with a temporary carrier substrate, provided that the layer is to be re-transferred to a permanent treatment substrate again (for example, for backside-illuminated CMOS image sensors).

The remaining part of the 1011 donor substrate is recovered for additional use. The treatment including the transferred layer 1010 may be subjected to further processing, for example, epitaxial (EPI) smoothing and thickening 1012 to produce a separable substrate 1014.

Figure 10A shows a simplified program flow 1050, which illustrates the basis of Figure 10 The downstream steps performed by the board provided by the board manufacturer. These steps may include IC processing 1052 (for example, see Figure 11 below) and/or thinning 1054 (for example, see Figures 12-15 below).

Specifically, FIG. 11 shows a simplified diagram of a general IC program flow 1100 according to an embodiment. Here, the IC maker receives the "special wafer" 1102 and processes the IC layer "n+1" 1104 without any modification.

Next, the IC layer is bonded to the wafer scale processing (WSP) stack (1 to n) 1106. After bonding, the wafer 1102 can be released.

The last shown in FIG. 11 is to perform steps such as interconnect processing, chemical mechanical polishing (CMP), etc. to treat the surface of the layer 1108. This step can be repeated for layer "n+2".

At least four layer transfer (LT) package changes are possible. Figures 12 to 15 describe four options for thinning LT.

Figure 12 shows an example of LT after IC processing. The simplified process flow 1200 shown in this figure involves placing a split plane 1202 in the substrate 1203, and then splitting 1204 after the IC processing 1206. It requires more invasive subsequent IC manufacturing steps.

Figure 13 shows an embodiment of the split used onto an etchable substrate. The simplified process flow 1300 according to this embodiment allows the substrate 1302 to be etched 1304 more easily than the SOI combined back-grinding process.

In these embodiments, the etchable substrate may be thin. An electrostatic (ES) chuck can be used to help strengthen the split and handle thin substrates. The transparent substrate can help the layers to align.

Figure 14 shows an embodiment of a process flow 1400 in which the substrate 1402 includes a "thin" substrate attached to a releasable base substrate. This thin substrate can be used in the final 3D product. The releasable substrate is only used for disposal during the IC manufacturing process.

FIG. 15 shows a simplified program flow 1500 according to another embodiment. Here, the silicon film 1502 is mounted to a releasable substrate 1504. This releasable substrate is only used in IC process 1506 During the treatment, resulting in a treated layer 1508. Use an internal release layer after LT. Place the release layer in the bonding plane. LT is used to release the processed Si layer and then thicken if necessary.

In the case of one or more embodiments, certain features and benefits can be accumulated. For example, through the specific application of dense stacking of fully manufactured integrated circuits (including transistor layers and multilayer interconnection networks), the H-cut segmentation and layer transfer technology can be extended beyond the lamination of uniform composition layers to achieve Wafer scale stacking of heterogeneous and uneven individual layers.

Embodiments can use "close bonding" with H-cutting and layer transfer technology to achieve high data transmission bandwidth through high-density inter-die interconnects with thin device stacks.

Embodiments can increase manufacturability and device yield by using a room temperature to appropriate temperature process throughout the stacking process.

Some implementations can use H-cutting and plasma bonding operations to draw device layer lamination (using high-alignment accuracy bonding tools).

Certain embodiments can take advantage of changes regarding front-rear stacking and front-front stacking combinations, with corresponding interconnect depths and locations.

Some embodiments can make the entire device layer components thinner (no need for inserts), accompanied by a reduction in RC loss, even for high-density device-to-conductor connections.

Certain embodiments can implement methods for post-dividing damage layer removal and substrate thickness reduction (selective etching) that are suitable for bonding and thermal transfer requirements (much less stringent than SOI wafer layer lamination).

Certain additional factors for specific embodiments are now also described. In various IC designs, some of these factors can cope with uneven total Cu interconnect thickness.

For example, weights and measures can be used. The scanning effect of uneven Cu density collects the backscattered proton current from the large-angle collector facing the IC metal surface. For MeV proton beam, it has<img file="TWM588362U_D0003.tif" />1×1μm²Aperture. A precision scanner for IC movement under the aperture The net Cu density is planned by backscattered current.

Design rules can be used to resolve non-uniformities. These design rules can specify the allowable variation of the total Cu thickness across the IC device area. A large-area checkerboard H distribution can be used to achieve wafer-level segmentation.

A manufacturing process can be used to solve the non-uniformity. For example, a layer of "dummy" Cu or other similar material can be added at a location with a low Cu thickness (such as an interlayer metal via channel). Examples of other materials include materials such as CVD deposited oxide and nitride dielectrics, polymers, and other metals. Generally speaking, the material should have sufficient ion stop power and thickness so that the position of the deep proton peak is within a substantially similar depth across a splitting plane.

Embodiments can set the split plane depth (not directly affected by changes in proton energy or total Cu layer density) by constructing an IC device on a high-stress surface layer (such as a graded Si-Ge thin layer) to limit the The H concentration stops automatically after the high-stress interface. The split plane will be set by the position of the accumulated high concentration H distribution at the stacking high stress interface.

By increasing the accumulation of proton grid-like damage (via nuclear auto-stop events) by reducing the wafer temperature during proton implantation, the total proton dose and the dielectric bonding damage from electron auto-stop events can be reduced (at low k interconnects and high-k gate dielectrics).

FIG. 1 is a schematic diagram of an embodiment when a two-device 3D stacking process is completed. After the formation process by hydrogen implantation and the associated splitting process, the upper device layer (the heterogeneous layer containing the transistor formed in the semiconductor material usually Si and the metal usually Cu is combined with the metal used for the lining and Conductors (layers separated by low dielectric constant electrical insulator materials) of dense networks of various other metals) are separated from a semiconductor wafer. During the proton implantation, the transfer device structure is covered with a uniform photoresist layer of sufficient thickness and properties to protect the device layer from damaging exposure to ultraviolet radiation from the recombination process in the proton beam line plasma. For the situation shown in Figure 1, the transferred device layer is also coated with a second photoresist layer which is patterned to adjust the depth of the proton beam, And the resulting split surface along the path of the network of coolant flow channels is designed to remove heat from the volume of the completed 3-D device stack. The conductive structure includes the transistor junction between the substrate and the metal interconnection network contacting the transistor layer.

After the upper device layer is mounted to a temporary bonding treatment band switch, the split lower surface of the transfer device is processed to remove implant damage in the area of the split surface and adjust the thickness of the substrate layer of the transfer device. A CVD oxide layer is then deposited on the lower surface to provide an efficient bonding surface and to provide an electrically insulating and passivated surface for the coolant flow channel (if present). The lower device surface is then etched and filled with metal to form an inter-level electrical connection to the interconnection layer of the transfer device through a substrate and a deposited oxide layer thickness of about 1 or more micrometers. The inter-level metal lines in the upper transfer device layer are terminated with bonding pads, wherein the bonding surface is at the same plane as the deposited oxide bonding layer.

A similarly deposited oxide is formed on the top surface of the lower device to provide efficient bonding, and the network of vias is etched and filled with metal to provide electrical connection with the interconnect layer of the lower device. The lower metal line is terminated by a metal bond pad at the same plane as the oxide surface deposited underneath.

The two sets of metal bonding pads are aligned in a precision bonding device and subjected to bonding annealing treatment to complete the 2-level stack (with coolant channels) shown in FIG. 1.

Figure 2 shows a view of the patterned PR and device layer after layer transfer to the lower device layer. In Figure 2, a heterostructure containing a transistor device layer and an upper network of metal and low dielectric constant material that provides interconnects for integrated circuits (IC) is coated with a uniform photoresistance (PR) The layer in which the photoresist properties and thickness are selected to provide sufficient protection for the sensitive IC layer and interface from ultraviolet (wavelength less than 400nm) radiation caused by exposure to recombination events in the plasma of the proton accelerator beamline. The thickness and termination of the uniform PR layer are also selected to adjust the range of the proton beam to a desired depth below one of the IC device transistor and the depletion layer.

In Figure 2, a second patterned PR layer is added on the uniform PR layer, which The thickness and termination of the second PR layer are selected to locally adjust the depth of the implanted proton distribution to provide a non-flat material dividing surface. When bonding the transferred device layer to the lower device layer, after removing the PR layer and temporarily bonding to a shelf layer, the uneven split surface provides for the flow of coolant in the completed IC device stack for device operation A network path during which heat is removed, the network path reflects the patterning of the upper PR layer.

Also shown in FIG. 2 are the inter-level metal vias and the bonding landing pads and oxide bonding interfaces added to the lower section of the upper transferred device layer before bonding to the lower device layer, described in more detail in the following figure .

The top absorption layer can be used to (1) locally control the depth of the peak of the proton damage profile in the substrate of the transfer device, thereby controlling the position of the split surface at the separation; (2) define the coolant channel formed by the change in the depth of the split surface The lateral position and depth; and/or (3) provide a protective layer to absorb UV radiation caused by electron capture and subsequent radiation processes performed by proton ions in the accelerator beam line.

Some embodiments of this process use an unpatterned cross-linked photoresist (PR) layer, where a second PR layer is deposited on top, exposed and developed by photolithography to leave a patterned PR upper layer.

Other embodiments of this process can use CVD-deposited dielectric films. In some embodiments, an unpatterned CVD oxide layer is deposited on the top surface of the metal interconnection network to be transferred to the device layer of the 3DIC stack. The thickness of this first CVD oxide layer can be selected so that the combination of CVD oxide, device metal interconnection network, and device substrate stops the power effect and places protons and damage peaks on the surface of the main split plane below the transistor layer of the transfer device. The desired depth.

A CVD nitride layer is then deposited on the first CVD oxide layer to serve as an etch stop layer to protect the underlying oxide layer during the etching of the top CVD oxide layer.

Next, a second CVD oxide layer is deposited on the nitride layer. top The thickness of the CVD oxide layer can be selected to locally shift the position of the peak of the incident proton beam according to the required height of the coolant flow channel to be shallower than the position of the main split surface. The coolant flow channels are to be passed through the transfer device layer. The subsequent bonding to a flat bonding surface on an underlying device layer in the 3DIC stack is formed.

A PR layer can then be deposited on the top oxide, lithographically exposed and developed to leave a patterned PR upper layer. This patterned PR layer protects the top CVD oxide layer in the location where the coolant channel will be formed during the subsequent oxide etching step, wherein the nitride layer protects the lower oxide layer.

Figure 2A is a simplified cross-sectional view of a transfer device layer at the proton implantation site, which shows an unpatterned top CVD layer with a top CVD layer selected to shift the peaks of the proton profile to be at the split surface The thickness of one depth at the desired position. Once the patterned second CVD oxide layer has a thickness selected to shift the peak of the proton beam to the height of the (optional) coolant channel to be formed during the subsequent bonding step to the 3DIC device stack. A CVD nitride layer deposited between the two oxide layers serves as an etch stop layer for the top oxide patterned etch.

2B is a simplified diagram of the upper layer of the transfer device after the deposition of the unpatterned CVD oxide and nitride layer, and the deposition of the top CVD oxide and PR layer. After the lithographic exposure and development of the PR pattern, the exposed top CVD layer material is etched away. The nitride layer protects the lower CVD layer from etching removal. Remove the PR layer before proton implantation.

The use of a CVD dielectric layer to form the top absorber layer can provide manufacturing benefits that avoid process complication, which is accompanied by high-energy implants passing through the polymer PR film, such as due to collisions with the passing proton beam In the PR material, the combination of destroyed hydrogen and other volatile materials outgassing.

Through the use of patterned and unpatterned CVD top layer The local control of the proton implantation profile in the substrate layer can be used to compensate for the pattern density and total layer thickness in the metal interconnection network for a variety of chip designs across complex wafers and for processing large-area wafers in the process Local changes. This capability for local control of the proton profile depth and the position of the split surface at the separation point enables the use of constant energy proton beams for processing a variety of device types, thereby improving the efficiency of in-line wafer manufacturing.

Figure 3 is a schematic diagram of the transferred device layer viewed at the uneven surface split point after the protons are implanted through the patterned double-layer PR layer, which is viewed after removing the PR layer and attaching a temporarily bonded transfer mount . After the uneven surface is divided, the damaged material surrounding the split plane (the small plate containing H filling and the adjacent grid-like damage area) is removed, and the additional underlying material is removed, leaving the IC device transistor and depleted The desired depth of the substrate material of the area.

In addition, the non-planar segmented surface is then processed by the deposited oxide film to form a passivated surface wall for the coolant channel, and an efficient bonding surface for attachment to the adjacent device layer is formed. The lower area of the transferred device layer is also processed to form an interlayer metal connection path between the device layers, which is described in the later figures and discussion.

Figures 4 to 9 illustrate the 3D stacking process for a group of general IC layers using a uniform top PR layer. For simplicity, no incorporated coolant channels are provided. Additional details of these drawings can be found throughout this specification and more specifically below.

Figure 4 outlines the IC device to be transferred at the high-dose proton implantation site, where a uniform PR layer is in place on the device metal interconnection layer. The metal interconnection layer is usually a densely patterned multi-layer structure used in advanced logic devices (not much used in memory devices), and includes 10 to 15 Cu metal layers. The Cu metal layer and the conductive body are electrically isolated by interlaced layers of low-k insulating materials. In modern practice, the net Cu layer thickness is usually 3 microns or less than 3 microns, and there is no 5 to 8 microns thick metal layer used for device synchronization or "clock", signal, power, and grounding. The provision for the extra in the thick metal interconnects is provided as part of the inter-level stacking process.

The density, optical properties and thickness of the PR are selected to provide sufficient protection for the underlying device layer from exposure to UV wavelength recombination radiation from the proton accelerator beamline plasma, and to adjust the proton peak and split plane to be doped in the transistor And the depth below the depletion layer.

The view of the transfer device layer after the completion of the proton implantation, the removal of the PR layer attachment of the temporarily bonded transfer mount and the completion of the wafer-level splitting process is shown in FIG. 5. The splitting action can be affected by the local application of energy in the form of mechanical, chemical, laser or other thermal exposure or global energy or any combination thereof. Splitting can occur using any of the techniques disclosed in the '563 patent (which has been incorporated by reference), foaming techniques, or others.

Figure 6 shows the main steps applied to the bottom area of the transferred device layer, which include removing the proton-damaging material and any additional materials in the immediate vicinity of the splitting plane in order to obtain the desired thickness of the transferred substrate, by chemical vapor deposition ( CVD) forming a flat bonding interface and forming an interlevel metal line connecting the metal interconnection network of the transfer device to the lower bonding pad at the plane of the deposited bonding oxide interface. The formation of interlayer conductors is shown.

Figure 7 shows the split and prepared transferred device layer at a point precisely aligned with the mating interconnect structure on the upper surface of the lower device layer in the developed 3D device stack. One embodiment uses the capabilities of advanced alignment and bonding equipment. For 300mm wafers, the equipment has a wafer-level alignment tolerance in the range of 150nm. Display of through-holes and through-body landing pads.

Figure 8 shows a close 3D stack completed by one of the transferred IC devices bonded to the lower device layer, where the alignment interlevel metal lines are in place and bonded at the landing pad along the oxide layer bonding interface. Also shown in FIG. 8 is a top-deposited oxide layer, in which metal vias and landing pads are used at the bonding interface level for an additional device layer to be subsequently stacked on top of the currently transferred device layer.

For the 3D stacking of large-area, high-performance logic IC devices, the accurate transmission of power, clock, and signal pulses requires low-resistance paths provided by several micron thick metal wires. And so on The metal layer is too thick to be implanted by a proper (1 MeV or 2 MeV) energy proton beam, and can be used as a part of implantation and splitting after inter-level processing if necessary and provided before the stacking of subsequent device layers . Figure 9 shows a schematic example of one of the two device layers stacked with a thick metal interconnection layer. The power device has a completed metal layer in place (if it is the bottom device layer), and the device transferred on the top has an in-device transfer And thick metal interconnections added after permanent bonding and before bonding oxide deposition and forming interlevel metal lines and bonding landing pads. The dual device stack has an incorporated thick metal clock and power distribution layer.

The discussion here is based on a stack of general CMOS devices. A useful example is a memory device connected to a stacked expansion of a data transfer layer for high-bandwidth signal processing and calculations, such as currently formed by the use of interposer layers and metal connection lines called via silicon vias (TSV) The memory stack in which the length is about 30-50 microns, is more than 10 times the length of the inter-level connections foreseen in one embodiment.

The use of the embodiment can be used to provide a combination of a variety of electrical and electromechanical devices combined with heterogeneous device layers (for sensing visual images, chemical environments, and various physical conditions) to provide an integrated and stable signal in a 3-D device A manufacturing method of close 3-D stacking of stacked integrated circuits for processing, memory and data transmission.

Although the above description is in terms of silicon wafers, other substrates can also be used. For example, the substrate can be almost any single crystal, polycrystalline or even amorphous substrate. In addition, the substrate may be made of III/V materials such as gallium arsenide, gallium nitride (GaN) and others. According to an embodiment, the multilayer substrate can also be used. Multilayer substrates include a silicon-on-insulator substrate, various interlayers on a semiconductor substrate, and many other types of substrates. Generally, those who are familiar with this technology will easily recognize many alternatives, modifications and changes.

Generally, high-performance logic devices generate heat in areas of high switching activity in the logic core. These switching heating sources are complex system-on-chip (SoC) and central processing unit (CPU) Well-known design concerns in the device. The preservation of data in memory devices usually degrades with increasing temperature, so the integrated stacking of logic and memory layers is challenged by these hot concerns. As the density and variety of 3D device stacks increase, thermal control becomes more important.

Although beneficial for thermal bonding efficiency, the use of oxide layers in bonding stacks can be limited by the relatively low thermal conductivity of SiO2 as a thermal transfer layer. The use of higher thermal conductivity, electrically insulating materials as the interlayer structure can increase the heat transfer from the heat source area of the local device.

Therefore, in some embodiments, it may be necessary to add a structured high thermal conductivity layer between the heat generating device layers in order to facilitate heat dissipation and remove heat from the device stack. Specifically, the use of high-energy proton implantation, low thermal budget layer splitting and transfer combination can help heat dissipation from local device structure "hot spots" and efficiently remove device heat energy through the use of local coolant flow.

Proton splitting and layer transfer methods, and the patterned top layer (bonded to a flat device surface by using photoresist (or oxide, as discussed below) during the proton implantation step to form interlayers for stacking coolant flow A combination of patterned split regions formed by channels) and an interlayer structure with high thermal conductivity (and low conductivity) are used to provide a flexible design element for controlling the thermal environment in a complex 3D device stack.

The thermal conductivity of a variety of common semiconductor materials indicates a variety of materials having a thermal conductivity substantially higher than that of SiO2. Among them, SiC and Al2O3 (sapphire) include candidates for this purpose. Compared with the equivalent SiO2 layer, for this purpose, other high thermal conductivity materials can also be used, so as to press<img file="TWM588362U_D0004.tif" />10 to<img file="TWM588362U_D0005.tif" />The factor of 100 enhances heat spreading and transportation.

Table 1 below lists the thermal conductivity of some common semiconductor and insulator films (in W/mK): Si: 130 (W/mK)

SiO₂:1.3(W/mK)

SiC: 120(W/mK)

Ge: 58(W/mK)

GaAs: 52(W/mK)

Al₂O₃:30(W/mK)

For efficient heat flow, it can be expected<img file="TWM588362U_D0006.tif" />The thickness of the interlayer heat spreading layer is 0.5μM to 2μM.

Figure 16 shows a simplified cross-sectional view of one of the high-K layers incorporating a coolant channel in place.

Integrated circuit devices containing a variety of semiconductor, dielectric, and metal material layers can generate a large amount of internal stress during manufacturing. What is unresolved is that these stresses can be high enough to warp Si wafers of sufficient thickness (where the thickness is greater than 700 microns) into a variety of concave, convex, and complex shapes. These deformations can be large enough to cause problems in the fine line lithography optical device during device manufacturing.

If a stress-containing device layer on a disassembled thin (for example, several micrometers) substrate is placed on a flat surface in an unsupported manner, the stress-induced deformation of the wafer-scale combination can cause bonding to the flat substrate surface problem. Due to these effects, the thin device layer can be attached to the rigid bonding structure before it is detached from its initial substrate wafer, and the planar bonding interface with the attached stressed layer can be maintained.

FIG. 17A shows a simplified diagram of an example of a detached, unsupported device layer 1702 deforming the thin substrate layer into a concave shape on a thin substrate layer under net compressive stress after its manufacture. The actual device layer 1702 can deform into concave, convex, and complex "signature" shapes. Such deformations can cause difficulties in bonding to a flat surface, and due to excessive local stress during additional manufacturing steps and during subsequent thermal cycling during device operation, resulting in bonding failure and device degradation.

Even by using a rigid temporary bonding mount to form a stress-containing layer into a flat form suitable for bonding, uncompensated stress in the stack of complex bonding can result in The bonding failure of thermal stress during subsequent manufacturing steps and during device operation and degradation of the IC device.

Therefore, embodiments can provide for adding a stress compensation layer to the backside of a stressed device thin transfer layer to facilitate a bonding process, including improved interlayer device and bonding pad alignment, and compensation for subsequent manufacturing and device operation thermal cycles The adverse effects. U.S. Patent No. 7,772,088 is hereby incorporated by reference for all purposes.

The backside stress compensation material can be selected from materials that have complementary thermal expansion properties with the device layer and have a thickness sufficient to offset the distortion effect of the stress in the device structure.

Figure 17B is a simplified cross-sectional view showing the effect of adding a stress compensation layer to the back side of a thin substrate containing a stressed device layer 1702 on the top side. The role of the stress-compensating backside layer is: (1) facilitate bonding to a flat bonding surface, (2) improve the accuracy of bonding pad alignment during wafer-level bonding, and/or (3) offset in subsequent manufacturing steps The effect of differential thermal stress during and during device stacking operations.

The stress compensation layer can be formed by direct layer transfer to the back side of the transfer device layer 1702 when the transfer device layer is attached to the temporary bonding structure. In some cases, the stress compensation layer can be deposited by CVD or other methods.

Note that the flat stress-compensated transfer layer can provide a desirable geometry for achieving high bond pad alignment during wafer-level bonding, which is a consideration for successful wafer-level bonding for 3DIC manufacturing.

Embodiments can use single crystal layer transfer to a chemical or mechanical "weak" separation layer. In detail, it may be necessary to allow a layer of high-purity single crystal material to be attached to a temporary holding layer that is strong enough to survive the thermal, chemical, and mechanical stress of IC or other device manufacturing processes, but sufficient. "Weak" to form a separation path under the guided chemical or mechanical action.

Examples of these weak temporary separation layers can include (but are not limited to) (1) an oxide layer that can be formed by direct implantation and subsequent heat treatment by thermal growth, CVD deposition, which can be selected by The chemical action of the selective etchant (such as HF attack on the underlying SiO2 layer) forms a separation path under an overlying layer, and (2) various forms that are sensitive to the formation of a separation path under selected chemical or mechanical attacks The general substrate material in the form of polycrystalline or porous. The form of guided mechanical attack may include (but is not limited to) (1) the formation of stress-assisted cracks initiated by the lateral guiding force on the separating wedge tool, and (2) the formation of cracks in areas such as porous substrate materials. The laterally guided fluid jet in the mechanically weak layer conducts a dynamic attack.

Some forms of chemically or mechanically weak separation layers may lack the high-order crystalline interface required for epitaxial growth of high-purity and high-quality crystalline upper layers suitable for manufacturing high-performance semiconductor devices.

High-energy proton implantation is used to form a hydrogen-rich layer for mechanical, room temperature separation along a well-defined split surface. Embodiments can be used to separate all device structures (including fully formed transistor layers and multilayer metal interconnections) and Combine it with a suitably selected temporary separation layer for later manufacturing and device integration processing. This can be followed by subsequent separation from the carrier substrate.

The methods and equipment according to the embodiments can also be used to separate and combine uniform, high-purity and crystalline layers to form electrical, mechanical or optical devices, followed by subsequent separation from the carrier substrate.

Figure 18 is a simplified diagram of bonding a high purity, single crystal transfer layer to a chemical or mechanical "weak" separation layer on a substrate. The upper crystal transfer layer is formed to the desired thickness by using high-energy proton implantation and room temperature separation along the peak of the proton distribution. The upper transfer layer can be a uniform crystalline layer, or a combination of IC, mechanical or optical device and its corresponding metal interconnection network.

The embodiment can also provide proton implantation suitable for separation and layer transfer stacking of highly sensitive CMOS device structures. As previously mentioned, the embodiment uses high-energy proton implantation to form a hydrogen-rich split surface several microns below the combined thickness, and stops the photoresist or CVD dielectric top layer and a multilayer metal interconnection network and transistor layer. A combined power effect.

Radiation caused by high-dose, high-energy proton beams passing through metal interconnects and transistor layers The damage effect can be at a manageable level that can be recovered by a standard annealing cycle at an appropriate temperature. In addition, in cases where specific radiation damage effects are of specific concern, embodiments may include an implementation that bypasses the concern about radiation damage effects in the dielectric layer of the device.

One issue regarding possible radiation damage during high-dose, high-energy proton implantation into the CMOS device layer and its associated metal interconnection network layer is the bond-damaging effect in the various dielectric layers. This can be attributed to the electron self-stop event from the passing of the high-energy proton beam or from the UV radiation from ion-electron relaxation, followed by the recombination event in the accelerator beam line.

When high-dose, high-energy proton implantation is performed at a specific point during the CMOS device manufacturing process, the radiation effect from the proton beam can be substantially avoided. A point in the CMOS process can be identified as occurring after the completion of the high temperature (for example, greater than 500C) process associated with the activation of the dopants in the CMOS junction and after the deposition of the sensitive gate stack oxide and the interlayer intermediation Electricity occurs before subsequent mergers in the metal interconnection network.

At this point in the CMOS manufacturing process, the main materials in the device wafer are the doped junction of the lateral isolation region filled with polysilicon and the crystalline silicon in the substrate wafer. The only massive, long-term radiation damage effect in major silicon materials is associated with lattice damage caused by the nuclear stop component of the proton slowing process.

The lattice damage event of the high-energy proton beam can be limited to the vicinity of the peak of the proton profile. According to the embodiment, the peak can be placed several micrometers below the CMOS junction in the transistor layer, and provide critical hydrogen trap sites for localization of the split surface during layer separation. Several micron separations between the CMOS transistor layer and its associated carrier depletion layer and the proton-induced lattice damage in the area of subsequent layer separation can be sufficient to avoid the risk of adverse device effects from the proton lattice damage layer.

In many advanced CMOS devices, the gate stack area consists of a temporary film at the beginning and a high dielectric constant ("high-k") gate oxide and multilayer The structure definition of the "replacement" of the final device structure of the metal gate electrode. After the "replacement gate" manufacturing cycle, the material properties of the final gate and intermetallic ("low-k") dielectric limit the allowable thermal cycle used in the final CMOS device manufacturing process to less than 500C.

The high-dose proton implantation performed at the point immediately before the "replacement gate" manufacturing will avoid the risk of damage to the gate of the final device and the intermetallic dielectric, and will not be exposed to 500C or high 500C thermal cycles. This can lead to spontaneous layer separation before the non-thermal separation procedure required for layer separation after the fabrication of the transfer device layer is completed.

Figure 19A shows a simplified cross-sectional view of a high-energy, high-dose proton implantation to form a hydrogen-rich layer placed several microns below the CMOS transistor layer. This is performed after the completion of the &gt;500C annealing associated with the activation of the dopants in the transistor junction and before the fabrication of the "replacement gate" including the gate dielectric of the final device and the metal gate electrode.

Figure 19B is a simplified cross-sectional view of the CMOS device layer after the formation of the final gate stack and metal interconnection structure.enterformed. The final gate and intermetal dielectric material properties limit the manufacturing process temperature to less than 500C, which also avoids spontaneous hydrogen-rich regions along the hydrogen-rich region before the desired separation after the complete device structure is completed by non-thermal methods. The status of the segmentation.

The use of the method and device according to the embodiment may permit the modulation of the inter-layer bandwidth according to the stacking order and inter-layer thickness. Specifically, the main goal of 3DIC stacking is to provide an alternative path for increasing the bandwidth for signal processing communication between devices.

The bandwidth is the product of the data signal frequency (usually estimated by the CPU clock frequency) and the number of external communication channels. For most of its history, IC development has focused on increasing the cycle frequency of CPUs and other data processing chips, possibly at the expense of increased chip power usage. The number of communication channels has been limited by the density of bond pads available along the periphery of the flat device.

The development of 3DIC stacking methods has increased the vertical measurement by density interlayer communication lines. The possible number of straight passages. This density of inter-layer communication channels increases as the density of vertical connection channels increases. A convenient measurement of the density of interlayer connections is the inverse square of the communication pin separation or "spacing". Specifically, IO density=1/(pin pitch)2.

The minimum metal channel or "pin" pitch depends on a variety of process and device considerations. One factor is the aspect ratio (AR) of the interlayer metal channel: the ratio of the diameter of the metal wire to the length of the via to be filled. The conventional "via silicon via" (TSV) structure can usually exhibit an AR between about 5 and 20. This is significantly higher than the typical design rule for vias in high-density metallization of IC devices that often have AR less than 2.

One device consideration factor that affects the packing density of the conventional TSV structure is the inter-device stress caused by the different thermal expansion of the micron-sized Cu cylinder and Si device materials. Poor local stresses in the near-edge environment of the Cu vias can lead to design rules defining micron-scale "forbidden" zones, in which active circuit components are excluded from the vicinity of the Cu via landing pads. This affects circuit density, performance and yield.

Therefore, the method and device of the specific embodiment can provide one or more procedures for locally increasing the metal channel density between layers and the corresponding communication bandwidth between adjacent device layers. A high-energy, high-dose proton implantation through a substantially completed metal interconnection network and a fully formed CMOS transistor layer is used to form a hydrogen-rich region for non-thermal layer separation and bonding to a 3DIC stack to provide a few microns (Or smaller for device layers on SOI buried oxide or other device types with the smallest carrier depletion layer thickness). This allows for layer separations that are substantially smaller than tens of microns typical of today's TSV and insert stacking methods. The thinner inter-device Si layer and the elimination of the interposer and the associated adhesion layer provided by the embodiments allow the fabrication of shorter and thinner inter-device metal signal connections, and greatly reduce the thermal stress from today's several micron thick CuTSV channels The "zero value zone" effect caused by it.

In the need for high-level bandwidth (for example, from the CMOS image sensor layer and signal In the case of processing device connection), some embodiments can use multiple layer transfer techniques to align and bond the top layer of the metal interconnection network of the transfer device to the interlayer connection channel in the top layer of the metal network of the lower device layer in the 3DIC stack . This layer transfer method is summarized in Figures 12-15.

With this specific procedure, it can be expected that the interlayer communication channel density is similar to the pin density in the top metallization layer of the two device layers, with a pin pitch of about a few microns or less. This "top-to-top" layer combination results in an interlayer connection density that is 100 to 1,000 times higher than the existing 2.5D and 3D chip stacking technologies, and a corresponding increase in bandwidth.

Figure 20 shows a simplified cross-sectional view of the "top-to-top" metal layer combination of a transfer device layer and a lower device layer in a 3DIC stack. Similar to the channel density of the top metal layer of CMOS devices, this method can provide inter-level metal connection channel density and correspondingly increased bandwidth.

The specific example of the 3DIC structure according to the embodiment can be characterized in that the lead pitch range (in nm) is between 1.E+02 and 1.E+04 between about 1.0E+06 and 1.0E+08 IO density (in terms of number of pins/cm²). In one example, for a TSV depth of 1 μm, the aspect ratio (depth: the smallest width of the diameter) may range from 10 to 1 on a series of TSV diameters from about 0.1 μm to 1 μm.

As mentioned above, proton implantation to form a 3DIC structure according to one of the embodiments can occur at an energy of about 1 MeV, including about 300 keV to 5 MeV, about 500 keV to 3 MeV, about 700 keV to 2 MeV, or Energy between about 800 keV and 1 MeV. For all purposes, US Patent Publication No. 2008/0206962 is incorporated herein by reference.

It should be noted that the implantation properties of hydrogen ions in these higher energy ranges can vary between the typical 40 keV energies of the layer transfer process used in SOI wafer fabrication. The first-level description reflects the ratio of the "half width" (&lt;ΔX&gt;) of the proton profile of "divergence" to the depth (&lt;X&gt;) of the "projection range" profile.

The comparison of these &lt;ΔX&gt;/&lt;X&gt; results in an example is as follows:

Proton implantation energy 40 keV: &lt;ΔX&gt;/&lt;X&gt;=0.196<img file="TWM588362U_D0007.tif" />0.2

Proton implantation energy 1 MeV: &lt;ΔX&gt;/&lt;X&gt;=0.048<img file="TWM588362U_D0008.tif" />0.05

Therefore, the 1 MeV proton profile is one of the 40 keV profile<img file="TWM588362U_D0009.tif" />4x "Quick".

3DIC structures are usually stacked at the wafer level. Wafer-level processing, especially when combined with the directness of the transfer method for fully metallized CMOS devices described herein, has a number of advantages for economical and efficient processing.

Wafer-level processing of bonded structures usually assumes the use of wafers of the same size, and the placement of dies on the bonded wafers is closely coordinated to result in a vertically stacked 3DIC structure after separation into discrete systems. For large-area logic and memory devices manufactured on 200mm or 300mm Si wafers in mass production casting processes, these conditions are usually met.

Many desirable components for communication links (such as RF tuners, amplifiers, and the like) are considerably smaller in die size than cm2 logic and memory devices. These smaller die size devices can be manufactured on a variety of wafer sizes such as 100mm and 150mm, and can use non-bulk silicon substrates such as radio frequency silicon-on-insulator (RF-SOI), GaAs, etc.

There are many difficulties associated with stacked structures with a wide variety of grain sizes. Device alignment is important and can be complicated by the thickness differences inherent in the backgrinding process used to thin the die. The total thickness variation (TTV) used in the back grinding process is usually in the range of about 5%. When multiple layers are stacked, this change can be complicated, making it difficult to perform a semiconductor formation process to facilitate interlayer connections. As a result, stacked devices use relatively large solder bumps and interposer layers to connect devices in a vertical stack. In addition, many devices use bond wires to connect multiple layers arranged side by side in a package.

Embodiments of the present disclosure include devices and processes for 3DIC structures including heterogeneous crystal grain sizes. By performing isolation through a circuit structure including dielectric and conductive materials The sub-implantation simplifies the thinning process of the die formed by splitting the base substrate, and has fewer changes than the back grinding process. The TTV value that can be obtained by ion splitting can be, for example, less than 2%, less than 1.5%, and less than 1.0%. In addition, backgrinding applies a large amount of mechanical stress to the semiconductor device, which can damage the structure in the device, causing further alignment and performance problems.

FIG. 21 shows an embodiment of a process 2100 for forming a 3DIC structure with different grain sizes. One of the advantages of the process 2100 is the economic advantages of combining wafer-level processing and the flexibility to incorporate smaller-area die layers that can be fabricated on a variety of substrate materials and wafer sizes into a composite 3DIC structure.

At 2102, a base device structure is prepared. FIG. 22 illustrates an embodiment of using high-energy hydrogen implantation to prepare a base device structure 2202, in which the peak concentration of high-dose hydrogen implantation is located in the substrate area below a metallization layer that can be, for example, a CMOS or MEMS device layer middle.

After splitting along the approximate location of the hydrogen concentration peak, the residual damage along the splitting plane is removed and transferred to the device layer bonded to another wafer-scale device layer as shown in FIG. 23. In the embodiment shown in FIG. 23, the base device structure 2202 includes two wafer-level bonded semiconductor layers 2202A and 2202B by implanting ions through the dielectric and conductive structures formed on the semiconductor wafer. form. In some embodiments, the base device structure 2202 can be more than two stacked semiconductor layers or a single stacked semiconductor layer.

Figure 23 illustrates wafer-level bonding in a device orientation, where bonding occurs along the metallization layer of two layers, where the upper (second) device layer is compared to the lower (first) device layer 2202A facing upwards 2202B faces downwards. Although only a single device of each of the first and second device layers is illustrated in FIG. 23, in one embodiment, the splitting and joining operations are performed on a plurality of devices on the wafer.

Before the two device layers 2202A and 2202B are combined together, there is an opportunity for the deposition and patterning of one or more intermediate layers 2204 insulated by an intermetallic dielectric material, which can provide Vertical (device-to-device) and lateral connections for signal, timing, insert and ground connections. The inter-device metal connection layer 2204 is similar in function to the redistribution layer (RDL) in modern 2.5D multi-chip packaging schemes.

After bonding the first device layer 2202A to the second device layer 2202B, including the intermediate connection layer 2204, the vertical vias 2206 are etched and filled with metal to provide connections between the device layer and the top surface array of the bonding signal pads.

In the process 2104, the interconnection layer 2208 is formed on the exposed upper surface of the base device structure 2202. The interconnection layer 2208 may include appropriate bonding pads on the top layer of the base device structure 2202 for direct pick-and-place addition of various smaller die components, and to the side of the interface between the contact pads exposed by the base device structure 2202 Wiring connection.

In one embodiment, the top metal layer of the interconnect layer 2208 includes a multi-layer metal network for lateral communication, power, and ground connections for a composite device, where the addition is designed for placement and bonding. The bonding pad array of the downward facing metal connectors of a variety of die types.

As illustrated in FIG. 24, in the process 2106, one or more dies 2210 are placed on the interconnect layer 2208. Known pick and place techniques can be used to place one or more smaller dies 2210 to align the terminals of the one or more smaller dies 2210 with the bond pads exposed on the upper surface of the interconnect layer 2208. The position and metal-to-metal bonding of discrete die types on the composite wafer-level bonding structure 2202 can be realized by an automated die picking, placing, and bonding equipment.

In some embodiments, the smaller dies 2210 have mutually different sizes and thicknesses. The smaller die 2210 may be a heterogeneous collection of devices or a homogeneous collection of devices that perform different functions.

Since the die 2210 can have various thicknesses, and in some embodiments can be thicker than the desired substrate thickness (for example, in the range of 1 μM to 10 μM), so at 2108, A layer of deposited material having an etching rate similar to that of the substrate grains of the added smaller device under the CMP process can be formed between and on the die 2210.

For example, as seen in FIG. 25, in process 2108, the dielectric material 2212 may be deposited on the exposed surface of the device structure including the die 2210. The dielectric material 2212 provides electrical isolation of the smaller die 2210. The dielectric material 2212 may be one or more of a variety of materials commonly used in the semiconductor industry that provide insulation from stray currents, including CVD oxide or other suitable insulating materials.

In some embodiments, at 2110, the filler material 2214 is deposited on the dielectric material 2212. When the die 2210 is a Si device, the deposited layer may be poly-Si or amorphous Si deposited by plasma. The filler material 2214 may be selected to have an etching rate similar to that of the dielectric material 2212 and the substrate material of the smaller die device 2210 when the structure is planarized at 2112 (for example, by performing CMP).

Although the process 2100 and associated figures describe the formation of separate dielectric material 2212 and filler material 2214, in some embodiments, only a single material or more than two materials are deposited on the die 2210.

At 2112, a planarization process is performed to planarize the upper surface of the device until the contact pads are exposed. The chemistry of the slurry used in the CMP process can be selected based on the dielectric material 2212 and the filler material 2214 to achieve approximately the same corrosion rate of the substrate in the added smaller grain structure 2210 and the layer material deposited on it. In one embodiment, the planarization process 2112 thins the added smaller die 2210 substrate to a thickness of about 10 μm or less than 10 μm for forming vertical metal vias for later addition of structures and bonding pads The interconnection. In an embodiment, the planarization 2112 is performed until a total layer thickness of 10 μm to 30 μm is obtained.

In addition, the planarization process 2112 provides a flat top surface for the newly expanded composite device structure for subsequent addition of multilayer metal interconnects for lateral signal, power, and ground connections. Links and bonding pads, which are designed for connection of additional layers added to the composite structure by wafer-level or discrete die placement methods. In one embodiment, the planarization process 2112 may be performed on the top surface until the surface roughness has an RA value of 5 angstroms or less than 5 angstroms or 3 angstroms or less than 3 angstroms.

The deposition and planarization elements of the program 2100 can be executed to thin the substrate of the smaller die 2110 to a desired thickness. In addition, the dielectric material 2208 and the filler material 2210 provide mechanical support, and in some embodiments, one or more of the layers formed on the die 2110 facilitate heat transfer away from the final 3DIC structure.

In some embodiments, no additional layer is placed on the smaller die 2210. In these embodiments, the device can be packaged after planarization 2112 without placing the upper device structure on the smaller die 2210.

As illustrated in FIG. 26, the interconnect structure 2216 is formed in the process to electrically couple at least one of the one or more smaller die 2210 to the upper device layer 2218 of the 3DIC. The interconnect structure 2216 may be formed on the exposed surface of the smaller die 2210 and/or on the exposed surface of the upper device structure 2218 before it is placed on the smaller die. In various embodiments, the upper device structure 2218 may be a single substrate, two wafer-level bonded substrates, or more than two substrates as illustrated in FIG. 23.

An embodiment of the process 2100 provides for adding layers of discrete dies to a wafer-level process flow for the integration of a multi-layer device structure to a composite 3DIC structure. The device fabricated according to the procedure 2100 can have lateral electrical isolation of a variety of added dies in a multi-chip layer, and can be included in a dense high-bandwidth network for composite device structures containing wafer-level and discrete die placement Vertical metal connection in road and lateral metal connection network. When providing smaller dies with different thicknesses, the process 2100 can adapt to these structures by flattening and thinning a variety of substrates in the composite device layer.

In the process of 3DIC manufacturing using metallized transistors and wafer-level transfer of MEMS device layers, it is advantageous to locally adjust the depth of hydrogen implantation, which determines the approximate split plane used for layer transfer in the steps of the process Local location.

The main challenge in the operation of dense, high-performance circuit elements with 3DIC stacked arrays (such as microprocessor logic and graphics processors and display drivers for image analysis) is the removal of heat from the active device core.

As described above, by adjusting the local penetration depth of the hydrogen implantation profile (by adding a patterned "range adjustment" layer composed of a material formed with a sufficient thickness) to cause the hydrogen depth and the localization of the subsequent split surface Offset, the network of channels used for the flow of the coolant fluid can be formed in the closest proximity to the heat generating transistor layer. After the splitting of the device transfer layer along the variable depth split surface, by bonding the transfer device layer to a flat surface (such as the flattened top layer of another device layer, as shown in FIG. 1), the channel The network can be formed in the bottom surface.

The range compensation layer may include a patterned layer of CVD silicon oxide of appropriate thickness combined with an unpatterned silicon nitride layer, which serves as an etch stop layer for the implantation step Then, the patterned oxide layer is removed. In another embodiment, the range compensation layer is a patterned layer of a thick photoresist.

FIG. 27 shows an embodiment of a device that includes dies 2710 of various sizes disposed between the lower portions that have features not present in the device of FIG. 26. FIG. A variety of dies 2710 are formed on a base device structure 2702, which includes the ability to form a split layer at the wafer level by implanting ions through metal and dielectric structures and to combine upper and lower parts to form a lower device Structure 2702 to form the upper and lower parts. In addition, the device of FIG. 27 shows a plurality of cooling channels 2720 disposed at the interface between the upper and lower portions of the base device structure 2702 and the lower surface of the substrate of the upper device structure 2718.

Another feature of the device shown in FIG. 27, which is different from the device of FIG. 26, is the vertical The location of the direct interconnection structure. Although the embodiment of FIG. 26 has vertical through holes 2206 penetrating through the upper device structure 2218 and the filler material 2214, FIG. 27 shows the device passing through the small grain structure 2710 to provide the lower structure 2702, and the difference between the small grain 2710 and the upper structure 2718 There is a vertical through hole 2722 in electrical communication between. Those familiar with the art will recognize that many variations beyond the specific features shown in FIGS. 26 and 27 are possible.

The procedure according to the present disclosure can be applied to a transfer device containing a large change in the density of the total metal layer in a local area of the transferred device. When hydrogen ions are implanted through the metal and dielectric structure of the semiconductor device, the depth of the split plane can be affected by the conductivity in the circuit layer and the configuration of the dielectric structure. For example, as seen in FIG. 28, the depth of the peak energy that appears as a split plane may be smaller in the high-density region of the device than in the low-density or sparse region. In some cases, for the purpose of the simplicity of the procedure in the layer transfer bonding, it may be necessary to have the implanted hydrogen profile depth at the same flat position under the circuit layer.

The depth of the hydrogen splitting plane can be varied in different sections of high-performance microprocessors, where a dense multi-layer metallization layer on the logic core consists of memory (for example, embedded SRAM) and timing and input/output circuits. Surrounded by a sparse metal interconnection network. Other examples include optical sensor (cellular phone camera, etc.) devices in which a denser metalized image processing circuit is surrounded by a more sparsely metalized photo sensor array. In addition, MEMS devices often contain multiple layers and open spaces of various material densities. These changes can be converted into different stopping powers of hydrogen ions, which can change the depth of the splitting plane. In an embodiment that includes a transfer device containing a MEMS device.

As seen in FIG. 29, the local hydrogen profile shift can be compensated by the patterned range compensation layer 2902 of appropriate thickness and the hydrogen stop power to result in a substantially flat hydrogen peak profile depth and split plane. Therefore, embodiments of the present disclosure may include forming a range compensation layer 2902 on a top surface of a semiconductor device to compensate for changes in the density and/or type of materials that exist between the top surface of the semiconductor device and the split plane. The change in the penetration depth of the ions.

In some embodiments, such as the example illustrated in FIG. 29, the compensation layer 2902 has a uniform thickness and is selectively deposited on regions of the device that will otherwise have a higher ion penetration depth than the regions without the compensation layer. In other embodiments, the compensation layer 2902 has variations in thickness to account for multiple variations in ion penetration depth. For example, ion implantation can be performed on a device lacking a compensation layer to measure the depth change in the split plane and form a mirror image of its thickness with the depth change (for example, a larger depth ion penetration region will Related to the thicker section of the compensation layer, and vice versa) one of the compensation layers to produce the shape of the compensation layer 2902.

In the change in the depth of the hydrogen profile, the stop power change at close intervals on the lateral scale (approximately 1 or more micrometers) roughly equal to the lateral divergence of the high-energy hydrogen ions is usually not replicated. Therefore, the thickness of the range compensation layer 2902 can vary between one functional area and another functional area of the circuit, as opposed to the variation based on individual nanoscale structures in one area.

In one embodiment, by forming cooling channels along the split surface defined by the high-concentration hydrogen profile, the heat generated by the circuit switching and resistive power loss in a volumetric 3D composite multi-device layer system is effectively provided Remove. The cleavage surface depth is defined by the thickness, the stop power, and the location of the patterned layer added to the device surface before hydrogen implantation.

As illustrated in FIG. 2A, the embodiment of the present disclosure includes a cooling channel. In the example of FIG. 2A, the cooling channel is created by modulating the depth distribution of the implanted hydrogen with a patterned CVD oxide overlying layer when hydrogen is implanted to form a split layer. An associated CVD nitride layer is used to provide etch stop for patterning of the CVD oxide layer. Both the CVD nitride and oxide layers are removed in later processing.

2 illustrates an embodiment of the cooling channel formed along the split surface by offsetting the proton depth with a patterned stop photoresist (PR) layer. In other embodiments, the stop layer may be a similar dense material deposited on the surface of the device wafer. The thickness and stop power of the underlying unpatterned PR layer can be used to modulate the split surface characteristics in the substrate material under the transferred device layer The depth. Figure 2 shows the formation of the completed cooling fluid channel by bonding the modulated split surface to the flat top surface of the underlying device or substrate layer.

In one embodiment, the cooling channel is enhanced by applying a surface coating. A surface coating material can be selected to improve the heat transfer from the active device layer to the cooling fluid in the cooling channel, and/or to reduce or eliminate the chemical reaction between the heat transfer fluid in the cooling channel and the substrate material. For example, in some embodiments, a cooling channel is disposed in a layer with high thermal conductivity, and the high thermal conductivity material reacts with a heat transfer fluid flowing through the coolant channel. In this embodiment, the exposed surface of the coolant channel may be coated with an inert material such as an oxide or nitride material, which prevents a chemical reaction between the heat transfer fluid and the material of the high thermal conductivity layer. For example, the inert material can be SiO2 or Si3N4.

Those familiar with the art will recognize that the characteristics of the coating material including the material type, thickness, and deposition technique can be selected based on the specific thermal conductivity layer material and heat transfer fluid used in an embodiment. In some embodiments, the coating material assists heat transfer and has a higher thermal conductivity than the substrate material on which the coating is formed. Other favorable characteristics of the coating on the coolant channel include excellent adhesion to the coolant channel wall material, good thermal conductivity for the coolant material and free-flowing uniform conformal coating thickness, and resistance to the device operating temperature The coolant fluid underneath is inert.

In one embodiment, the fluid in the coolant channel may be a heat transfer fluid with relatively high thermal conductivity. In some embodiments, the fluid is an inert substance such as water or a highly diluted solution. In other embodiments, the heat transfer fluid may be a nanofluid containing nanoparticles that enhance the thermal conductivity of the fluid compared to the liquid phase component. The heat transfer fluid can be circulated through an external heat exchanger to transfer heat away from the device.

The location of the cooling channel can be selected to be at a transfer device bonding layer as seen in Figure 2, or for the case where direct bonding of the device metal layer is required for high-bandwidth circuit connection, in an alternate position, such as in Seen in Figure 20. In Figure 20, the cooling channel is located Near a flat bonding surface of a subsequently added device layer.

In some embodiments, one or more thermal transfer layers can be included in a 3DIC device. The heat transfer layer may be a material with superior heat transfer characteristics than the material used in an active layer. The heat transfer layer may be positioned adjacent to the cooling channel so that the heat transfer fluid traveling through the cooling channel transfers heat from the device circuit system to the heat transfer layer. In other embodiments, the cooling channel is directly formed in the high thermal conductivity heat transfer layer.

The multilayer lamination of the device allows the insertion of layers of high thermal conductivity materials and interfaces to improve the lateral spread of heat from the local active circuit area and the vertical heat transfer to the network of fluid flowing in the cooling channel. The deployment to control the local depth of the split surface in the material also allows cooling channels to be formed in the subsequently laminated high thermal conductivity layer in a similar manner to the transferred device layer. For example, FIG. 16 illustrates a high thermal conductivity heat spreading layer having a coolant flow channel bonded between two circuit layers by a CVD oxide bonding layer.

As indicated in Table 1 above, the room temperature thermal conductivity of silicon (the main substrate material used in current IC manufacturing) has a relatively high thermal conductivity that is closely matched only by silicon carbide (SiC). In one embodiment, it is necessary to use a material with higher thermal conductivity than Si as the high thermal conductivity layer.

The consideration for materials used for high thermal conductivity heat transfer materials is the thermal conductivity properties of the material under the temperature characteristics of the circuit operation in action (which are generally 80C to 120C). For Si at room temperature (25C, 300K) and above room temperature, the thermal conductivity decreases strongly with increasing temperature, leading to the risk of "thermal runaway" in the local area heated by the active circuit power. As seen in FIGS. 30 and 31, due to phonon dopant scattering, for increasing dopant concentration, the thermal conductivity of Si decreases at all temperatures. For commonly used Si substrates, the dopant content is relatively low (<img file="TWM588362U_D0010.tif" />1015 dopants/cm ^ 3), resulting in a relatively high thermal conductivity compared to the higher concentration illustrated in Figure 30 and Figure 31.

Figure 32 illustrates the various temperatures and blends as reported by Morelli et al. (1993) Thermal conductivity of 6H-SiC at impurity concentration. In Figure 32, sample 1 is a very pure or highly compensated sample, and the remaining samples have the following electron concentrations: sample 2-n=3.5×1016cm-3; sample 3-n=2.5×1016cm-3; sample 4- n=8.0×1017cm-3; sample 5-n=2.0×1017cm-3; and sample 6-n=3.0×1018cm-3. The thermal conductivity of various forms of silicon carbide has been reported to be higher than that of silicon. Among them, the conductivity of 3C, 4H and 6H polytypes is twice as high as that of silicon at 300K.

As illustrated in Figure 33, some carbon-based materials have a much higher thermal conductivity than silicon. In detail, diamond, graphite, graphene, and carbon nanotubes all have a thermal conductivity value that is substantially higher than that of silicon (especially at higher temperatures). Although Figure 30 and Figure 31 show the dramatic decrease in the thermal conductivity of silicon above room temperature, the decrease in thermal conductivity of carbon-based materials is relatively shallow, and in the case of amorphous carbon, the thermal conductivity is lower than Increased above room temperature. In detail, the thermal conductivity value reported for diamond and graphene is one order of magnitude larger than the thermal conductivity of silicon at 300K. Another material with a high thermal conductivity comparable to the diamond form is cubic boron arsenide. In the embodiments of the present disclosure, one of these materials can be used as a bulk substrate material.

In the present disclosure, the term "plane" is used to describe a split plane, which is generally understood as a location where a split layer is separated from the substrate. However, as explained above, before ion implantation, a range compensation layer can be applied to a substrate, which can result in an original split surface that can define, for example, one or more contours of a cooling channel. Therefore, the use of the term "split plane" in the present disclosure should not be interpreted as limiting the embodiments of the present disclosure to perfectly flat split surfaces.

In one embodiment, the chemically or mechanically weakly split surface is formed by ion implantation before the interface of any sensitive or reliability-focused device layer or structure is formed. This embodiment can be used in the formation of a complete device structure (including a complete network of metal interconnects and intermetal dielectric), followed by a splitting action initiated at the pre-formed split surface for transfer to a 3DIC stacked structure.

This embodiment will reduce the concern about device yield and reliability issues related to the formation of the buried split surface. In the case of hydrogen-based split surface formation, this embodiment allows a substantially lower proton ion energy to be used for the implantation step for a desired split surface depth.

The benefits of this embodiment include that mechanical, thermal and chemical conditions for the manufacturing and testing procedures of the post-split plane forming device should be performed to avoid premature initiation of the splitting action. In one embodiment using hydrogen-driven splitting, this involves limiting the post-split surface formation process to below<img file="TWM588362U_D0011.tif" />The temperature of 500C.

Many advanced devices (for example, devices containing high dielectric constant or high-K gate oxides such as HfO2 and related forms) have thermal budget constraints in this general area.

Figure 34 illustrates a bonding step for a transfer layer. In one embodiment, the transfer layer is a high-purity crystal transfer layer that is bonded to a substrate layer containing a chemistry of a mechanically weak separation layer, which can then be split after initial appropriate split surface formation conditions.

Figures 35 and 36 illustrate an embodiment of forming a buried hydrogen profile having a peak concentration suitable for forming a split surface at a depth lower than a partially completed device layer before forming a sensitive device layer, interface, or structure . Figure 36 illustrates a fully completed device structure including fully constructed metal interconnects and intermetal dielectric layers before introducing process conditions for initiating a split surface at the buried hydrogen-rich split surface.

A process of forming a chemically or mechanically weak layer in a partially completed device substrate before forming a sensitive device layer, interface or structure can be performed. The thermal, mechanical, and chemical processing of subsequent device manufacturing may be limited by the conditions that do not initiate the splitting action at the location of the splitting surface. The sensitive structure may include gate dielectric and intermetal dielectric layer. One example of a subsequent process limitation for the case of split surfaces formed by hydrogen implantation includes processing at temperatures at or below 500°C. In one embodiment, after the initial splitting at the splitting surface, the completed fully metalized device structure is transferred to a 3DIC stack.

The control of implantation conditions during proton implantation is important for the successful layer transfer of electronic devices. One aspect of this control is radiation damage associated with protons passing through the electronic device material and into the underlying substrate.

As high-energy ions enter the solid target, they transfer their kinetic energy in the slowing down process through collisions with the target material. The details of this stopping process are important, because the energy transfer from the protons passing through produces several forms of material cracking or damage, which play a specific role in the layer transfer process and in the performance of the transferred electronic device.

Despite the possibility of collisions and other complex interactions, the stop of ions is controlled by two main types of collisions: (1) The collision between the high-energy implanted atom and the core electron and the nucleus of the target atom is called nuclear stop. And (2) The collision between the high-energy atom and the loosely bound electrons in the outer shell of the target atom is called electron stop.

The effects of these two forms of ion-target atom collisions depend on the type of material in the target. In the embodiments of the present disclosure, the types of target materials include electronic devices and surrounding structures. The nucleus ceases to collide and causes a large transfer of kinetic energy to the target atom, often driving the target atom out of its original lattice site and establishing interstitial target atoms and empty lattice sites. These gaps and voids can be combined with similar defects to form a stable structure, which can collectively be referred to as implant damage.

In a layer transfer procedure using proton implantation, there is an effect of residual implant damage. During and shortly after the implantation is performed, the accumulated recoil damage from the nucleus stop of the protons in the target results in the formation of a stable damage structure that provides effective sinking sites for the implanted protons. The protons trapped in the implanted damage layer near the end of the ion rail hold the hydrogen in place instead of rapidly diffusing away, and allow the formation of hydrogen-filled small plates, which are used to form the transfer-allowing device layer The seed crystal of the split surface separated from the substrate.

The self-stop of electrons in electronic materials causes local scattering of electrons, which is often referred to as "ionization". In conductive materials such as Cu wires and doped Si materials, the local Scattering can be quickly repaired by the local movement of electrons in these materials. However, in the low dielectric constant (low-k) layer used to insulate the Cu and Co metal interconnection layers, the high dielectric constant (high-k) which is commonly used as the gate dielectric between the CMOS gate and the channel region ) In the insulating material of oxide and oxide or nitride spacers formed along the sidewall of the gate electrode, it is not easy to neutralize the local electron scattering, which leads to the isolated charged area related to the broken atomic bonding in the dielectric material And well sites. This application discloses the procedure to repair this damage.

The key aspects of the proton range and damage effect are explained by Monte Carlo modeling, for example, by the modeling of the stop and range of ions in a substance (SRIM) software. An example of SRIM modeling of proton range and damage effect is illustrated in FIG. 37.

Figure 37 is a graphical illustration of a model calculation of a 1 MeV proton in a 3μm thick multilayer containing Cu metal and SiO2 dielectric layer implanted on a Si substrate, where a CMOS device layer is located in the metal/oxide Multiple layers immediately below. The proton track shows that 1 MeV protons extend more than 10 μm deep below the top metal layer. In addition, FIG. 37 shows that the ions emitted from a single point on the surface of the wafer are laterally scattered on several micrometers near the deepest part of the cross-section, which is called lateral divergence. The insertion of protons at a point on the surface of the metal/oxide multilayer results in a dispersion of the implanted protons approximately 15 μm below the surface and several μm in the lateral direction.

FIG. 38A illustrates the 1 MeV proton and target atom recoil profile for high-dose proton implanted through the 3μm thick metal and oxide multilayer structure, CMOS transistor region, and silicon substrate illustrated in FIG. 37, and FIG. 38B illustrates the corresponding Ionization profile. In FIG. 38A, the depth profile of the implanted protons has a peak concentration of about 14 μm below the top surface, which is about 11 μm below the CMOS transistor and the depletion layer.

The proton and Si recoil distributions are all clearly peaked near the deep part of the implantation profile. The Si recoil concentration at the CMOS device layer (which is about 3 μm deep) is more than ten times lower than the peak recoil concentration at the approximate depth of the 14 μm layer split surface. At a depth of 14μm The high level of Si recoil at the high temperature produces a dense network of accumulated damage structures that trap the implanted hydrogen in the proper position under proper process conditions.

Another effect of protons passing through the model device layer is the deposited energy from the scattering of high-energy protons by loosely bound target electrons. The deposited energy, which is commonly referred to as the ionization energy expressed in eV/Angstrom, has strong peaks in the Cu metal and deep Si layers, as seen in FIG. 38B. These effects are quickly neutralized by the movement of nearby electrons in these two conductive materials. Although the deposited energy from electron scattering in the oxide layer is relatively small at about 4 eV/angstrom in this example, any scattered collision establishment of electrons that causes displacement is not easily damaged by electron movement in the insulating dielectric layer. Combine.

Although this damage may not have a strong effect on highly conductive materials, it may have a large adverse effect on other structures such as dielectric structures. In certain relatively large-scale structures such as thin film transistors (TFTs) and some MOSFETs where reduced switching times and leakage current are less important, the adverse effects may be less significant. However, the creators of the present disclosure have discovered that in the range where many high-performance devices are rendered inoperable due to ion implantation, damage caused by ion implantation through sensitive structures can affect smaller-scale and high-performance devices (such as , Modern processors and memory devices) have profound effects.

One way to reduce the damage effect of ion implantation is to select an appropriate implant energy. In one embodiment, the proton energy can be set high enough so that the peak of the proton and recoil damage distribution is higher than the position of the transistor layer of the electronic device and the thickness of the depletion layer formed when the device is at the operating potential (for example, It is 1 μm deep in 10 Ohm-cm Si which is commonly used resistivity. Any overlap between the proton damage layer and the depleted region of the device can lead to strong leakage currents, carrier recombination, and other adverse effects on device performance.

Since the split surface can then be bonded to another surface to form a 3D stack structure, the proton depth and associated depletion width under the transistor layer should allow the majority to be removed Or all split surface damage areas to form a bonding surface with sufficient flatness and smoothness for high-strength atom bonding.

In an embodiment, the implantation conditions are set to be favorable for forming a dense and stable accumulation of damage areas at the location of the desired split surface, where most of the protons of the collapse peak are distributed. In detail, the embodiment can use high proton ion density beam, slow beam and wafer scanning speed, and maintain the target temperature during implantation below the in-situ annealing for recoil damage. For Si, this temperature It is approximately 100C, and lower for other materials of interest such as III-V compounds. Implantation machines suitable for the embodiments of this application include trimmed ion implanters manufactured before about 2002.

The heat treatment (such as the deposition of the CVD layer, the heat treatment of the intermediate bonding layer, etc.) after implantation and before splitting along the hydrogen-rich layer can be performed to maintain the integrity of the hydrogen trapping damage layer. The study of hydrogen release from the implanted Si after thermal annealing and the inspection of the proton damage structure show that the maximum allowable temperature for maintaining the proton collapse is approximately 400C. Therefore, the embodiments of the present application may include limiting all thermal processes performed after hydrogen implantation and before splitting to a temperature that does not exceed the maximum temperature that may be, for example, one of 500C, 450C, or 400C.

The creator of this disclosure has discovered that damage caused by hydrogen implantation can be repaired under specific conditions, including auto-stop and recoil damage. Without repair operations, the device may have damaged performance or be completely inoperable. Recovery of damages associated with the automatic stop of electrons in the various layers of electronic devices is important to the success of 3DIC device stacking using proton implantation process technology.

In one embodiment, in an environment including hydrogen gas, a thermal process of repairing the damage of the dielectric and conductive structures is performed at a temperature of 350°C or greater. The conditions in a repair procedure should be sufficient to allow hydrogen to penetrate the surface of the device and bind to molecules damaged by an implantation process. In a specific embodiment, the repair annealing is performed at a temperature of 400°C in an atmosphere including from 2% to 5% hydrogen (the rest is one or more inert gases).

In one embodiment, the repair annealing is performed sufficiently to allow hydrogen to diffuse despite the installation It is placed in the circuit structure (which may include an interconnection network of metal and low-k dielectric materials) and occupies the passivation site of the damaged dielectric junction for a period of time. For example, in a specific embodiment, annealing is performed at a temperature of 400°C for one hour to repair implant damage.

Several variables affect the appropriate time and temperature for implant repair. The specific temperature relates to the amount of time it takes for hydrogen to diffuse through the metal and dielectric interconnection network and gate stack to the area where the damaged bond is located, and it can be specific to each device. The diffusion of atoms in the material is proportional to (Dt) 1/2, where D is a diffusivity that depends exponentially on temperature, and t is the diffusion time.

For many silicon-based dielectrics and device designs, using a blend of 4% hydrogen and 96% nitrogen at 400C for one hour is suitable for repairing implant damage. The repair procedure can be performed at a temperature as low as 300C. In another embodiment, a temperature of up to 500C can be used. However, certain materials are sensitive to high temperatures. Exposing the device to high temperatures and longer periods of time can cause unfavorable phase changes in high-k dielectric gate oxides such as HfO2, HfSiO2, etc., and control the lateral dimensionality of dopant diffusion in sub-20nm gate length finFETs The loss and degradation of dopant activation in the laser-doped junction contact area. Keeping these principles in mind, those who are familiar with the technology will realize that a suitable thermal repair procedure can be performed in a gas environment containing at least 1% hydrogen at a temperature from 300C to 500C for at least 30 minutes.

Therefore, those skilled in the art will recognize that in various embodiments, the changes in time, temperature, and hydrogen concentration may be different because these variables are related to each other. A combination of a lower time, temperature, and concentration may not be sufficient to repair implant damage, while a longer time and temperature may cause hydrogen ions accumulated in the split layer to diffuse into the substrate, or have other factors associated with an expanded heat distribution Negative effects. Higher hydrogen concentration is an explosion hazard. During a repair procedure, the temperature can also be changed.

After ion implantation, some embodiments may use synthetic gas for the thermal repair procedure. Syngas is a mixture of nitrogen and hydrogen with a hydrogen concentration usually between 3% and 5%. NS However, other embodiments may use inert gas other than nitrogen and different hydrogen concentration. For example, the embodiment may use an inert gas such as argon, and the embodiment may use a hydrogen concentration greater than 1%. Lower hydrogen concentration may require longer exposure, while higher hydrogen concentration represents an explosion hazard. When the thermal repair process is performed, hydrogen penetrates the exposed surface of the damaged device, and the combination of damage can be terminated in order to repair the damage.

Thermal annealing by forming gas or other hydrogen-bearing gas has appropriate time and temperature conditions to allow hydrogen to diffuse into the sensitive dielectric layers of electronic devices (including low-k insulators in metal interconnection networks, gate oxides such as SiO2, SiON, high-k dielectrics such as HfO2 and oxide and nitride spacers (gate sidewall insulators). Materials with higher K values are more sensitive to damage from implantation, so the thermal repair procedure is more effective for higher K materials. For example, a thermal repair procedure can be performed after implanting a material with a K value of 10 or greater or a material with a K value of 15, 20, 25 or greater. Specific high-K materials that benefit from the thermal repair process include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), hafnium silicate (HfSiO4), tantalum oxide (TaO5), tungsten oxide (WO3), cerium oxide (CeO2), oxide Titanium (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), niobium pentoxide (NiO5), zirconium silicate (ZrSiO4), zirconium oxide (ZrO2), barium titanate ( BaTiO3) and lead titanate (PbTiO3). Experiments have determined that when ions are implanted through a high-K material to form a split layer, the circuit that depends on the high-K property has no function without performing a thermal repair procedure according to an embodiment of the present disclosure.

In one embodiment, the thermal cycle of the repair process does not exceed a threshold of the dissolution of the hydrogen trapped implant damaged structure in the area of the intended split surface. If the temperature exceeds the dissolution threshold, the trapped hydrogen will be dispersed into the substrate, making it impossible to perform the splitting operation. In addition, after repair and before splitting, the temperature to which the substrate is exposed after a repair procedure can be limited to below a threshold (for example, 500C, 450C, or 400C) to limit dispersion.

It is necessary to directly access the dielectric layer in the metal interconnection network and the transistor gate stack area by the ambient gas to perform a thermal repair process to repair the ion damage. Therefore, on the surface of the electronic device Before sealing, perform a hot repair procedure. Therefore, it is preferable to perform a thermal repair process before performing a deposition process that can restrict access to damaged sites. In a 3DIC device, thermal annealing is performed before the layers are bonded.

In an embodiment of the present disclosure, the network of channels for the flow of cooling fluid is modulated by modulating the implanted hydrogen depth by a patterned layer of material at the surface of the device wafer during hydrogen implantation To define, where the thickness, stop power and position are selected to create an uneven split surface in the transfer device substrate. Similar methods for modulating the depth of the split plane can be used to define cooling channels in selected layers of high thermal conductivity materials for subsequent insertion into the laminated multilayer, multi-device 3DIC stack. In one embodiment, the surface area of the cooling fluid flow network is coated with a device layer selected to increase the thermal conductivity between the heated device layer and the substrate and the flowing cooling fluid and to prevent chemical reactions between the device substrate and the cooling fluids material. The material.

The embodiment also has the advantages of the wafer-level bonding process, including the incorporation of cooling fluid network channels, and the design flexibility for the incorporation of dies manufactured on different wafer sizes, different wafer thicknesses, and different substrate materials . The device formed using the split and stack technology provided in the present disclosure has many advantages over the prior art. The substrate formed by back grinding undergoes a substantially higher level of mechanical stress and a higher level of thickness variation on the surface of the substrate. Ion splitting can be performed with fewer process steps than back grinding, thereby simplifying the process and reducing the amount of processing required. The layers of the 3DIC structure according to the present disclosure can be interconnected via dense high-bandwidth vertical and lateral metal connections, which can shift the requirements for the interposer and the solder bump structure, resulting in a more efficient manufacturing that is smaller and smaller. Tightly integrated, higher-speed devices.

Although the above is a full description of specific embodiments, various modifications, alternative configurations, and equivalents may be used. Therefore, the above description and explanation should not be regarded as limiting the scope of this disclosure.