Vertical power MOSFET including planar channel

Vertical power metal oxide half field effect transistor with planar channel

VERTICAL POWER MOSFET INCLUDING PLANAR CHANNEL

This creation is about power MOSFETs (hereinafter referred to as MOSFETs), especially a vertical super junction MOSFET with a planar DMOS part and a vertical conductive part.

The priority claimed in this application is an application filed by Jun Zeng et al. to the U.S. Intellectual Property Office on February 4, 2014. The application number is 61/935,707, and the entire reference content is incorporated herein.

Vertical MOSFETs are popular as high-voltage and high-power electrocrystalline systems because they can provide a thick drift layer with a low doping concentration to achieve a high breakdown voltage in the off state. Generally, the MOSFET includes a highly doped N-type substrate, a thick and low-doped N-type drift layer, a P-type body layer abutting on the drift layer, and an N-type source on the top of the body layer. And a gate separated from the main body by a thin gate oxide. It usually provides a vertical groove gate. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface. When the gate is positive enough for the source, the channel region of the P-type body between the N-type source and the N-type drift layer is reversed and creates a gap between the source and the drain. A vertical conductive path.

In the off state of the device, when the gate and the source are short-circuited or negative, the drift layer consumption between the source and the drain and the large breakdown voltage (for example, more than 600 volts) can be suppressed continued. However, due to the low doping required by the thick drift layer, the on-resistance becomes worse. Increase the The doping of the drift layer will reduce the on-resistance, but will reduce the breakdown voltage.

Forming vertical columns of alternating P-type silicon and N-type silicon extending to the substrate to replace a single N-type drift layer is a conventional technology, in which the charges in the columns are balanced, and when the MOSFET is turned off , P-type column and N-type column at a high voltage are completely consumed. It is called a super junction. In this configuration, the doping concentration of the N-type column can be higher than the doping concentration of the conventional N-type drift layer. As a result, the on-resistance can be reduced under the same breakdown voltage. A super junction MOSFET can be formed by a multiple epitaxial growth and implantation process. The formation of alternating P-type column and N-type column system extending to the thickness of the substrate requires multiple cycles. The cycle system is epitaxial growth of a part of the column thickness, and then masking and implanting the P-type dopant Doping with the N-type, then grow more column thickness and repeat the masking and implanting process. The number of implant steps may exceed 20, depending on the thickness. Between each implantation cycle, the doping causes undesirable lateral diffusion due to the high process temperature. It greatly increases the cell spacing required in the cell array, which makes the crystal grain change large. As a result, the MOSFET is not ideally formed, and the manufacturing process is very time-consuming.

In addition, a super junction can be formed by etching deep grooves in N-type silicon filled with a P-type extension layer. The grooves must be deep so that they are a vertical drift layer long enough to act as a depletion region at a high breakdown voltage. Forming deep grooves is time-consuming and therefore expensive.

The power MOSFETs are formed to have a large number of identical parallel cells. Any changes between the devices may cause uneven current and temperature on the MOSFET, reducing its efficiency and breakdown voltage.

What a power MOSFET needs is that it does not have the disadvantages and limitations of the above-mentioned conventional technology.

In one embodiment, a MOSFET is formed with a planar channel region for a lateral current flow, and a vertical conductive path for a vertical current flow.

In one embodiment, a P-well (a body region) is formed in an N-type layer, which has a groove formed in the N-type layer and the groove is deeper than the P-well to produce the N-type The sidewall of the layer. The N-type layer has higher doping than the N-type drift layer in the MOSFET. The MOSEFT includes a shielded vertical field plane formed by a conductive material (for example, doped polysilicon) that fills the groove with a dielectric material (for example, oxide) and is insulated from the sidewalls. A P mask layer is formed at the bottom of the groove and abuts against the bottom of the side wall. The P mask layer also rests on the top of a P column. An N column is located below the channel area and laterally abuts the P column. For low on-resistance, the N columns and P columns are relatively highly doped. The groove field plane is deeper than the P well to provide an effective electric field reduction in the N-layer. When the MOSFET is turned off, the field plane and the P mask help to consume the N-layer laterally, allowing the N-layer to be relatively highly doped for low on-resistance. The combined effect of the groove field plane, the P mask, the N-type layer, an N-type drift layer with reduced thickness, and the relatively high-doped N column and P column provide an increased breakdown voltage , Lower turn-on resistance and lower cost per die. For faster switching, the conductive field plane electrode can be connected to the gate electrode or the source electrode to provide a lower gate-drain capacitance.

The lower turn-on resistance of each unit area allows more dies to be formed on each wafer.

In a preferred embodiment, the depth of the field plane groove is the thickness of the insulating material, the doping and thickness of the N-type layer, and the doping and depth of the P mask are selected so that the N layer is at The breakdown voltage is completely consumed. In addition, the doping, depth and width of the P column and the N column are The P column and the N column are completely consumed at the breakdown voltage.

In one embodiment, a power MOSFET includes a highly doped N-type substrate with a low doping concentration of the first N-type layer (the drift layer), which is about 30 microns thick, and is epitaxially grown on the substrate . The first N-type layer is thinner than the conventional drift layer because it does not need to maintain the entire source-drain voltage in the off state.

The first N-type layer is masked and implanted and doped to form alternate P-type and N-type regions about 4 microns thick, which are called columns. The N-type doping concentration in the N-type column is higher than the doping concentration in the N-type drift layer. In one embodiment, only one implant is required for each type of doping to form the columns, because the column layer is thinner than the conventional column layer. Therefore, compared with the conventional technology, it has less lateral diffusion, making the columns more ideal.

A second N-type layer (for example, 8 microns thick) is formed above the column layer, which has a higher doping concentration than the doping concentration of the first N-type layer.

The second N-type layer is formed with a P-well, and the P-well is formed in an N-type source region on the surface. The top surface of the p-well between the source region and the top of the second N-type layer forms a lateral channel along the top surface of the device.

In each of the cells, a groove is etched in the second N-type layer between the P-wells, and the groove is deeper than the P-wells. Then, a thin gate dielectric is formed above the lateral channel at the top and along the sidewall of the groove. Then, a polysilicon gate is formed above the top channel and along the vertical sidewall of the groove, so that the depth of the polysilicon gate is deeper than the P-well. The dielectric layer separating the gate from the channel and the sidewall can have the same thickness or different thicknesses to have different advantages. The groove field plane results in a lower electric field and a higher breakdown voltage, which allows the doping of the second N-type layer to increase and the on-resistance to decrease.

A source electrode of metal contacts the P-well and the source regions, and a drain electrode of metal contacts the bottom surface of the substrate.

In another embodiment, the P columns can be formed during the same step of forming the P mask by single or multiple high-energy implants.

In one example, a load is coupled between the source electrode and ground, and a positive voltage is applied to the drain. When the gate is sufficiently positively biased with respect to the source electrode, the top lateral channel between the source region and the second N-type layer is reversed, and electrons travel along the second N-type layer The vertical sidewall of the groove to accumulate. The horizontal and vertical accumulation of electrons forms a low-resistance path between the source electrode and the N-type column under the channel. Then, the N-type column and the first N-type layer complete a vertical conductive path to the drain electrode.

Since there is no thick drift region with low doping concentration between the channel and the drain electrode, the on-resistance of each cell area (especially the on-resistance Ron*Area) is compared with the on-resistance of the conventional vertical power MOSFET Will be lower. Part of the reason for the lower on-resistance is the use of high-doped N columns and a second N-type layer (like the higher doping of the second N-type layer), where the second N-type The higher doping of the layer is enabled by the groove field plane effect, the P mask, and the accumulation of electrons along the vertical sidewalls of the second N-type layer when the gate is positively biased. In one embodiment, the specific turn-on resistance reaches 4.5 Ohms-mm², Which is about half of the conventional power MOSFET.

Due to such a low turn-on voltage in each cell area, the size of the die can be smaller than that of the conventional die, so that the number of dies per wafer can be achieved when each die has the same turn-on resistance. double.

When the MOSFET is off and a source-drain voltage is slightly lower than the breakdown voltage, the first N-type layer, the columns, and the second N-type layer are completely consumed. The crash The voltage can be the same as that of a conventional vertical MOSFET with the same thickness, but the on-resistance is smaller. Conversely, the breakdown voltage can be increased by forming a thicker layer to be higher than the breakdown voltage of the prior art, and the on-resistance can be the same as the prior art. In addition, due to the thinner column layer and the shallower grooves, the process complexity of forming the vertical MOSFET is lower than that of the conventional vertical MOSFET with super junction.

After the PN diode in the MOSFET is turned on by a bias voltage, the MOSFET structure can also reduce the recovery time. If the MOSFET is used with an AC voltage, when the drain is more negative than the source, the diode will conduct electricity. When the polarity is reversed and the diode is reverse biased, after the gate is biased to an on state, the stored charge must be removed before the MOSFET is fully turned on. Due to the higher degree of doping in the second N-type layer and the N column, the stored charge is removed faster, so that a faster switching time can be achieved.

In a preferred embodiment, a P-type mask layer is formed above the P column under the groove to abut the sidewall of the second N-type layer. The P-type mask layer helps to consume the second N-type layer laterally to increase the breakdown voltage.

The illustrated gate configuration also helps to consume the second N-type layer laterally to increase the breakdown voltage.

The various variations of the aforementioned cells using a horizontal channel at the top, a vertical field plane facing the reinforced vertical "channel" part, and a super junction are described. The innovative technology used to form the vertical MOSFET is also explained.

An insulated gate bipolar transistor (IGBT) can be formed by using a P-type substrate instead.

<p>10cell</p><p>12Drain electrode</p><p>14Source electrode</p><p>16Gate</p><p>18P well</p><p>20N-layer</p><p>22N++ source area</p><p>24N type column</p><p>26N--Floor</p><p>28N++ silicon substrate</p><p>30P type column</p><p>35Phosphorus</p><p>36N Tandem layer</p><p>38Photoresist layer</p><p>40Boron</p><p>42,44,46Floor</p><p>48Oxide layer</p><p>50Photoresist</p><p>52Groove</p><p>54Boron</p><p>56P Mask</p><p>58Thermal sacrificial oxide layer</p><p>60Oxide layer</p><p>64Polysilicon layer</p><p>66Photoresist layer</p><p>68Boron</p><p>70Phosphorus</p><p>72Insulation layer</p><p>74Boron</p><p>76P+ contact area</p><p>80N column</p><p>82P column</p><p>84P well</p><p>86,88Column layer</p><p>90Groove oxide</p><p>92Gate polysilicon layer</p><p>94,96,98,100,102,104polysilicon layer</p><p>106Gate oxide</p><p>108,110oxide</p><p>112P column</p><p>114N column</p><p>116,118P column</p><p>120Conductive polysilicon part</p><p>124N floor</p><p>126N-layer</p><p>130P+Substrate</p><p>132Buffer layer</p><p>134Collector electrode</p><p>136,138N type area</p><p>140P+ area</p><p>142N+ District</p><p>144N buffer layer</p>

Figure 1 is a cross-sectional view of a single vertical MOSFET cell in a large array of the same continuous MOSFET cell according to an embodiment of the invention.

Figures 2A to 2R show the various steps used to manufacture the MOSFET of Figure 1.

Figure 3 is the equipotential line of the depletion zone between the top surface of the substrate of the device and a P-well in a closed state, and shows a virtual maximum of the breakdown voltage.

Figure 4 shows a MOSFET with a shallower column layer or a shallower groove, so that the P mask does not touch the bottom P column.

Figure 5 shows a MOSFET with N columns thinner than P columns.

Figure 6 is a MOSFET with the P-well extending to the sidewall of the groove.

Figures 7A and 7B show MOSFETs without N and P columns.

Figures 8A and 8B show a MOSFET with multiple tandem layers.

Figure 9 shows a MOSFET with a thinner oxide above the edge of the N-layer to reduce the possibility of oxide collapse.

Figure 10A shows a MOSFET with a gate polysilicon layer with a more uniform thickness.

Figure 10B shows a MOSFET with a split polysilicon layer, where the gate overlaps the N-layer.

Figure 10C shows a MOSFET with a split polysilicon layer, where the gate overlaps the P mask.

Figure 10D shows a MOSFET with a split polysilicon layer without polysilicon facing the edge of the N-layer.

FIG. 11A is a MOSFET in which a uniformly thin gate oxide overlaps the lateral channel, the sidewall of the groove and the P mask.

Figures 11B and 11C show MOSFETs with a thinner oxide above the P shield.

Figure 11D is a MOSFET with a variable thickness oxide adjacent to the groove.

Figures 12A and 12B show a MOSFET with a P column below the P well.

Figures 13A and 13B show a MOSFET with a split polysilicon layer.

Figures 14A to 14C show a MOSFET with an N-layer conformal around the P column.

FIG. 15A to FIG. 15E show an embodiment of a modified MOSFET converted into an IGBT by using a P+ type substrate.

FIG. 16 is a top view of a type of cell array using either the MOSFET cell or the IGBT cell, in which the cells are arranged in a strip shape.

FIG. 17 is a top view of another type of cell array using either the MOSFET cell or the IGBT cell, in which the cells are arranged in a strip shape.

FIG. 1 is a cross-sectional view of a single vertical MOSFET cell 10 in a large array of the same continuous MOSFET cell according to an embodiment of the present invention. The width of the cell shown is approximately 8-11 microns. The MOSFET cell 10 may have a breakdown voltage exceeding 600 volts, and the number of cells 10 in an array of the same cell determines the current handling capacity, for example, 20 amperes. The cell array can be ribbon, quadrilateral, hexagon or other conventional shapes.

During normal operation, a positive voltage is applied to the drain electrode 12 on the bottom and a load, which is connected between the ground and the source electrode 14 on the top. When a positive voltage is applied to the conductive gate 16 and is greater than the threshold voltage, the top surface of the P-well 18 is reversed, and electrons move along the N-layer 20 vertical sidewalls to accumulate. The gate extends along the sidewall below the P well 18 and creates a field plane to a lower electric field in the N-layer 20. The N++ source region 22, the P well 18, and the top surface of the N- layer 20 form a lateral DMOS transistor portion of the MOSFET cell 10. Therefore, in the open state, through the N++ source region 22, the reversed channel of the P well 18, the sidewall of the N-layer 20, the N-type column 24 under the channel, the N-- layer 26 (the drift layer) and the N++ silicon substrate 28 have a conductive N-type channel between the source electrode 14 and the drain electrode 12.

The combination of the lateral DMOS transistor portion, the higher doping of the N-layer 20 (allowing the groove field plane effect and the vertical gate portion to accumulate electrons along the sidewall of the N-layer 20), alternate Moreover, the highly doped N-type columns 24 and P-type columns 30, and the N layer 26 can reduce the on-resistance compared with the prior art, which will be described below. If the PN diodes inside the MOSET become forward biased, the structure also increases the breakdown voltage and speeds up the switching time compared to the prior art, which will be described below.

In the cross-sectional view, the depth of the P well 18 is exaggerated for convenience of description, and the polysilicon gate electrode 16 extends along the sidewall of the N-layer 20 to below the P well 18. For example, the polysilicon gate 16 along the sidewall of the N-layer 20 (and any virtual field plane along the sidewall) can extend 1-4 microns below the P well 18. Since Figure 3 is a simulation, the size of the gate electrode 16 in Figure 3 is relatively more accurate than that of the P well 18.

FIGS. 2A to 2R are various steps used to manufacture the MOSFET cell 10 of FIG. 1. FIG.

Figure 2A shows that, when doped in-situ during growth, the N-- layer 26 is epitaxially grown on an N++ silicon substrate 28, or the N-- layer 26 is periodically Take about 1.5E12cm²The dose is implanted with N-type doping. The N++ silicon substrate 28 may have about 5E19cm³The doping concentration. To make A device has a breakdown voltage of about 600V, and the final doping density of the N-- layer 26 is about 3.5E14cm³. The N-- layer 26 may be 30 microns thick.

FIG. 2B shows that a thin thermal oxide is longer than the N-- layer 26, and then a blanket phosphor 35 is implanted to form an N column layer 36. FIG. The implant dose can be approximately 1-2E12cm²。

FIG. 2C shows a patterned photoresist layer 38 formed above a predetermined position of the N-type column 24. Then Boron 40 is about 1E13cm²The metering to cover implant to form a P-shaped column 30.

In Figure 2D, the photoresist and oxide are split, and an N-layer 20 is epitaxially grown to have a thickness of approximately 2.3E15 cm³A doping density of, which is higher than the doping density of the N-- layer 26. The N-layer 20 is approximately 8 microns thick. In another embodiment, the doping density of the N- layer 20 is the same as that of the N- layer 26.

In FIG. 2E, a thermal oxide layer 42 is longer than the N-layer 20. The dopants of the N-type column 24 and the P-type column 30 are driven and dispersed to form a column layer with a thickness of about 4-5 microns, which has an N-type dopant in the N-type column 24 Concentration is about 2E15cm³, And having a P-type doping concentration in the P-type column 30 is about 1E16cm³. The doping density of the N-type column 24 can be higher or lower than the doping density of the N-layer 20.

In Figure 2F, a polysilicon layer is formed to be approximately 1000 angstroms thick, followed by a nitride layer 46 approximately 2000 angstroms thick, and then an oxide layer 48 approximately 10,000 angstroms thick.

In Figure 2G, one layer of the photoresist 50 is patterned, and the exposed portions of the layers 42, 44, 46 are etched away.

In Figure 2H, the photoresist is stripped and a dry etching is performed on the exposed silicon to form a groove 52 in the N-layer 20. Below the groove 52, the groove etching leaves approximately N-layer 20 of 3-4 microns. Next, Boron 54 was implanted approximately 4E12cm²To the groove 52 to form a P mask 56.

In Figure 2I, the thick oxide layer is peeled off by dry etching, and a thermal sacrificial oxide layer 58 about 1000 angstroms thick is grown on the P mask 56 and on the sidewalls of the N- layer 20 .

In Figure 2J, the thermal sacrificial oxide layer is stripped, and a LOCOS process is used to form an oxide layer 60 with a thickness of about 6000 angstroms above the P mask 56 and the sidewalls of the N-layer 20.

In Figure 2K, the layers 42, 44, 46 are peeled off.

In Figure 2L, a thin gate oxide layer with a thickness of about 900 angstroms is grown on the N-layer 20. Then, a conductive polysilicon layer 64 is deposited and patterned.

In Figure 2M, a photoresist layer 66 is patterned to expose the central portion of the polysilicon layer 64, and then the gate electrode 16 is formed by a dry etching.

In Figure 2N, the photoresist layer is stripped off, and boron 68 is implanted into the N-layer 20 and embedded to form a self-aligned P-well 18 with the gate electrode 16. The P well 18 has a depth of about 2-3 microns.

In Figure 2O, Arsenic or Phosphorus 70 is implanted approximately 5E15cm²The dose is embedded to form an N++ source region 22 about 0.2-0.5 microns deep, and self-calibrates with the gate 16 together.

In Figure 2P, the insulating layer 72 is deposited on and around the gate electrode 16 composed of a backing oxide layer, which has a thickness of about 800 angstroms, followed by a boro-phospho-silicate glass (boro-phospho-silicate- glass, BPSG) layer, which has a thickness of about 10,000 angstroms. Then, the central portion of the insulating layer 72 is shielded by photoresist, and is etched to expose the N++ source region 22. Then, the photoresist Be stripped.

In FIG. 2Q, the exposed portion through the N++ source region 22 is etched to expose the P well 18. Then, boron 74 is about 2E15cm²The dose of is implanted and embedded in the P-well 18 to form a P+ contact area 76. The lateral width of the P+ contact area 76 is about 1 micron. If the P well 18 extends to the edge of the crystal grain, the P+ contact area 76 only needs to be disposed at the edge of the crystal grain.

In Figure 2R, the structure is metalized (for example, using sputtering) to form a source electrode 14 on the top, which is in contact with the side surfaces of the P+ contact region 76 and the N++ source region 22 to make contact with the The areas are electrically shorted together. The source electrode 14 may be formed by sputtering AlCu or AlSiCu, and may be about 4 microns thick. A drain electrode 12 at the bottom is formed by sputtering layers of titanium, nickel and silver, wherein the thickness of the titanium layer is about 1000 angstroms, the thickness of the nickel layer is about 2000 angstroms, and the thickness of the silver layer is about 10,000 angstroms. Then, the structure is protected by a protective layer, and the protective layer is patterned/etched to expose the electrodes for contact with the leads of the package. For example, a wire bonding can bond the source electrode 14 to a lead of the package, and the drain electrode 12 can be directly bonded to a heat sink electrode of the package.

Fig. 3 shows the equipotential lines of the depletion region between the top surface of the N++ silicon substrate 28 of the device and the P-well 18 in an off state and the voltage is slightly lower than the breakdown voltage, showing that the voltage is basically uniformly distributed. This uniform voltage distribution maximizes the breakdown voltage. It is worth noting that at a maximum allowable voltage in the closed state, all areas below the P well 18 and above the N++ silicon substrate 28 will be consumed.

The P mask 56 increases the breakdown voltage by effectively increasing the vertical size of the P-type column 30 without having to grow an extra epitaxial layer. When the gate is grounded or negative, the P mask 56 except for the vertical field plane of the gate 16 adjacent to the sidewall of the N-layer 20 helps to consume the N-layer 20 laterally to achieve The uniform distribution of the voltage shown in Figure 3. This lateral consumption allows one of the higher N-layers 20 to be doped to reduce the on-resistance.

Please refer to Figure 1 again. The N-- layer 26 is thinner than the conventional drift layer because it does not need to extend to the channel region. Forming adjacent P-type columns 30 and N-type columns 24 creates a super junction, where the columns are completely consumed and the charges in the P region and the N region are balanced. In the open state (positive gate bias), the current flows from the source electrode 14, through the source region 22, through the lateral channel, and then vertically through the N-layer 20 (including along an electron gathering The sidewalls of the layer pass through), and then vertically pass through the bottom N-type column 24, the N-- layer 26 and the N++ silicon substrate 28 to reach the drain electrode 12.

Since the N-type column 24 has a relatively high doping concentration higher than that of the N-- layer 26, it reduces the on-resistance and makes the conductivity better than the N-- layer 26. In addition, due to its proximity to the positively biased gate 16, the N-layer 20 is heavily doped and has an enhanced electron group along its sidewalls, so that there is a gap between the lateral channel and the N-type column 24 The vertical path is very conductive. The specific on-resistance (Ron*Area) is so low that all on-resistances of the cell array are less than 1Ohm. In one embodiment, the specific on-resistance reaches 4.5 Ohms-mm², Which is about half of the conventional power MOSFET. Will produce smaller dies and double the yield per wafer.

Since a groove gate is used instead of a vertical channel, the groove in Figure 1 can be very shallow (for example, 4-10 microns), making it easier to form. Since there is no need to form a deep groove, the process is quite simple. Therefore, the MOSFET cell 10 in Figure 1 can be formed using standard process equipment, and the cost per wafer can be reduced.

In addition to the increased breakdown voltage and lower on-resistance of the MOSFET cell 10, the MOSFET cell 10 has a faster recovery time after the MOSFET PN diode is biased on. After the source/drain voltage is reversed, the delay in gate control switching after the PN diode has been biased on is due to the stored charge when the diode is reversely biased. The stored charge must be removed so that the diode turns off and the MOSFET turns on. The removal of charge in the MOSFET cell 10 can not only be accelerated by the very highly doped N-type column 24 and the N-layer 20, but the positive gate effect on the sidewall of the N-layer 20 can also be extracted (drawing) the electrons of the side wall.

The basic MOSFET cell 10 in Figure 1 has many changes and maintains the advantages of a lower on-resistance and a higher breakdown voltage. Figures 4-15E show some of these changes.

Figure 4 shows a MOSFET with a shallower column layer, so the P mask 56 will not contact the bottom P-type column 30. The P mask 56 also has the effect of consuming the N-layer 20 laterally, so that the N-layer 20 can be relatively highly doped to reduce on-resistance.

Figure 5 shows a MOSFET with N column 80 deeper than P column 82. Since the N column 80 has a higher doping than the N-- layer 26, it can be used to diffuse current to avoid hot spots, and can reduce on-resistance.

Figure 6 shows a MOSFET with the P well 84 extending to the sidewall of the groove. When the gate 16 is positively biased to turn on the MOSFET, the overlapping gate 16 and the sidewalls of the gate 16 oppose the top and side surfaces of the P-well 84. Since the thin gate oxide only overlaps the P-well 84, this structure reduces the possibility of the top thin gate oxide with a high drain-gate voltage from collapsing, and the P-well 84 is at the source voltage .

Figures 7A and 7B show MOSFETs without N-column and P-column columns. In these embodiments, the advantages of the super junction in Figure 1 cannot be used, so the N-- layer 26 is relatively thin. Therefore, the on-resistance cannot be as good as the MOSFET in Figure 1. However, the gate structure combined with the N-layer 20 can still reduce the on-resistance compared to the conventional technology.

8A and 8B show a MOSFET with a plurality of column layers 86 and 88. It allows the use of thinner column layers to achieve a more uniform doping concentration in the columns. Have a thick The implanted dopants take longer to be embedded in the column layer of, the same is true for the lateral diffusion of the dopants. By using multiple thinner tandem layers, the required embedding time is reduced, so that the doping does not need to be laterally diffused for such a long time. It allows smaller cell spacing and smaller grain size. Assuming a sufficiently high source-drain voltage, the column layers are consumed when the MOSFET is turned off, and due to the consumption characteristics of the super junction, the P column and the N column are allowed to be in the vertical The doping concentration in the column is quite high.

FIG. 9 shows a MOSFET with a thinner groove oxide 90 at the upper edge of the N-layer 20. As shown in FIG. Since the electric field is usually concentrated at low-radius corners, the thicker oxide helps prevent the oxide layer between the N-layer 20 and the gate 16 from collapsing. The different oxide thicknesses are achieved by a masking etch.

FIG. 10A is a MOSFET with a gate polysilicon layer 92 with a more uniform thickness than the gate polysilicon layer in FIG. 1. Due to the thinner polysilicon layer, it can reduce the process time.

FIG. 10B shows a MOSFET with split polysilicon layers 94 and 96, where the gap overlaps the N-layer 20. The gate above the P well 18 reverses the channel. The polysilicon layer 96 can be connected to the source or floated to serve as a field plane for spreading the electric field distribution to achieve a more uniform electric field profile. When the MOSFET is turned on, the polysilicon layer 96 is essentially at a voltage lower than the gate. This makes the polysilicon layer 96 and the N-layer 20 have a smaller voltage difference. Since the gate part only reverses the channel, the N-layer 20 has a smaller conductivity adjustment. The gate-to-drain capacitance (Miller capacitance) is significantly reduced, reducing switching losses. Therefore, compared with the gate voltage, the conductivity of the MOSFET is slightly more linear than that of the MOSFET in Figure 1, the on-resistance is slightly increased, and the switching power loss is reduced.

Figure 10C shows a MOSFET with split polysilicon layers 98 and 100. The gap overlaps the P mask 56. The gates above the sidewalls of the P-well 18 and the N-layer 20 reverse the channel, and accumulate electrons along the sidewalls of the N-layer 20 for a lower on-resistance. The polysilicon layer 100 is connected to the source or floated.

FIG. 10D shows a MOSFET with split polysilicon layers 102 and 104, without polysilicon facing the edge of the N-layer 20. Since the field is concentrated on the edge, the possibility of oxide collapse between the edge of the N-layer 20 and the polysilicon is reduced.

FIG. 11A shows a MOSFET in which a uniformly thin gate oxide 106 overlaps the lateral channel, the sidewall of the groove, and the P mask 56. Therefore, in terms of reducing the on-resistance, the effect of the gate 16 of this embodiment is the most obvious; however, the possibility of the gate oxide collapse is increased.

11B and 11C show a MOSFET with a thinner oxide 108 on the P mask 56 to reduce the possibility of the oxide on the P mask 56 from collapsing.

FIG. 11D shows a MOSFET with a variable thickness oxide 110 adjacent to the groove, which reduces the possibility of oxide collapse due to field accumulation.

In the above-mentioned embodiment, a wide N column is vertically arranged under the P well 18. FIGS. 12A and 12B show MOSFETs having a narrow P column 112 below the P well 18 and a narrow N column 114 adjacent to the center P column 112. When the MOSFET is turned off, the narrower columns improve the lateral consumption of the columns, so the columns can be more highly doped to reduce the on-resistance. Since the current path is mainly along the edges of the N-layer 20 (and the N column 114 is below the edges), the position of the narrow P column 112 below the middle of the P well 18 will not affect the opening resistance. Bad effect.

In FIG. 12B, the central P column 116 extends to the P well 18. In the closed state, it helps to consume the N-layer 20 laterally, allowing the N-layer 20 to have higher doping to improve the opening resistance.

Figures 13A and 13B show a MOSFET similar to that of Figure 10B (with a split polysilicon layer), but in which the P column 118 in the middle extends to the P well 18 and a conductive polysilicon portion 120. The conductive polysilicon The portion 120 is connected to the source electrode 14, protrudes to the P column 118 and is insulated from the P column 118. In the closed state, it helps to consume the P column 118.

14A to 14C are MOSFETs having an N layer 124 conforming to surround the P column 118, and the P column 118 extends to the P well 18. The N layer 124 has a doping concentration approximately equal to the doping concentration of the P column 118. When the PN diode is forward biased, the N layer 124 reduces carrier injection into the P column 118 so as to enable faster recovery when the source and drain voltages change polarity. After the polarity has been reversed, it enables a faster switching time. The N layer 124 also reduces the current diffusion resistance to a lower on-resistance.

In FIGS. 14B and 14C, another N-layer 126 around the P-well 18 is added, which has a higher doping than the N-layer 20 to reduce on-resistance. The N-layer 126 helps spread current along the entire width of the P-well 18, and the N-layer 124 runs along the N-type column 24 to vertically conduct the current to the N-layer 26.

FIGS. 15A to 15E show embodiments of various MOSFETs converted into IGBTs by a P+ type substrate 130. A thin N-type buffer layer 132 is added. The buffer layer 132 is used to control the implantation of holes from the P+ substrate 130 and the breakdown characteristics of the IGBT. At this time, the drain electrode is a collector electrode 134 of a PNP transistor, and at this time, the source electrode is an emitter electrode of a NPN transistor. Therefore, a vertical NPN transistor and a PNP transistor are formed, and the current is blocked when the gate bias voltage is low. When there is enough positive gate bias, an initial current flows between the source and the drain, and enough current is implanted to forward bias the NPN and the PNP transistor to create the IGBT action. This makes the on-resistance lower than that of a vertical MOSFET. However, the maximum switching frequency is reduced. The general operation of IGBT is a conventional technology.

FIG. 15B is an N-type buffer with N-type regions 136 and 138 with different doping. The doping concentrations of the N-type regions 136 and 138 are about 1E17 cm, respectively³With 2E17cm³. A higher doping concentration reduces the breakdown voltage from the collector to the emitter, but increases the turn-off switching speed of the device. In addition, a different doping level of the N-type regions 136 and 138 can improve the trade-off between the breakdown voltage and the forward voltage of the device.

15C shows the collector electrode 134, which is directly connected to the P+ region 140 of the substrate and the N+ region 142 of the substrate. When the collector electrode 134 is sufficiently negative for the source (emitter) electrode, the N+ regions 142 allow the IGBT to be a PN diode. It integrates a free power isolation diode into an IGBT, which is useful for certain applications when the voltage changes polarity.

In FIG. 15D, an N buffer layer 144 is added above the P+ region 140 to adjust the hole implantation efficiency from the P+ region 140 (collector).

Figure 15E combines many of the aforementioned features into a single IGBT.

Figure 16 is a top view of a type of cell array used in either of the above-mentioned MOSFET cells or IGBT cells, wherein the cells are arranged in a strip shape. Only the gate 16, the source region 22 and the P+ contact region 76 are shown here. The P+ contact area 76 may be only at one end of each of the belt shapes.

FIG. 17 is a top view of another type of cell array used in either of the above-mentioned MOSFET cells or IGBT cells, in which the cells are arranged in a quadrilateral shape. Only the gate 16, the source region 22 and the P+ contact region 76 are shown here. Hexagonal shapes or other shapes can also be used.

Any of the above features can be combined in any combination of a MOSFET or IGBT to achieve a specific advantage of the feature in a specific application.

Although the specific embodiment of this creation has been shown and explained, it enables those with ordinary knowledge in the technical field to which this creation belongs to change and modify without departing from the broad scope of this creation. Therefore, any changes to the scope of patent application described below And revisions fall into the true spirit and scope of this creation.