Optoelectronic semiconductor device and fabricating method thereof

Photoelectric semiconductor component

OPTOELECTRONIC SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

The present invention relates to a semiconductor package structure, and more particularly to an optoelectronic semiconductor component.

The light-emitting semiconductor element has good photoelectric characteristics such as low power consumption, low heat generation, long operating life, impact resistance, small volume, fast reaction speed, no mercury, and color light which can emit stable wavelength. With the advancement of photoelectric technology, it has been One of the better choices for new generation light sources.

For example, a white light emitting diode (LED) component is conventionally used in a package design in which wire bonding is performed for wire bonding. However, due to the limitation of the wire bonding process, the wire bonding distance must be reserved between the wafer and the wafer, which not only causes a large increase in the package structure size, but also limits the number of components of the wafer matrix, which is disadvantageous for miniaturization of components. Furthermore, when a wafer matrix is used for multi-chip packaging, since the wafer arrangement is relatively dispersed, it is more likely to affect the uniformity of the coating of the phosphor layer, which not only causes a problem that the yield of the subsequent processing of the component is low, but also because of the fluorescence. The layer is mixed unevenly, causing problems of polarized or color cast of the white light emitting diode element.

Therefore, there is a need to provide an advanced optoelectronic semiconductor chip package structure that addresses the problems faced by conventional techniques.

In one aspect, the present invention provides an optoelectronic semiconductor component including a substrate, a first solid via plug, an optoelectronic semiconductor wafer, a phosphor layer, and a sealant. Wherein, the first solid interlayer plug penetrates the substrate. The optoelectronic semiconductor wafer has a first electrode that is aligned and in electrical contact with the first solid via plug. The phosphor layer covers at least one surface of the optoelectronic semiconductor wafer. The encapsulant encapsulates the substrate, the optoelectronic semiconductor wafer, and the phosphor layer.

In an embodiment of the present invention, the optoelectronic semiconductor component further includes: a first patterned metal layer on the first surface of the substrate; and a second patterned metal layer on the second surface of the substrate. Wherein the second surface is on the opposite side of the substrate relative to the first surface. a first patterned metal layer having at least one first pad aligned and directly in contact with the first solid via plug; the second patterned metal layer having at least one second pad aligned and aligned A solid via plug is in direct contact.

In an embodiment of the present invention, the first electrode is electrically connected to the first solid via plug via the first pad.

In an embodiment of the present invention, the optoelectronic semiconductor component further comprises: a carrier substrate coupled to the substrate, wherein the substrate, the photodiode wafer and the phosphor layer are separated from the outside air by the carrier substrate and the encapsulant .

In an embodiment of the present invention, the carrier substrate has a metal line in direct contact with the second pad.

In an embodiment of the present invention, the optoelectronic semiconductor component further includes: a second solid via plug extending through the substrate, aligned and in electrical contact with the second electrode of the optoelectronic semiconductor wafer.

According to the above embodiments, the present invention provides an optoelectronic semiconductor component that uses a flip chip bonding method to align the electrodes of at least one optoelectronic semiconductor wafer with a solid via through the substrate. The plug pads are electrically connected. Thereafter, the phosphor layer is overlaid on at least one surface of the optoelectronic semiconductor wafer, and the substrate, the optoelectronic semiconductor wafer, and the phosphor layer are coated with an encapsulant.

Compared with the conventional wire-bonding technology, when the optoelectronic semiconductor chip is packaged, the package structure must be laterally extended to electrically connect the wire to the pad of the substrate. The optoelectronic semiconductor wafer adopting the flip chip package structure is in contact with the solid via plug under the longitudinal alignment of the wafer electrode system, and the required package size is small, which is advantageous for miniaturization of the optoelectronic semiconductor component.

In addition, due to the small package size, the optoelectronic semiconductor wafer can be arranged more closely. When the phosphor layer is coated and packaged, the uniformity of the phosphor layers of the respective optoelectronic semiconductor components can be increased, and the polarized light of the conventional optoelectronic semiconductor components can be solved. Or the problem of color cast. In addition, the solid-state plug used in the flip chip packaging technology of the present invention can efficiently transfer the heat generated by the optoelectronic semiconductor wafer to the back surface of the substrate, compared with the conventional wire-bonding technology. The heat dissipation effect is better, and the performance of the optoelectronic semiconductor component can be improved.

<p>100Optoelectronic semiconductor components</p><p>101Substrate</p><p>101a First surface of the substrate</p><p>101bSecond surface of the substrate</p><p>102asolid interlayer plug</p><p>102bsolid interlayer plug</p><p>103 patterned metal layer</p><p>103a pads</p><p>103b solder pads</p><p>104 patterned metal layer</p><p>104a pads</p><p>104b solder pads</p><p>105patterned insulation</p><p>106Optoelectronic semiconductor wafer</p><p>106aElectroelectric semiconductor wafer electrodes</p><p>106belectrodes of optoelectronic semiconductor wafers</p><p>106c upper surface of optoelectronic semiconductor wafer</p><p>106d sidewalls of optoelectronic semiconductor wafers</p><p>107 solder balls</p><p>108Loading substrate</p><p>108aMetal lines</p><p>109Fluorescent layer</p><p>110 solder balls</p><p>111Insulating adhesive</p><p>112 Sealant</p><p>201Substrate</p><p>209Fluorescent layer</p><p>212 Wafer cutting steps</p><p>300Optoelectronic semiconductor components</p><p>308bearing substrate</p><p>312 Sealing body</p>

1A to 1G are cross-sectional views showing the structure of an optoelectronic semiconductor device 100 fabricated in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing a structure in which a phosphor layer is coated on a plurality of optoelectronic semiconductor wafers in accordance with another embodiment of the present invention.

3 is a cross-sectional view showing the structure of an optoelectronic semiconductor device according to an embodiment of the present invention.

The present invention is to provide an optoelectronic semiconductor component having a small package size, which can increase the uniformity of the phosphor layer of the optoelectronic semiconductor component and solve the conventional phototransistor. The body element has problems such as polarization or color cast due to uneven mixing of the phosphor layers. The above and other objects, features and advantages of the present invention will become more apparent and understood.

1A to 1G, FIGS. 1A to 1G are cross-sectional views showing the structure of an optoelectronic semiconductor device 100 according to an embodiment of the present invention. The method of fabricating the optoelectronic semiconductor component 100 includes the following steps:

First, a substrate 101 having a first surface 101a and a second surface 101b (as shown in FIG. 1A) is provided. The second surface 101b is located on the substrate 101 opposite to the first surface 101a. In some embodiments of the present invention, the substrate 101 may be a lead frame, a printed circuit board (PCB), a flexible circuit board, a ceramic substrate, or any other type of die carrier (die) Carrier). In the present embodiment, the substrate 101 is a printed circuit board, and the material thereof may be, for example, bismaleimide-triazine resin (BT), or other similar materials.

Thereafter, in the substrate 101, at least one solid via plug penetrating the substrate 101, such as solid via plugs 102a and 102b, is formed from the first surface 101a of the substrate 101 to the second surface 101b (eg Figure 1B)). In some embodiments of the present disclosure, the solid via plugs 102a and 102b are metal (e.g., copper or aluminum) plugs that extend through the substrate 101.

Then, on the first surface 101a of the substrate 101, a patterned metal layer 103 is formed, wherein the patterned metal layer 102 includes at least one pad (for example, pads 103a and 103b), and the pads 103a and 103b are respectively paired The quasi-solid via plugs 102a and 102b are directly connected to the solid via plugs 102a and 102b. And on the second surface 101b of the substrate 101, another patterned metal layer 104 is formed, wherein the patterned metal layer 103 includes at least one pad (for example, pads 104a and 104b) to align the pads 104a and 104b, respectively. Solid via plugs 102a and 102b, and directly connected to solid via plugs 102a and 102b (as depicted in Figure 1B) Show).

It is to be noted that although in the present embodiment, the solid via plugs 102a and 102b are formed prior to the patterned metal layers 103 and 104. However, in other embodiments, the formation of the solid via plugs 102a and 102b and the patterned metal layer 103 or 104 are not limited thereto. It is also possible to form the patterned metal layer 103 or 104 on the surface of the substrate 101 such that the pads 103a and 103b are aligned with the pads 104a and 104b, respectively. Thereafter, solid via plugs 102a and 102b are formed through the substrate 101 to align and directly connect the pads 103a, 103b, 104a and 104b.

Next, a patterned insulating layer 105 is selectively formed over the metal layer 103 to expose the pads 103a and 103b (as shown in FIG. 1C). In some embodiments of the present invention, the material constituting the patterned insulating layer 105 may be, for example, ceria, tantalum nitride, hafnium oxynitride, epoxy resin or the like. In other embodiments of the present invention, the insulating layer 105 may not be formed, and the patterned metal layer 103 may be exposed to directly define the range of the pads 103a and 103 to save cost.

Subsequently, at least one optoelectronic semiconductor wafer 106 is provided, and the electrodes 106a and 106b of the optoelectronic semiconductor wafer 104 are aligned with the solid via plugs 102a and 102b, respectively, and are in electrical contact with the solid via plugs 102a and 102b (eg, 1D is shown). In some embodiments of the present invention, the optoelectronic semiconductor wafer 106 may be a Light-Emitting Diode (LED) wafer, an Organic Light-Emitting Diode (OLED) wafer, or a laser diode. Laser diode wafer, photodiode wafer, charge-coupled device (CCD) wafer or solar cell wafer. In the present embodiment, the optoelectronic semiconductor wafer 106 is a light emitting diode wafer, and the cathode and anode electrodes (ie, the electrodes 104a and 104b) of the light emitting diode wafer are located on the same side of the optoelectronic semiconductor wafer 106. .

The optoelectronic semiconductor wafer is formed by aligning the electrodes 106a and 106b of the optoelectronic semiconductor wafer 106 with the solid via plugs 102a and 102b, respectively. The 106 is placed over the patterned insulating layer 105, and the electrodes 106a and 106b of the semiconductor wafer 106 are bonded to the exposed pads 103a and 103b using solder balls 107. Since the pads 103a and 103b are respectively aligned and directly connected to the solid via plugs 102a and 102b; the electrodes 106a and 106b coupled to the pads 103a and 103b are respectively aligned and aligned with the solid via plugs 102a and 102b electrical contact.

Then, a phosphor layer 109 is applied to at least one surface of the optoelectronic semiconductor wafer 106. In some embodiments of the present invention, an insulating paste 111 is preferably formed around the solder balls 107 and the electrodes 106a and 106b before the phosphor layer 109 is applied. Thereafter, a phosphor layer 109 (as shown in FIG. 1E) is applied over the upper surface 106c and the sidewall 106d of the optical semiconductor wafer 106 that is not covered by the insulating paste 111.

It should be noted that the aforementioned phosphor layer 109 coating step can be simultaneously performed on a plurality of optoelectronic semiconductor wafers 106. For example, in some embodiments of the present application, please refer to FIG. 2. FIG. 2 is a cross-sectional view showing the structure of a fluorescent layer 209 coated on a plurality of optoelectronic semiconductor wafers 106 according to another embodiment of the present invention. First, a plurality of optoelectronic semiconductor wafers 106 are arranged in an array pattern and fixed on a substrate 101 by wafer-level processing using steps as shown in FIGS. 1A to 1D. The phosphor layer 209 coating step as shown in FIG. 1E is performed on a plurality of optoelectronic semiconductor wafers 106 in synchronization. Subsequently, a wafer dicing step 212 is performed to form a structure similar to that shown in FIG. 1E. Due to the wafer level process, a plurality of optoelectronic semiconductor wafers 106 can be closely arranged on the substrate 101 to shorten the spacing between adjacent two optoelectronic semiconductor wafers 106. Therefore, the uniformity of the fluorescent layer 109 of each of the optoelectronic semiconductor elements 106 can be increased when the step of applying the phosphor layer 209 is performed.

Next, referring again to FIG. 1E, the substrate 101 bonded to the optoelectronic semiconductor wafer 106 is fixed to the carrier substrate 108. In some embodiments of the present invention, pads 104a and 104b of second surface 101 of substrate 101 are bonded to metal lines 108a on carrier substrate 108 using solder balls 110, and optoelectronic semiconductor wafers 106 and carrier substrates 108 are provided. produce Electrical contact (as shown in Figure 1F). In some embodiments of the present invention, the carrier substrate 108 may be a metal core printed circuit board (MCPCB), a ceramic circuit board, or a substrate having good heat conduction effects.

Due to embodiments of the present invention, the optoelectronic semiconductor wafer 106 is packaged using a flip chip package structure. That is, the solder balls 107 and 110 which are longitudinally aligned and directly in contact with the solid via plugs 102a and 102b are used to fix the optoelectronic semiconductor wafer 106 to the carrier substrate 108 and to the metal trace 108a of the carrier substrate 108. Electrical connection. Therefore, the package structure does not need to be laterally extended, and the required package size is small, which is advantageous for miniaturization of the optoelectronic semiconductor device 100. Further, more optoelectronic semiconductor wafers 106 can be closely arranged on the carrier substrate 108, thereby greatly increasing the packaging density of the optoelectronic semiconductor device 100.

Subsequently, the substrate 101, the optoelectronic semiconductor wafer 106, the phosphor layer 109, and a portion of the carrier substrate 108 are covered with the encapsulant 112, thereby isolating the substrate 101, the luminescent semiconductor crystal 106, and the phosphor layer 109 from the outside air to form The optoelectronic semiconductor chip package structure 100 is illustrated in FIG. 1G.

The optoelectronic semiconductor component 100 includes a substrate 101, solid via plugs 102a and 102b, an optoelectronic semiconductor wafer 106, a phosphor layer 109, a carrier substrate 108, and a sealant 112. Among them, the solid via plugs 102a and 102b penetrate the substrate 101. Optoelectronic semiconductor wafer 106, having electrodes 106a and 106b, is aligned and in electrical contact with solid via plugs 102a and 102b. The phosphor layer 109 covers the upper surface 106c of the optoelectronic semiconductor wafer 106 and the sidewall 106d. The substrate 101 is fixed on the carrier substrate 108. The encapsulant 112 covers the substrate 101, the optoelectronic semiconductor wafer 106, the phosphor layer 109, and a portion of the carrier substrate 108, thereby isolating the substrate 101, the light-emitting semiconductor crystal 106, and the phosphor layer 109 from the outside air.

In some embodiments of the present invention, the material of the encapsulant 112 may preferably be a transparent encapsulant compound such as epoxy resin, silicone rubber or polyimide (PI). (Molding Compounds). The solidified encapsulant 112, in addition to protecting the optoelectronic semiconductor component 100, can form a hemispherical transparent microlens structure for enhancing the optical efficiency of the optoelectronic semiconductor component 100.

Although in the present embodiment, the encapsulant 112 has a single transparent microlens structure, and only one substrate 101 and the light emitting semiconductor crystal 106 are coated, the other embodiments of the present invention are not limited thereto. For example, please refer to FIG. 3. FIG. 3 is a cross-sectional view showing the structure of an optoelectronic semiconductor device 300 according to an embodiment of the present invention. The structure of the optoelectronic semiconductor component 300 is substantially similar to that of the optoelectronic semiconductor component 100. The difference is that in the optoelectronic semiconductor component 300, the single transparent microlens structure composed of the encapsulant 312 can be coated at the same time and fixed in plurality. The light-emitting semiconductor crystal 106 on the substrate 308 is carried.

According to the above embodiment, the present invention provides an optoelectronic semiconductor component in which the electrodes of at least one optoelectronic semiconductor wafer are directly bonded to a solid via plug via the substrate by flip chip bonding. Thereafter, the phosphor layer is overlaid on at least one surface of the optoelectronic semiconductor wafer, and the substrate, the optoelectronic semiconductor wafer, and the phosphor layer are coated with an encapsulant.

Compared with the conventional wire-bonding technology, when the optoelectronic semiconductor chip is packaged, the package structure must be laterally extended to electrically connect the wire to the pad of the substrate. The optoelectronic semiconductor wafer adopting the flip chip package structure is in contact with the solid via plug under the longitudinal alignment of the wafer electrode system, and the required package size is small, so that the optoelectronic semiconductor wafer arrangement is more tight and the optoelectronic semiconductor component is small. Chemical.

Further, when the phosphor layer coating and packaging are performed, the uniformity of the phosphor layers of the respective optoelectronic semiconductor elements can be increased, and the problem of polarized or color cast of the conventional optoelectronic semiconductor elements can be solved. In addition, the solid-state plug used in the flip chip packaging technology of the present invention can efficiently transfer the heat generated by the optoelectronic semiconductor wafer to the back surface of the substrate, compared with the conventional wire-bonding technology. The heat dissipation effect is better, and the performance of the optoelectronic semiconductor component can be improved.

Although the present disclosure has been disclosed above in the preferred embodiment, it is not intended to be limiting. The original creation. Anyone with ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of this creation. Therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached.