Package structure of integrated circuit

Integrated circuit packaging structure

This creation is related to an integrated circuit packaging structure, especially it relates to a kind of X/Cu/Sn metal layer structure with reduced number of layers and simplified metal structure under bumps, especially it has a better circuit structure, and can be To achieve effective cost reduction while simplifying the manufacturing process and improving productivity.

In recent years, with the continuous maturity and development of semiconductor process technology, various high-performance electronic products have continued to introduce new ones, and the integration of integrated circuit (IC) components has also continued to increase. In the packaging process of integrated circuit components, integrated circuit packaging (IC Packaging) plays a very important role, and the types of integrated circuit packaging can be roughly divided into wire bonding package (WB) and automatic tape Types such as Tape Automatic Bonding (TAB) and Flip Chip (FC), and each type of package has its particularity and application field. Among them, for chips and substrates with high-density output/input (I/O) circuit line design, when the electrical connection path is too long, the inductance (Inductance) will increase. In addition, manual wire bonding technology requires expensive production costs, low process quality reliability, and relatively low productivity. In order to improve the above-mentioned problems, another Flip-Chip technology has been developed to reduce the package area and shorten the signal transmission path, or it is called Controlled Collapse Chip. Connection, C4), please refer to Figure 3. The bumps on the semiconductor chip 40 in the integrated circuit package structure 400 are usually solder balls 50. To solder the solder balls 50 to the semiconductor chip 40, you must first An under bump metallization [UBM] 60 with a structure of one to multiple metal layers is formed on the metal bonding pad 441 of the semiconductor chip 40, and a direction from the semiconductor chip 40 to the solder ball 50 includes one formed on the The adhesion layer 61 on the metal pad 441 is, for example, a titanium metal layer; a conductive conductive layer 62 is, for example, aluminum, copper, gold or silver metal; and one prevents the solder ball 50 A barrier layer 63 that penetrates and reacts with the conductive layer 62, such as nickel, chromium or platinum metal; and a wettable layer for providing wettability of the solder ball 50 and protecting the underlying metal layer. ) 64, such as gold, silver, copper, tin or other organic compounds. It is characterized by using the under-bump metal layer 60 to provide solder balls, diffusion barriers (Diffusion Barrier) and proper adhesion between the solder ball 50 and the metal pad 441 of the semiconductor chip 40, so that the solder can be coated on the metal layer 60 under the bump, and then through the reflow process (Reflow) to The applied solder is formed into the required solder balls 50. The methods generally used in the process of the under-bump metal layer include sputtering, evaporation, and plating.

Please refer to FIGS. 4A to 4F, which are the conventional processes for forming an under-bump metal layer on a semiconductor wafer. As shown in FIG. 4A, a semiconductor chip 40 with a plurality of electrical pads 41 on the surface is first provided. A passivation layer 42 is formed on the surface of the semiconductor chip 40, and the electrical connections on the semiconductor chip 40 are exposed. Pad 41, a first dielectric layer 43 and a second dielectric layer 45 are formed on the protective layer 42, and a metal layer is formed between the first dielectric layer 43 and the second dielectric layer 45 (Trace The metal 44 is on the electrical contact pad 41, and the second dielectric layer 45 exposes the metal bonding pad 441 on the metal layer 44. As shown in FIG. 4B, a titanium layer and a first copper layer 62a are formed on the second dielectric layer 45 and the metal pad 441 by sputtering, wherein the titanium layer serves as the adhesion layer 61. As shown in Figs. 4C and 4D, a photoresist layer 65 is coated on the adhesive layer 61, and after exposure and development, a second copper layer 62a is successively formed by electroplating. The copper layer 62b, a nickel layer and a gold layer, wherein the first and second copper layers 62a, 62b serve as the conductive layer 62; the nickel layer serves as the barrier layer 63; and the gold layer serves as the wetting layer 64. As shown in FIGS. 4E and 4F, the photoresist layer 65 is finally peeled off, and the adhesive layer 61 and the first copper layer 62a exposed under the photoresist layer 65 are etched. So far, an under-bump metal layer 60 with a four-layer structure of titanium/copper/nickel/gold (Ti/Cu/Ni/Au) is completed.

However, when the above structure is used for flip-chip solder bumps, when the solder ball 50 encounters gold-containing solder, a eutectic reaction will occur to produce brittle Intermetallic Compound Layer (IMC), and even create holes, resulting in subsequent A crack occurs between the solder ball and the metal layer 60 under the bump, which seriously affects the reliability of the manufacturing process.

In view of the above-mentioned conventional technology of forming an under-bump metal layer on a semiconductor chip, a variety of materials are used and multiple processes are required, which not only increases the complexity and cost of the process, but also increases the reliability risk in the process. After the material undergoes the high-temperature reflow process, the quality reliability of the formed solder structure is reduced, and the electrical connection quality of the final product is reduced, and there is a risk of electrical short circuit. Therefore, it will relatively increase the process cost and reduce the cost-effectiveness. And it still cannot solve the problem of low yield. Therefore, general users cannot meet the needs of users in actual use.

The main purpose of this creation is to overcome the above-mentioned problems encountered by the prior art and provide a simpler X/Cu/Sn metal layer structure for the under-bump metal structure layer without additional barrier layers, not only It can reduce the number of layers and have a better circuit structure, and can reduce the cost while simplifying the manufacturing process and improving the productivity.

In order to achieve the above purpose, this invention is an integrated circuit packaging structure, which mainly includes a semiconductor device, a metal structure layer under the bump, and a solder bump. The surface of the semiconductor device is provided with a plurality of electrical pads. And cover a surface protection layer. The surface protection layer has a plurality of openings corresponding to the electrical pads to partially expose the electrical pads, wherein a first surface protection layer is formed on the surface protection layer. The dielectric layer has a plurality of first openings to at least partially expose the electrical pads, and a metal layer is formed on the first dielectric layer, and has a plurality of metal pads to pass through the first dielectric layer. The first openings of the electrical layer are electrically connected to the corresponding electrical pads, and a second dielectric layer is formed on the first dielectric layer and the metal layer, which has a plurality of second openings to expose Corresponding to the metal pads; the under-bump metal structure layer is formed on the metal pad exposed in the second opening of the semiconductor device, and covers a part of the second dielectric layer around the second opening, which is mainly It includes an adhesive layer, which is arranged on the metal pad and part of the second dielectric layer, can be attached to the substrate and can be attached to the subsequent metal layer, a conductive layer (Conductor Layer) is arranged on the adhesive layer, And a protective layer disposed on the conductive layer to provide a solder-ability surface and prevent the conductive layer from being oxidized; and the solder bump is disposed on the protective layer of the metal structure layer under the bump superior.

Please refer to "Figure 1 and Figures 2A~2F", which are the schematic diagram of the integrated circuit package structure of this creation, the schematic diagram of the semiconductor chip structure of the preferred embodiment of this creation, and the production of titanium/copper layer in this creation. The schematic diagram of the structure on the semiconductor chip in Figure 2A, the schematic diagram of the structure of this creation coated with the photoresist layer on the titanium/copper layer of Figure 2B, the schematic diagram of the structure of this creation partially etched the titanium/copper layer of Figure 2C, this creation was created in Figure 2D is a schematic diagram of the structure of the stripped photoresist layer on the partial titanium/copper layer, and the structural diagram of the original immersion tin layer on the partial titanium/copper layer of Figure 2E. As shown in the figure, the present invention is an integrated circuit packaging structure 100, which mainly includes a semiconductor device 10, an under bump metallization (UBM) 20 and a solder bump 30.

The semiconductor device 10 is one of a semiconductor chip (Chip), a wafer (Wafer), a semiconductor package substrate, and a circuit board. The surface of the semiconductor device 10 is provided with a plurality of electrical contact pads 11 and covered with a surface protection layer ( Passivation Layer) 12, in the surface protection layer 12 corresponding to the electrical pads 11, there are a plurality of openings 13 to partially expose the electrical pads 11, wherein the surface protection layer 12 is formed with a The first dielectric layer 14 has a plurality of first openings 15 to at least partially expose the electrical pads 11, and a metal layer (Trace Metal) 16 is formed on the first dielectric layer 14 with a plurality of Metal pads 161 to be electrically connected to the corresponding electrical pads 11 through the first openings 15 of the first dielectric layer 14, and the first dielectric layer 14 and the metal layer 16 are additionally formed There is a second dielectric layer 17 with a plurality of second openings 18 to expose the corresponding metal pads 161.

The under-bump metal structure layer 20 is formed on the metal pad 161 exposed in the second opening 18 of the semiconductor device 10, and covers a part of the second dielectric layer 17 around the second opening 18, which mainly includes An adhesion layer (Adhesion layer) 21 is disposed on the metal pad 161 and part of the second dielectric layer 17, which can be attached to the substrate and can be attached to the subsequent metal layer. A conductive layer (Conductor Layer) 22 is Is disposed on the adhesive layer 21 and a protective layer 23 is disposed on the conductive layer 22 to provide a solder-ability (Solder-ability) surface and prevent the conductive layer 22 from being oxidized, wherein the under-bump metal The structure layer 20 is X/Cu/Sn (X/Cu/Sn), and X is one or more selected from titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), palladium (Pd) , Titanium-tungsten (Ti/W), chromium-nickel (Cr/Ni) alloys composed of platinum (Pt) metal elements or their mixtures.

The solder bump 30 is disposed on the protective layer 23 of the metal structure layer 20 under the bump. The above is to constitute a brand new integrated circuit packaging structure 100.

When this creation is used, the above-mentioned semiconductor device 10 is a semiconductor chip (Chip), its electrical pad 11 is an aluminum pad (Al Pad), and the covering metal layer 16 may be titanium/copper (Ti/Cu) alloy. In a preferred embodiment, a titanium layer is first formed on the surface of the second dielectric layer 17 by sputtering or other film forming methods as the adhesion layer 21, the thickness of which is between 300 and 3000 angstroms (<img file="TWM397597U_D0001.tif" />), and then form a copper layer as the conductive layer 22, the thickness of which is between 2-20 micrometers (μm). Then, a photoresist layer 24 is coated (Coat) on part of the copper layer, and after exposure and development (Develop), the titanium layer and copper layer exposed outside the photoresist layer 24 are etched, and finally peeled off The photoresist layer 24 is immersed on the copper layer to form an Immersion Tin layer with a thickness of 0.1 to 1 micron as the protective layer 23; so far, the under-bump metal structure The layer 20 forms a titanium/copper/tin (Ti/Cu/Sn) structure. Thereby, the wettability between the solder bumps 30 and the copper layer that are subsequently disposed on the metal structure layer 20 under the bumps can be provided, so as to make the bonding well and avoid copper oxidation. In this embodiment, the solder bump 30 is a tin ball, and the protective layer 23 can also be an Electroless Tin layer formed by electroless plating, and the adhesive layer 21 can also be selected from tungsten, Titanium-tungsten, chromium-nickel alloy composed of elements of chromium, nickel, palladium, platinum or their mixtures.

If so, the under-bump metal structure layer obtained by this creation can provide a more simplified X/Cu/Sn metal layer structure compared to the conventional technology, without the need for additional barriers of expensive materials such as nickel, chromium or platinum. The barrier layer not only reduces the number of layers to have a better circuit structure, but also simplifies the manufacturing process and improves productivity while achieving effective cost reduction.

In summary, this creation is an integrated circuit packaging structure, which can effectively improve the various shortcomings of the conventional use. It can provide a relatively simplified X/Cu/Sn metal for the Under Bump Metallization (UBM) layer. Layer structure, without additional barrier layer, not only can reduce the number of layers and have a better circuit structure, but also can reduce the cost while simplifying the manufacturing process and improving the productivity, thereby making the creation of this creation more advanced and more practical , It is more in line with the needs of the user, and it has indeed met the requirements of the creation patent application, and the patent application is filed in accordance with the law.

However, the above are only the preferred embodiments of this creation, and should not be used to limit the scope of implementation of this creation; therefore, all simple equivalent changes and modifications made according to the scope of the patent application for this creation and the content of the new specification , Should still be within the scope of this creation patent.

<heading>(This creation part)</heading><p>100. . . Integrated circuit packaging structure</p><p>10. . . Semiconductor device</p><p>11. . . Electrical contact pad</p><p>12. . . Surface protection layer</p><p>13. . . Perforation</p><p>14. . . First dielectric layer</p><p>15. . . First opening</p><p>16. . . Metal layer</p><p>161. . . Metal pad</p><p>17. . . Second dielectric layer</p><p>18. . . Second opening</p><p>20. . . Metal structure layer under bump</p><p>twenty one. . . Adhesive layer</p><p>twenty two. . . Conductive layer</p><p>twenty three. . . The protective layer</p><p>twenty four. . . Photoresist layer</p><p>30. . . Solder bumps</p><heading>(Used part)</heading><p>400. . . Integrated circuit packaging structure</p><p>40. . . Semiconductor wafer</p><p>41. . . Electrical contact pad</p><p>42. . . The protective layer</p><p>43. . . First dielectric layer</p><p>44. . . Metal layer</p><p>441. . . Metal pad</p><p>45. . . Second dielectric layer</p><p>50. . . Solder balls</p><p>60. . . Metal layer</p><p>61. . . Adhesive layer</p><p>62. . . Conductive layer</p><p>62a. . . First copper layer</p><p>62b. . . Second copper layer</p><p>63. . . Barrier layer</p><p>64. . . Wetting layer</p><p>65. . . Photoresist layer</p>

Figure 1 is a schematic diagram of the integrated circuit package structure of this creation.

Figure 2A is a schematic diagram of the semiconductor chip structure of the preferred embodiment of the present invention.

Figure 2B is a schematic diagram of the structure of the titanium/copper layer on the semiconductor wafer in Figure 2A.

Fig. 2C is a schematic diagram of the structure of this invention coating the photoresist layer on the titanium/copper layer in Fig. 2B.

Figure 2D is a schematic diagram of the structure of the titanium/copper layer of Figure 2C partially etched in this creation.

Figure 2E is a schematic diagram of the structure of the photoresist layer peeled off on the partial titanium/copper layer created in Figure 2D.

Figure 2F is a schematic diagram of the structure of the original immersion tin layer on the partial titanium/copper layer in Figure 2E.

Figure 3 is a schematic diagram of the conventional integrated circuit package structure.

FIG. 4A is a schematic diagram of the structure of a conventional semiconductor wafer.

FIG. 4B is a schematic view of the conventional sputtering titanium/copper layer on the semiconductor wafer in FIG. 4A.

Fig. 4C is a schematic diagram of the conventional structure of coating the photoresist layer on the titanium/copper layer in Fig. 4B.

Fig. 4D is a schematic view showing the structure of the conventional electroplated copper/nickel/gold layer on the exposed titanium/copper layer in Fig. 4C.

Fig. 4E is a schematic diagram of the structure of the photoresist layer peeled off on the titanium/copper layer in Fig. 4D.

Figure 4F is a schematic view of the conventional partial etching of the titanium/copper layer under the stripped photoresist layer of Figure 4E.