Method and system for pulse frequency modulated switching mode power supplies

Pulse frequency modulation controller

The present invention relates to a pulse frequency modulation controller, and more particularly to a pulse frequency modulation controller for a switched power supply.

Regulated power supplies are an integral part of the modern electronics industry. For example, a power supply in a personal computer needs to receive power from a variety of different external sources. Desktops and laptops typically have a regulated power supply on the motherboard that powers the CPU, memory, and peripheral circuitry. Regulated power supplies have a wide range of applications, such as portable chargers for home appliances, automobiles, and mobile electronics.

Typically, the power supply can be regulated with a linear regulator or a switched power supply. Linear regulators regulate by releasing too much power. Conversely, the switched power supply uses a variable duty cycle or variable frequency to quickly switch the power transistor such that its average output is the desired output voltage.

Compared to linear regulators, switched power supplies offer the advantages of small size, high efficiency, and high output power. On the other hand, they also have the disadvantage of large noise, especially the electromagnetic interference at the power transistor switching frequency or its resonant frequency.

Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) are two control architectures for switched power supplies. Recently, emphasis has been placed on practical green power supplies that require higher conversion efficiency and lower standby power consumption. In a PWM controlled switched power supply, the system can be forced into a burst mode under standby conditions to reduce power consumption. In a PFM-controlled switched-mode power supply, the switching frequency is reduced under light load conditions. The PFM controlled switched power supply has a simple control topology and a small quiescent current. Therefore, it is suitable for low-cost small output power applications such as battery chargers and power adapters.

Although conventional pulse frequency modulation controllers have been used in some applications, they have significant limitations, including electromagnetic interference and conversion efficiency to be further improved.

Thus, there is a need for a switching power supply controller that can improve conversion efficiency and suppress electromagnetic interference.

The present invention relates to a control circuit of a switching power supply. More specifically, the present invention is a pulse frequency modulation (PFM) controller. The present invention utilizes a pulse frequency modulation controller to provide a control signal in a resonance. The voltage ringing waveform turns on a power transistor. In an embodiment, an oscillator can be used to provide twice the frequency of the resonant ringing waveform to determine the timing of the control signal. Such a control signal is different from reducing power. The conduction loss of the transistor introduces a random jitter mechanism in the switching frequency of the power transistor.

In the switching power supply, when the control signal pulse stops, there is often a ringing waveform of the resonant voltage. If the next control signal pulse is sent at the peak of the ringing waveform, a large power transmission loss will occur. In the embodiment of the present invention, the switching frequency spectrum of the switching power supply with reduced power transmission loss and any extended PFM control can be simultaneously achieved; the above advantages can be achieved by forcing the power transistor to turn on the valley of the resonant voltage ringing waveform. And reached.

In order to suppress the electromagnetic interference (EMI) of the switched power supply, the method used in the present invention includes any change of the switching frequency of a power transistor, for example, any extending the switching frequency spectrum of the power transistor. In one embodiment, the present invention provides a technical means for forcing the power transistor to conduct during the valley of the resonant voltage ringing waveform, and thus can be arbitrarily changed even if the load and transmission state of the PFM controlled power supply remain unchanged. The switching frequency of the power transistor.

According to an aspect of the present invention, a pulse frequency modulation (PFM) controller is provided for controlling a switched power supply, the controller comprising: an output providing a control signal to turn on or off a switched power supply a current to regulate an output of the switched power supply; a first input for receiving a feedback signal associated with an output of the switched power supply, the feedback signal being turned off when the current in the switched power supply is off Presenting as a ringing waveform; a second input for receiving a voltage signal related to a current in the switched power supply; and a control circuit for providing a control signal in response to the feedback signal, the control signal being used in the The signal is turned on when the signal is in the valley of the feedback signal ringing waveform.

In an embodiment, the control circuit includes a driver circuit coupled to the output to provide a control signal, the driver circuit having a first state and a second state, wherein the driver circuit provides control in the first state Signaling to turn on current in the switched mode power supply, and in the second state the driver circuit provides a control signal to turn off current in the switched mode power supply; a first circuit coupled to the first input to receive a feedback signal, the first circuit for providing a first signal in response to the feedback signal; a second circuit coupled to the first circuit and a driver circuit, the second circuit responsive to the first signal Providing a second signal to set the driver circuit to the first state when the feedback signal is in a valley of the ringing waveform; and a third circuit for providing the third signal to set the driver circuit to the second state.

In an embodiment, the driver circuit includes a T flip-flop and a register, the clock input of the T flip-flop is for receiving a second signal, and the reset input of the T flip-flop is for receiving the third signal.

In an embodiment, the second circuit includes: a comparator that compares the feedback signal with a first reference signal, the ringing waveform of the feedback signal has a first oscillation frequency; and the oscillator responds to the comparison The output signal of the device provides an oscillating signal having a 50% duty cycle and a second oscillating frequency, wherein the second oscillating frequency is twice the first oscillating frequency; a T flip-flop coupled to the comparator And an oscillator; a first D flip-flop coupled to the oscillator and the T flip-flop; and a second D flip-flop coupled to the first D flip-flop, the second D flip-flop for receiving The first signal is responsive to the output of the first D flip-flop to provide a second signal.

According to a second aspect of the present invention, there is provided a pulse frequency modulation (PFM) controller for controlling a switched power supply, the pulse frequency modulation controller having random frequency jitter, the pulse frequency modulation controller coupled to The power transistor controls the output of the switched power supply with a regulated voltage, and the pulse frequency modulation controller includes: means for turning on the power transistor for the valley of the ringing oscillating voltage waveform of the power transistor to maintain the load and linear conditions The switching frequency of the power transistor is randomly changed at any time.

According to an embodiment of the present invention, a switched power supply is provided, comprising: a power supply; a transformer having a primary winding coupled to the power supply and a secondary winding providing an output; a switch coupled to the primary winding of the transformer, The switch is configured to receive a control signal to turn on or off the current in the primary winding; the feedback circuit provides a feedback signal associated with the output of the switched power supply, the feedback signal exhibiting a ringing waveform when the switch is off, The ringing waveform has a first oscillating frequency; and a pulse frequency modulation controller responsive to the feedback signal to provide a control signal to the switch, the control signal turning on the switch when the feedback signal is in a valley of the ringing waveform .

According to an embodiment, the pulse frequency modulation controller includes: an output terminal that provides a control signal to turn on or off the current in the switched power supply to regulate the output of the switched power supply; and a first input terminal for receiving and An output related feedback signal of the switched power supply, the feedback signal is represented as a ringing waveform when the current in the switched power supply is turned off; and a second input is configured to receive a voltage signal related to a current in the switched power supply; And a control circuit for providing a control signal in response to the feedback signal, the control signal being used to turn on a current when the feedback signal is located in a valley of the feedback signal ringing waveform.

In a variant embodiment, the present invention provides a signal processing circuit including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a peak representing a resonance waveform and a valley An input signal, the second input receiving a second input signal formed by the transition of the first state and the second state, the output providing an output signal, the signal processing power is set to generate the output signal In order to switch to a third state and a fourth state, the timing of the switching is basically to reflect the peak or trough of the first input signal.

In an embodiment of the signal processing circuit, a comparator is provided to compare the first input signal with a first reference signal.

According to an embodiment, the control circuit includes a driver circuit coupled to the output to provide a control signal, the driver circuit having a first state and a second state, wherein the driver circuit provides control in the first state Signaling to turn on current in the switched mode power supply, and in the second state the driver circuit provides a control signal to turn off current in the switched mode power supply; a first circuit coupled to the first input to receive a feedback signal, the first circuit for providing a first signal in response to the feedback signal; a second circuit coupled to the first circuit and a driver circuit, the second circuit responsive to the first signal Providing a second signal to set the driver circuit to the first state when the feedback signal is in a valley of the ringing waveform; and a third circuit for providing the third signal to set the driver circuit to the second state.

According to an embodiment, the driver circuit comprises: a T flip-flop and a register, the clock input of the T flip-flop is for receiving the second signal, and the reset input of the T flip-flop is for receiving the third signal; The second circuit includes: a comparator that compares the feedback signal with a first reference, a ringing waveform of the feedback signal has a first oscillation frequency; and an oscillator that provides an oscillation signal in response to an output signal of the comparator The oscillation signal has a 50% duty cycle and a second oscillation frequency, wherein the second oscillation frequency is twice the first oscillation frequency; a T flip-flop coupled to the comparator and the oscillator; the first D a flip flop coupled to the oscillator and the T flip flop; and a second D flip flop coupled to the first D flip flop, the second D flip flop for receiving the first signal and responsive to The output of the first D flip-flop provides a second signal. The novel scheme adjusts the timing of the control pulse for turning on the transistor, reduces the voltage with which the transistor is turned on, and reduces the power consumption of the power supply. Furthermore, by adjusting the timing of the control pulses such that they align with the valley points of the ringing waveform, additional frequency jitter is introduced into the power supply. Thereby, electromagnetic interference (EMI) is suppressed.

1 shows a simplified block diagram of a switched power supply system 100 using pulse frequency modulation (PFM) control in accordance with an embodiment of the present invention. The drawings are only an example and are not intended to limit the scope of the claims. Other variations, changes, and variations will be apparent to those skilled in the art. As shown, the switched power supply system 100 includes a power supply VIN. According to this embodiment, the power supply VIN can come from a variety of different power sources. In the embodiment shown in FIG. 1, VIN is a rectified DC power source that is obtained from an AC power source VAC through a rectifier circuit that includes at least one bridge 101 and capacitor 102. The switched power supply system 100 includes a transformer 110 that includes a coil 111 as a primary winding. The output circuit of the power supply provides a regulated output voltage VOUT. As shown, the output circuit includes a primary winding coil 116, a diode 137, and a capacitor 135.

As shown in FIG. 1, the coil 111 is coupled to a power source VIN to which a power transistor 120 is coupled. The power transistor 120 is configured to receive a control signal 122 and to turn the current in the coil 111 on or off. The feedback circuit includes an auxiliary winding 113 and provides a feedback signal 123 associated with the output voltage VOUT of the power supply. In another embodiment, the feedback signal can be obtained from the output voltage VOUT using device sampling such as an optocoupler.

In Figure 1, the power transistor 120 is shown as a bipolar transistor, and VCE is the voltage between the collector and emitter of the bipolar transistor. When power transistor 120 is turned on, current is flowing through coil 111 and energy is stored; when power transistor 120 is turned off, an induced secondary current is generated in coil 116. Thereafter, the rectified output voltage VOUT is generated at the output of the power supply. Although the power transistor 120 shown in Figure 1 is an NPN bipolar transistor, it is to be understood that any suitable power switching device, such as a power MOSFET, can be used.

The switched power supply system 100 shown in FIG. 1 further includes a pulse frequency modulation (PFM) controller 150 that provides a control signal 122 to the power transistor 120 in response to a feedback signal 123. In the particular embodiment illustrated in FIG. 1, pulse frequency modulation controller 150 has a plurality of externally connected pins. These pins include: FB pin: receive a feedback signal 123; DRV pin: provide a control signal 122; CS pin: detect the emitter current of the switch 120 through a resistor 125; VCC pin: receive operating power ; GND pin: Ground.

In one embodiment, the auxiliary winding 114, the diode 133, and the capacitor 131 provide a rectified power supply to the pulse frequency modulation controller 150 during normal operation.

In an embodiment, the switched power supply system 100 is designed to operate in a discontinuous current mode. In this setting, the control signal 122 includes a series of pulse signals. Each pulse turns on the power transistor 120 when the feedback signal indicates that additional power is required. When the emitter current in the power transistor 120 (detected by the voltage on the CS pin) reaches a predetermined limit value, the pulse frequency modulation controller 150 turns off the power transistor 120, thus turning on the power transistor 120. Time is fixed when VIN is constant. Thus, each pulse has a substantially constant width, wherein the interval between control pulses can be determined based on the load requirements of the power supply. When the power supply output voltage VOUT is higher than the required amplitude, the feedback signal 123 (received at the FB terminal) is also higher than a predetermined value. In this case, the pulse frequency modulation controller 150 no longer continues to supply current. The pulse frequency modulation controller increases the interval between control pulse signals when the output meets the demand. Therefore, at this stage, the duty cycle is reduced and the input power is also reduced, causing VOUT to go low. Thus, during normal operation, the voltage loop of Figure 1 can be considered a negative feedback loop.

It is noted that when the power transistor 120 is turned off, the current in the coil 111 is also turned off. However, due to the presence of impedance such as inductance and capacitance in the power supply circuit, the VCE will appear as a ringing oscillating voltage wave after the power transistor 120 is turned off. The ringing oscillating voltage wave includes a series of peaks and troughs. The ringing voltage also appears in the feedback signal 123 received at the FB pin. This ringing oscillating voltage can cause many limitations of the power supply using conventional pulse frequency modulation controllers. This phenomenon is further illustrated in Figures 2-1 and 2-2.

Figure 2-1 is a simplified waveform diagram showing the change in power transistor voltage VCE for a constant linear load condition using a conventional pulse frequency modulation controller. Figure 2-2 is a simplified waveform diagram showing the change in feedback voltage of a power supply using a conventional pulse frequency modulation controller under constant linear load conditions. As shown, the single switching cycle consists of three time periods: Ton1, Ton2, and Tondis. During the time period Ton1, the control signal 122 is at a high potential, the power transistor 120 is turned on, and the VCE is smaller than VIN.

Referring to Figure 1, when the power transistor 120 is in the off state, there are two stages before the power transistor 120 is next turned on. In the first phase Ton2, the energy in the secondary winding 116 is transferred to the output capacitor 135 and the load (not shown). The VCE voltage is approximately equal to VIN plus VOUT*Np/Ns, where Np and Ns are the number of turns of the primary winding 111 and the secondary winding 116, respectively. That is, during time period Ton2, the power transistor 120 is turned off and the reaction from the secondary winding 116 causes the VCE to be overloaded and greater than VIN. The current in the rectifying diode 137 of the secondary winding 116 drops from a peak to zero. During time period Ton2, FB voltage 123 follows the power supply output and is approximately equal to VOUT, as shown in Figure 2-2.

In FIGS. 2-1 and 2-2, the second phase in the off state of the power transistor 120 is designated Tondis, at which time there is no current in the diode 137. There is also a ringing oscillating voltage in the 110 transformer due to the presence of inductance, parasitic capacitance, and resistance. The ringing oscillating voltage waveform is also present in the auxiliary winding 113 and the main winding 111, as indicated by the VCE signal in Figure 2-1 and the feedback signal in Figure 2-2.

The power transistor 120 remains off when the power supply output voltage VOUT reaches a predetermined desired threshold. As shown in Figures 2-1 and 2-2, Tondis indicates the duration of the system in discontinuous mode. When the power supply output voltage VOUT falls below a certain threshold, the pulse frequency modulation controller 150 turns on the power transistor 120 to charge the power source. In the pulse frequency modulation controller 150 shown in FIG. 1, the turn-on trigger signal 122 of the pulse frequency modulation controller 150 (assuming the high potential is active) may appear at any point of the ringing oscillating voltage waveform. When the turn-on trigger signal 122 becomes a high voltage or close to the peak of the ringing oscillating voltage waveform, as shown by the peaks 211, 212 of the ringing oscillating voltage waveform as shown in FIG. 2-1, the VCE voltage of the power transistor 120 is higher than the VIN during the turn-on transition. . Thus, the loss of the turn-on conversion is high. That is, more power is needed during the turn-on operation.

In some examples, there is no frequency jittering mechanism in conventional pulse frequency modulation controllers. Under this condition, if the first turn-on trigger signal becomes high at the peak position of the ringing oscillating voltage waveform, if the linearity and load conditions are not changed, the next turn-on trigger signal can also be changed at the peak position of the ringing oscillating voltage waveform. High potential. The duty cycle of two consecutive cycles is basically the same, as shown in Figure 2-1. Therefore, the power loss of the power-on switching is doubled.

According to an embodiment, the present invention reduces the turn-on switching loss by issuing an turn-on trigger signal substantially at the valley position of the ringing oscillating voltage waveform. In addition to reducing power loss, this solution introduces frequency jitter into the control pulses. In other words, by making the pulse transition substantially coincide with the valley of the ringing oscillating voltage waveform, random timing variations are introduced into the control pulse.

Since the pulse spectrum of the power supply system is very wide, frequency jitter is an effective way to suppress electromagnetic interference (EMI) of the switched power supply. In conventional circuits, the frequency jitter in the pulse frequency modulation controller is achieved by using an algorithm to perturb the output voltage of the error amplifier to achieve pseudo-random conditions under linear and load conditions ( Quasi random) frequency change. Frequency jitter in conventional pulse frequency modulation controllers has two major drawbacks: First, the frequency jitter value is pseudo-random because the algorithm is actually fixed. Second, the synthesized turn-on trigger signal may become high at the peak of the ringing oscillating voltage waveform, which means a larger turn-on switching loss.

According to an embodiment of the present invention, two major drawbacks of frequency jitter in a conventional pulse frequency modulation controller can be substantially eliminated by opening the power transistor in the valley of the ringing oscillating voltage waveform. In an embodiment, timing variations are introduced in the turn-on time. Timing changes can be random depending on the application and operating conditions. Thus, even if the linearity and load conditions remain the same, the pulse frequency can still be changed by the random timing variation.

In a particular embodiment of the present invention, turning on the power transistor in the valley of the ringing oscillating voltage waveform in a PFM controlled switched mode power supply can serve two purposes simultaneously. This mode randomly changes the switching frequency of the power transistor even if the load and linear conditions do not change. The pulse spectrum of the pulse frequency modulation controller is randomly expanded and electromagnetic interference is suppressed. In addition, the solution reduces the turn-on switching loss of the power transistors in the PFM controlled switched mode power supply. The power conversion efficiency of the PFM system is thus improved.

FIG. 3 is a simplified block diagram of a pulse frequency modulation controller 300 in accordance with an embodiment of the present invention. The drawings are only an example and are not intended to limit the scope of the claims. Other variations, changes, and variations will be apparent to those skilled in the art. As shown, pulse frequency modulation (PFM) controller 300 is used to provide control functionality in switched power supply system 100. For example, the pulse frequency modulation controller 300 can be used in the switched power supply system 100 shown in FIG. In this application, the pulse frequency modulation controller 300 can provide the functionality of the pulse frequency modulation controller 150 of FIG. In this embodiment, the pulse frequency modulation controller 300 is integrated in an integrated circuit chip. The controller of FIG. 1 has an output DRV for providing a control signal 122 to turn the current in the power transistor 120 of the power supply on or off. In this particular example, the power transistor 120 is a bipolar transistor (BJT), but other suitable power switching elements are also possible. The pulse frequency modulation controller 300 has an input FB for receiving a feedback signal 123 associated with an output voltage VOUT of the power supply.

As discussed above, the current in the power transistor 120 also exhibits a ringing waveform when the power transistor 120 is off. This current reflects the ringing voltage waveform of the VCE of the power transistor 120. The feedback signal 123 received at the FB terminal also exhibits a ringing voltage waveform when the current is turned off. As mentioned above, in a particular embodiment, the ringing voltage has a first oscillating frequency. The first oscillation frequency can be determined by observing the feedback signal or the waveform of the VCE signal.

In FIG. 3, the pulse frequency modulation controller 300 includes a control circuit including circuit blocks 310, 320, 330, and 350 for providing a control signal DRV for outputting power to the power output in response to the feedback signal FB. Voltage regulation. Here, the control signal DRV is set to turn on the current in the switch when the feedback signal is substantially in the valley of the ringing voltage waveform.

As shown in FIG. 3, the pulse frequency modulation controller 300 includes a circuit block 330 coupled to an output terminal DRV, the circuit block 330 being a driver circuit for providing control signals. The circuit block 330 can be in a first state or a second state, such as a high potential state and a low potential state. In a particular embodiment, the circuit block 330 provides a control signal DRV for turning on the circuitry on the power transistor 120 shown in FIG. 1 in the first state. In the second state, the circuit block 330 provides a control signal to turn off the current. In the particular embodiment illustrated in FIG. 3, the circuit block 330 includes a T flip-flop 331 that is switchable between two states. The T flip-flop 331 is turned to a high potential state at the rising leading edge of the clock input signal CK. At the rising leading edge of the latter clock input signal, the T flip-flop 331 is flipped to a low potential state. In addition, the T flip-flop 331 can be reset to a low state by the signal of the RESET terminal. As shown in FIG. 3, circuit block 330 also includes a register 334.

In FIG. 3, circuit block 310 is coupled to the FB input to receive a feedback signal and provide signal 318 to set the driver circuit to a first state in response to the feedback signal. In FIG. 3, circuit block 310 includes an error amplifier 314 and a comparator 316. The error amplifier 314 receives the sampled feedback signal through the FB terminal and a sampling circuit 312. The error amplifier 314 also receives the reference voltage V1. As shown, the error amplifier 314 produces an amplified voltage signal 315 that is the differential voltage between the sampled FB voltage and the reference voltage V1. Alternatively, a frequency jitter block (not shown) may be included to introduce a pseudo-random voltage to the voltage signal 315 of the error amplifier 314. Voltage signal 315 is input to the inverting input pin of comparator 316. A voltage ramp signal (or sawtooth signal) 317 is provided to the forward input pin of the comparator 316. When the voltage ramp signal 317 is equal to the voltage signal 315, the signal 318 of the comparator 316 switches to a high potential.

In a power supply such as that shown in Figure 1, the FB signal is related to the output voltage of the power supply. When the output voltage of the power supply is low, the FB signal is also low, and the comparator 316 generates a high potential at its output. The rising leading edge of the output signal of the comparator 316 will trigger the circuit block 330 (driver circuit) to output a high potential, thereby switching the power transistor 120 to the on state and causing the power supply to boost its output voltage. If the sampled FB voltage is high, the output of the comparator 316 takes longer to switch to a higher potential. Therefore, the interval between consecutive rising leading edges in the output signal of the comparator 316 changes in response to the feedback signal FB.

The pulse frequency modulation controller 300 also includes an input CS for detecting current in the power supply. Circuit block 320 provides a signal to turn off the control pulse in response to the current signal at the CS terminal. In the embodiment shown in FIG. 1, the CS terminal is coupled to a resistor 125, and the voltage at the CS terminal can be used to sense the current of the emitter of the power transistor 120. The circuit block 320 provides a signal 329 to set the circuit block 330 (driver circuit) to a second state (eg, a low potential state). As mentioned above, the low potential state of the circuit block 330 (driver circuit) provides a signal DRV to turn off the power transistor 120.

In particular, in FIG. 1, in the on state of the power transistor 120, the emitter current of the power transistor 120 is boosted. The CS voltage across resistor 125 is provided to comparator 322 in FIG. The comparator 322 generates a high output voltage to clear the T flip-flop 331 in the driver circuit block 330 when the CS voltage is equal to the predetermined voltage V2. Thereafter, the power transistor 120 is turned off. The output of the comparator 322 is coupled to the output of the protection circuit 323 to the inverse OR gate 324.

The controller 300 also includes a second circuit block 350 coupled to the first circuit block 310 and the driver circuit 330. Circuit block 350 adjusts the timing of signal 318 and provides signal 319 to the driver circuit. In accordance with an embodiment of the present invention, signal 319 is substantially provided to the circuit block 330 at the valley of the feedback signal FB, as will be described below in connection with FIG.

4 is a simplified block diagram of signal processing circuit 400 in accordance with an embodiment of the present invention. As shown, the signal processing circuit 400 has inputs IN1 and IN2 and an output OUT. In a particular application, the signal processing circuit 400 can be used as the circuit block 350 in the pulse frequency modulation controller 300 shown in FIG. For example, corresponding to FIG. 3, the input terminal IN1 can receive the feedback signal FB, the input terminal IN2 can receive the signal 318, and the output terminal OUT can provide the signal 319. The input signal FB appears as a waveform having peaks and troughs of known oscillation frequency. In the switched mode power supply system 100 of Figure 1, the waveform is the ringing voltage waveform of the feedback signal in the power supply. The signal 318 is characterized by a transition between the first state and the second state. The signal processing circuit 400 is operative to switch the output signal in response to the switching of the signal 318 between a third state and a fourth state, the timing of the switching being substantially the peak or valley of the feedback signal FB.

In FIG. 4, the signal processing circuit 400 includes a comparator 416 having an inverting input, a forward input, and an output. The inverting input receives an input signal FB that is coupled to a reference voltage V3. The output of the comparator 416 provides a signal A, which is high when FB is below V3.

The signal processing circuit 400 also includes an oscillator 417 and a plurality of gate lock circuits or flip flops (having a T flip-flop 419, D flip-flops 420, 421 as shown). The oscillator 417 has an input ENABLE and an output OUT connected to the output of the comparator 416 to receive the signal A. The oscillator 417 has an oscillation frequency approximately twice the oscillation frequency of the signal FB. The oscillator 417 also has a duty cycle of approximately 50%. In a particular embodiment, the oscillator 417 begins to oscillate with a low initial voltage and a 50% duty cycle when the input voltage is high.

The T flip-flop 419 has a clock input terminal CK, a set input terminal SET, and an output terminal Q. The clock input CK is coupled to an inverted signal of the output signal B of the oscillator 417, which is coupled to the output of the comparator 416 to receive the signal A. The D flip-flop 420 has a clock input terminal CK, a data register terminal D, a reset input terminal RESET, and an output terminal Q. The data register D of the D flip-flop 420 is coupled to the output of the T flip-flop 419. A reset input RESET is coupled to the output of comparator 416 to receive signal A. A clock input is coupled to the output of the oscillator to receive the oscillating signal B. The second D flip-flop 421 has a clock input terminal CK, a data register terminal D, a reset input terminal RESET, and an output terminal Q. The clock input CK is coupled to the output of the first D flip-flop 420 to receive the D signal. The data entry terminal D is coupled to the input IN of the signal processing circuit 400 to receive an external signal. In the embodiment shown in FIG. 3, the external signal can be signal 318. Additionally, the reset input RESET can be coupled to the start reset signal shown in FIG. The operation of the signal processing circuit 400 is described below in connection with FIG. 5 for the introduction of a pulse frequency modulation controller application.

FIG. 5 is a simplified block diagram illustrating waveforms of different signals in the signal processing circuit 400 in accordance with an embodiment of the present invention. As shown in FIG. 5, the comparator output voltage A is high every time when the ringing voltage of the FB is lower than the reference voltage V3 (for example, 0.1 V). Signal A causes oscillator 417 to oscillate from low to high with a 50% duty cycle. Here, the rising leading edge of the oscillator output signal B is used to identify the valley of the ringing oscillating voltage waveform of FB. In one embodiment, the oscillator's start-up time is synchronized with the FB voltage based on the time at which the ringing oscillating voltage is one cycle across the ground voltage potential. Therefore, the turn-on trigger of the power transistor 120 occurs substantially in the valley of the ringing oscillation waveform. As shown in FIG. 5, when the ringing signal FB is attenuated to an amplitude smaller than V3, the signal A remains at a high potential, and the oscillator output B continues to oscillate.

In a particular embodiment, inverter 418 causes the clock inputs of flip flops 419 and 420 to have a phase shift of 180 degrees. Flip-flop 419 is a T-flip whose SET pin is coupled to the output of comparator 416. The falling edge of the output signal of the oscillator 417 triggers the T flip-flop 419. The output Q of the flip flop 419 (signal C in Fig. 5) is connected to the data register side of the flip flop 420. Flip-flop 420 is a D flip-flop whose RESET pin is coupled to the output of comparator 416. The rising edge of the output of oscillator 417 triggers the D flip-flop. The output Q of flip flop 420 (signal D in Figure 5) is coupled to the clock input of flip flop 421. In one embodiment, flip-flop 421 is a D flip-flop whose RESET pin is coupled to the start reset signal of the pulse frequency modulation controller. When the PFM system is turned on, the initial value of the output Q of the flip-flop 421 is low.

In a particular embodiment, the flip flops 419 and 420 act as frequency dividers. As shown in FIG. 5, the waveforms of the signals C and D have a frequency of half of the signal B. Furthermore, the rising leading edge of signal D is substantially aligned with the valley point of the ringing waveform FB. As discussed below, signal D is used to adjust the timing of inputting the signal 318.

As shown in FIG. 5, the rising leading edge of the signal 319 outputted at the OUT terminal is delayed to substantially align the rising leading edge of the signal D, which is aligned with the valley point of the ringing waveform FB. It is noted that the amplitude of the ringing waveform FB in Figure 5 is shown as decreasing to represent different features of the waveform. In the application of the pulse frequency modulation controller 300, the signal 319 at the OUT terminal can be provided when the FB signal still appears to be ringing. Figure 6 shows an example in which the rising leading edge of signal 319 (in dashed circle a) is substantially aligned with the valley of the FB waveform (in dashed circle b).

In Figures 5 and 6, signal 319 is shown as having a rising leading edge that is substantially aligned with the valley of input signal FB. However, the particular embodiment of the present invention shown in Figure 4 can be used in other applications. For example, the rising leading or trailing edge of the output signal can be substantially aligned with the peak or valley of the input signal waveform. Of course, those skilled in the art will recognize other variations, variations, or alterations.

Figure 7 is a simplified voltage waveform diagram of a particular circuit node in the power supply of the embodiment of Figure 1. The drawings are only an example and are not intended to limit the scope of the claims. Other variations, changes, and variations will be apparent to those skilled in the art. As shown, VCE is the collector-emitter voltage of power transistor 120 and FB is feedback signal 123. Both VCE and FB are related to the current in the power supply. As shown in FIG. 7, when the transistor 120 is turned on, the pulse frequency modulation controller provides a control pulse 721, which becomes a low potential, as shown by pulses 701, 702, 703, 704. When the transistor 120 is turned off, the VCE start ringing waveform gradually approaches VIN. It can be seen that the starting point of the control pulses, such as pulses 702, 703, 704, is substantially aligned with the valley points of the VCE ringing waveform. The valley points 712, 713, 714 of the VCE ringing waveform are seen in FIG. Similarly, in FIG. 7, the FB waveform also shows that the timing of the control pulses 722, 723, 724 are valley points 732, 733, 734 that are substantially aligned with the FB ringing waveform, respectively.

As shown in FIG. 7, by adjusting the timing of the control pulse for turning on the power transistor 120, the VCE voltage at the turn-on timing of the transistor is lowered. Therefore, the conversion power consumption of the power supply is reduced. Furthermore, by adjusting the timing of the control pulses such that they align with the valley points of the ringing waveform, additional frequency jitter is introduced into the power supply. Thereby, electromagnetic interference (EMI) is attenuated. The above embodiments are provided to those skilled in the art to implement or use the present invention, and those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept. The scope of protection of the present invention is not limited by the above embodiments, but should be the maximum range of the innovative features mentioned in the claims.

<p>100. . . Switched power system</p><p>101. . . Bridge</p><p>102. . . capacitance</p><p>110. . . transformer</p><p>111. . . Coil</p><p>113. . . Auxiliary winding</p><p>114. . . Auxiliary winding</p><p>116. . . Secondary winding</p><p>120. . . Power transistor</p><p>122. . . control signal</p><p>123. . . Feedback signal</p><p>125. . . resistance</p><p>131. . . capacitance</p><p>133. . . Dipole</p><p>135. . . capacitance</p><p>137. . . Dipole</p><p>150. . . Pulse frequency modulation controller</p><p>211, 212. . . crest</p><p>300. . . Pulse frequency modulation controller</p><p>310, 320, 330, 350. . . Circuit block</p><p>312. . . Sampling circuit</p><p>314. . . Error amplifier</p><p>315. . . Voltage signal</p><p>316. . . Comparators</p><p>317. . . Voltage ramp signal</p><p>318. . . signal</p><p>319. . . signal</p><p>322. . . Comparators</p><p>323. . . Output and protection circuit</p><p>324. . . Reverse or gate</p><p>329. . . signal</p><p>331. . . T trigger</p><p>334. . . Register</p><p>400. . . Signal processing circuit</p><p>416. . . Comparators</p><p>417. . . Oscillator</p><p>418. . . Inverter</p><p>419. . . T trigger</p><p>420. . . D flip-flop</p><p>421. . . trigger</p><p>701, 702, 703, 704. . . pulse</p><p>712, 713, 714. . . Wave point</p><p>721, 722, 723, 724. . . Control pulse</p><p>732, 733, 734. . . Wave point</p>

1 is a simplified block diagram of a switched power supply system using pulse frequency modulation (PFM) control, in accordance with an embodiment of the present invention.

Figure 2-1 is a simplified waveform diagram showing the change in power transistor voltage VCE for a constant linear load condition using a conventional pulse frequency modulation controller.

Figure 2-2 is a simplified waveform diagram showing the change in feedback voltage of a power supply using a conventional pulse frequency modulation controller under constant linear load conditions.

3 is a simplified block diagram of a pulse frequency modulation controller in accordance with an embodiment of the present invention.

4 is a simplified block diagram of a signal processing circuit in accordance with an embodiment of the present invention.

5 is a simplified block diagram illustrating waveforms of different signals in a signal processing circuit in accordance with an embodiment of the present invention.

6 is a simplified block diagram illustrating waveforms of different signals in a signal processing circuit in accordance with another embodiment of the present invention.

Figure 7 is a simplified voltage waveform diagram of a particular circuit node in the power supply of the embodiment of Figure 1.