Current mirror and light emitting device with the current mirror
Abstract
This invention provides current mirrors. There are an input current and an output current flowing through a first and second transistor, respectively. The ratio of the input and output current is 1:N. The first and second transistors have equal VGS. With a first and second operational amplifier and a control circuit, VDS of the first and second transistors are set to a control voltage. With a proper control voltage, the first and second transistors can operate in a triode region. In contrast to conventional current mirror, the current mirror of the invention provides larger output current and larger cross voltage for a load. The transistors of the invention can be operated at larger VGS.

Term
No projected expiry on record.
- Priority and filed
- Granted
- Today
12 claims: 12 independent, 0 dependent
- 1A current mirror includes:an input stage circuit including a first transistor, and the current flowing through the first transistor is an input current;an output stage circuit includes a second transistor, the second transistor Has the same gate-source voltage as the first transistor, and the current flowing through the second transistor is an output current, and there is a fixed ratio between the output current and the input current;a first operational amplifier, according to the The drain-source voltage of the first transistor and the second transistor generate an output signal;a control circuit adjusts the drain-source voltage of the second transistor according to the output signal, so that the first transistor and the second transistor The drain-source voltage of the transistor is equal;and a second operational amplifier controls the first transistor according to a control voltage and the drain-source voltage of the first transistor, so that the drain-source voltage of the first transistor is equal to The control voltage;wherein the first and second transistors can be operated in a triode region by setting the control voltage. Μ3〇38^2θ610 號申請專利範圍修正本 修正日期:95.10.12 九、申請專利範圍: 1. 一種電流鏡,其中包括: 一輸入級電路,包括一第一電晶體,流經該第一電晶體之 - 電流為一輸入電流; . 一輸出級電路,包括一第二電晶體,該第二電晶體與該第 一電晶體具有相同的閘源極電壓’流經該弟二電晶體之電流為 一輸出電流,該輸出電流與該輸入電流之間具有一固定比値; 一第一運算放大器,根據該第一電晶體與該第二電晶體之 鲁汲源極電壓產生一輸出信號; 一控制電路,根據該輸出信號調整該第二電晶體之汲源極 電壓,使該第一電晶體與該第二電晶體之汲源極電壓相等;以 及 一第二運算放大器,根據一控制電壓以及該第一電晶體之 汲源極電壓控制該第一電晶體,使該第一電晶體之汲源極電壓 等於該控制電壓; 其中,藉由設定該控制電壓,可將該第一與第二電晶體操 作在二極體區。 2. 如申請專利範圍第1項所述之電流鏡,其中該控制電路 包括一第三電晶體,該第三電晶體之閘極耦接該第一運算放大 器之輸出端、源極I禺接該第一運算放大器之反相輸入端與該第 二電晶體之汲極,該第三電晶體之汲極為該電流鏡之負載端, 該負載端可柄接一負載’流經該負載的電流即該輸出電流。 3. 如申請專利範圍第1項所述之電流鏡,其中該第一電晶 體之閘極耦接該第二運算放大器之輸出端、汲極耦接該第二運 0119-A21604TWF1(N2);Princeton9507;glorious_tien 12 M302832 算放大器之非反向輸入端。 4. 如申請專利範圍第1項所述之電流鏡,其中該固定比値 可藉由調整該第一電晶體與該第二電晶體之通道區域寬長比 . 來決定。 5. 如申請專利範圍第1項所述之電流鏡,上述電晶體皆為 ' NMOS電晶體。 6. 如申請專利範圍第1項所述之電流鏡,上述電晶體皆為 PMOS電晶體。 φ 7.—種發光裝置,其中包括: 複數個發光二極體;以及 一電流鏡,其中包括: 一輸入級電路,包括一第一電晶體,流經該第一電晶體之 電流為一輸入電流; 一輸出級電路,包括一第二電晶體,該第二電晶體與該第 一電晶體具有相同的閘源極電壓,流經該第二電晶體之電流為 一輸出電流,該輸出電流與該輸入電流之間具有一固定比値; • 一第一運算放大器,根據該第一電晶體與該第二電晶體之 没源極電壓產生一輸出信號; 一控制電路,根據該輸出信號調整該第二電晶體之汲源極 電壓,使該第一電晶體與該第二電晶體之汲源極電壓相等,該 控制電路具有一負載端耦接該等發光二極體並且提供該輸出 . 電流給該等發光二極體;以及 一第二運算放大器,根據一控制電壓以及該第一電晶體之 汲源極電壓控制該第一電晶體,使該第一電晶體之汲源極電壓 等於該控制電壓; 0119-A21604TWF1 (N2);Princeton9507;glorious_tien 13 M302832 其中,藉由設定該控制電壓,可將該第一與第二電晶體操 作在二極體區。 8.如申請專利範圍第7項所述之發光裝置,其中該控制電 _ 路包括一第三電晶體,該第三電晶體之閘極耦接該第一運算放 . 大器之輸出端,該第三電晶體之源極耦接該第一運算放大器之 • 反相輸入端與該第二電晶體之汲極、汲極即該負載端。 * 9.如申請專利範圍第7項所述之發光裝置,其中該第一電 晶體之閘極耦接該第二運算放大器之輸出端、汲極耦接該第二 春運算放大器之非反向輸入端。 10.如申請專利範圍第7項所述之發光裝置,其中該固定比 値可藉由調整該第一電晶體與該第二電晶體之通道區域寬長 比來決定。 ^ 11.如申請專利範圍第7項所述之發光裝置,上述電晶體皆 為NMOS電晶體。 12.如申請專利範圍第7項所述之發光裝置,上述電晶體皆 為PMOS電晶體。 0119-A21604TWF1(N2);Princeton9507;glorious_tien 14 M302832 七、指定代表圖: (一) 本案指定代表圖為:第(3 )圖。 (二) 本代表圖之元件符號簡單說明: 300〜電流鏡; 302〜輸入級電路; 304〜輸出級電路; 306〜第一運算放大器; 308〜控制電路; 310〜第二運算放大器; 312〜輸出信號; I〜輸入電流; 輸出電流; Vc〜控制電壓; Mnl〜第一 NMOS電晶體; Mn2〜第二NMOS電晶體; Mn3〜第三NMOS電晶體; Vdd〜電源; VdSI、Vj)S2〜〉及源極電壓, Vgs〜閘源極電壓。 一種電流鏡,其中包括:一輸入級電路,包括一第一電晶體,流經該第一電晶體之電流為一輸入電流;一輸出級電路,包括一第二電晶體,該第二電晶體與該第一電晶體具有相同的閘源極電壓,流經該第二電晶體之電流為一輸出電流,該輸出電流與該輸入電流之間具有一固定比值;一第一運算放大器,根據該第一電晶體與該第二電晶體之汲源極電壓產生一輸出信號;一控制電路,根據該輸出信號調整該第二電晶體之汲源極電壓,使該第一電晶體與該第二電晶體之汲源極電壓相等;以及一第二運算放大器,根據一控制電壓以及該第一電晶體之汲源極電壓控制該第一電晶體,使該第一電晶體之汲源極電壓等於該控制電壓;其中,藉由設定該控制電壓,可將該第一與第二電晶體操作在三極體區。 0119-A21604TWF1(N2);Princeton9507;glorious_tien 4
- 2The current mirror according to item 1 of the patent application scope, wherein the control circuit includes a third transistor, the gate of the third transistor is coupled to the output terminal of the first operational amplifier, and the source is coupled to the first transistor. The inverting input of the operational amplifier and the drain of the second transistor, and the drain of the third transistor is the load of the current mirror. The load can be coupled to a load, and the current flowing through the load is the output. Current. 如申請專利範圍第1項所述之電流鏡,其中該控制電路包括一第三電晶體,該第三電晶體之閘極耦接該第一運算放大器之輸出端、源極耦接該第一運算放大器之反相輸入端與該第二電晶體之汲極,該第三電晶體之汲極為該電流鏡之負載端,該負載端可耦接一負載,流經該負載的電流即該輸出電流。
- 3The current mirror according to item 1 of the scope of patent application, wherein the gate of the first transistor is coupled to the output of the second operational amplifier, and the drain is coupled to the non-inverting input of the second operational amplifier. 如申請專利範圍第1項所述之電流鏡,其中該第一電晶體之閘極耦接該第二運算放大器之輸出端、汲極耦接該第二運算放大器之非反向輸入端。
- 4The current mirror according to item 1 of the scope of patent application, wherein the fixed ratio can be determined by adjusting a width-to-length ratio of a channel region of the first transistor and the second transistor. 如申請專利範圍第1項所述之電流鏡,其中該固定比值可藉由調整該第一電晶體與該第二電晶體之通道區域寬長比來決定。
- 5According to the current mirror described in the first item of the patent application scope, the above transistors are all NMOS transistors. 如申請專利範圍第1項所述之電流鏡,上述電晶體皆為NMOS電晶體。
- 6According to the current mirror described in the first item of the patent application scope, the above transistors are all PMOS transistors. 如申請專利範圍第1項所述之電流鏡,上述電晶體皆為PMOS電晶體。
- 7A light-emitting device includes:a plurality of light-emitting diodes;and a current mirror, including: an input stage circuit including a first transistor, and a current flowing through the first transistor is an input current;an output A stage circuit includes a second transistor having the same gate-source voltage as the first transistor, and the current flowing through the second transistor is an output current, and the output current and the input current There is a fixed ratio between them;a first operational amplifier generates an output signal according to the drain-source voltage of the first transistor and the second transistor;a control circuit adjusts the voltage of the second transistor according to the output signal Sink source voltage to make the drain voltage of the first transistor equal to that of the second transistor. The control circuit has a load terminal coupled to the light emitting diodes and provides the output current to the light emitting diodes. And a second operational amplifier, which controls the first transistor according to a control voltage and a drain-source voltage of the first transistor, so that the drain-source voltage of the first transistor is equal to the control transistor ;Wherein, by setting the control voltage, the first transistor and the second operation in the triode region. 一種發光裝置,其中包括:複數個發光二極體;以及一電流鏡,其中包括:一輸入級電路,包括一第一電晶體,流經該第一電晶體之電流為一輸入電流;一輸出級電路,包括一第二電晶體,該第二電晶體與該第一電晶體具有相同的閘源極電壓,流經該第二電晶體之電流為一輸出電流,該輸出電流與該輸入電流之間具有一固定比值;一第一運算放大器,根據該第一電晶體與該第二電晶體之汲源極電壓產生一輸出信號;一控制電路,根據該輸出信號調整該第二電晶體之汲源極電壓,使該第一電晶體與該第二電晶體之汲源極電壓相等,該控制電路具有一負載端耦接該等發光二極體並且提供該輸出電流給該等發光二極體;以及一第二運算放大器,根據一控制電壓以及該第一電晶體之汲源極電壓控制該第一電晶體,使該第一電晶體之汲源極電壓等於該控制電壓;其中,藉由設定該控制電壓,可將該第一與第二電晶體操作在三極體區。
- 8The light-emitting device according to item 7 of the scope of patent application, wherein the control circuit includes a third transistor, and a gate of the third transistor is coupled to an output terminal of the first operational amplifier and a source of the third transistor. A terminal is coupled to the inverting input terminal of the first operational amplifier and the drain terminal of the second transistor, and the drain terminal is the load terminal. 如申請專利範圍第7項所述之發光裝置,其中該控制電路包括一第三電晶體,該第三電晶體之閘極耦接該第一運算放大器之輸出端,該第三電晶體之源極耦接該第一運算放大器之反相輸入端與該第二電晶體之汲極、汲極即該負載端。
- 9The light-emitting device according to item 7 of the scope of patent application, wherein a gate of the first transistor is coupled to an output terminal of the second operational amplifier, and a drain is coupled to a non-inverting input terminal of the second operational amplifier. 如申請專利範圍第7項所述之發光裝置,其中該第一電晶體之閘極耦接該第二運算放大器之輸出端、汲極耦接該第二運算放大器之非反向輸入端。
- 10The light-emitting device according to item 7 of the scope of patent application, wherein the fixed ratio can be determined by adjusting a width-to-length ratio of a channel region of the first transistor and the second transistor. 如申請專利範圍第7項所述之發光裝置,其中該固定比值可藉由調整該第一電晶體與該第二電晶體之通道區域寬長比來決定。
- 11According to the light-emitting device described in item 7 of the scope of patent application, the transistors are all NMOS transistors. 如申請專利範圍第7項所述之發光裝置,上述電晶體皆為NMOS電晶體。
- 12According to the light-emitting device described in item 7 of the patent application scope, the transistors are all PMOS transistors. 如申請專利範圍第7項所述之發光裝置,上述電晶體皆為PMOS電晶體。
Independent claims12
16 paragraphs, as filed
Current mirror and light emitting device using the same
This creation relates to a current mirror, and particularly to a current mirror that provides a large current.
Figure 1 shows the drain-source voltage V of an n-type metal-oxide-semiconductor (NMOS) transistor.<sub>DS</sub>Gate source voltage V<sub>GS</sub>, And drain current i<sub>D</sub>The relationship between. V<sub>t</sub>Is the threshold voltage of the NMOS transistor. When V<sub>DS</sub><V<sub>GS</sub>-V<sub>t</sub>When the NMOS transistor is located in a triode region,<img file="TWM302832U_D0001.tif" />. When V<sub>DS</sub>> V<sub>GS</sub>-V<sub>t</sub>When the NMOS transistor is in a saturation region,<img file="TWM302832U_D0002.tif" />. According to the above formula, the gate-source voltage V<sub>GS</sub>The larger the drain current i<sub>D</sub>Bigger.
FIG. 2 is a conventional current mirror 200 including two NMOS transistors 202 and 204. Transistors 202 and 204 have the same gate-source voltage V<sub>GS</sub>, The channel area width-to-length (W / L) ratio is 1: N, and has the same μ<sub>n</sub>, C<sub>ox</sub>. The drain and the gate of the transistor 202 are connected together, so the transistor 202 operates in a saturation region. To make the load current 206<sub>L</sub>N times the drain current of transistor 202 (I<sub>L</sub>= NI), the transistor 204 must also operate in the saturation region. Drain-source voltage V of transistor 204<sub>DS</sub>It should not be too large, so as not to limit the pressure drop that the load 206 can use. Refer to Figure 1 for low V<sub>DS</sub>Operating in the saturation region, the gate-source voltage V<sub>GS</sub>Must be very low, at which time the current value will be small. Therefore, in the conventional current mirror 200, in order to provide a large current to the load 206, the demand for providing a large current to the load can only be achieved by increasing the size of the transistor 204 (increase N), but this method does not meet the current reduction Wafer volume trends. Therefore, we need a new current mirror that can provide a large current without using an excessively large transistor size and maintain the usable range of the voltage drop of the load.
This creation provides a current mirror that provides a large current without the need for an excessively large transistor size and maintains a usable range of load voltage drop. The current mirror includes an input stage circuit, an output stage circuit, a first operational amplifier, a control circuit, and a second operational amplifier. The input stage circuit includes a first transistor. The current flowing through the first transistor is an input current. The output stage circuit includes a second transistor. The second transistor has the same gate-source voltage as the first transistor. The current flowing through the second transistor is an output current. There is a fixed ratio between the output current and the input current. The first operational amplifier generates an output signal according to the drain-source voltage of the first transistor and the second transistor. According to the output signal, the control circuit adjusts the drain-source voltage of the second transistor so that the drain-source voltage of the first transistor and the second transistor are equal. According to a control voltage and a drain-source voltage of the first transistor, the second operational amplifier controls the first transistor so that the drain-source voltage of the first transistor is equal to the control voltage. The first and second transistors can be operated in the triode region by setting the control voltage.
The control circuit includes a third transistor. The gate of the third transistor is coupled to the output of the first operational amplifier, and the source is coupled to the inverting input of the first operational amplifier and the drain and drain of the second transistor. end. The load terminal can be coupled to a load. The current flowing through the load is the output current. The gate of the first transistor is coupled to the output terminal of the second operational amplifier, and the drain is coupled to the non-inverting input terminal of the second operational amplifier. The fixed ratio can be determined by adjusting the width-to-length ratio of the channel region of the first transistor and the second transistor. The transistors may be all NMOS transistors or all PMOS transistors.
The load may also be a plurality of light emitting diodes connected in series. Since the second transistor can be operated in the triode region, the drain voltage drop of the second transistor is sufficiently small, and the load end of the current mirror can be connected in series with more light-emitting diodes.
FIG. 3 is a current mirror 300 provided in this application, which includes an input stage circuit 302, an output stage circuit 304, a first operational amplifier 306, a control circuit 308, and a second operational amplifier 310. The input stage circuit 302 includes a first NMOS transistor M<sub>n1</sub>. Flow through the first NMOS transistor M<sub>n1</sub>The current is an input current I. Output stage circuit 304 includes a second NMOS transistor M<sub>n2</sub>. While flowing through the second transistor M<sub>n2</sub>The current is an output current I<sub>L</sub>. Among them, the output current I<sub>L</sub>There is a fixed ratio N to the input current I. First NMOS transistor M<sub>n1</sub>The gate is coupled to the output terminal of the second operational amplifier 310, and the drain is coupled to the non-inverting input terminal of the second operational amplifier 310. First NMOS transistor M<sub>n1</sub>With the second NMOS transistor M<sub>n2</sub>Have the same gate-source voltage V<sub>GS</sub>, And has a channel length aspect ratio of 1: N. According to the first and second NMOS transistors M<sub>n1</sub>With M<sub>n2</sub>Drain-source voltage V<sub>DS1</sub>With V<sub>DS2</sub>The first operational amplifier 306 generates an output signal 312. The control circuit 308 adjusts the second NMOS transistor M according to the output signal 312<sub>n2</sub>Drain-source voltage V<sub>DS2</sub>To make the first and second NMOS transistors M<sub>n1</sub>With M<sub>n2</sub>Drain-source voltage V<sub>DS1</sub>With V<sub>DS2</sub>equal. In FIG. 3, the control circuit 308 includes a third NMOS transistor M<sub>n3</sub>. Third NMOS transistor M<sub>n3</sub>The gate is coupled to the output of the first operational amplifier 306, the source is coupled to the inverting input of the first operational amplifier 306 and the second transistor M<sub>n2</sub>The drain terminal and the drain terminal are the load terminals of the current mirror 300. The load terminal can be coupled to a load 314. The current flowing through the load 314 is the output current I<sub>L</sub>. According to a control voltage V<sub>c</sub>And the first NMOS transistor M<sub>n1</sub>Drain-source voltage V<sub>DS1</sub>The second operational amplifier 310 controls the first NMOS transistor M<sub>n1</sub>To make the first NMOS transistor M<sub>n1</sub>Drain-source voltage V<sub>DS1</sub>Equal to the control voltage V<sub>c</sub>。
Since the current mirror 300 will be V<sub>DS1</sub>With V<sub>DS2</sub>Are controlled at the control voltage V<sub>c</sub>And the first and second transistors M<sub>n1</sub>With M<sub>n2</sub>Have the same gate-source voltage V<sub>GS</sub>, So by adjusting the control voltage V<sub>c</sub>, The first and second transistors M<sub>n1</sub>With M<sub>n2</sub>Operates in the triode region, where<maths><img file="TWM302832U_D0003.tif" /></maths>
Control voltage at this time V<sub>c</sub>It is small, so the load 314 has a large usable voltage drop. And the first and second transistors M<sub>n1</sub>With M<sub>n2</sub>Gate source voltage V<sub>GS</sub>It is not necessary to be limited to a low voltage value like the conventional current mirror 200, so when the input current I is large, the first and second transistors M<sub>n1</sub>With M<sub>n2</sub>Will automatically increase the gate-source voltage V<sub>GS</sub>Without the need to expand the transistor size. Therefore, the current mirror 300 can provide a large current to the load 314 with an appropriate transistor size, and the load 314 can have a sufficient voltage drop.
The current mirror 400 in FIG. 4 is another embodiment of the present invention. The transistors used therein are all PMOS transistors. The remaining technical features are the same as those of the current mirror 300.
FIG. 5 is a light emitting device 500, which is an embodiment of the present invention. The light-emitting device 500 includes a current mirror 300 shown in FIG. 3 and a load 502. The load 502 is formed by connecting a plurality of light emitting diodes (LEDs) in series. Since the voltage of the load terminal 504 of the current mirror 300 is very low, a plurality of light emitting diodes can be connected in series. The current mirror 400 can also be used to implement the light-emitting device proposed in this creation.
A chip usually has a plurality of output stage circuits coupled to the same input stage circuit. If the distance between the output stage circuit and the input stage circuit is too far, a gradient effect will occur. In this case, the gate-source voltage of the transistor of the output stage and the input stage will have an error and cannot be exactly equal. The transistor provided in this work can be operated at a large gate-source voltage without increasing the size of the transistor. Compared to the traditional current mirror 200, the gradient effect is greatly improved in the current mirror of this work. In addition, the error of the output current of each output stage will be smaller.
The above implementations are only used to help understand this creation, not to limit the scope of this creation. Any product or technology developed based on the scope of the patent application for this creation belongs to the scope of protection of this specification.
<p>200 traditional current mirror</p><p>202,204NMOS transistor</p><p>206Load</p><p>300Current Mirror</p><p>302input stage circuit</p><p>304Output stage circuit</p><p>306The first operational amplifier</p><p>308Control circuit</p><p>310Second Operational Amplifier</p><p>312output signal</p><p>400current mirror</p><p>502, 314 load</p><p>504Load side</p><p>IInput current</p><p>I<sub>L</sub>Output current</p><p>V<sub>c</sub>Control voltage</p><p>M<sub>n1</sub>, M<sub>n2</sub>, M<sub>n3</sub>The first, second and third NMOS transistors</p><p>V<sub>DD</sub>power supply</p><p>V<sub>DS1</sub>, V<sub>DS2</sub>Drain source voltage</p><p>V<sub>GS</sub> Gate-source voltage</p>
Figure 1 shows the drain-source voltage V of an n-type metal-oxide-semiconductor (NMOS) transistor.<sub>DS</sub>Gate source voltage V<sub>GS</sub>, And drain current i<sub>D</sub>Figure 2 is a traditional current mirror; Figure 3 is an embodiment of the current mirror of the creation; Figure 4 is another embodiment of the current mirror of the creation; An embodiment of a light emitting device.
5 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| TWI460990B | Cited by | Taiwan Province of China | Examiner |
| US8786359B2 | Cited by | United States of America | Applicant |
4 members in 3 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 95209610 | Taiwan Province of China | U | |
| TW20060209610U | – | – | – |
Members4
| Document | Office | Kind | |
|---|---|---|---|
| TWM302832UThis record | Taiwan Province of China | U | |
| JP3135667U | Japan | U | |
| US2008042741A1 | United States of America | A1 | |
| US7463082B2 | United States of America | B2 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Annulment or lapse of a utility model due to non-payment of feesLapsedMM4K | MM4K |
Numbers
- Publication
- M302832
- Publication, DOCDB
- M302832
- Publication, EPODOC
- TWM302832U
- Application
- 95209610
- Application, DOCDB
- 95209610
- Application, EPODOC
- TW20060209610U
Titles2
- English
- Current mirror and light emitting device with the current mirror
- Chinese
- ????????????????
Classification
- CPC, 1
- G05F3/262