User equipment calculating CDMA system transmission matrix coefficient

User equipment for calculating CDMA system transmission matrix coefficients

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This creation is about wireless digital communication systems. In particular, this creation is about the response matrix used to generate such a system.

In a code division multiple access communication system, multiple users simultaneously transmit multiple communications. This multiple communication system uses different channel codes for transmission. The channel code used in the time-sharing duplex mode of 3GPP is obtained by combining a spreading code and a scrambling code, and then applying a channel code specific multiplier. During transmission, each transmission experiences a channel response. One method of recovering data from transmitted bursts is joint detection, in which all data are received at the same time. Such a system is shown in Figure 1. This joint detection receiver may be used in a user equipment or base station.

These multiple communications 10 are received as a combined reception signal at the antenna 22 or the antenna array after experiencing the channel response. The received signal is reduced to the fundamental frequency by, for example, the demodulator 24, and the chip rate of the code or the chip rate of the multiple codes is reduced by the analog-to-digital converter (ADC) 26 or multiple analog-to-digital bits. The converter ADCs samples to generate a receiving matrix r. The channel evaluation device 28 uses a reference signal, such as a midamble code or pilot code, to evaluate the channel response of the communication 20. The joint detector 30 uses the estimated or known spreading code sent by the user and the estimated or known channel response to evaluate the original transmission data of all users as a data vector d.

This joint detection problem is generally represented by Formula 1.<maths><img file="TWM240734U_D0001.tif" /></maths>d is the transmitted data vector, r is the received vector, n is the additional white guassian noise (AWGN), A is the system response matrix, and the channel response is convolved with the known channel code. Become.

Two methods for solving Formula 1 include a zero forcing (ZF) and a minimum mean square error (MMSE) method. A ZF solution, where n is approximately 0, is obtained by formula 2.<maths><img file="TWM240734U_D0002.tif" /></maths>

The MMSE method is obtained by programs 3 and 4.<maths><img file="TWM240734U_D0003.tif" /></maths><maths><img file="TWM240734U_D0004.tif" /></maths>σ²Is the variance of the noise, and I is the identity matrix.

For zero forcing or MMSE method, derive the Hermetian (hermetian) A of the system response matrix^H. In TDD proposed by 3GPP, the system response matrix uses spreading code, scrambling code, and the multiplier of the channel specific code to And the determined channel is derived in response. The real spreading code is mixed with a complex scrambling code. The result of this mixing is multiplied by a channel code specific multiplier (hereinafter referred to as the real part or the imaginary part), and the result is convolved with the complex channel response. After the system response is derived, get Hermetian to produce A^Hmatrix. Produces A^HMatrix is a complex operation process that requires complex multipliers. It is undesirable to implement the multiplication function in hardware (such as an integrated circuit), because generating a multiplier requires a large number of transistors to complete.

Therefore, it is desirable to have another method to generate the hermetian of the system response matrix.

Comprehensive description

A user equipment receives a plurality of data signals in a code division multiple access format. The user equipment includes an antenna, an analog-to-digital converter, a channel evaluation device and a joint detection device. The joint detection device has a mutual exclusion or gate for generating channel codes. The mutex or gate has an input for receiving a real spreading code, a complex scrambling code, and a symbol of a channel code specific multiplier. The channel code specific multiplier has a real value and an imaginary value. A circuit has an input for receiving the channel code and channel evaluation and generating a hermetian of the system response matrix.

Description of the preferred embodiment

Although the preferred embodiment combines the use of the third generation partnership project (3GPP) The invention of time-sharing duplex communication system of code multiple access is used for description. This creation can be applied to any code multiple access communication system. The receiver using the following embodiment can be used in user equipment or base station.

In the preferred embodiment of the present invention, it is best to mix specific receiving bursts, spreading codes, scrambling codes, and channel code specific multiplier symbols by a mutual exclusion or gate to generate an approximate channel code. This approximate channel code and channel response are convoluted to generate a pair A^HApproximate matrix B^HContribution. The real and imaginary parts of the channel code specific multiplier are applied to the pair B^HThe real part and the imaginary part of the matrix's approximate contribution to generate a^HThe bursting contribution of the matrix.

2A and 2B, which show circuits 100 and 200 that perform a series of real and imaginary channel response matrix values and approximate channel codes, respectively. The channel response value is divided into a real CRR and an imaginary CRI. The real channel response CRR is processed by the circuit 100, and the virtual channel response CRI is performed in the circuit 200 serially.

In FIG. 2A, the register RR is preferably a 16-position shift register that receives the real part of the channel response CRR. Each position Ci (i=0 to 15) of the register RR has F bits in each position, where F is the size of the selected data bit, preferably 10. The number of positions corresponding to the better channel code size is 16 in the TDD mode of 3GPP, and the better power number is 2. The real circuit 100 includes a complex number of elements A1-A14, and each element has an adder with two inputs and a single output which is the sum of the two inputs. The better situation of the adder/subtractor components A1-A8 is as shown in Figure 4. Adder elements A9-A14 are simple adders in the better case.

The adder/subtractor components A1, A2, A3, A4 receive the odd position input from the register RR and perform addition or subtraction on the two inputs. Similarly, the adder/subtractor A5, A6, A7, A8 are coupled to the register RR to perform the addition and subtraction of the channel response value, but only in the even register R_RExecuted on. Overall, the adder elements A1-A4, A9-A11 form an adder tree with inputs defined by the elements A1-A4 and outputs defined by the element A11. Similarly, the adder elements A5-A8, A12-A14 form a second adder tree circuit. The correlation between the adder tree circuit and the register RR is through the register R_RThe real part and the imaginary part of the processed value of the processed CRR value are calculated.

A control signal is driven, and the channel code CC with bits CC0 to CC15 is input to the adder/subtractor elements A1 to A8. This binary channel code controls whether the adders A1-A8 perform an addition or a subtraction, depending on the individual control bits. When the channel code CC bit = 0, it is best to add. When the channel code CC bit = 1 The best way is to subtract.

FIG. 4 shows a preferred structure of the input adder element A1 with an adder A1' and two 2's complement devices TC1, TC2. The input CRR1 and CRR3 receive the real channel response values contained in the second and fourth positions C1, C3 of the register RR and processed by the 2's complement device TC1, TC2. The addition or subtraction of the CCR value is made by adding the output of the 2's complement device TC1, TC2 by the adder A1'. The 2's complement device TC1, TC2 operates on the input value by passing this value or its 2's complement through the adder A1'. The second bit CC1 of the 16-bit channel code control signal CC determines the operation performed by the 2's complement device TC1, and the fourth bit CC3 of the channel code determines the operation performed by the 2's complement device TC2.

2A, the adder A9 performs the summation of the sums performed by A1 and A2. Similarly, the adder A10 sums the sum of A3 and the sum of A4, the adder A12 sums the sum of A5 and A5, and the adder A13 sums A7 and A8. The adder A11 generates the output AC, the real part of the real channel response value, by adding the sum of A9 and the sum of A10. The imaginary part of the real channel response value, the output jAD is generated by the sum of the adder A14, which is the sum of the outputs of the adders A12 and A13.

The structure of the circuit 200 shown in FIGS. 2A and 2B is similar to the circuit 100 shown in FIG. 2A. However, the shift register R_IThe receiving channel responds to the imaginary part of the CRI. Components A15 to A28 correspond to adder components A1 to A14 to provide register R_ITwo related adder circuits. The second output of the tree circuit of the circuit 200 shown in FIG. 2B is opposite to the output of the circuit 100 shown in FIG. 2A, wherein the value corresponding to the real part of the output BD enters from the even position of the register RI, and corresponds to the virtual output jBC The value is the final sum of the odd-numbered positions of the register RI. The output structure of the real and imaginary parts related to the even and odd registers can be completely reversed, and the same result can be obtained. In particular, regarding the R shown in Figures 2A and 2B_RAnd R_I, The output AC and jBC will be derived from the even register position, and the output BD and jAD will be derived from the odd register position.

Although the registers of Figures 2A and 2B have been shown as having 16 locations each, the channel response according to this creation can generally be used to have 2N register locations and more or less all designed to perform even and odd temporary It is achieved by the combination of the sum of the register positions.

The four output values AC, BD, jAD, jBC of circuits 100 and 200 represent the real and imaginary parts of the multiplication operation shown in formula 1.<maths><img file="TWM240734U_D0005.tif" /></maths>Where A is the real part of the channel response, B is the imaginary part of the channel response, and C corresponds to the bits C1, C3, C5, C6, C9, C11, C13, C15, and D of the channel code. C0, C2, C4, C6, C8, C10, C12, C14. Each channel bit represents the value of a pure real number or a pure imaginary number. Therefore, this tree circuit can be hardware connected to the register R_RAnd R_IOf all odd or all even positions. According to the tree used in this creation to determine the channel code bit, the real or virtual elimination will consume a large amount of hardware space multiplication requirements.

As shown in Figure 3, an additional circuit is provided to combine the output of the tree of circuits 100 and 200 to produce the corresponding approximation B^HThe coefficient value of the real and imaginary output values, and input the specific multiplier of the channel code to generate A^H. A subtractor S1 is related to the output AC of the circuit 100 and the output BD of the circuit 200 to subtract the real part of the processed real channel response signal and the real part of the virtual channel response signal. An adder A29 correlates the output jBC of the circuit 200 and the jAD of the circuit 100 to sum the imaginary part of the processed virtual channel response signal and the imaginary part of the real channel response signal. The sum generated by the adder A29 then passes through the 2's complement device TC3 for the virtual output, which produces B^HThe complex conjugate of the matrix.

On B^HAfter the real part and imaginary part of the contribution of the matrix burst are determined, the imaginary/real form of the channel code specific multiplier is input to generate a pair A^HThe matrix's explosive contribution. Referring to Figure 3, the channel code specific multiplier is preferably stored in a two-bit register. Bit 1 in the register represents whether the channel code specific multiplier is Positive (a value of 0) or negative (a value of 1). The bit 0 in the register represents whether the specific multiplier of the channel code is an imaginary number (a value of 1) or a real number (a value of 0).

Referring to Figure 3, the real contribution is input to the demultiplexer D1. After entering the channel code specific multiplier,^HMay correspond to the actual contribution to A^HReal contribution (Real_Real) or to A^HThe virtual contribution (Imag_Real). Demultiplexer D1 responds to the bit 0 of the specific multiplier of the channel code to separate B^HReal contribution. If bit 0 is 0, this output is for Real_Real, and if bit 0 is 1, this output is for Imag_Real, after the 2's complement is obtained by the 2's pu number device TC4.

Similarly, for B^HThe imaginary contribution of may correspond to A^HImaginary contribution (Imag_Imag) or to A^HReal contribution (Real_Real). Demultiplexer D2 responds to the bit 0 of the channel code specific multiplier to separate B^HS imaginary contribution. If bit 0 is 0, this output is for Image_Image, and if bit 0 is 1, this output is for Real_Image.

After separation, a pair of multipliers M1, M2 are used to generate a pair A^HThe real and imaginary contributions of the matrix's explosion. A real multiplexer M1 selects Real_Real or Real_Imag as the real contribution (ah_out_real). If bit 0 is 0, select Real_Real, and if bit 0 is 1, select Real_Imag. Similarly, the virtual multiplexer M2 selects Imag_Imag or Imag_Real as the virtual contribution (ah_out_imag). If bit 0 is 0, Imag_Imag is selected, and if bit 0 is 1, Imag_Real is selected. Therefore, it can be determined to A^HContributions. After all the bursts have been decided, the entire A^HIt is decided. As shown in the preferred embodiment, the multiplier pair A^HThe matrix is not needed.

In 3GPP, it is recommended to transmit broadcast channels on two antennas using different scrambling codes for each antenna. Hereinafter, it is referred to as space code transmission diversity (space code transmission diversity). code transmit diversity, SCTD). Because the same broadcast material is transmitted on the two channels, the contribution of each channel can be combined before the material is evaluated. In addition, it is recommended to use SCTD to transmit multiple broadcast channels and other channels.

Fig. 5 is a combination of two channel codes for determining whether a single BCH needs to support SCTD, as currently proposed. The main common control entity channel (P-CCPCH) is monitored to determine whether the SCTD mode supports SPEP1, step 1. If not (I_pccpch is 0), SCTD mode is not supported. If it is, a midamble detection device determines whether the midamble m2 appears, step 2. If m2 appears, SCTD mode is supported. If not, SCTD mode is not supported.

Figures 6A, 6B and 7 show preferred embodiments for selectively supporting SCTD. The selected SCTD is preferably used with a single BCH, multiple BCHs, and other channels that use the selected SCTD transmission. Figure 6A deals with the imaginary part of the channel. If SCTD is supported, the real contribution of the first code is called ah_sctd_out_real and the second code ah_out_real. If SCTD is not supported, ah_sctd_out_real will not appear.

ah_sctd_out_real is one of the inputs of the multiplexer M3. Other inputs are set to 0 (0x0). If SCTD is supported (sctd_on &amp; second_channel bit a 1), ah_sctd_out_real passes through the adder A100. If SCTD is not supported, send 0 to adder A100. ah_out_real is also input to the adder A100 to generate the contribution of the real part combination of the two channels, if SCTD is supported, or simply through the channel (ah_out_real) (note that if it is not the SCTD channel, there is no first and second channel). Saturation logic SL1 is used to prevent the contribution of the combination from recording The bit width of the memory has overflowed. As shown in FIG. 6A, preferably, two registers R1 and R2 are used to temporarily buffer the contribution of the second channel (ah_out_real).

Figure 6B deals with the false contribution of the channel. If SCTD is supported, the required contribution of the first code is called ah_sctd_out_imag and the second code ah_out_imag. If SCTD is not supported, ah_sctd_out_imag will not appear. ah_sctd_out_imag is one of the inputs of the multiplexer M4. Other inputs are set to 0 (0x0). If SCTD is supported (sctd_on&amp; second_channel bit a 1), ah_sctd_out_imag passes through the adder A100. If SCTD is not supported, send 0 to adder A101. ah_out_imag is also input into the adder A101 to generate the contribution of the required combination of the two channels, if SCTD is supported, or simply through the channel (ah_out_imag). Saturation logic is used to prevent the contribution of the combination from overflowing from the bit width of the memory. As shown in FIG. 6b, preferably, the two registers R3 and R4 are used to temporarily buffer the contribution of the first channel (ah_out_imag).

This method of combining two channels reduces memory requirements and the amount of time required to calculate the final result. When the second channel contribution is processed, its first channel combination is stored and the combined channel is stored. Therefore, the second channel has never been stored. Preferably, the combined channel is written back to the address of the first channel. If the first channel is not stored in a read_modify_write memory, it is better to use the two registers R1, R2, R3, R4 shown in Figures 6A and 6B. If the first channel memory system reads, modifies, and writes to the memory, it is best to only use the registers R1, R3.

Figure 7 is a better circuit for use with Figures 6A and 6B. When determining the SCTD Whether the address of the second code is supported. When A^HWhen expanded, each generated value is best stored in a subsequent memory address. If the first and second channels are combined for SCTD, the combined channel contribution is best to be overwritten on the first channel to reduce the required memory. To illustrate, if SCTD is not supported, the subsequent address for the first position of the second channel may be address 516. If SCTD is supported, this value will be combined with the first channel and written back to the first address of the first channel memory, address 0.

When SCTD is not supported, the address where the determined channel value is written is ah_addr_write. A control signal, sctd_on &amp; second_channel indicates whether SCTD is supported. If SCTD is supported, sctd_on &amp; second_channel has the value 0, and if not, sctd_on &amp; second_channel has the value 1. This address is input to the demultiplexer D3. If SCTD is not supported (sctd_on &amp; second_channel has the value 1), this address passes through the multiplexer M5. Multiplexer M5 passes the address if SCTD is not supported.

If SCTD is supported, the address (ah_addr_write) is input to the subtractor S2. The subtractor subtracts the number of memory values of the first channel (sctd_fold_dec) from the address. When SCTD is not supported, to reduce power consumption, a second multiplexer M6 is used. The multiplexer M6 selects sctd_fold_dec as the input of the subtractor S2, when SCTD is supported (sctd_on is 1). If SCTD is not supported (sctd_on is 0), input a 0 (0x0) to the subtractor S2 and the output of the multiplexer M6 is input to the multiplexer M5. When SCTD is supported, the multiplexer M5 selects the subtracted input.

<p>0, 1. . . Bit</p><p>1, 2, 3, 4. . . Program</p><p>10. . . Multiple communication</p><p>20. . . Communication</p><p>twenty two. . . antenna</p><p>twenty four. . . Demodulator</p><p>26. . . Analog to Digital Converter (ADC)</p><p>28. . . Channel evaluation device</p><p>30. . . Joint detector</p><p>100, 200. . . Circuit</p><p>A1-A8. . . Adder/subtractor components</p><p>A1', A9-A14, A29, A100, A101. . . Adder element</p><p>A15-A28. . . element</p><p>TC1, TC2, TC3, TC4. . . 2's complement device</p><p>CRR1, CRR3. . . enter</p><p>C1, C3. . . Location</p><p>CC. . . 16-bit channel code control signal</p><p>CC3. . . The fourth bit of the channel code</p><p>CRI. . . Receive channel response</p><p>AC, BD, jAD, jBC. . . Output</p><p>A. . . Real part of the channel response</p><p>B. . . Imaginary part of channel response</p><p>CC. . . Channel code</p><p>C0-C15. . . Bit</p><p>R1, R2, R3, R4, RR, RI. . . Register</p><p>S1, S2. . . Subtractor</p><p>M1-M6. . . Multiplexer</p><p>D1, D2, D3. . . Demultiplexer</p><p>SL1. . . Saturation logic</p>

The first figure is a brief block diagram of a joint detection receiver.

Figure 2A shows the device used for the real part of the gyro channel response.

Figure 2B shows a device for the imaginary part of the gyro channel response.

The third diagram shows a device that sums the outputs of FIGS. 2A and 2B to generate the real and imaginary output for building the system response matrix.

The fourth diagram shows the specific circuit of the addition tree of FIGS. 2A and 2B.

The fifth figure shows the flow chart of determining whether to support the diversity of spatial code transmission for the broadcast channel.

Figures 6A and 6B show a better circuit for combining Hermetian code contributions used to input the system response matrix.

Figure 7 shows a preferred circuit for determining the addresses of the circuits of Figures 6A and 6B.