High-speed time division duplexing transceiver for wired communication and method thereof

High-speed time-division duplex transceiver for wired communication and method thereof

HIGH-SPEED TIME DIVISION DUPLEXING TRANSCEIVER FOR WIRED COMMUNICATION AND METHOD THEREOF

related applications

The present invention claims the international priority of US Patent Application No. 17/140175 (filing date: January 4, 2021), the entire content of which is incorporated as a part of the patent specification of the present invention for reference.

The present invention generally relates to a time-division duplex transceiver, and more particularly, to a high-speed time-division duplex transceiver capable of reducing signal interference.

A conventional wired communication system includes a first transceiver, a second transceiver and a communication medium. The first transceiver encodes the first message into a first signal, and the first message is sent through the communication medium and received and decoded by the second transceiver. The second transceiver encodes the second message into a second signal, and the second signal is sent through the communication medium and received and decoded by the first transceiver. During the transmission of the first signal and the second signal, the communication medium is shared according to a duplex scheme. For example, the communication medium is a cable. There are three duplexing schemes: Full Duplexing (FD), Frequency Division Duplexing (FDD) and Time Division Duplexing (Time Division Duplexing, TDD). In the FD scheme, the first signal and the second signal are sent simultaneously and overlap in the frequency domain; the FD scheme is the most efficient scheme to utilize the capacity of the communication medium, but due to the strong interference between the first signal and the second signal, Therefore, it is technically the most difficult to achieve. In the FDD scheme, the first signal and the second signal are sent simultaneously, but nominally do not overlap in the frequency domain; in this scheme, although the interference between the first and second signals is greatly reduced, due to the frequency domain It is not without the effect of nonzero side-lobe leakage, and the interference is not completely eliminated. Therefore, the scheme needs sharp filtering to mitigate the interference. In the TDD scheme, the first signal and the second signal are sent alternately. If there are enough guard intervals to ensure that the transmission process of the first signal can be switched to the transmission process of the second signal cleanly, the interference between the first signal and the second signal can be significantly eliminated. However, the above-mentioned guard interval cannot be used for sending the first signal or the second signal, and thus is regarded as an extra expense in the communication process, which causes a loss in the utilization efficiency of the capacity of the communication medium.

Although the FD scheme is very efficient, it is difficult to implement when seeking high throughput applications (eg, 10 Gb/s transmission over 15m twisted pair cable). The FDD scheme is also difficult to implement for high throughput applications due to the need to have a highly sophisticated filter response. In contrast, for high-throughput applications, the TDD scheme is relatively easy to implement. However, transceivers for TDD schemes still have some issues to deal with. First, at the interface connected to the communication medium, impedance matching is required for both the first signal and the second signal, otherwise undesired reflections may occur and cause interference. Secondly, a fast handover is required to reduce the extra cost and efficiency loss in utilizing the communication medium due to the guard interval. Third, the transceiver must have a fast response when processing the first signal and the second signal, because high-throughput applications require the first signal and the second signal to change rapidly to carry a large amount of information in a short period of time.

Therefore, there is an urgent need for a transceiver that can be used in high-speed TDD schemes and effectively solve the above problems.

In one embodiment, a transceiver is provided, comprising: a Medium Dependent Interface (MDI) for providing between a first voltage signal at a first node and a second voltage signal at a second node AC coupling. A broadband matching network 120 configured to couple the second voltage signal at the second node to a third voltage signal at a third node; an amplifier with a settable gain configured to receive the third voltage a voltage signal and output a fourth voltage signal according to a first logic signal; an analog digital converter configured to receive the fourth voltage signal and output a first voltage signal according to the first logic signal and a first clock data; a digital-to-analog converter configured to receive a second data and output a first current signal to the third node according to a second logic signal and a second clock, wherein the first logic signal and The second logic signal is alternately asserted.

In one embodiment, a method for time division duplexing is provided, comprising: using a medium dependent interface to provide AC coupling between a first voltage signal at a first node and a second voltage signal at a second node; using a a broadband matching network to couple the second voltage signal at the second node to a third voltage signal at a third node; using a gain-settable amplifier for the third voltage according to a first logic signal Amplifying the signal into a fourth voltage signal; using an analog-to-digital converter to convert the fourth voltage signal into a first data according to the first logic signal and a first clock; and using a digital-to-analog converter to A second data is converted into a first current signal output to the third node according to a second logic signal and a second clock, wherein the first logic signal and the second logic signal are alternately asserted )of.

For a further understanding of the features and technical content of the present invention, please refer to the following detailed descriptions and drawings of the present invention. However, the drawings provided are only for reference and description, and are not intended to limit the present invention.

The following are specific specific embodiments to illustrate the embodiments of the "high-speed time-division duplex transceiver for wired communication and method thereof" disclosed in the present invention, and those skilled in the art can understand the present invention from the content disclosed in this specification. advantages and effects. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to the actual size, and are stated in advance. The following embodiments will further describe the related technical contents of the present invention in detail, but the disclosed contents are not intended to limit the protection scope of the present invention. In addition, the term "or", as used herein, should include any one or a combination of more of the associated listed items, as the case may be.

The present invention is directed to a time-division duplex transceiver and a related method thereof. While the specification describes several example embodiments of the invention which are considered to be advantageous modes of carrying out the invention, it should be understood that the invention may be practiced in a variety of ways and is not limited to the specific examples described below, or to implementations specific manner of any feature of these examples. In other instances, well-known details have not been shown or described in order to avoid obscuring aspects of the invention.

Those of ordinary skill in the art understand terms and basic concepts related to microelectronics used in the present invention, such as "circuit node", "power node", "ground node", "differential signal", "differential pair", "voltage", "current", "complementary metal oxide semiconductor (CMOS)", "p-channel metal oxide semiconductor (PMOS)", "n-channel metal oxide "n-channel metal oxide semiconductor", "resistance", "inductance", "capacitor", "clock", "signal", "amplifier", "common source", "impedance", "impedance matching" , "return loss", "AC", "AC coupled," "DC", "DC coupled", "gain", "stacked" and "load". When used in paragraphs dealing with microelectronics, such The terminology and basic concepts are obvious to those skilled in the art, and therefore will not be described in detail here.

A person of ordinary skill in the art can read a schematic diagram of a circuit including elements such as capacitors, inductors, resistors, NMOS transistors, PMOS transistors, etc., and does not need a lengthy description of how one element is connected to another in the schematic diagram. Those with ordinary knowledge in the art can also recognize the symbols of PMOS transistors and NMOS transistors, and identify their "source terminal", "gate terminal" and "drain terminal". In short, related to MOS transistors, the "source terminal" is abbreviated as "source" hereinafter, the "gate terminal" is abbreviated as "gate", and the "drain terminal" is abbreviated as "drain". The NMOS transistor has a threshold voltage; when the gate voltage of the NMOS transistor is higher than its source voltage by more than its threshold voltage, the NMOS transistor is turned on, otherwise it is turned off. The PMOS transistor has a threshold voltage; when the gate voltage of the PMOS transistor is lower than its source voltage by more than its threshold voltage, the PMOS transistor is turned on, otherwise it is turned off. Those of ordinary skill in the art also understand such things as gigahertz (GHz), μm (micrometers), nanometers (nm), ohms (Ohm), nanohenries (nH), femtofarads (fF), and picofarads (pF).

A MOS transistor, PMOS or NMOS, has a width and a channel length. Sometimes "channel length" is simply referred to as "length" when it is clear from the context that "length" refers to the "channel length" of a transistor without causing confusion. The width and length of the MOS transistor are expressed in "W/L". For example, when it is mentioned that "the W/L of the NMOS transistor is 10 μm/30 nm", it means that "the width and length of the NMOS transistor are 1 μm and 30 nm, respectively".

The present invention is presented in an engineering sense rather than a strictly mathematical sense. For example, "A equals B" means "the difference between A and B is less than the engineering tolerance." "X is zero" means "the absolute value of X is less than the engineering tolerance".

In the present invention, a "circuit node" is often simply referred to as a "node" when the meaning of the "circuit node" can be clearly understood from the context.

Throughout the present specification, a ground node is a substantially zero voltage (0V) node. A power supply node is a substantially fixed voltage node and is denoted by "VDD", which is a widely used convention in the literature. Since in the present invention, there are multiple power supply nodes including the first power supply node and the second power supply node, the first power supply node is denoted as "V _DD1", and denote the second supply node as "V _DD2". In the present invention, sometimes "V _DD1" refers to the first power supply node "V _DD1" at the voltage level. For example, clearly "V _DD1is 1.8V" means at the first supply node V _DD1The voltage level above is 1.8V.

A circuit is a collection of transistors, capacitors, resistors, and/or other electronic devices that are interconnected in a particular way to perform a particular function. A net is a single circuit or a collection of multiple circuits.

In the present invention, a signal is a variable level voltage or current that carries specific information and can vary over time. The signal level at a specific time point represents the state of the signal at that time point.

A logic signal refers to a signal with two states: a low-level state and a high-level state. The low-level state is also referred to as the "0" state, and the high-level state is also referred to as the "1" state. Regarding the logic signal Q, "Q is high level" or "Q is low level" means "Q is in a high level state" or "Q is in a low level state". Likewise, "Q is 1" or "Q is 0" means "Q is in a 1 state" or "Q is in a 0 state". In the present invention, the high-level state is also referred to as an "asserted" state, and the low-level state is also referred to as a "de-asserted" state.

A clock is a logic signal that periodically switches back and forth between a low level and a high level.

If the state of X is always the opposite of the state of Y, the logic signal X is called the logic inversion of the logic signal Y. That is, when X is high, Y will be low, and vice versa.

Data carries information that is usually represented in a numerical representation. Data can vary over time and can be encoded as a collection of time-varying logic signals.

The switch is controlled by a logic signal; when the logic signal is active, the switch is in the "on" state and behaves like a short circuit; when the logic signal fails, the switch is in the "off" state and behaves like is an open circuit; a short circuit has nominally zero resistance. An open circuit has nominally infinite resistance.

When a MOS transistor is used to implement the switch, it is controlled by a control signal, which is a logic signal applied to the gate of the MOS transistor. When the control signal is high, the switch implemented by the NMOS transistor is in the "on" state, and when the control signal is low, it is in the "off" state.

Throughout the present specification, differential transmission schemes are widely used. When implemented in a differential transmission scheme, the voltage signal includes two voltages, denoted by the suffixes "+" and "-" respectively, and marked with subscripts, and the value of the voltage signal is indicated by the difference between the above two voltages . For example, the voltage signal V in the differential transmission embodiment ₁(V ₂, V ₃, V ₄) including V ₁₊(V ₂₊, V ₃₊, V ₄₊) and V _1-(V _2-, V _3-, V _4-), and the voltage signal V ₁(V ₂, V ₃, V ₄) value is determined by V ₁₊(V ₂₊, V ₃₊, V ₄₊) and V _1-(V _2-, V _3-, V _4-) is the difference between. Likewise, when implemented in a differential transmission scheme, the current signal includes two currents, denoted by the suffixes "+" and "-", respectively, and labeled below. For example, the current signal I in the differential transmission embodiment ₁including current I ₁₊and current I _1-, and the current signal I ₁The value is determined by the current I ₁₊and current I _1-The difference between . Each circuit that implements a signal in the differential transmission scheme includes two half-circuits, including a first-half circuit and a second-half circuit; the first-half circuit is the same as the second-half circuit. In the first half of the circuit, nodes denoted with a suffix "+" have corresponding nodes in the second half of the circuit denoted with a suffix "-" in the subscript. For example, when implemented in a differential transmission scheme, the voltage signal V at node 101 ₁Node 101 included in the upper half of the circuit ₊The voltage at V ₁₊and node 101 in the second half of the circuit _-The voltage at V _1-。

FIG. 1 shows a functional block diagram of a TDD transceiver according to an embodiment of the present invention. The TDD transceiver 100 includes a medium dependent interface (MDI) 110 for the first voltage signal V at the first node 101 ₁and the second voltage signal V at the second node 102 ₂AC coupling is provided between; the broadband matching network 120 is used to convert the second voltage signal V at the second node 102 ₂coupled to the third voltage signal V at the third node 103 ₃; a programmable gain amplifier (PGA) 130 for receiving the third voltage signal V ₃And output the fourth voltage signal V according to the first logic signal C1 ₄; an analog-to-digital converter (ADC) 140 for receiving the fourth voltage signal V ₄, and output the first data D according to the first logic signal C1 and the first clock CK1 ₁; and a digital-to-analog converter (DAC) 150 for receiving the second data D ₂, and outputs the first current signal I to the third node 103 according to the second logic signal C2 and the second clock CK2 ₁. The first node 101 is connected to a communication medium 191 . When the first logic signal C1 is valid, the TDD transceiver 100 is in the receiver mode, wherein the first voltage signal V ₁Sent by the remote TDD transceiver 192 and via the communication medium 191 to the first node 101 . When the second logic signal C2 is valid, the TDD transceiver 100 is in the transmitter mode, wherein the first voltage signal V ₁Sent by TDD transceiver 100 and received by remote TDD transceiver 192 via communication medium 191 .

The first logic C1 and the second logic C2 are alternately active. The first logic C1 and the second logic C2 cannot be enabled at the same time, but can be disabled at the same time.

In one embodiment, a differential transmission scheme is used for the first (second, third, fourth) voltage signals V ₁(V ₂, V ₃, V ₄), where the voltage signal V ₁(V ₂, V ₃, V ₄) including the voltage V ₁₊(V ₂₊, V ₃₊, V ₄₊) and the voltage V _1–(V _2–, V _3–, V _4–), and the voltage signal V ₁(V ₂, V ₃, V ₄) value is determined by the voltage V ₁₊(V ₂₊, V ₃₊, V ₄₊) and the voltage V _1–(V _2–, V _3–, V _4–) is expressed as a difference between , as described above. Similarly, the differential transmission scheme is used for the first current signal I ₁, wherein the first current signal I ₁including current I ₁₊and current I _1-, and the first current signal I ₁The value is determined by the current I ₁₊and current I _1-The difference between .

By way of example and not limitation, the communication medium 191 has a characteristic impedance Z _Ocable.

The MDI 110 provides AC coupling between the first node 101 and the second node 102 . In one embodiment, the MDI 110 includes a transformer 210, as shown in Figure 2A. In another embodiment, the MDI 110 includes a common mode choke coil 220 and a pair of capacitors 221 and 222, as shown in FIG. 2B. Transformers, common mode choke coils and capacitors are well known in the art and will not be described in detail. In any embodiment, the first voltage signal V ₁The AC component of is substantially the same as the second voltage signal V ₂The AC component is short-circuited. Therefore, the impedance entering the broadband matching network 120 from the MDI 110 is substantially equal to the impedance entering the MDI 110 from the communication medium 191 .

In one embodiment, the entire TDD transceiver 100 except the MDI 110 is integrated and fabricated on a silicon substrate using CMOS process technology. By way of example and not limitation, a 28nm CMOS process technology with a minimum channel length of 30nm is used.

The purpose of the broadband matching network 120 is to ensure that the input impedance from the MDI 110 into the broadband matching network 120 is substantially equal to the characteristic impedance Z of the communication medium 191 _O. A schematic diagram of an embodiment of a broadband matching network 300 that may be used to implement broadband matching network 120 is depicted in FIG. 3A. For the sake of brevity, only one half of the circuit is shown, where the suffix "+" appended to the suffix is used to designate the half circuit. The broadband matching network 300 includes: a T-coil inductor 320 , a capacitor 310 , an electrostatic discharge (ESD) diode 330 and a resistor 340 . Here, "V _DD1" represents the first power supply node. For this half of the circuit, the input impedance needs to be equal to the characteristic impedance Z _Ohalf of , so the resistance value of resistor 340 is chosen to be the characteristic impedance Z _Ohalf of . The T-coil inductor 320 includes two coupled inductors 321 and 322 with a coupling coefficient of k, wherein the center-tap structure of the T-coil inductor 320 is connected to the node 103 ₊. ESD diode 330 is used at node 103 ₊Clamping voltage at V ₃₊, to prevent damage and thereby protect the TDD transceiver 100 in the event of an electrostatic discharge event. For effective protection, the physical size of ESD diode 330 must be large, which also results in node 103 ₊has a large parasitic capacitance. T-coil inductance 320 is used to mitigate node 103 ₊Capacitive load at 310, while capacitor 310 is used to achieve a broadband response. when the node 102 ₊The seen input impedance is approximately equal to the characteristic impedance Z _O, the return loss of the broadband matching network 300 will be very small. For example, but not limited to, the characteristic impedance Z _Ois 100Ohm; V _DD1is 1.5V; inductor 321 is 1nH, with a quality factor of 10 at 10GHz; inductor 322 is 1nH, with a quality factor of 10 at 10GHz; coupling coefficient k is 0.25; resistor 340 is 50 ohms; capacitor 310 is 150fF; node 103 ₊The total parasitic capacitance is 1pF. Return loss (for connection to node 102 ₊and a voltage source with an impedance of 50 ohms) as shown in Figure 3B. As shown, the return loss is small, below 19dB, over a very wide frequency range (from 1GHz to 20GHz). This appears to satisfy the purpose of broadband matching. Those with ordinary knowledge in the art should be able to properly understand the concepts of "impedance matching" and "return loss", and therefore will not be explained in detail.

A schematic diagram of PGA 400 that may be used to implement PGA 130 is shown in FIG. 4 . Again, this embodiment uses a differential transmission scheme and only half of the circuit is shown for brevity. PGA 400 includes a common source amplifier 430 for receiving voltage V via AC coupling capacitor 410 ₃₊, and output the voltage V at the resistor load 460 whose resistance value can be set ₄₊; and a controllable bias voltage network 420 for determining the bias voltage condition of the common source amplifier 430 according to the first logic signal C1. Here, "V _DD2" denotes the second power supply node. Common source amplifier 430 includes a gain device implemented by NMOS transistor 431 and a stacking device implemented by NMOS transistor 432. Controllable bias network 420 includes: DC coupling resistor 421 to The first gate voltage V _G1is coupled to the gate of the NMOS transistor 431; the switch 422 is used to convert the second gate voltage V according to the first logic signal C1 _G2connected to the gate of the NMOS transistor 432; and another switch 423 for connecting the ground node to the gate of the NMOS transistor 432 according to the logical inversion C1B of the first logic signal C1. When the first logic signal C1 is valid, the gate of the NMOS transistor is connected to the second gate voltage V _G2and turn on. When the first logic signal C1 is deactivated, the logic inversion C1B is activated, and the gate of the NMOS transistor 432 is connected to the ground node, and thus turned off. In this way, when the first logic signal C1 is valid, the common-source amplifier 430 is turned on, otherwise it is turned off. The resistor load 460 whose resistance value can be set includes a plurality of resistors 471 , 472 , etc. connected in series with a plurality of switches 481 , 482 , etc. controlled by a plurality of logic signals E1 , E2 , etc. respectively. In this way, the net resistance of the resistor load 460 with configurable resistance is configurable and depends on the logic signals E1, E2, and so on. The gain of the common source amplifier depends on the resistance of the resistive load of the common source amplifier. Therefore, the gain of the common source amplifier 430 depends on the net resistance of the resistor load 460 whose resistance can be set and is therefore settable. This realizes the function that the gain can be set.

By using low-resistance switches and having a light capacitive load, the PGA 400 can respond very quickly to changes in the first logic signal C1, so the PGA 400 can switch quickly. The PGA 400 can also handle rapidly changing signals with high bandwidth due to the use of an open-loop amplifier topology that is inherently fast and stable. In one embodiment, by way of example and not limitation: V _DD2is 1.05V; the W/L (representing width/length) of the NMOS transistor 431 is 10μm/50nm; the capacitance 410 is 1pF; the resistance 421 is 100K ohm; the first gate voltage V _G1is 600mV; the W/L of the NMOS transistor 432 is 10μm/30nm; the second gate voltage V _G2is 850mV; the switch 422 is realized by an NMOS transistor with a W/L of 10μm/250nm; the switch 423 is realized by an NMOS transistor with a W/L of 10μm/250nm; the first logic signal C1 is 3.3V when it takes effect, otherwise it is 0V; The logic inversion C1B is 3.3V when it is in effect, otherwise it is 0V; the resistance range of the resistor load 460 with a settable resistance is 50 ohms to 400 ohms; and the total parasitic capacitance at the drain of the NMOS transistor 432 is 40fF. The switching time is less than 1ns. When the PGA 400 is programmable at the highest gain (ie, when the resistance of the programmable resistor load 460 is set to its maximum value of 400 ohms), the 3-dB bandwidth is approximately 10 GHz.

Analog-to-digital converters are well known in the art. The circuit designer may choose any suitable analog-to-digital converter circuit known in the art to implement ADC 140 . In one embodiment, the first clock CK1 is effectively 10GHz, but is implemented by a 32-phase 600MHz clock; the ADC 140 is a 32-channel time-interleaved successive approximation register with 7-bit resolution (Successive Approximation Register, SAR) ADC. Timing interleaved SAR ADCs are well known in the art and therefore will not be described in detail. When the first logic signal C1 is valid, the ADC 140 is powered, otherwise it is powered off. De-energizing a circuit according to a logic signal can be accomplished using a de-energizing switch controlled by the logic signal; this is commonly practiced in the art and therefore will not be explained in detail.

In one embodiment, a schematic diagram of a DAC 500 that may be used to implement the DAC 150 is shown in FIG. 5 . The DAC 500 includes: an encoder 505 for converting the second data D ₂It is encoded as a plurality of logic signals B1, B2, B3, etc., and their logical inversions B1B, B2B, B3B, etc. A plurality of current mode logic (CML) circuits 510 , 520 , 530 , etc. are used according to the third gate voltage V _G3, the second logic signal C2, the fourth gate voltage V _G4Output multiple currents and multiple logic signals B1, B2, B3, etc. (and their logical inversions B1B, B2B, B3B, etc.). According to the coding scheme, the second data D ₂Encoded by the encoder 505 into logic signals B1, B2, B3, etc.; that is, the logic signals B1, B2, B3, etc. jointly realize the second data D according to the encoding scheme ₂. In one embodiment, the encoding scheme is a "binary code" scheme; in another embodiment, the encoding scheme is a "thermometer code" scheme; both "binary code" and "thermometer code" are well known , and therefore will not be described in detail. CML circuit 510 includes seven NMOS transistors: 511 , 512 , 513 , 514 , 515 , 516 and 517 . CML circuit 520 includes seven NMOS transistors: 521 , 522 , 523 , 524 , 525 , 526 and 527 . CML circuit 530 includes seven NMOS transistors: 531 , 532 , 533 , 534 , 535 , 536 and 537 . The NMOS transistors 511 ( 521 , 531 ) are implemented to be based on the third gate voltage V _G3Output current I _S1(I _S2, I _S3) current source. When using the "thermometer code" scheme, the CML circuits 510, 520, 530, etc. are all the same, so the current I _S1, I _S2and I _S3are the same; when using the "binary code" scheme, CML circuit 520 shrinks from CML circuit 510 to twice, CML circuit 530 shrinks from CML circuit 520 to twice, so the current I _S2Yes _S1half of the current I _S3is the current I _S2half of . Scale down in two ways: keep the same transistor length, but reduce the transistor width by half.

In CML circuit 510 (520, 530), NMOS transistors 512 (522, 532), 514 (524, 534) and 516 (526, 536) form current I _S1(I _S2, I _S3) flows to the "+" side (ie, the left side in the schematic diagram), and the NMOS transistors 513 (523, 533), 515 (525, 535) and 517 (527, 537) form a current I _S1(I _S2, I _S3) flow path to the "" side (that is, the right side of the schematic diagram); NMOS transistors 512 (522, 532) and 513 (523, 533) form a circuit composed of logic signals B1 (B2, B3) and logic inversion B1B ( B2B, B3B) controlled differential pair to convert the current I _S1(I _S2, I _S3) leads to the "+" side or the "-" side; the NMOS transistors 514 (524, 534) and 515 (525, 535) form a pair of switches to conditionally cut off the power from the NMOS according to the second logic signal C2 The currents of crystals 512 (522, 532) and 513 (523, 533); NMOS transistors 516 (526, 536) and 517 (527, 537) form a stacked pair to relay from NMOS transistors 514 (524, 537), respectively 534) and 515 (525, 535). Currents of CML circuits 510, 520, 530, etc. from the "+" side are at node 103 ₊Summing up to get the current I ₁₊; the "" side current of CML circuits 510, 520, 530, etc. is at node 103 _-Add up to get the current I _1–. When the second logic signal C2 takes effect, the CML circuits 510, 520, 530, etc. are all turned on, and the current I ₁₊and I _1-Generated according to the logic signals B1, B2, B3, etc., and thus according to the second data D ₂produce. When the second logic signal C2 fails, I ₁₊and I _1-are all zero.

As an example and not a limitation, in one embodiment: the second clock CK2 is a 10GHz clock; the second data D ₂is a 2-bit metadata with four possible values: 0, 1, 2, 3; the encoder 505 is a thermometer code encoder, the second data D ₂It is encoded as three logic signals B1, B2 and B3, and the three logic signals are 1V or 0V respectively. The three CML circuits 510, 520 and 530 are identical. The W/L of the transistor 511 is 40 μm/100 nm; the third gate voltage V _G3is 0.7V; the W/L of NMOS transistors 512 and 513 are both 10μm/30nm; the W/L of NMOS transistors 514 and 515 are both 10μm/30nm; the second logic signal C2 is 1V when it is valid, otherwise it is 0V ; The W/L of NMOS transistors 516 and 517 are both 10 μm/30 nm; the fourth gate voltage V _G4is 1.2V; when the second logic signal C2 takes effect, the current I _S1, I _S2and I _S3is 8mA. The DAC 500 is capable of fast switching and fast response due to a current mode circuit using NMOS transistors with short channel lengths, and wherein the current mode circuit can respond to fast changes in the second logic signal C2 and logic signals B1, B2, B3, etc. . As previously mentioned, the broadband matching network 120 can effectively alleviate the ₊and 103 _-Impedance mismatch caused by parasitic capacitance at the

As shown in the flowchart 600 shown in FIG. 6 , referring to FIG. 6 , a method for time-sharing duplexing according to an embodiment of the present disclosure includes: (step 610 ) using a medium-dependent interface to provide a first node at a first node AC coupling between the voltage signal and the second voltage signal at the second node; (step 620 ) using a broadband matching network to couple the second voltage signal at the second node to the third voltage signal at the third node ; (step 630) use a gain-settable amplifier to amplify the third voltage signal into a fourth voltage signal according to the first logic signal; (step 640) use an analog-to-digital converter to according to the first logic signal and the first clock, converting the fourth voltage signal into first data; and (step 650) using a digital-to-analog converter to convert the second data into a first current signal output to the third node according to the second logic signal and the second clock, wherein , the first logic signal and the second logic signal are asserted alternately.

Those of ordinary skill in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as being limited only by the scope of the appended claims.

The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

<p>100: TDD transceiver &lt;br/&gt;01, 101+, 101-, 102, 102+, 102-, 103, 103+, 103-: Node &lt;br/&gt;10: Media Dependency Interface &lt;br/&gt;20, 300: Broadband matching network &lt;br/&gt;30: Amplifier with adjustable gain &lt;br/&gt;40: Analog-to-Digital Converter &lt;br/&gt;50, 500: Digital-to-Analog Converter &lt;br/&gt;91: Communication medium &lt;br/&gt;92: Remote TDD Transceiver &lt;br/&gt;10: Transformer &lt;br/&gt;20: Common mode choke coil &lt;br/&gt;21, 222, 310: Capacitance &lt;br/&gt;20: T coil inductance &lt;br/&gt;21, 322: Inductance &lt;br/&gt;30: ESD diodes &lt;br/&gt;40, 471, 472: Resistance &lt;br/&gt;00: PGA &lt;br/&gt;10: AC coupling capacitor &lt;br/&gt;20: Controllable Bias Voltage Network &lt;br/&gt;21: DC coupling resistor &lt;br/&gt;22, 423, 481, 482: switch &lt;br/&gt;30: Common source amplifier &lt;br/&gt;31, 432, 511, 512, 513, 514, 515, 516, 517, 521, 522, 523, 524, 525, 526, 527, 531, 532, 533, 534, 535, 536, 537: NMOS transistor &lt;br/&gt;60: Resistor load with adjustable resistance &lt;br/&gt;05: Encoder &lt;br/&gt;10, 520, 530: CML circuit &lt;br/&gt;1, B2, B3, E1, E2: logic signal &lt;br/&gt;1B, B2B, B3B, C1B: logical inversion &lt;br/&gt;1: The first logic signal &lt;br/&gt;2: Second logic signal &lt;br/&gt;K1: The first clock &lt;br/&gt;K2: Second clock &lt;br/&gt; ₁: first data &lt;br/&gt; ₂: Second data &lt;br/&gt; ₁: Current signal &lt;br/&gt; ₁₊, I _1-, I _S1, I _S2, I _S3: Current &lt;br/&gt;: Coupling coefficient &lt;br/&gt; ₁, V ₂, V ₃, V ₄: Voltage signal &lt;br/&gt; ₁₊, V _1-, V ₂₊, V _2-, V ₃₊, V ₄₊:Voltage &lt;br/&gt; _DD1: first power node &lt;br/&gt; _DD2: second power node &lt;br/&gt; _G1: first gate voltage &lt;br/&gt; _G2: second gate voltage &lt;br/&gt; _G3: third gate voltage &lt;br/&gt; _G4: Fourth gate voltage </p>

FIG. 1 shows a functional block diagram of a TDD transceiver according to an embodiment of the present invention.

FIG. 2A illustrates an embodiment of a media dependent interface that may be used in the TDD transceiver of FIG. 1 .

FIG. 2B illustrates another embodiment of a medium dependent interface that may be used in the TDD transceiver of FIG. 1 .

FIG. 3A shows a schematic diagram of one half of a wideband matching network that may be used in the TDD transceiver of FIG. 2 .

FIG. 3B shows a simulation result of the return loss of a broadband matching network according to an embodiment of the present invention.

FIG. 4 shows a schematic diagram of a gain-settable amplifier that may be used in the TDD transceiver of FIG. 3 .

FIG. 5 shows a schematic diagram of a digital-to-analog converter that may be used in the TDD transceiver of FIG. 1 .

FIG. 6 shows a flowchart of a method for time-division duplexing according to an embodiment of the present invention.