Buffer system, buffer circuit and operating method thereof

Buffer system, buffer circuit and operation method thereof

BUFFER SYSTEM, BUFFER CIRCUIT AND OPERATING METHOD THEREOF

The present disclosure relates to a buffer system, and in particular, to a buffer circuit and an operation method thereof.

Integrated circuits (ICs) are often protected by external protection circuits called overvoltage protection circuits (OPCs) or in some cases by transient voltage suppressor (TVS) circuits. For electrostatic discharge (ESD) and other transient events that may cause damage. This protection is usually provided when the IC is in the startup state, and can include turning on the clamp circuit to release the transient current, thereby avoiding large voltage stress on the input pad.

A buffer circuit includes an input terminal, an output terminal, a buffer, and a resistance capacitor circuit. A resistance-capacitance circuit and the buffer are coupled in series between the input terminal and the output terminal, and the resistance-capacitance circuit is used to compare an input signal received at the input terminal between a plurality of logic voltage levels. Transition time, increasing a transition time between a plurality of logic voltage levels of an output signal generated at the output terminal, the output The transition time of the signal is based on a duration of a logical inversion of the input signal.

A buffer system includes an overvoltage protection circuit and a buffer circuit. The overvoltage protection circuit is used to generate a protected signal at an output terminal of the overvoltage protection circuit; the buffer circuit is used to generate a buffer circuit output signal at a buffer circuit output terminal. The buffer circuit includes an input terminal, a buffer, and a buffer circuit. Resistor capacitor circuit. The input terminal is coupled to the output terminal of the overvoltage protection circuit; a resistance-capacitance circuit is coupled in series with the buffer between the input terminal and the output terminal of the buffer circuit, wherein the resistance-capacitance circuit is used to be opposite to the output terminal of the buffer circuit. A transition time of the protection signal between the multiple logic voltage levels increases a transition time of the output signal of the buffer circuit between the multiple logic voltage levels.

A method of operating a buffer circuit. The method includes the following operations. Receive a logic signal at an input terminal of the buffer circuit; use each of a resistance-capacitance circuit and a buffer to sequentially invert the logic signal, and the resistance-capacitance circuit is coupled to an input terminal of the buffer; An output terminal of the buffer circuit outputs the logic signal that is sequentially inverted, wherein the step of using the resistance-capacitance circuit to invert the logic signal includes using a resistance-capacitance network to couple the input terminal of the buffer to a One of the power supply voltage node or a reference voltage node.

<p>100: IC system</p><p>110: Protection circuit</p><p>111, 121, 123, 125, 127: input terminals</p><p>112, 124, 128, 224: output terminal</p><p>113: Voltage reference terminal</p><p>114: detection circuit</p><p>116: clamp circuit</p><p>120: IC chip</p><p>122, 222A, 222B, 400, 422: buffer circuit</p><p>126, 300A~300D: Delay circuit</p><p>VDD: power supply voltage</p><p>VSS: Reference voltage</p><p>VSSN: Reference voltage node</p><p>RST: signal path</p><p>Rext, RextPC, Rint, IN, OUT, RDint, RinPC, IN1, IN2, OUT1, OUT2: signal</p><p>VDDN: power supply voltage node</p><p>INV1~INVN: inverter</p><p>C1: Capacitive device</p><p>R1: Resistive device</p><p>N1~NM: NMOS transistor</p><p>P1~PM: PMOS transistor</p><p>430, 440: Logic Circuit</p><p>t1, t2: time</p><p>600: method</p><p>610, 620, 630, 640: operation steps</p>

The following detailed description can be better understood by referring to various aspects of the content of this disclosure with the accompanying drawings. Its worth noting that according to the industry According to standard practice, the features are not drawn to scale. In fact, the size of various features can be increased or decreased arbitrarily for clarity of discussion.

Figure 1 is a schematic diagram of an IC system according to some embodiments.

FIG. 2A is a schematic diagram of a buffer circuit according to some embodiments.

Figure 2B is a schematic diagram of a buffer circuit according to some embodiments.

3A to 3D are schematic diagrams of delay circuits according to some embodiments.

Figure 4 is a schematic diagram of a buffer circuit according to some embodiments.

FIG. 5 is a representation diagram of the operating parameters of the buffer circuit according to some embodiments.

Fig. 6 is a flowchart of a method of operating a buffer circuit according to some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. can be envisaged. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include that it may be between the first feature and the second feature An embodiment in which an additional feature is formed so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself represent the various The relationship between various embodiments and/or configurations.

In addition, spatially relative terms, such as "below", "below", "lower", "above", "upper", etc. can be used here to simplify the description to describe one element or feature as shown in the figure and another The relationship of elements or features. In addition to the orientations shown in the figures, spatially relative terms are intended to include different orientations of devices/elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other directions), and the spatial relative descriptors used here can be similarly interpreted accordingly.

In many embodiments, a buffer circuit includes a delay circuit connected in series to one or more buffers, and the buffer circuit generates an output signal whose transition time between multiple logic voltage levels is compared with that of an input signal. The signal has a longer transition time. By using a delay circuit, such as an RC (Resistor Capacitor) circuit, the transition time is increased, and the buffer circuit can avoid the logic inversion of the short-term input signal, such as the input signal based on an electrostatic discharge event, which triggers the unnecessary output signal transition. Compared with some implementation methods that do not include a delay circuit, the buffer circuit is more capable of generating an output signal with a fixed logic voltage level in response to the logic inversion of a short-term input signal.

Figure 1 is a schematic diagram of an IC system 100 according to some embodiments. The IC system 100 includes a protection circuit 110 which is coupled to an IC chip 120 through a signal path RST. In some embodiments, the IC system 100 includes a protection circuit 110 and an IC chip 120, and the protection circuit 110 and the IC chip 120 are separate components mounted on a substrate, such as a printed circuit board (PCB). In some embodiments, the IC system 100 is an IC device package (e.g., a 2.5D IC package, a Part or all of a 3D IC package, or an integrated fan-out (InFO) package. In some embodiments, the IC system 100 includes additional components in addition to the components shown in FIG. 1, such as an interposer and/or one or more IC chips other than the IC chip 120.

Two or more circuit elements are considered to be coupled based on a direct electrical connection or an electrical connection including one or more additional circuit elements (such as one or more logic or transmission gates), so that these Circuit elements can be controlled, for example made resistive, or turned on by a transistor or other switching device.

In the embodiment shown in FIG. 1, the protection circuit 110 is directly connected to the IC chip 120 through the signal path RST. In many embodiments, one or more additional circuit elements, such as one or more switching devices, are coupled between the protection circuit 110 and the IC chip 120 along the signal path RST. In many embodiments, the signal path RST includes a bonding wire, one or more redistribution layers of a post-passivation interconnection (PPI) structure including multiple redistribution layers (RDLs), and/ Or one or more other conductor elements suitable for transmitting one or more signals between the protection circuit 110 and the IC chip 120.

The protection circuit 110 is a circuit including an input terminal 111 coupled to the output terminal 112. The protection circuit 110 further includes a voltage reference terminal 113, a detection circuit 114 coupled between the input terminal 111 and the voltage reference terminal 113, and The clamp circuit 116 between the output terminal 112 and the voltage reference terminal 113.

In many embodiments, the input terminal 111 is coupled to a circuit (not shown) inside or outside the IC system 100, and thus is used to receive a signal Rext. The output terminal 112 is coupled to the signal path RST, and therefore is used to output a signal RextPC to the signal path RST. The voltage reference terminal 113 is coupled to a reference voltage node VSSN, and therefore is used to receive a reference voltage VSS from the reference voltage node VSSN. In some embodiments, the reference voltage VSS has a reference voltage level of the IC system 100, such as a ground voltage level.

A signal, such as one or both of the signal Rext or RextPC, can have multiple voltage levels corresponding to multiple logic states. A voltage level lower than a first threshold relative to the reference voltage level corresponds to a low logic state, which is referred to as a low logic voltage level in some embodiments, and is higher than the reference voltage level A voltage level of a second threshold value of the voltage level, the voltage level higher than the second threshold value corresponds to a high logic state, the second threshold value is higher than the first threshold value, and the high logic state is In some embodiments, it is referred to as a high logic voltage level.

The detection circuit 114 is a circuit for detecting the voltage level of the signal Rext relative to the reference voltage level, and outputting a control signal (not shown) in response to an overvoltage condition of the signal Rext (such as an electrostatic discharge event) ), the control signal can be used by the clamp circuit 116 to indicate the overvoltage condition. In some embodiments, the detection circuit 114 is used to output the control signal. The control signal has a low logic voltage level or a first logic voltage level of a high logic voltage level, and the first logic voltage level corresponds to Under normal operating conditions, and with low logic voltage level or high logic voltage level A second logic voltage level, the second logic voltage level corresponding to an overvoltage condition.

The clamp circuit 116 is a circuit for receiving the control signal output by the detection circuit 114, and the clamp circuit 116 includes one or more switching devices (not shown) for selectively connecting the output terminals 112 and A current path responsive to the control signal is established between the voltage reference terminals 113. In some embodiments, the clamping circuit 116 includes the one or more switching devices for selectively coupling the output terminal 112 to the voltage reference terminal 113 by directly coupling the output terminal 112 to the voltage reference terminal 113 Establish a current path. In many embodiments, the one or more switching devices include n-type metal oxide semiconductor (NMOS) transistors or p-type metal oxide semiconductor (PMOS) transistors, and the current of channels including NMOS transistors or PMOS transistors path.

In some embodiments, the clamp circuit 116 is used to interrupt the current path in response to the control signal having the first logic voltage level corresponding to the normal operating condition, and to establish the current path in response to the current path corresponding to the overvoltage condition. A control signal for the second logic voltage level.

In many embodiments, the detection circuit 114 and the clamp circuit 116 are used to detect and respond to the transient overvoltage condition of the signal Rext. The transient overvoltage condition is based on one or more electrostatic discharge events, for example, based on the human body. Discharge mode (human body model, HBM) or component charging mode (charge device model, CDM), electrical overstress (EOS) events, or other transient overvoltage conditions. In many embodiments, one or both of the detection circuit 114 or the clamping circuit 116 includes It includes one or more sub-circuits (not shown) and is therefore used to respond to more than one over-voltage condition.

The protection circuit 110 is thus used to detect the voltage level of the signal Rext, and in response to the normal operating condition of the signal Rext, output the signal Rext as the signal RextPC to the output terminal 112, and respond to the detected overvoltage condition of the signal Rext, The output has a voltage level close to or exactly the reference voltage VSS, so as to correspond to the signal RextPC of the low logic voltage level.

The example of the configuration of the protection circuit 110 shown in FIG. 1 is for illustration and not for limitation. In many embodiments, the protection circuit 110 additionally outputs the output signal Rext as the signal RextPC to the output terminal 112 (for example, by including one or more circuit components between the input terminal 111 and the output terminal 112) Detect and respond to the normal operating condition of the signal Rext, and detect and respond to the over-voltage condition of the signal Rext by outputting the signal RextPC with a low logic voltage level. In some embodiments, the protection circuit 110 does not include the detection circuit 114 and is used to receive a control signal from an external circuit (not shown) and/or to detect an overvoltage condition based on another signal other than the signal Rext. It is used to output a signal RextPC with the low logic voltage level in response to the detected over-voltage condition.

The protection circuit 110 is used to output a signal RextPC with a low logic voltage level, and the duration of this output is based on the timing characteristics of the detected overvoltage condition or the configuration of the detection circuit 114 and the clamp circuit 116 One or both. In operation, the output of the protection circuit 110 is detecting In the case of the signal RextPC with a high logic voltage level before and after the measured overvoltage condition, the signal RextPC with a low logic voltage level represents the duration of the logic inversion corresponding to the low logic voltage level of the protection circuit 110 The duration of the bit signal RextPC. In some embodiments, the case where the protection circuit 110 outputs the signal RextPC with a high logic voltage level before or after one or more logic inversions corresponds to the normal operation mode of the IC system 100.

In many embodiments, the protection circuit 110 is used to output the signal RextPC having a voltage level close to or just the reference voltage level. The duration of the output signal is a predetermined duration, a variable duration, or any duration of the two, depending on the nature of the detected overvoltage condition, for example, based on the detected electrostatic discharge event The predetermined duration, and the variable duration based on the detected electrical overload event.

In some embodiments, the protection circuit 110 is used to output a signal RextPC having a voltage level close to or just the reference voltage level, and the duration is one or both of a predetermined or variable duration. Its duration ranges from 0.1 microseconds to 100 microseconds. In some embodiments, the protection circuit 110 is used to output a signal RextPC having a voltage level close to or just the reference voltage level, and the duration is one or both of a predetermined or variable duration. Its duration ranges from 0.2 microseconds to 10 microseconds. In some embodiments, the protection circuit 110 is used to output a signal RextPC having a voltage level close to or just the reference voltage level, and the duration is one of a predetermined or variable duration. Or both, the duration ranges from 0.5 microseconds to 2 microseconds.

The IC chip 120 is a semiconductor chip and includes an input terminal 121 coupled to a power supply voltage node VDDN. The power supply voltage node VDDN is used for a power supply voltage VDD with a power supply voltage level. The IC chip 120 further includes a buffer circuit 122, and the buffer circuit 122 includes an input terminal 123 coupled to the signal path RST and the output terminal 124. The IC chip 120 also includes an input terminal 125 coupled to the reference voltage node VSSN, and one or more additional components not shown in FIG. 1 for the sake of clarity. In some embodiments, one or more of the input terminal 121, the input terminal 123, or the input terminal 125 includes a contact pad of the IC chip 120.

In some embodiments, the IC chip 120 includes a system on a chip (SoC). A single chip system includes multiple integrated circuits, such as processors, coprocessors, signal processing circuits, logic circuits, controllers, memory circuits, special application integrated circuits (ASICs), input/output (I/O) interfaces, Combinations of communication circuits or the like are all integrated in a single semiconductor chip.

At least one component of the IC chip 120 includes a power-on circuit (POC) (not shown) for initiating a power-on procedure in response to the signal Rint received by the output terminal 124. In operation, the power-on procedure includes one or more steps, so that at least a part of the IC chip 120, such as one or more registers, flip-flops, and/or latches, can be controlled to be used Operates in a normal operation mode, and the IC chip 120 is prohibited from being in the normal operation mode during the execution of the power-on procedure Which operates. In many embodiments, the power-on circuit is used to initiate a power-on process in response to a signal Rint having a high logic voltage level or a low logic voltage level. In many embodiments, one or more of the signal Rext, RextPC, or Rint is called a reset signal, the signal RextPC is called a protected signal or a protected reset signal, and/or the input terminal 123 is called a reset signal. Reset pin.

The buffer circuit 122 is a circuit for receiving the signal RextPC input terminal 123, generating a signal Rint based on the signal RextPC, and outputting the signal Rint at the output terminal 124. The buffer circuit 122 includes at least one buffer (not shown in FIG. 1) and at least one delay circuit 126. The delay circuit 126 is coupled between the input terminal 123 and the output terminal 124 in series. At least one buffer included in the buffer circuit 122 is coupled between the delay circuit 126 and the output terminal 124. In some embodiments, in addition to the above-mentioned components, the buffer circuit 122 also includes one or more other components (not shown), which are not shown or discussed further for illustrative purposes.

The delay circuit 126 includes an input terminal 127 and an output terminal 128. In many embodiments, the input terminal 127 is coupled to the input terminal 123 of the buffer circuit 122, or is coupled to a buffer of the buffer circuit 122 having at least one buffer. The output terminal 128 is coupled to the input terminal of the buffer of the buffer circuit 122 having at least one buffer.

The delay circuit 126 is used to increase the transition time of the signal OUT between the logic voltage level by inverting the signal IN received from the input terminal 127 and the transition time between the logic voltage level relative to the signal IN. The signal OUT is generated as described below. In many embodiments, the delay circuit 126 is used to increase one or both of the transition of the signal OUT from a low logic voltage level to a high logic voltage level, or a transition from a high logic voltage level to a low logic voltage level. Transition time.

By including the delay circuit 126, the buffer circuit 122 is used to increase the transition time between the logic voltage levels of the signal Rint, relative to the transition time between the logic voltage levels of the signal RextPC. In many embodiments, the buffer circuit 122 includes one of the following buffer circuits 222A or 222B corresponding to FIG. 2A and FIG. 2B, or includes the following buffer circuit 400 corresponding to FIG. 4.

The transition time of the signal RextPC corresponds to the transition time from the high logic voltage level to the low logic level. For example, in response to the overvoltage condition detected by the signal Rext, the protection circuit 110 outputs a voltage close to or exactly the reference voltage VSS. The beginning of the duration of the voltage level signal RextPC. The transition time of the signal Rint corresponds to the transition time from the high logic voltage level to the low logic level in some embodiments, or the transition time from the low logic voltage level to the high logic level in some embodiments. Corresponding to Figure 5, non-limiting examples of signal transition times are as follows.

In some embodiments, the delay circuit 126 includes a resistor-capacitor (RC) network (not shown in Figure 1), for example, as described below, the RC network corresponding to the delay circuits 300A to 300D in Figures 3A to 3D The delay circuit 126 is thus used to increase the transition time of the signal Rint relative to the transition time of the signal RextPC based on the signal OUT. In some embodiments, The delay circuit 126 includes an inverter delay, a counter, or other suitable circuit components, and is thereby additionally used to increase the transition time of the signal Rint relative to the transition time of the signal RextPC based on the signal OUT.

In many embodiments, at least one buffer and delay circuit 126 included in the buffer circuit 122 is used to output a signal Rint, which has the same low logic voltage level or high logic voltage as the input signal RextPC in the steady state. The synchronization signal of the level, or a complementary signal with a low logic voltage level or a high logic voltage level opposite to the input signal RextPC in the steady state.

At least one buffer included in the buffer circuit 122 is a circuit for responding to the threshold voltage of the output terminal relative to the buffer circuit (for example, the threshold voltage of a transistor), and an input terminal (not shown in FIG. 1) An input signal is received, and an output signal is generated at an output terminal (not shown in Figure 1). In many embodiments, the at least one buffer included in the buffer circuit 122 includes one or both of an inverter or a non-inverting circuit component (for example, an amplifier).

In some embodiments, the at least one buffer included in the buffer circuit 122 and the delay circuit 126 are used to increase the transition of the signal Rint based on the threshold voltage of the buffer coupled to the output terminal 128 and the transition time of the signal RextPC. time. In some embodiments, the threshold voltage corresponds to an NMOS transistor, and the transition time of the signal Rint corresponds to the time required for the signal OUT to climb from the reference voltage level of the reference voltage VSS to the threshold voltage. In some embodiments, the threshold voltage corresponds to a PMOS transistor, and the transition time of the signal Rint corresponds to the transition time of the signal OUT from the electric The time required for the power supply voltage level of the power supply voltage VDD to drop to the threshold voltage.

The delay circuit 126 is used for raising the signal OUT to the threshold voltage in response to the signal IN, and the signal IN has a first logic voltage level of a low logic voltage level or a high logic voltage level. The delay circuit 126 is also used for raising the signal OUT to one of the corresponding reference voltage level or the power supply voltage level in response to the signal IN. The signal IN has a second logic voltage level or a high logic voltage level. Logic voltage level.

In operation, because the output signal of the buffer coupled to the delay circuit 126 does not experience a transition from the first logic voltage level to the second logic voltage level, until the signal OUT reaches the threshold voltage, so if the signal IN is at the first The time length of the logic voltage level is less than the time required for the signal OUT to reach the threshold voltage, and the buffer output signal will not transition. The combination of the delay circuit 126 and the threshold voltage defines a time threshold so that when the time length of the signal IN having the first logic voltage level is less than the time threshold, the signal IN is prevented from causing a transition of the buffer output signal.

In some embodiments, the delay circuit 126 is used to define a time threshold for a given threshold voltage based on one or more expected logic inversion duration values of the signal RextPC output by the protection circuit 110, such as Described above. In some embodiments, the one or more expected values include a predetermined duration corresponding to an electrostatic discharge mode (for example, a human body discharge mode or a device charging mode).

In some embodiments, the IC system 100 does not include the protection circuit 110, and the delay circuit 126 is used based on a signal (for example, having the above-mentioned characteristics). One or more expected values of the logic inversion duration in the sexual signal RextPC) define the time threshold. The signal comes from another source other than the protection circuit 110 and is received by the buffer circuit 122. In some embodiments, the logic inversion in the signal received by the buffer circuit 122 corresponds to a transition from a low logic voltage level to a high logic voltage level, which is then followed by a transition from a high logic voltage level to a low logic voltage level. One transition.

Through the above configuration, the buffer circuit 122 can increase the transition time of the signal Rint with respect to the transition time of the signal RextPC, so that in response to the signal RextPC in the logic inversion duration less than the time threshold, the buffer circuit 122 is maintaining a given logic voltage. At the same time as the level, the signal Rint is output. In some embodiments, the buffer circuit 122 is additionally used to increase the transition time of the signal Rint relative to the transition time of the signal RextPC.

By increasing the transition time of the signal Rint with respect to the transition time of RextPC, the buffer circuit 122 is used to increase the transition time of a circuit receiving the signal Rint with respect to the signal RextPC, for example, with respect to the signal RextPC or Rext. A transition time of one or both. In some embodiments, the buffer circuit 122 is used to increase the transition time of the signal Rint relative to the transition time of the signal RextPC, and the increase is less than a predetermined response time, for example, it includes a specification of a circuit such as SoC. A response time.

In some embodiments, the buffer circuit 122 is used to increase the transition time of the signal Rint to a time ranging from 0.2 microseconds to 1000 microseconds. In some embodiments, the buffer circuit 122 is used to increase The transition time of the signal Rint is to a time, and the time ranges from 1 microsecond to 100 microseconds. In some embodiments, the buffer circuit 122 is used to increase the transition time of the signal Rint to a time ranging from 2 microseconds to 10 microseconds.

By including the delay circuit 126 and thereby used to increase the transition time of the signal Rint with respect to the transition time of the signal RextPC, the buffer circuit 122 can prevent the transition of the output signal from being reversed by the short-term logic of the input signal (such as short-term logic based on electrostatic discharge events). Reverse) trigger. Compared with some implementation methods that do not include a delay circuit, the buffer circuit 122 is more capable of generating an output signal with a fixed logic voltage level in response to the logic inversion of the short-term input signal.

In an IC system including the buffer circuit 122, such as the IC system 100, the power-on circuit that receives the signal Rint of a fixed voltage level responds to a logic inversion with a short enough duration to prevent unnecessary startup procedures.

FIG. 2A is a schematic diagram of a buffer circuit 222A according to some embodiments. The buffer circuit 222A can be used as the buffer circuit 122 in Figure 1 as described above.

The buffer circuit 222A includes an input terminal 123 and a delay circuit 126. The delay circuit 126 includes an input terminal 127 coupled to the input terminal 123. The input terminal 123, the delay circuit 126, and the input terminal 127 all correspond to FIG. 1, as described above. The buffer circuit 222A also includes an output terminal 224 and a number of N inverters INV1~INVN. The inverters INV1~INVN are coupled to the delay circuit 126 in series. Between the output terminal 128 and the output terminal 224. The output terminal 224 can be used as the output terminal 124, and the inverters INV1 to INVN can be used as at least one buffer of the buffer circuit 122, corresponding to FIG. 1, as described above. In many embodiments, the delay circuit 126 of the buffer circuit 222A includes one of the delay circuits 300A to 300D, corresponding to FIGS. 3A to 3D, as described below. In some embodiments, in addition to the above, the buffer circuit 222A further includes one or more components (not shown), which are not shown or discussed further for illustrative purposes.

Each of the inverters INV1 to INVN is a logic gate, and the logic gate is used to receive an input signal at an input terminal and generate a complementary output signal at an output terminal. In some embodiments, each of the inverters INV1~INVN includes a PMOS transistor (not shown), and the PMOS transistor and an NMOS transistor (not shown) are coupled in series to the power supply voltage VDD And between the reference voltage VSS. The gates of the PMOS and NMOS transistors are coupled together and used to receive input signals, and the drains of the PMOS and NMOS transistors are coupled together and used to generate output signals.

In the embodiment shown in FIG. 2A, the inverter INV1 includes one or more circuits (such as a Schmitt trigger) for transitioning from a low logic voltage level to a high logic voltage The threshold voltage setting of the level is higher than the threshold voltage of the transition from the high logic voltage level to the low logic voltage level to perform a hysteresis function. In operation, the hysteresis circuit functions to provide protection against transient phenomena triggered by noise whose scale is smaller than the threshold voltage, so the hysteresis circuit can be used as a noise filter. In some real In the embodiment, the inverter INV1 does not include one or more circuits for performing the hysteresis function.

In many embodiments, the buffer circuit 222A includes a delay circuit 126 and an odd-numbered N inverters INV1~INVN, so that the signal RDint is synchronized with the signal RextPC, and the buffer circuit 222A may include a delay circuit 126 and an even-numbered N inverters INV1~ INVN makes the signal RDint complementary to the signal RextPC.

In the embodiment shown in FIG. 2A, the buffer circuit 222A includes more than one inverter among the inverters INV1 to INVN. In some embodiments, the buffer circuit 222A includes inverters INV1 ˜INVN where the number N is equal to 1. In some embodiments, the buffer circuit 222A includes inverters INV1 ˜INVN. The number N ranges from 2 to 8. In some embodiments, the buffer circuit 222A includes inverters INV1 ˜INVN. The number N ranges from 3 to 5. In some embodiments, the buffer circuit 222A includes inverters INV1 ˜INVN where the number N is greater than 8.

The buffer circuit 222A is thus used to receive the signal RextPC at the input terminal 123 and to generate the signal RDint at the output terminal 224. The signal RDint has a longer transition time between multiple logic voltage levels than the signal RextPC. The generated signal RDint corresponds to the buffer circuit 122 used to generate the signal Rint in Figure 1 as described above, and in the embodiment where the output terminal 224 corresponds to the output terminal 124, the signal RDint can be used as the signal Rint.

FIG. 2B is a schematic diagram of the buffer circuit 222B according to some embodiments. Corresponding to Figure 1, the buffer circuit 222B can be used as the buffer circuit 122 Use as described above.

The buffer circuit 222B includes an input terminal 123, an output terminal 224, a delay circuit 126, and inverters INV1 to INVN, each of which corresponds to FIG. 2A and the buffer circuit 222A. In some embodiments, the buffer circuit 222B, in addition to the above, also includes one or more components (not shown), which are not shown or discussed further for illustrative purposes.

The buffer circuit 222B has a configuration consistent with the configuration of the buffer 222A described above, except that the delay circuit 126 is coupled between the two inverters of the inverters INV1~INVN, instead of being coupled to the input terminal 123 and the inverter. Between INV1. In the embodiment shown in FIG. 2B, at least two of the inverters INV1 to INVN are coupled between the input terminal 123 and the delay circuit 126. In some embodiments, the inverter INV1 is a single inverter among the inverters INV1 to INVN, and the inverter INV1 is coupled between the input terminal 123 and the delay circuit 126.

The buffer circuit 222B is thus used to receive the signal RextPC at the input terminal 123 and generate the signal RDint at the output terminal 224, corresponding to the manner of the above-mentioned FIG. 2A and the buffer 222A.

By including the delay circuit 126 and inverters INV1~INVN configured as described above, the respective buffer circuits 222A and 222B are used to increase the transition time of the signal RDint with respect to the transition time of the signal RextPC, and thus can achieve multiple benefits, such as As described above, with respect to the buffer circuit 122 and the IC system 100, the transition of the output signal triggered by the logic inversion of the short-term input signal is prevented.

3A to 3D are schematic diagrams of delay circuits 300A to 300D according to some embodiments. With respect to the aforementioned FIGS. 1 to 2B, each of the delay circuits 300A to 300D can be used like the delay circuit 126. In some embodiments, the delay circuits 300A to 300D are referred to as RC circuits.

Each of the delay circuits 300A to 300D includes an input terminal 127 for receiving a signal IN, an output terminal 128 for outputting a signal OUT, each of the power supply voltage node VDDN, and the reference voltage node VSSN is on Figure 1 to Figure 2B are discussed. Each of the delay circuits 300A to 300D also includes a resistive device R1. In the delay circuits 300A and 300B, the resistive device R1 is coupled between the output terminal 128 and the power supply voltage node VDDN. In the delay circuits 300C and 300D, the resistive device R1 is coupled to the output terminal 128 and the reference voltage node VSSN. between.

In some embodiments, the resistive device R1 is arranged in parallel with the capacitive device C1. The parallel arrangement is coupled between the output terminal 128 and the power supply voltage node VDDN in the delay circuits 300A and 300B. This parallel arrangement Arranged in the delay circuits 300C and 300D, they are coupled between the output terminal 128 and the reference voltage node VSSN. In some embodiments, the parallel arrangement of the resistive device R1 and the capacitive device C1 coupled to the output terminal 128 and the power supply voltage node VDDN or the reference voltage node VSSN is called an RC network.

In some embodiments, the resistive device R1 is arranged in series with the capacitive device C1, and the capacitive device C1 is in the delay circuit 300A. And 300B is coupled between the output terminal 128 and the reference voltage node VSSN, and the capacitive device C1 is coupled between the output terminal 128 and the power supply voltage node VDDN in the delay circuits 300C and 300D. In some embodiments, the series arrangement of the resistive device R1 and the capacitive device C1 coupled to the output terminal 128 and the power supply voltage node VDDN or the reference voltage node VSSN is called an RC network.

The delay circuits 300A and 300B include an NMOS transistor N1. The NMOS transistor N1 is coupled between the output terminal 128 and the reference voltage node VSSN, and the NMOS transistor N1 has a gate coupled to the input terminal 127. Compared with the delay circuit 300A, the delay circuit 300B further includes at least one PMOS transistor P2~PM. The PMOS transistors P2~PM are coupled in series between the output terminal 128 and the resistive device R1, and each of the transistors P2~PM One has a gate coupled to the input terminal 127.

The delay circuits 300C and 300D include a PMOS transistor P1, and the PMOS transistor P1 is coupled between the output terminal 128 and the power supply voltage node VDDN, and the PMOS transistor P1 has a gate coupled to the input terminal 127. Compared with the delay circuit 300C, the delay circuit 300D further includes at least one NMOS transistor N2~NM. The NMOS transistor N2~NM is coupled in series between the output terminal 128 and the resistive device R1, and each of the transistors N2~NM One has a gate coupled to the input terminal 127.

In many embodiments, the resistive device R1 includes an IC device, such as a part of polysilicon and/or a metal or other A layer of a suitable material with a predetermined resistance value to operate as a resistor in the delay circuits 300A to 300D.

In many embodiments, the capacitive device C1 includes one or more IC devices, and one or more IC devices are used according to the corresponding first or second predetermined capacitance value and thus used as one of the delay circuits 300A~300D. The capacitor is operated. In many embodiments, the capacitive device C1 includes a metal-insulator-metal (MIM) capacitor, a transistor configured as a capacitor, or another IC device suitable for providing a controlled capacitance value.

In operation, the parallel or series arrangement of the resistive device R1 and the capacitive device C1 configured as described above functions to control a rate, which means that the corresponding transistor N1 or P1 is sent from the power supply voltage node at the output terminal 128 After the VDDN or the reference voltage node VSSN is decoupled, the voltage level of the output terminal 128 is increased to the corresponding rate at which another power supply voltage node VDDN or the reference voltage node VSSN.

Corresponding to the predetermined rate used by the delay circuits 300A to 300D to pull up the signal OUT, the resistive device R1 has a predetermined resistance value and the capacitive device C1 has a predetermined capacitance value. In operation, in the delay circuits 300A and 300B, the resistive device R1 is coupled between the output terminal 128 and the power supply voltage node VDDN, and is coupled to the output terminal 128 and the power supply voltage node VDDN or the reference voltage node The capacitive device C1 between one of the VSSNs causes the signal OUT to rise from the logic low voltage level to the logic high voltage level at a predetermined rate. In the delay circuits 300C and 300D, they are coupled to the output terminal 128 and the reference voltage node The resistive device R1 between VSSN and the capacitive device C1 coupled between the output terminal 128 and one of the power supply voltage node VDDN or the reference voltage node VSSN cause the signal OUT to change from a logically high voltage level at a predetermined rate The bit drops to a logic low voltage level.

Through the above configuration, in operation, when the signal IN has a high logic voltage level, at least one transistor P2~PM in the delay circuit 300B electrically isolates the resistive device R1 from the output terminal 128, so as to be relative to the delay circuit 300A, reducing a leakage current between the power supply voltage level VDDN and the output terminal 128. In many embodiments, the delay circuit 300B includes at least one transistor P2~PM of M, and the number M ranges from 1 to 8.

Similarly, through the above configuration, in operation, when the signal IN has a low logic voltage level, at least one transistor N2~NM of the delay circuit 300D electrically isolates the resistive device R1 from the output terminal 128, thereby The delay circuit 300C reduces a leakage current between the reference voltage level VSSN and the output terminal 128. In many embodiments, the delay circuit 300D includes at least one M transistors N2˜NM, and the number M ranges from 1 to 8.

The configurations of the delay circuits 300A to 300D shown in FIGS. 3A to 3D and described above are non-limiting examples, so that in operation, the signal OUT is raised to the power supply voltage node VDDN or VDDN at a predetermined rate. One of the reference voltage nodes VSSN. In many embodiments, an RC circuit, such as one of the delay circuits 300A to 300D, includes at least one resistive device and at least one capacitive device, and these devices It is set in operation to control the rate at which a signal, such as the signal OUT, is raised to one of the power supply voltage level VDDN or the reference voltage level VSSN.

Through the above configuration, each of the delay circuits 300A to 300D can increase the transition time of the signal OUT relative to the transition time of the signal IN. By being included in the buffer circuit, such as the buffer circuit 122 and each of the delay circuits 300A to 300D, the above benefits can be achieved corresponding to the buffer circuit 122 and the IC system 100.

Figure 4 is a schematic diagram of a buffer circuit according to some embodiments. Corresponding to FIG. 1, the buffer circuit 400 can be used as the buffer circuit 122 as described above.

The buffer circuit 400 includes an input terminal 123 and an output terminal 124, respectively corresponding to FIG. 1 to FIG. 2B, as described above. The buffer circuit 400 also includes a buffer circuit 422 coupled to the input terminal 123, a logic circuit 430 coupled to the input terminal 123, and a logic circuit 440 coupled to the output terminal 124. The buffer circuit 422 includes the output terminal 224 and one of the buffer circuits 222A or 222B, respectively corresponding to FIG. 2A and FIG. 2B, as described above. The output terminal 224 is coupled to the first input terminal (not labeled) of the logic circuit 440, and the logic circuit 430 includes an output terminal (not labeled), and the output terminal (not labeled) is coupled to the second input of the logic circuit 440 Terminal (unmarked).

The logic circuit 430 includes at least one logic device (not shown) and is thereby used to output a signal RinPC to the second input terminal of the logic circuit 440 based on the input signal RextPC, corresponding to FIG. 1 to FIG. 2B, such as As mentioned above. In some embodiments, the at least one logic device includes at least one buffer coupled between the input terminal 123 and the output terminal of the logic circuit 430. In some embodiments, corresponding to FIG. 2A and FIG. 2B as described above, at least one logic device includes a plurality of inverters coupled in series between the input terminal 123 and the output terminal of the logic circuit 430, the inverter The number of inverters is greater than the number N of inverters INV1~INVN mentioned above.

The logic circuit 440 includes at least one logic device (not shown) and is used to receive the signal RDint from the buffer circuit 422 except for the signal RinPC from the logic circuit 430, and to be based on the signals RDint and RinPC. The output signal Rint is output to the output terminal 124, each corresponding to FIG. 1 to FIG. 2B, as described above. In some embodiments, at least one logic device includes a NAND gate, and the NAND gate includes the first and second input terminals of the logic circuit 440. The at least one logic device also includes at least one buffer coupled in series between the NAND gate and the output terminal 124.

In some embodiments, one or both of the logic circuit 430 or 440 includes one or more input terminals and/or output terminals other than those shown in FIG. 4, and the buffer circuit 400 is thus used based on One or more signals other than the signal RextPC generate a signal Rint and/or one or more signals other than the signal Rint (not shown).

By including the logic circuits 430 and 440 in addition to the buffer circuit 422, the buffer circuit 400 is used to generate a signal Rint with higher flexibility than the aforementioned buffer circuits 122, 222A, and 222B. By including the buffer circuit 422, and the buffer circuit 422 includes the buffer circuit 222A Or one of 222B, the buffer circuit 400 can increase the transition time of the signal Rint relative to the transition time of the signal RextPC, so as to achieve benefits, such as the buffer circuit 122 and the IC system 100 as described above, preventing short-term input The output signal transition triggered by the signal logic inversion.

FIG. 5 is a representation diagram of the operating parameters of the buffer circuit according to some embodiments. Figure 5 shows non-limiting examples of many signals as a function of time: the signal IN1 or IN2 received by the delay circuit, the corresponding signal OUT1 or OUT2 generated by the delayed signal, and the buffer circuit including the delayed signal (for example, including The signal generated by the buffer circuit 122) of the delay circuit 126 is Reset.

The signals IN1 and OUT1, corresponding to the above-mentioned Figures 1 to 3D, are non-limiting examples corresponding to the signals IN and OUT in an embodiment. In this embodiment, the delay circuit 126 is relatively high relative to the signal IN. The transition time from the logic voltage level to the low logic voltage level increases the transition time for the signal OUT from the low logic voltage level to the high logic voltage level. The signals IN2 and OUT2 correspond to non-limiting examples of the signals IN and OUT in an embodiment. The delay circuit 126 in this embodiment corresponds to the transition time of the signal IN from a low logic voltage level to a high logic voltage level. Increase the transition time of the signal OUT from the high logic voltage level to the low logic voltage level. The signal Reset, corresponding to Figures 1 to 4 described above, is a non-limiting example of the signal Rint.

Each of the signals IN1, IN2, OUT1, OUT2, and Reset is drawn relative to a high logic level H and a low logic level L Show. In many embodiments, the high logic level H corresponds to a high logic voltage level or threshold voltage, such as the threshold voltage of a buffer, and the low logic level L corresponds to a low logic voltage level or threshold voltage, such as the threshold voltage of a buffer. Critical voltage.

Before time t1, the signal IN1 has a high logic level H and the signal OUT1 has a low logic level L. From time t1 to time t2, the signal IN1 transitions and remains at the low logic level L, while the signal IN1 returns to the high logic level H at this time. The signal IN1 having a low logic level L represents that the logic inversion has a duration from time t1 to time t2. At time t1, the signal OUT1 is increased from the low logic level L to the high logic level H, and the rate of increase is determined by the configuration of the delay circuit 126. Based on the relatively increased transition time, the signal OUT1 remains below the high logic level H at time t2. At this time, the signal OUT1 returns to the high logic level H and returns to the low logic level L in response to the signal IN1.

Before time t1, the signal IN2 has a low logic level L and the signal OUT2 has a high logic level H. From time t1 to time t2, the signal IN2 transitions and remains at the high logic level H, while the signal IN2 returns to the low logic level L at this time. The signal IN2 having a high logic level H represents that the logic inversion has a duration from time t1 to time t2. At time t1, the signal OUT2 falls from the high logic level H to the low logic level L, and the falling rate is determined by the configuration of the delay circuit 126. Based on the relatively increased transition time, the signal OUT2 remains higher than the low logic level L at time t2. At this time, the signal OUT2 returns to the low logic level L and returns to the high logic level H in response to the signal IN2.

In the first embodiment, since the signal OUT1 remains below the high logic level H during the entire process of the logic inversion of the signal IN1, the buffer of the buffer circuit 122 receiving the signal OUT1 is not between the logic voltage levels. Transition, and the buffer circuit 122 outputs a signal Reset with a constant level corresponding to the high logic level H or the low logic level L.

Similarly, in the second embodiment, since the signal OUT2 remains higher than the low logic level L during the entire process of the logic inversion of the signal IN2, the buffer of the buffer circuit 122 receiving the signal OUT2 is not at the logic voltage. There is a transition between the levels, and the buffer circuit 122 corresponding to the high logic level H or the low logic level L outputs a signal Reset with a constant level.

FIG. 6 is a flowchart of a method 600 of operating a buffer circuit according to some embodiments. The method 600 can be used for a buffer circuit, such as the buffer circuit 122, 222A, 222B, or 400 corresponding to FIGS. 1 to 4 as described above. The method 600 is also applicable to an IC system including a buffer circuit, such as the IC system 100 including the buffer circuit 122 corresponding to FIG. 1 as described above.

The sequence of the operations of the method 600 shown in FIG. 6 is for illustration only; the operation system of the method 600 can be performed in a sequence different from that shown in FIG. 6. In some embodiments, operation steps other than the operation steps shown in FIG. 6 are performed before, during, during, or after the operation steps shown in FIG. 6. In some embodiments, some or all of the operation steps of the method 600 are part of the operation of the SoC (for example, including the SoC included in the IC chip 120 corresponding to FIG. 1 described above).

In operation 610, in some embodiments, the logic signal is Output from the overvoltage protection circuit. The output logic signal includes outputting any one of a high logic voltage level or a low logic voltage level, and has a corresponding transition from a high logic voltage level to a low logic voltage level or a transition from a low logic voltage level to a high logic voltage level One or both of the logic signals for the first transition time.

In some embodiments, outputting the logic signal from the overvoltage protection circuit includes outputting the signal RextPC from the protection circuit 110, corresponding to FIG. 1, as described above. In some embodiments, outputting a logic signal includes outputting a logic signal including a logic inversion, as described above, corresponding to FIG. 1 to FIG. 5.

In operation 620, the logic signal is received at the input terminal of the buffer circuit. Receiving the logic signal also includes receiving the logic signal with the first transition time. In some embodiments, receiving a logic signal includes receiving a logic signal with a logic inversion, as described above corresponding to FIG. 1 to FIG. 5.

In some embodiments, receiving the logic signal at the input terminal of the buffer circuit includes receiving the signal RextPC at the input terminal 123 of the buffer circuit 122, which corresponds to FIG. 1 to FIG. 2B and FIG. 4 as described above.

In some embodiments, receiving the logic signal at the input terminal of the buffer circuit includes receiving the logic signal at the input pad of the IC chip (for example, the IC chip 120 including SoC, as described above corresponding to FIG. 1).

In operation 630, the logic signal is sequentially inverted by the RC circuit and the buffer. Inverting the logic signal sequentially by the RC circuit and the buffer includes first inverting the logic signal through the RC circuit, and then inverting the signal through the buffer. The RC circuit is coupled to the input terminal of the buffer, and the transparent Inverting the logic signal through the RC circuit also includes using the resistive device of the RC network to couple the input terminal of the buffer to one of the power supply voltage node or the reference voltage node.

Using an RC circuit to invert the logic signal includes coupling the input terminal of the buffer to one of the power supply voltage node or the reference voltage node by using an RC network to change the transition time of the logic signal from the first transition time Increase to the second transition time.

In some embodiments, one of using the resistive device of the RC network to couple the input terminal of the buffer to the power supply voltage node or the reference voltage node also includes using a transistor to transfer the input signal from the power supply The other of the voltage node or the reference voltage node is decoupled.

In some embodiments, using the RC circuit to invert the logic signal includes using one of the delay circuits 300A to 300D to invert the signal IN to generate the signal OUT, as described above corresponding to FIGS. 3A to 3D.

In some embodiments, using an RC network to couple the input terminal of the buffer to one of the power supply voltage node or the reference voltage node includes using the RC network to couple the input terminal of the buffer including a hysteresis circuit. In some embodiments, using an RC network to couple the input terminal of the buffer to one of the power supply voltage node or the reference voltage node includes using an RC network to couple the input terminals of the inverters INV1 to INVN, as described above The above corresponds to Fig. 2A and Fig. 2B.

In many embodiments, using the RC circuit to invert the logic signal includes inverting the logic signal received by the input terminal of the buffer circuit, or the logic signal has been buffered between the input terminal of the buffer circuit and the buffer between the RC circuit. After reversing, reverse again.

In some embodiments, using a buffer to invert the logic signal includes using a plurality of buffers to sequentially invert the logic signal. In some embodiments, using a buffer to invert the logic signal includes using one or more buffers INV1 to INVN to invert the logic signal, as described above, corresponding to FIG. 2A and FIG. 2B.

In operation 640, the sequentially inverted logic signal is output from the output terminal of the buffer circuit. Outputting the sequentially inverted logic signal from the buffer circuit includes outputting the inverted logic signal with the second transition time. In many embodiments, outputting the sequentially inverted logic signal from the buffer circuit includes outputting the inverted logic signal synchronized with the received logic signal or the complementary signal of the received logic signal.

In some embodiments, the logic signal whose output is sequentially inverted includes the output signal Rint, which corresponds to FIG. 1 to FIG. 5 as described above. In some embodiments, the logic signal whose output is sequentially inverted includes the output signal RDint, which corresponds to FIG. 2A, FIG. 2B, and FIG. 4 as described above.

In some embodiments, outputting the sequentially inverted logic signal includes outputting a reset signal of an IC chip (for example, an IC chip 120 including SoC, corresponding to FIG. 1 as described above).

By performing some or all of the operations of the method 600, the buffer circuit outputs a logic signal with a longer transition time between the logic voltage levels relative to the received logic signal, thereby obtaining the logic signal corresponding to the IC system 100 as described above. And the benefits of buffer circuits 122, 222A, and 222B.

In some embodiments, the buffer circuit includes an input terminal, an output terminal, a buffer, and a resistance-capacitance circuit. The resistance-capacitance circuit and the buffer are coupled in series between the input terminal and the output terminal, wherein the resistance-capacitance circuit is Used to increase a transition time between a plurality of logic voltage levels of an output signal generated at the output terminal relative to a transition time between a plurality of logic voltage levels of an input signal received at the input terminal , And the transition time of the output signal is based on a duration of a logical inversion of the input signal. In some embodiments, the resistance-capacitance circuit includes a first transistor, the first transistor and a resistance-capacitance network are coupled in series between a power supply node and a reference node, and the resistance-capacitance network A resistor is included, and the resistor is connected in parallel with a capacitor. In some embodiments, the first transistor system is an NMOS transistor. In some embodiments, the resistance-capacitance circuit further includes a second transistor coupled in series between the first transistor and the resistance-capacitance network, the first and second transistor systems Different transistor types, a gate of each of the first and second transistors is coupled to an input terminal of the resistance-capacitance circuit, and a drain of each of the first and second transistors The pole system is coupled to an output terminal of the resistance-capacitance circuit. In some embodiments, the resistance-capacitance circuit includes a transistor coupled in series with a resistor between a power supply node and a reference node, and a capacitor, the capacitor and the transistor are arranged in parallel. In some embodiments, the buffer includes a hysteresis circuit. In some embodiments, the buffer includes an inverter. In some embodiments, the resistance-capacitance circuit is coupled between the buffer and the input terminal. In some embodiments, the buffer is multiple One of the buffers is coupled between a whole of the plurality of buffers and the input terminal.

In some embodiments, a system includes an overvoltage protection circuit for generating a protected signal at an output terminal of the overvoltage protection circuit, and a buffer circuit for generating a buffer circuit output at the output terminal of a buffer circuit Signal. The buffer circuit includes an input terminal, the input terminal is coupled to the overvoltage protection circuit output terminal, a buffer, and a resistance capacitance circuit, the resistance capacitance circuit and the buffer are coupled in series to the input terminal and the buffer Between the output terminals of the circuit, wherein the resistance-capacitance circuit is used to increase the transition time between the output signal of the buffer circuit between the multiple logic voltage levels relative to a transition time between the multiple logic voltage levels of the protected signal A transition time. In some embodiments, the buffer circuit is a part of an integrated circuit chip separated from the overvoltage protection circuit, and the input terminal of the buffer circuit includes a contact pad of the IC chip. In some embodiments, the overvoltage protection circuit includes a switching device, and the switching device is used for generating by coupling the output terminal of the overvoltage protection circuit to a reference node responsive to a detected voltage level The protected signal. In some embodiments, the resistance-capacitance circuit is used to increase the transition time of the output signal of the buffer circuit based on a threshold voltage of the buffer. In some embodiments, the overvoltage protection circuit is used to couple the output terminal of the overvoltage protection circuit to the reference voltage node for a duration based on an electrostatic discharge model, and the resistance-capacitance circuit is used for the resistance-capacitance The circuit is used to increase the transition time of the output signal of the buffer circuit based on the duration. In some embodiments, the buffer circuit is a single chip system A component of the system, the single chip system is used to perform a reset operation in response to the output signal of the buffer circuit. In some embodiments, the resistance-capacitance circuit includes an NMOS transistor coupled to a gate of the input terminal of the buffer circuit, a source terminal coupled to a reference node, and a source terminal coupled to the buffer circuit. A drain terminal of an input terminal of the buffer, and a resistor-capacitor network. The resistor-capacitor network includes a parallel configuration of a resistor and a capacitor, and the parallel configuration is coupled to the drain terminal of the NMOS transistor Between the sub and a power supply node of the integrated circuit chip. In some embodiments, the resistance-capacitance circuit further includes a PMOS transistor. The PMOS transistor includes a gate coupled to the input terminal of the buffer circuit, and a gate coupled to the drain terminal of the NMOS transistor. A drain terminal and a source terminal coupled to the resistance-capacitance network.

In some embodiments, a method of operating a buffer circuit includes receiving a logic signal at an input terminal of the buffer circuit, using each of a resistor-capacitor circuit and a buffer to sequentially invert the logic signal, and the resistor The capacitor circuit is coupled to an input terminal of the buffer, and outputs the logic signal sequentially inverted at an output terminal of the buffer circuit, wherein the step of using the resistor capacitor circuit to invert the logic signal includes using a resistor The capacitor network couples the input terminal of the buffer to one of a power supply voltage node or a reference voltage node. In some embodiments, using the resistor-capacitor network to couple the input terminal of the buffer to one of the power supply voltage node or the reference voltage node includes using a transistor for the input of the buffer The terminal is decoupled from the other of the power supply voltage node or the reference voltage node. In some embodiments, Receiving the logic signal at the input terminal of the buffer circuit includes receiving the logic signal by an input pad of a single chip system, and outputting the sequentially inverted logic signal includes outputting a reset signal of the single chip system .

The features or examples of several embodiments are summarized above, so that those skilled in the art can better understand the aspect of the present disclosure. Those who are familiar with the technology should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures in order to implement the same purpose and/or achieve the same advantages of the embodiments or examples introduced herein. Those familiar with this technology should also realize that such equivalent structures do not depart from the spirit and scope of this disclosure, and can produce various changes, substitutions and alterations in this article without departing from the spirit and scope of this disclosure. .