Atomic layer deposition of iii-v compounds to form v-nand devices

Atomic layer deposition of Group III to V compounds to form V-NAND devices

ATOMIC LAYER DEPOSITION OF III-V COMPOUNDS TO FORM V-NAND DEVICES

<b>[Cross reference of related applications]</b>

This application claims the rights and priority of provisional application No. 62/272,345 filed on December 29, 2015 entitled "Atomic Layer Deposition of Group III to V Compounds to Form V-NAND Devices", the content of which is quoted The method is incorporated into this article and does not conflict with the content of this disclosure.

The present invention is in the field of semiconductor manufacturing. In detail, the specific example of the present invention relates to the formation of a vertical non-AND (V-NAND) gate device by atomic layer deposition (ALD), chemical vapor deposition (CVD) or interface pretreatment before semiconductor material deposition.

For example, V-NAND devices are logic gates that can be embedded in vertical three-dimensional structures such as flash memory. V-NAND devices include channels for conducting signals. Currently, channels are usually made of polysilicon layers, usually deposited by low pressure chemical vapor deposition (LPCVD).

The channels can be formed in narrow, deep cylindrical openings that are approximately 80 nm wide and 2 μm deep. The channel itself can be about 10 nm thick. The rest of the cylindrical opening can be thought of as a "Macaroni" structure of silicon dioxide (SiO₂)filling.

The conductivity of a polysilicon channel can depend on the length and width of the channel. along with V-NAND devices are further scaled to be smaller, the length of the channel becomes longer and the width becomes narrower. As a result, the current through the channel is reduced, resulting in a reduction in the speed of the V-NAND device. In addition, other factors that potentially affect the conductivity of the polysilicon channel include the intrinsic mobility of electrons in the silicon and the resistance induced by the grain boundaries in the polysilicon.

The conductivity of the channel is critical because it can directly affect the read and write speed of the V-NAND device in the memory device. Due to the structure of the memory device, conductivity is critical. At present, the memory cell is formed by a tunnel dielectric, a trapping material, a blocking oxide, and a polysilicon channel above the control gate. This is basically a channel where many transistors are stacked vertically on top of each other. The completed vertical channel may consist of a series of transistors, for example 32 or more than 32 transistors. Therefore, due to the possibility of vertical alignment of many transistors, the conductivity or speed of the channel will become increasingly important.

In a typical logic device, a single crystal channel material is preferably used. However, there is currently no feasible way to fabricate monocrystalline channels in V-NAND channels. For example, bottom-up selective epitaxial growth may take a very long time and is very expensive to manufacture. For these reasons, a conformal LPCVD polysilicon layer is currently used to form V-NAND devices. Therefore, there is a need for a method for forming stable channel materials for V-NAND devices having the necessary necessary conductivity.

According to a specific example of the present invention, a method of forming a channel for a V-NAND device is disclosed. The method includes: providing a substrate having an opening; depositing a semiconductor material in the opening via atomic layer deposition to form a channel layer; And filling the remaining part of the opening with a dielectric material.

According to a specific example of the present invention, a method for forming a structure is disclosed. The method includes: providing a substrate having a surface containing an oxide; pretreating the oxide surface; A semiconductor material is deposited on the surface; wherein the pretreatment includes a gallium compound and an oxygen compound.

According to a specific example of the present invention, a method of forming a channel for a V-NAND device is disclosed. The method includes: providing a substrate having an opening; preprocessing a surface formed in the opening; A semiconductor material is deposited in the opening to form a channel layer; and the remaining part of the opening is filled with a dielectric material.

According to a specific example of the present invention, a method for forming a channel for a V-NAND device is disclosed. The method includes: providing a substrate having an opening; and depositing a first semiconductor material in the opening via atomic layer deposition to form the channel Layer; and filling the remaining portion of the opening with a second semiconductor material.

According to a specific example of the present invention, a method of forming a channel for a V-NAND device is disclosed. The method includes: providing a substrate having a cylindrical opening; preprocessing the surface formed in the cylindrical opening; Layer deposition deposits a first group III-V material in the cylindrical opening to form a channel layer; and fills the remaining part of the cylindrical opening with a second semiconductor material.

According to a specific example of the present invention, a method for performing pretreatment before depositing channels for V-NAND devices is disclosed. The method includes: performing a cyclic pretreatment process, which includes pulses of the first metal reactant and non-metal reactions And performing a second pulse containing a second metal reactant in the opening of the channel to be deposited; wherein the cyclic pretreatment process improves the adhesion of the material to be deposited in the opening.

In order to summarize the present invention and the advantages achieved with respect to the prior art, some objectives and advantages of the present invention have been described above. Of course, it should be understood that not all of these objects or advantages can be achieved according to any specific example of the present invention. Therefore, for example, those with ordinary knowledge in the technical field to which the invention belongs will understand that the invention can be embodied or implemented in a way that realizes or optimizes an advantage or a group of advantages as taught or suggested herein, without having to realize as taught or suggested herein. Or suggest other purposes or advantages.

These specific examples are intended to fall within the scope of the invention disclosed herein. For those of ordinary knowledge in the technical field to which the invention belongs, it is obvious from the detailed descriptions of some specific examples and the reference drawings below that these specific examples and other specific examples, and the present invention is not limited to any specific specific examples disclosed. .

<p>100Provide substrates with openings</p><p>110Deposit the first material to form the channel layer</p><p>120Fill the remaining openings with the second material</p><p>200Provide substrate with openings</p><p>210ALD pretreatment to improve adhesion</p><p>220Deposit the first material to form the channel layer</p><p>230Fill the remaining openings with the second material</p><p>300Provide substrate with openings</p><p>310Deposit the first material to form the channel layer</p><p>320Fill the remaining openings with the second material</p><p>400Substrate provided</p><p>410ALD pretreatment to improve adhesion</p><p>420Deposit the first material to form the channel layer</p><p>430Fill the remaining openings with the second material</p><p>500Provide silicon oxide surface</p><p>510Halide precursor pretreatment</p><p>520Alkylsilyl compound precursor pulse</p><p>530Metal halide precursor pulse</p>

The following describes these and other features, aspects and advantages of the present invention disclosed herein with reference to the drawings of some specific examples, which are intended to illustrate rather than limit the present invention.

Fig. 1 is a flowchart of a method according to at least one specific example of the present invention.

Fig. 2 is a flowchart of a method according to at least one specific example of the present invention.

Fig. 3 is a flowchart of a method according to at least one specific example of the present invention.

Fig. 4 is a flowchart of a method according to at least one specific example of the present invention.

Fig. 5 is a flowchart of a method according to at least one specific example of the present invention.

It should be understood that the elements in the drawings are shown for brevity and clarity, and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be enlarged relative to other elements to help understand the specific examples shown in the present disclosure.

Although some specific examples and embodiments are disclosed below, those skilled in the art to which the invention pertains will understand that the present invention extends beyond the specific examples and/or uses specifically disclosed by the present invention, as well as obvious changes and equivalents thereof. Therefore, it is intended that the scope of the disclosed invention should not be limited by the specific disclosed examples described below.

A specific example of the present invention relates to a method of manufacturing or processing a V-NAND device. In detail, the method includes manufacturing channel materials or processing channel materials to achieve optimal performance and stability. Specific examples of the present invention can be carried out in batch, small batch or single wafer reactors.

Figure 1 depicts a method according to the invention. The method includes a step 100 of providing a substrate. The substrate for providing step 100 has an opening that can be formed through, for example, etching. The substrate opening seen from above the substrate in the bird's-eye view may be circular, square, rectangular, or other shapes. The substrate opening may additionally extend into the substrate, resulting in a three-dimensional shape, such as a cylindrical shape, a cubic shape, a through-hole shape, a tapered three-dimensional shape, or other shapes. After providing step 100, an additional step of forming or depositing additional layers (ie, tunnel dielectric, trapping material, and/or blocking oxide) is performed.

The method includes a step 110 of depositing a first material to form a channel layer. The first material may be a compound semiconductor material. Suitable compound semiconductor materials may include group III-V materials, group II-VI materials, and group IV-VI materials. The deposition step 110 may be accomplished through atomic layer deposition (ALD), chemical vapor deposition (CVD) or other cyclic deposition processes to produce a layer for the channel layer, in some specific examples the channel layer is polycrystalline. ALD can provide the advantages of high conformal deposition in high aspect ratio structures that are similar to structures in V-NAND applications. Group III-V materials that can be used in the deposition step 110 include: gallium arsenide (GaAs); gallium antimonide (A); indium phosphide (InP); gallium nitride (GaN); indium antimonide (InSb); Indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide. In some concrete In an example, the III-V group material can be deposited by an ALD process, and the group III-V material includes an alkyl silyl compound of As or Sb and/or a halide of a group 13 element (such as Al, Ga, and In) (Such as chloride). Group II-VI materials that can be used in the deposition step 110 include: zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium telluride (CdTe), and selenide Cadmium (CdSe). Group IV-VI materials that can be used in the deposition step 110 include: tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), tellurium Germanium (GeTe) and tin telluride (SnTe).

Other materials that may be deposited by atomic layer deposition in the deposition step 110 may include semiconductor materials such as germanium (Ge), silicon germanium (SiGe), germanium selenide (GeSe), zinc oxide (ZnO), zinc oxynitride ( ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), tin selenide (SnSe), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin ( GeSn), diamond, tungsten sulfide (WS₂) Or Boron Nitride Carbide (BNC). The applicability of the aforementioned materials depends on the availability of the forming process and a sufficiently high internal mobility.

The channel layer formed in the deposition step 110 may be about 10 nm thick. The method also includes a step 120 of filling the remaining openings with a second material. Materials that can be used in the filling step 120 include silicon oxide (such as silicon dioxide, hafnium oxide, or aluminum oxide), polysilicon, or other conductive materials. Each of the steps discussed above can be repeated and sequenced in a different order to allow the formation of desired channels.

Figure 2 depicts a method according to the invention. The method includes a step 200 of providing a substrate. The substrate for providing step 200 has an opening that can be formed through, for example, etching. The substrate opening seen from above the substrate in the bird's-eye view may be circular, square, rectangular, or other shapes. The substrate opening may additionally extend into the substrate, resulting in a three-dimensional shape, such as a cylindrical shape, a cubic shape, a through-hole shape, a tapered three-dimensional shape, or other shapes. After the step 200 of providing, forming or depositing another The additional step of the layer (ie tunnel dielectric, trapping material and/or blocking oxide).

The method includes a pretreatment step 210, such as cyclic pretreatment, to improve adhesion. The pretreatment step 210 can be used to help attach ALD-grown compound semiconductor films (such as group III-V materials) on the surface. In other specific examples, CVD or other cyclic deposition processes can be used. For example, the surface may include a dielectric material, such as a silicon oxide-based dielectric used as a tunnel oxide in the V-NAND structure, so that the formed V-NAND device has greater stability. The pretreatment step 210 may include a first pulse of a combination of a metal reactant and a non-metal reactant. The pretreatment step 210 may additionally include a second pulse of the metal reactant.

In a specific example according to the present invention, the III-V group material (such as GaSb) is deposited onto the hot SiO at the beginning₂The pre-processing step 210 on the substrate may include several GaCl₃With H₂O's pulse. The deposition can also be performed on high-k materials. The pretreatment step 210 may include gallium trichloride (GaCl₃) The first pulse with water. Can be carried out including Sb (SiMe₃)₃With GaCl₃The second pulse of the deposition step 220. The first pulse or the second pulse can be repeated as needed. Typical pulse lengths can range from about 0.05 to 20 seconds, about 0.1 to 5 seconds, or about 0.2 to 2 seconds. However, if necessary, such as in the case of high conformal step coverage for extremely high aspect ratio structures or structures with high surface area or other structures with complex surface morphology, or in the case of batch reactors, other structures can be used. Pulse length. Similarly, typical removal/purging times are about 0.05 to 20 seconds, about 0.5 to 10 seconds, or about 1 to 5 seconds. However, if necessary, such as in the case of high conformal step coverage for extremely high aspect ratio structures or structures with high surface area or other structures with complex surface morphology, or in the case of batch reactors, other structures can be used. Removal/purging time.

<tables><img file="TWI728021B_D0001.tif" /></tables>

Chemicals that can be used as the metal reactant of the first pulse of the pretreatment step 210 include metal compounds. The metal compound may include metal organic or organometallic compounds, such as: metal organic or organometallic compounds of group 13 or 15 elements; metal organic or organometallic compounds of gallium or antimony; or metal halides, such as metal chlorides, Semi-metal halide, semi-metal chloride, gallium trichloride (GaCl₃) And other gallium halides. Chemicals that can be used as non-metallic reactants for the second pulse of the pretreatment step 210 include oxygen-containing reactants, such as H₂O, H₂O₂, O₃, And plasma and free radicals incorporating oxygen. Other non-metallic reactants may include chemicals with hydroxide groups and the like. The first pulse and the second pulse of the preprocessing step 210 can be performed in any order. In some specific examples, the pre-processing step 210 may include₂O₃The material is deposited on the substrate. In some specific examples, the pre-processing step 210 may not deposit a large amount of material film on the substrate ( Such as Ga₂O₃). In some specific examples, the temperature of the pretreatment step 210 is about 20 to about 500°C, about 40 to about 250°C, about 50 to about 150°C, or about 60 to about 130°C. In some specific examples, the temperature of the pretreatment step 210 may be substantially the same as the temperature of the deposition step 220. In some specific examples, the difference between the temperature of the pretreatment step 210 and the temperature of the deposition step 220 may be less than about 100°C, less than about 50°C, or less than 20°C.

The method includes a step 220 of depositing a first material to form a channel layer. The first material may be a compound semiconductor material. Suitable compound semiconductor materials may include group III-V materials, group II-VI materials, and group IV-VI materials. The deposition step 220 can be accomplished via atomic layer deposition (ALD) to produce a layer for the channel layer, which in some specific examples is polycrystalline. ALD can provide the advantages of high conformal deposition in high aspect ratio structures that are similar to structures in V-NAND applications. In other specific examples, CVD or other cyclic deposition processes can be used. Group III-V materials that can be used in the deposition step 220 include: gallium arsenide (GaAs); gallium antimonide (GaSb); indium phosphide (InP); gallium nitride (GaN); indium antimonide (InSb); Indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide. In some specific examples, the III-V group material may be deposited by a deposition process, and the III-V group material includes an alkyl silyl compound of As or Sb and/or a group 13 element (such as Al, Ga, and In) The halide (such as chloride). Group II-VI materials that can be used in the deposition step 220 include: zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium telluride (CdTe), and selenide Cadmium (CdSe). Group IV-VI materials that can be used in the deposition step 220 include: tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), tellurium Germanium (GeTe) and tin telluride (SnTe).

Other materials that may be deposited in the deposition step 220 may include germanium (Ge), silicon Germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), carbon nanotubes, graphene, Silicon carbide (SiC), germanium tin (GeSn), germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂) Or Boron Nitride Carbide (BNC). The applicability of the aforementioned materials depends on the availability of the forming process and a sufficiently high internal mobility.

The channel layer formed in the deposition step 220 may be about 10 nm thick. The method also includes a step 230 of filling the remaining openings with a second material. The second material in the filling step 230 includes silicon oxide (such as silicon dioxide, hafnium oxide, or aluminum oxide), polysilicon or other conductive materials. Each of the steps discussed above can be repeated and sequenced in a different order to allow the formation of desired channels.

Figure 3 depicts a method according to the invention. The method includes a step 300 of providing a substrate with openings. The substrate provided in step 300 has an opening that can be formed through, for example, etching. The substrate opening seen from above the substrate in the bird's-eye view may be circular, square, rectangular, or other shapes. The substrate opening may additionally extend into the substrate, resulting in a three-dimensional shape, such as a cylindrical shape, a cubic shape, a through-hole shape, a tapered three-dimensional shape, or other shapes. After providing step 300, an additional step of forming or depositing additional layers (ie, tunnel dielectric, trapping material, and/or blocking oxide) is performed.

The method includes a step 310 of depositing a first material to form a channel layer. The first material may be a compound semiconductor material. Suitable compound semiconductor materials may include group III-V materials, group II-VI materials, and group IV-VI materials. The deposition step 310 can be accomplished via atomic layer deposition (ALD) to produce a layer for the channel layer, which in some specific examples is polycrystalline. ALD can provide the advantages of high conformal deposition in high aspect ratio structures that are similar to structures in V-NAND applications. In other specific examples, CVD or other cyclic deposition processes can be used. Group III-V materials that can be used in the deposition step 310 include: gallium arsenide (GaAs); gallium antimonide (GaSb); indium phosphide (InP); gallium nitride (GaN); indium antimonide (InSb); indium gallium arsenide (InGaAs); or aluminum, gallium or indium and nitride, Combination of phosphide, arsenide or antimonide. In some specific examples, the III-V group material can be deposited by an ALD process, and the III-V group material includes an alkyl silyl compound of As or Sb and/or a group 13 element (such as Al, Ga, and In) The halide (such as chloride). Group II-VI materials that can be used in the deposition step 310 include: zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium telluride (CdTe), and selenide Cadmium (CdSe). Group IV-VI materials that can be used in the deposition step 310 include: tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), tellurium Germanium (GeTe) and tin telluride (SnTe).

Other materials that may be deposited in the deposition step 310 may include germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn), germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂) Or Boron Nitride Carbide (BNC). The applicability of the aforementioned materials depends on the availability of the forming process and a sufficiently high internal mobility.

The channel layer formed in the deposition step 310 may be about 10 nm thick. The method also includes a step 320 of filling the remaining openings with a second material (for example, a compound semiconductor material, such as a group II-VI or a group III-V material). In some specific examples, the group III-V material used in the filling step 320 may be different from the group III-V material deposited in the deposition step 310. In other specific examples, the group III-V material used in the filling step 320 may be the same as the group III-V material deposited in the deposition step 310. The suitability of the material used in the filling step 320 may depend on the conductivity, the band gap (higher, lower or approximately the same band gap), and the difference in the deposition step 310 The ability of the dielectric and/or group III-V materials to bond, the mobility of electrons and/or holes, the density of charge carriers, and the effective mass of electrons of the group III-V materials. Each of the steps discussed above can be repeated and sequenced in a different order to allow the formation of desired channels.

Figure 4 depicts a method according to the invention. The method includes a step 400 of providing a substrate with openings. The substrate for providing step 400 has an opening that can be formed through, for example, etching. The substrate opening seen from above the substrate in the bird's-eye view may be circular, square, rectangular, or other shapes. The substrate opening may additionally extend into the substrate, creating a three-dimensional shape, such as a cylindrical shape, a cubic shape, a through hole shape, or other shapes. After the providing step 400, an additional step of forming or depositing additional layers (ie, tunnel dielectric, trapping material, and/or blocking oxide) is performed.

The method includes a step 410 of pretreatment to improve adhesion. The pre-processing step 410 can be used to help attach ALD-grown compound semiconductor films (such as group III-V materials) to dielectrics (such as silicon oxide-based dielectrics used as tunnel oxides in V-NAND structures) Above, the resulting V-NAND device has greater stability. In other specific examples, CVD or other cyclic deposition processes can be used. The pretreatment step 410 may include a first pulse of a combination of metal reactants and non-metal reactants. The pretreatment step 410 may additionally include a second pulse of the metal reactant.

In a specific example according to the present invention, the III-V group material (such as GaSb) is deposited onto the hot SiO at the beginning₂The pre-processing step 410 on the substrate may include several GaCl₃With H₂O's pulse. The pretreatment step 410 may include gallium trichloride (GaCl₃) The first pulse with water. Can be carried out including Sb (SiMe₃)₃With GaCl₃The second pulse of the deposition step 420. The first pulse or the second pulse can be repeated as needed. Typical pulse lengths can range from about 0.05 to 20 seconds, about 0.1 to 5 seconds, or about 0.2 to 2 seconds. However, if necessary, such as in the need for extremely high aspect ratio structures or In the case of high-conform step coverage of structures with high surface area or other structures with complex surface morphology or in the case of batch reactors, other pulse lengths can be used. Similarly, typical removal/purging times are about 0.05 to 20 seconds, about 0.5 to 10 seconds, or about 1 to 5 seconds. However, if necessary, such as in the case of high conformal step coverage for extremely high aspect ratio structures or structures with high surface area or other structures with complex surface morphology, or in the case of batch reactors, other structures can be used. Removal/purging time.

<tables><img file="TWI728021B_D0002.tif" /></tables>

Chemicals that can be used as the metal reactant of the first pulse of the pretreatment step 410 include metal compounds. The metal compound may include metal organic or organometallic compounds, such as: metal organic or organometallic compounds of group 13 or 15 elements; metal organic or organometallic compounds of gallium or antimony; or metal halides, such as metal chlorides, Semi-metal halide, semi-metal chloride, gallium trichloride (GaCl₃) And other gallium halides. Chemicals that can be used as non-metallic reactants for the second pulse of pretreatment step 410 include oxygen-containing reactants, such as H₂O, H₂O₂, O₃, And plasma and free radicals incorporating oxygen. Other non-metallic reactants may include chemicals with hydroxide groups and the like. The first pulse and the second pulse of the preprocessing step 410 can be performed in any order.

In some specific examples, the pre-processing step 410 may be used for processing such as Ga₂O₃The material is deposited on the substrate. In some specific examples, the pre-processing step 410 may not deposit large amounts on the substrate. Amount of material film (such as Ga₂O₃). In some specific examples, the temperature of the pretreatment step 410 is about 20 to about 500°C, about 40 to about 250°C, about 50 to about 150°C, or about 60 to about 130°C. In some specific examples, the temperature of the pretreatment step 410 may be substantially the same as the temperature of the deposition step 420. In some specific examples, the difference between the temperature of the pretreatment step 410 and the temperature of the deposition step 420 may be less than about 100°C, less than about 50°C, or less than 20°C.

The method includes a step 420 of depositing a compound semiconductor material to form a channel layer. Suitable compound semiconductor materials may include group III-V materials, group II-VI materials, and group IV-VI materials. The deposition step 420 may be accomplished via atomic layer deposition (ALD) to produce a layer for the channel layer, which in some specific examples is polycrystalline. ALD can provide the advantages of high conformal deposition in high aspect ratio structures that are similar to structures in V-NAND applications. In other specific examples, CVD or other cyclic deposition processes can be used. Group III-V materials that can be used in the deposition step 420 include: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); indium antimonide (InSb); Indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide. In some specific examples, the III-V group material may be deposited by an ALD process, and the III-V group material includes an alkyl silyl compound of As or Sb and/or a group 13 element (such as Al, Ga, and In) The halide (such as chloride). Group II-VI materials that can be used in the deposition step 420 include: zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium telluride (CdTe), and selenide Cadmium (CdSe). Group IV-VI materials that can be used in the deposition step 420 include: tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), tellurium Germanium (GeTe) and tin telluride (SnTe).

Other materials that may be deposited in the deposition step 420 may include germanium (Ge), silicon Germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), carbon nanotubes, graphene, Silicon carbide (SiC), germanium tin (GeSn), germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂) Or Boron Nitride Carbide (BNC). The applicability of the aforementioned materials depends on the availability of the forming process and a sufficiently high internal mobility.

The channel layer formed in the deposition step 420 may be about 10 nm thick. The method also includes a step 420 of filling the remaining openings with another semiconductor material (for example, a compound semiconductor material, such as a group II-VI, a group III-V, or a group IV-VI material). In some specific examples, the group III-V material used in the filling step 420 may be different from the group III-V material deposited in the deposition step 410. In other specific examples, the group III-V material used in the filling step 420 may be the same as the group III-V material deposited in the deposition step 410. The suitability of the material used in the filling step 420 may depend on the conductivity, the band gap (higher, lower, or approximately the same band gap), the dielectric material of the deposition step 410, and/or the III-V The ability of group materials to bind, electron and/or hole mobility, charge carrier density, and the effective mass of electrons in group III-V materials. Each of the steps discussed above can be repeated and sequenced in a different order to allow the formation of desired channels.

Figure 5 depicts a specific example according to the present invention. The method of forming the III-V group film may include: providing a silicon oxide surface 500; treating a halide precursor 510; depositing an alkylsilyl compound precursor 520; and depositing a metal halide precursor 530.

The surface of the silicon oxide in step 500 may have hydroxyl (-OH) groups. Therefore, the halide precursor of step 510 can convert the hydroxyl groups into Si-Cl bonds. The halide precursor of step 510 may include carbon tetrachloride (CCl₄) Or chloroform (CHCl₃). For example, the halide precursor of step 510 may also include the formula CX₄Or CH_aX_4-aChemical substances, where X is a halide, all Such as F, Cl or Br. The halide precursor of step 510 may include at least one of the following: Cl, Cl₂, HCl, or free radicals containing halides (such as chlorine), stimulating substances, or plasma.

The halide precursor pretreatment step 510 may include multiple cycles of exposure to the halide precursor that exceed 10 cycles, 50 cycles, 100 cycles, 150 cycles, 200 cycles, or 250 cycles. For such reactions occurring in small batch or single wafer reactors, the halide precursor pretreatment step 510 may include exposure for 0.1 to 10 seconds, 1 to 8 seconds, or 3 to 7 seconds. In some specific examples, such as in a batch reactor, the exposure and purging and other times may be longer.

The halide precursor pretreatment step 510 may also include pre-stabilization lasting 2 to 10 minutes. Pre-stabilization includes waiting in the reactor before depositing the precursors in steps 520 and 530. The benefits obtained by pre-stabilization can include complete adhesion of the film and avoidance of any delamination. In addition, the halide precursor pretreatment step can be performed at a temperature below 500°C, below 450°C, below 400°C, or below 350°C.

The alkylsilyl compound precursor of step 520 may additionally react with the Si-Cl bond. Step 520 may require a higher temperature exceeding about 100°C to react with the alkylsilyl compound precursor. For example, the alkyl silyl compound precursor may include As or Sb alkyl silyl compound, such as Sb (SiMe₃)₃. In addition, the alkyl silyl compound precursor step can be carried out at a temperature below 150°C, below 130°C, below 115°C, or below 105°C.

After depositing the alkyl silyl compound precursor, a metal halide precursor 520 may be deposited to form a group III-V material. The metal halide precursor in step 520 may include a halide (such as chloride) of a group 13 element (such as Al, Ga, and In). An example of the metal halide precursor in step 520 can be gallium trichloride (GaCl₃). The formed III-V group material may include: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); Indium antimonide (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide. In addition, the metal halide precursor step can be performed at a temperature below 150°C, below 130°C, below 115°C, or below 105°C.

In some specific examples, the deposited compound semiconductor material may have a conformality of greater than about 50%, greater than about 80%, greater than about 90%, greater than about 95%, greater than about 98%, or greater than about 99%. The deposited compound semiconductor material may have an aspect ratio (depth: width) greater than about 2, greater than about 5, greater than about 10, greater than about 20, or even greater than about 40, or greater than about 80 in some cases. It can be noted that the aspect ratio of the V-NAND structure may be difficult to determine, but in this article, the aspect ratio can be understood as the total surface area of the structure in the wafer (or part of the wafer) and the wafer (or part of the wafer) The ratio of the surface area of the plane.

In some specific examples, the reaction temperature for depositing a compound semiconductor material film (such as a III-V material (such as GaSb or GaAs), II-VI or IV-VI material) may be less than about 700°C, less than About 500°C, less than about 400°C, less than about 300°C, less than about 200°C, or less than about 150°C.

In some specific examples, the growth rate of the deposited compound semiconductor material may be less than about 3 Å/cycle, less than about 2 Å/cycle, less than about 1.5 Å/cycle, or less than about 1 Å/cycle. In some specific examples, the growth rate of the deposited compound semiconductor material may be about 0.05 Å/cycle to about 2 Å/cycle, or about 0.1 Å/cycle to about 1.5 Å/cycle.

In some specific examples, the compound semiconductor material may have impurities less than about 20 at-%, less than about 10 at-%, less than about 5 at-%, or less than about 3 at-% (ie, a material different from the compound semiconductor material itself). In some specific examples, the compound semiconductor material may have less than about 5 at-%, less than about 2 at-%, less than about 1 at-%, or less than about 0.5 at-% of halide impurities. Quality (such as chlorine). In some specific examples, the compound semiconductor material may have less than about 25 at-%, less than about 15 at-%, less than about 10 at-%, or less than about 5 at-% hydrogen impurities. In some specific examples, the compound semiconductor material may have less than about 5 at-%, less than about 2 at-%, less than about 1 at-%, or less than about 0.5 at-% silicon impurities. In some specific examples, the compound semiconductor material has carbon impurities less than about 5 at-%, less than about 2 at-%, less than about 1 at-%, or less than about 0.5 at-%.

The embodiments listed below are descriptions of various aspects of some specific examples of this disclosure. The methods and various parameters reflected therein are only used to illustrate various aspects and specific examples of the present disclosure, and are not intended to limit the scope of the claimed invention.

1. A method of forming a channel for a V-NAND device, comprising: providing a substrate having an opening; depositing a first material in the opening via atomic layer deposition to form a channel layer; and filling the opening with a second material The remaining part.

2. According to the method of embodiment 1, wherein the opening surface includes the second material.

3. The method according to embodiment 2, wherein the second material includes at least one of the following: a conductive material; a semiconductive material; a dielectric material; or silicon oxide.

4. According to the method of embodiment 1, wherein the first material is a compound semiconductor.

5. The method of embodiment 1, wherein the first material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimonide Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

6. According to the method of embodiment 1, wherein the first material is deposited by an ALD process, and the first material includes an alkyl silyl compound of antimony or arsenic.

7. According to the method of embodiment 1, wherein the first material is deposited through an ALD process, and the first material includes chlorides of Al, Ga or In.

8. The method according to embodiment 1, wherein the first material comprises at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium telluride (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn) , Germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or Boron nitride carbide (BNC).

9. A method for forming a structure, comprising: providing a substrate having a surface containing an oxide; pretreating the oxide surface; and depositing a semiconductor material on the oxide surface after the pretreatment; wherein the pretreatment Contains gallium compounds and oxygen compounds.

10. According to the method of embodiment 9, wherein the semiconductor material is a compound semiconductor deposited by one of the following: atomic layer deposition, chemical vapor deposition or cyclic deposition.

11. The method of embodiment 9, wherein the compound is gallium chloride , gallium oxide compound and the water.

12. According to the method of embodiment 9, wherein the gallium compound and the oxygen compound are periodically and/or selectively applied to the surface.

13. According to the method of embodiment 9, wherein the gallium compound and the oxygen compound are applied to the surface in a cyclic manner.

14. A method of forming a channel for a V-NAND device, comprising: providing a substrate having an opening; pretreating a surface formed in the opening; depositing a first material inside the opening to form a channel layer; and The second material fills the remaining part of the opening.

15. The method according to embodiment 14, wherein the substrate includes at least one silicon oxide.

16. The method according to embodiment 14, wherein the second material includes at least one of: a conductive material; a semiconductive material; a dielectric material; or silicon oxide.

17. The method according to embodiment 14, wherein the pretreatment step comprises a cycle of at least one of the following: gallium trichloride (GaCl₃) And water (H₂O).

18. The method of embodiment 14, wherein the first material comprises a compound semiconductor material deposited by at least one of the following: atomic layer deposition, chemical vapor deposition, or cyclic deposition.

19. The method of embodiment 14, wherein the first material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimony Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

20. The method of embodiment 14, wherein the first material comprises at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium telluride (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn) , Germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), Tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or nitride Boron carbide (BNC).

twenty one. A method of forming a channel for a V-NAND device includes: providing a substrate having an opening; depositing a first material in the opening to form a channel layer; and filling the remaining part of the opening with a second material, wherein The second material includes at least one of a conductive material or a semi-conductive material.

twenty two. According to the method of embodiment 21, wherein the opening surface comprises a dielectric material.

twenty three. The method of embodiment 21, wherein the first material is a compound semiconductor deposited by at least one of the following: atomic layer deposition, chemical vapor deposition, or cyclic deposition.

twenty four. The method of embodiment 21, wherein the first material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimony Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

25. The method of embodiment 21, wherein the first material comprises at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn), Germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or Boron Nitride Carbide (BNC).

26. The method of embodiment 21, wherein the second material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimony Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

27. The method of embodiment 21, wherein the second material includes at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium telluride (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn) , Germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or Boron nitride carbide (BNC).

28. A method of forming a channel for a V-NAND device, comprising: providing a substrate having an opening; pretreating a surface formed in the opening; depositing a first material inside the opening to form a channel layer; and The second material fills the remaining part of the opening.

29. The method according to embodiment 28, wherein the opening surface includes the second material.

30. The method according to embodiment 28, wherein the pretreatment step comprises gallium trichloride (GaCl₃) And water (H₂O) cycle.

31. The method according to embodiment 28, wherein the first material passes at least one of the following Deposition of compound semiconductors: atomic layer deposition, chemical vapor deposition or cyclic deposition.

32. The method of embodiment 28, wherein the first material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimonide Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

33. The method of embodiment 28, wherein the first material includes at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium telluride (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn) , Germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or Boron nitride carbide (BNC).

34. The method according to embodiment 28, wherein the second material is at least one of the following: conductive material; semi-conductive material; dielectric material; or silicon oxide.

35. The method of embodiment 28, wherein the second material comprises at least one of the following: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); antimonide Indium (InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium, or indium with nitride, phosphide, arsenide, or antimonide.

36. The method of embodiment 28, wherein the second material includes at least one of the following: germanium (Ge), silicon germanium (SiGe), zinc oxide (ZnO), zinc oxynitride (ZnON), indium gallium zinc oxide (IZGO), indium tin oxide (ITO), titanium oxide (TiOx), cadmium telluride (CdTe), zinc sulfide (ZnS), carbon nanotubes, graphene, silicon carbide (SiC), germanium tin (GeSn), germanium selenide (GeSe), tin selenide (SnSe), diamond, tungsten sulfide (WS₂), tin sulfide (SnS), silicon selenide (SiSe), germanium selenide (GeSe), tin selenide (SnSe), silicon telluride (SiTe), germanium telluride (GeTe), tin telluride (SnTe) or Boron nitride carbide (BNC).

37. A method for performing pretreatment before depositing channels for V-NAND devices, comprising: performing a cyclic pretreatment process, which includes pulses of a first metal reactant and pulses of a non-metal reactant; and in the channel to be deposited A second pulse containing a second metal reactant is executed in the opening; wherein the cyclic pretreatment process improves the adhesion of the material to be deposited in the opening.

38. The method of embodiment 37, wherein the first metal reactant of the first pulse comprises at least one of the following: a metal compound; a metal organic compound or an organometallic compound; a metal organic or organic group 13 or 15 element Metal compounds; metal organic or organometallic compounds of gallium or antimony; metal halides; metal chlorides; semi-metal halides; semi-metal chlorides; gallium trichloride (GaCl₃); or other gallium halides.

39. The method of embodiment 37, wherein the non-metallic reactant of the first pulse comprises at least one of the following: H₂O, H₂O₂, O₃, Plasma and free radicals incorporating oxygen, or chemicals with hydroxide groups.

40. The method of embodiment 37, wherein the second metal reactant of the second pulse comprises at least one of the following: indium chloride, gallium trichloride (GaCl₃), Sb(SiMe₃)₃, Or antimony or arsenic alkyl silyl compounds.

41. A method for forming a channel for a V-NAND device, comprising: performing a pulsed cyclic pretreatment process containing a first halide reactant onto a silicon oxide surface; pulsed an alkyl silyl compound precursor; and pulsed metal halide Substance precursor; wherein the reaction of the alkyl silyl compound precursor and the metal halide precursor forms a III-V group film.

42. The method of embodiment 41, wherein the III-V group film comprises: gallium antimonide (GaSb); gallium arsenide (GaAs); indium phosphide (InP); gallium nitride (GaN); indium antimonide (GaSb) InSb); indium gallium arsenide (InGaAs); or a combination of aluminum, gallium or indium and nitride, phosphide, arsenide or antimonide.

43. According to the method of embodiment 41, wherein the alkylsilyl compound precursor comprises As or Sb alkylsilyl compound or Sb(SiMe₃)₃。

44. The method of embodiment 41, wherein the first halide precursor comprises at least one of the following: carbon tetrachloride (CCl₄); Trichloromethane (CHCl₃); Chloride (Cl); Chlorine (Cl₂); free radicals containing halide, exciting substances or plasma; or having the formula CX₄Or CH_aX_4-aThe chemical substance, where X is a halide, such as F, Cl or Br.

45. The method according to embodiment 41, wherein the cyclic pretreatment process occurs at a temperature lower than 700°C, lower than 500°C, lower than 450°C, lower than 400°C, or lower than 350°C.

46. The method of embodiment 41, wherein the cyclic pretreatment process comprises more than 10 cycles, 50 cycles, 100 cycles, 150 cycles, 200 cycles, or 250 cycles of exposure to the first halide precursor. Cycles.

47. The method according to embodiment 41, wherein the cyclic pretreatment process comprises exposure to the first halide precursor for a duration in the range of 0.1 to 10 seconds, 1 to 8 seconds, or 3 to 7 seconds.

48. The method according to embodiment 41, wherein pulsing the alkylsilyl compound precursor and pulsing the metal halide precursor occurs at a temperature of less than 150°C, less than 130°C, less than 115°C, or less than 105°C.

49. A method for forming a structure, comprising: providing a substrate having a surface containing an oxide; pretreating the oxide surface; and depositing a compound semiconductor material on the oxide surface after the pretreatment; wherein the pretreatment The treatment contains halides.

50. The method of embodiment 49, wherein the pretreatment improves the adhesion of the compound semiconductor material to the substrate.

The specific implementation shown and described is an illustration of the present invention and its best mode, and is not intended to additionally limit the aspect and the scope of implementation in any way. In fact, for the sake of brevity, the conventional manufacturing, correlation, preparation, and other functional aspects of the system may not be described in detail. In addition, the connecting lines shown in each figure are intended to represent exemplary functional relationships and/or physical couplings between various elements. Many alternative or additional functional relationships or physical relationships may exist in the actual system, and/or may not exist in some specific instances.

It should be understood that the configurations and/or methods described herein are illustrative in nature, and these specific specific examples or embodiments should not be considered restrictive, as there may be many variations. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various actions shown can be performed in the order shown, in other orders, or Omitted in some cases.

The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems, and configurations disclosed herein, as well as other features, functions, actions, and/or properties, and any and all equivalents thereof.