Display device and method for manufacturing the same

Display device and its manufacturing method

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a display device using an oxide semiconductor.

In recent years, the technology of forming a transistor by using a semiconductor thin film formed on a substrate with an insulating surface has attracted attention. Transistors are widely used in electronic devices such as ICs or electro-optical devices, especially as switching elements of image display devices, and are actively being researched and developed. There are many kinds of metal oxides, and they are used for various purposes. Indium oxide is a well-known material, and it is used as a transparent electrode material required for liquid crystal displays and the like.

Among the metal oxides, there are metal oxides exhibiting semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide. It is already known that these metal oxides exhibiting semiconductor characteristics are used for transistors in the channel formation region (refer to Patent Documents 1 and 2).

In addition, the field-effect mobility of transistors using oxide semiconductors is relatively high. Therefore, the transistor can also be used to form a drive circuit of a display device or the like.

[Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[Patent Document 2] Japanese Patent Application Publication No. 2007-96055

In a display device, etc., when the pixel portion (also referred to as a pixel circuit) and the drive circuit are formed on the same substrate, the transistor used in the pixel portion needs superior switching characteristics, such as a large switching ratio, and is used in the drive circuit The transistor needs to work at high speed.

In particular, because the higher the pixel density of the display device, the shorter the writing time of the displayed image, so the transistor used in the drive circuit is preferably operated at a high speed. In addition, a problem occurs in the pixel portion that the higher the pixel density, the lower the aperture ratio.

Thus, the present invention describes an embodiment of the disclosed invention regarding a display device and a manufacturing method thereof that solve the above-mentioned problems.

An embodiment of the present invention disclosed in the description of the present invention is a display device that includes: a pixel portion; and a driving circuit portion on the same substrate, wherein the pixel portion includes: a first transistor, and the first transistor includes: a first transistor. A gate electrode layer; a gate insulating layer on the first gate electrode layer; a first source electrode layer and a first drain electrode layer on which a part of the gate insulating layer overlaps the first gate electrode layer; And a first oxide semiconductor whose part of the gate insulating layer overlaps the first source electrode layer and the first drain electrode layer Layer, the first source electrode layer, the first drain electrode layer, and the first oxide insulating layer on the first oxide semiconductor layer; the connection on the first oxide insulating layer that is electrically connected to the first drain electrode layer An electrode layer; a first oxide insulating layer and a second oxide insulating layer on the connecting electrode layer; a protective insulating layer on the second oxide insulating layer; and a pixel electrode layer on the protective insulating layer electrically connected to the connecting electrode layer , The driving circuit part includes: a second transistor, the second transistor including: a second gate electrode layer; a gate insulating layer on the second gate electrode layer; a second oxide semiconductor layer on the gate insulating layer And a second source electrode layer and a second drain electrode layer on the second oxide semiconductor layer, a part of which overlaps the second oxide semiconductor layer; a second source electrode layer, a second drain electrode layer and A second oxide insulating layer on the second oxide semiconductor layer; and a protective insulating layer on the second oxide insulating layer, and, the first gate electrode layer, the gate insulating layer, the first oxide semiconductor layer, the second A source electrode layer, a first drain electrode layer, a first oxide insulating layer, a second oxide insulating layer, a protective insulating layer, and a pixel electrode layer are transparent.

Note that the ordinal numbers added as "first" and "second" in the description of the present invention are used for convenience, and do not indicate the order of steps and the order of stacking. In addition, the ordinal number in the description of the present invention is not an inherent name of a specific invention.

The first gate electrode layer, the first source electrode layer, and the first drain electrode layer of the first transistor are formed of metal oxide, and the second gate electrode layer and the second source electrode of the second transistor The layer and the second drain electrode layer are formed of metal.

As the above-mentioned metal oxide, indium oxide, indium oxide tin oxide alloy, indium oxide zinc oxide alloy, or zinc oxide can be used.

In addition, a flattening insulating layer having translucency may be formed between the second oxide insulating layer and the protective insulating layer of the pixel portion.

In addition, a conductive layer may be formed on the protective insulating layer overlapping the second oxide semiconductor layer of the drive circuit section.

In addition, as the first oxide insulating layer and the second oxide insulating layer, an inorganic insulating film formed by a sputtering method is preferably used. For example, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, or the like can be used.

In addition, an oxide conductive layer may be formed between the second oxide semiconductor layer of the second transistor and the second source electrode layer and between the second oxide semiconductor layer and the second drain electrode layer. Structure. By adopting this structure, the contact resistance can be reduced to realize a transistor capable of high-speed operation. In addition, as the oxide conductive layer, an oxide conductive layer containing a zinc oxide component but not indium oxide is preferably used. Examples of such oxide conductive layers include zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, and the like.

In addition, another embodiment of the present invention disclosed in the description of the present invention is a method of manufacturing a display device, which includes the steps of: forming a first gate electrode layer in a region that becomes a pixel portion; and forming a second gate electrode layer in a region that becomes a driving circuit portion. Two gate electrode layers; forming a gate insulating layer on the first gate electrode layer and the second gate electrode layer; forming a first source electrode overlapping a part of the first gate electrode layer on the gate insulating layer Layer and a first drain electrode layer; forming a first oxide semiconductor layer overlapping a part of the first source electrode layer and a part of the first drain electrode layer on the gate insulating layer to form a first transistor; A second oxide semiconductor layer overlapping with a portion of the second gate electrode layer is formed on the gate insulating layer; a first oxide insulating layer is formed on the first oxide semiconductor layer; and a second oxide semiconductor layer is formed on the first oxide insulating layer. A part of the second oxide semiconductor layer overlaps the second source electrode layer and the second drain electrode layer to form a second transistor; forms a connection electrode layer electrically connected to the first drain electrode layer; Forming a second oxide insulating layer on the insulating layer, the second oxide semiconductor layer, the second source electrode layer, and the second drain electrode layer; forming a protective insulating layer on the second oxide insulating layer; and forming a pixel portion A pixel electrode layer electrically connected to the connection electrode layer is formed on the protective insulating layer in the region.

In the structure of the above manufacturing method, the first gate electrode layer, the gate insulating layer, the first oxide semiconductor layer, the first source electrode layer, the first drain electrode layer, the first oxide insulating layer, and the second oxide semiconductor layer The oxide insulating layer, the protective insulating layer, and the pixel electrode layer are transparent.

Preferably, after the oxide semiconductor layer is dehydrated or dehydrogenated, the oxide insulating layer formed on the first oxide semiconductor layer and the second oxide semiconductor layer is formed without exposure to the atmosphere to prevent the oxide The semiconductor layer is mixed with water and hydrogen again.

In the description of the present invention, dehydration or dehydrogenation not only includes making water, H₂The detachment also includes the detachment of H, OH, etc.

It is best to perform heat treatment to achieve dehydration or dehydrogenation under the following conditions: in an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), at a temperature above 400°C and below the strain point of the substrate, it is best At a temperature above 425°C and below 700°C.

When the heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), it can be said that the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and the resistance is reduced, that is, the n-type (n^-Modeling, etc.). Then, by forming an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer is in a state of excess oxygen, and the resistance is increased, that is, the i-type is performed. As a result, a display device including a transistor with good electrical characteristics and high reliability can be manufactured and provided.

As for the oxide semiconductor layer that has undergone dehydration or dehydrogenation, the following heat treatment conditions are used: When the oxide semiconductor layer after dehydration or dehydrogenation is measured by TDS (Thermal Desorption Spectroscopy) up to 450°C At this time, two peaks showing the desorption of water were not detected, at least not detecting the level of one peak at around 300°C. Therefore, when a transistor using a dehydrated or dehydrogenated oxide semiconductor layer is measured with TDS up to 450°C, at least the water peak appearing around 300°C is not detected.

It is important not to expose the dehydrated or dehydrogenated oxide semiconductor layer to the atmosphere, and to prevent the remixing of water or hydrogen. Used for dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, n-type (n^-Type, n⁺After that, the threshold voltage value of the transistor of the i-type oxide semiconductor layer is positive by increasing the resistance, and exhibits a so-called normally-off characteristic. The transistor used in the display device preferably has a positive threshold voltage whose gate voltage is as close as possible to 0V. In an active matrix display device, the electrical characteristics of the transistors constituting the circuit are important, and the performance of the display device depends on the electrical characteristics. Of particular importance is the threshold voltage of the transistor. When the threshold voltage of the transistor is negative, it becomes a so-called normally-on state, in which current flows between the source electrode and the drain electrode even if the gate voltage is 0V, so it is difficult to control the circuit composed of the transistor . In addition, even if the threshold voltage value is positive, when a transistor with a high absolute value is used, sometimes the switching operation cannot be performed due to insufficient driving voltage. As an n-channel type transistor, it is best to use a transistor that forms a channel only when a positive voltage is applied to the gate voltage, and the drain current starts to flow. The following transistors are not suitable for circuit transistors: unless the driving voltage is increased, a channel transistor is not formed; a channel is also formed in a negative voltage state and the drain current flows through the transistor.

The atmosphere when the temperature is lowered from the temperature for dehydration or dehydrogenation may be switched to an atmosphere different from the atmosphere when the temperature is raised or during the heat treatment. For example, in the same furnace as the furnace for dehydration or dehydrogenation, the furnace can be filled with high-purity oxygen gas, N₂O gas or ultra-dry air (the dew point is below -40°C, preferably below -60°C) for cooling.

Since the transistor is easily damaged by static electricity or the like, it is better to provide a protection circuit for protecting the transistor of the pixel portion on the same substrate as the gate line or the source line. The protection circuit is preferably composed of a non-linear element using an oxide semiconductor layer.

The display device of one embodiment of the present invention manufactures a driving circuit part including a transistor for a driving circuit and a pixel part including a transistor for a pixel on the same substrate. Therefore, the manufacturing cost of the display device can be reduced.

By using an oxide semiconductor layer subjected to heat treatment for dehydration or dehydrogenation, a transistor with good electrical characteristics can be produced. In addition, by forming the transistor for the pixel circuit using a material having light-transmitting properties, a display device with a high aperture ratio and superior display characteristics can be manufactured. In addition, in a display device including a pixel circuit and a driving circuit on the same substrate, these circuits can be formed separately by using transistors with different structures to easily obtain the electrical characteristics required by these circuits.

<p>11Wiring </p><p>12Wiring </p><p>13Wiring </p><p>14Wiring </p><p>15Wiring </p><p>21Input terminal </p><p>22Input terminal </p><p>23Input terminal </p><p>24Input terminal </p><p>25Input terminal </p><p>26Output terminal </p><p>27Output terminal </p><p>28Transistor </p><p>31Transistor </p><p>32Transistor </p><p>33Transistor </p><p>34Transistor </p><p>35Transistor </p><p>36Transistor </p><p>37Transistor </p><p>38Transistor </p><p>39Transistor </p><p>40Transistor </p><p>41Transistor </p><p>42Transistor </p><p>43Transistor </p><p>51Power cord </p><p>52Power cord </p><p>53Power cord </p><p>61period </p><p>62period </p><p>400Substrate </p><p>402Gate insulation layer </p><p>403Oxide semiconductor layer </p><p>404Oxide semiconductor layer </p><p>405Oxide semiconductor layer </p><p>411Terminal </p><p>412Connect the electrode layer </p><p>414Terminal </p><p>415Conductive layer </p><p>416electrode layer </p><p>417Conductive layer </p><p>418: Conductive layer</p><p>422: source wiring layer</p><p>423: Channel Formation Area</p><p>426: oxide insulating layer</p><p>427: oxide insulating layer</p><p>428: Protective insulating layer</p><p>429: Connect the electrode layer</p><p>430: Capacitor wiring layer</p><p>431: Capacitor electrode</p><p>432: Capacitor wiring layer</p><p>440: Transistor</p><p>442: Connect the electrode layer</p><p>443: Channel Formation Area</p><p>447: oxide conductive layer</p><p>448: oxide conductive layer</p><p>449: Connect the electrode layer</p><p>450: Transistor</p><p>452: Connect the electrode layer</p><p>453: oxide semiconductor layer</p><p>454: oxide semiconductor layer</p><p>456: flattening insulating layer</p><p>457: pixel electrode layer</p><p>460: Transistor</p><p>421a: Gate electrode layer</p><p>421b: Gate electrode layer</p><p>421c: Gate wiring layer</p><p>424a: High resistance source region</p><p>424b: high resistance drain region</p><p>424c: District 1</p><p>424d: District 2</p><p>425a: source electrode layer</p><p>425b: Drain electrode layer</p><p>444a: high resistance source region</p><p>444b: high resistance drain region</p><p>444c: District 1</p><p>444d: District 2</p><p>445a: source electrode layer</p><p>445b: Drain electrode layer</p><p>446a: Oxide conductive layer</p><p>446b: Oxide conductive layer</p><p>451a: Gate electrode layer</p><p>451b: Gate electrode layer</p><p>455a: source electrode layer</p><p>455b: Drain electrode layer</p><p>600: substrate</p><p>601: Opposite substrate</p><p>602: Gate Wiring</p><p>603: gate wiring</p><p>604Capacitor wiring </p><p>605Capacitor wiring </p><p>606Gate insulation layer </p><p>607electrode layer </p><p>609Common potential line </p><p>615Capacitance electrode </p><p>616Wiring </p><p>617Capacitor wiring </p><p>618Wiring </p><p>619Wiring </p><p>620Insulation film </p><p>621Insulation film </p><p>622Insulation film </p><p>623Contact hole </p><p>624Pixel electrode layer </p><p>625Slit </p><p>626Pixel electrode layer </p><p>627Contact hole </p><p>628Transistor </p><p>629Transistor </p><p>630Storage capacitor department </p><p>631Storage capacitor department </p><p>633Contact hole </p><p>634Color film </p><p>636Color film </p><p>637Planarization film </p><p>638Color film </p><p>640Counter electrode layer </p><p>641Slit </p><p>644Protrusion </p><p>646Alignment film </p><p>648Alignment film </p><p>650Liquid crystal layer </p><p>651Liquid crystal element </p><p>652Liquid crystal element </p><p>690Capacitor wiring </p><p>1100Mobile phone </p><p>1101Frame </p><p>1102Display </p><p>1103Operation button </p><p>1104External port </p><p>1105Speaker </p><p>1106Microphone </p><p>1800Frame </p><p>1801Frame </p><p>1802Display Panel </p><p>1803Speaker </p><p>1804Microphone </p><p>1805Operation keys </p><p>1806Positioning device </p><p>1807Image capture device </p><p>1808External connection terminal </p><p>1810Keyboard </p><p>1811External memory slot </p><p>2600Transistor substrate </p><p>2601Opposite substrate </p><p>2602Sealing material </p><p>2603Pixel </p><p>2604Display element </p><p>2605Coloring layer </p><p>2606Polarizer </p><p>2607Polarizer </p><p>2608Wiring circuit department </p><p>2609Flexible Wiring Board </p><p>2610Cold cathode tube </p><p>2611Reflector </p><p>2612Circuit board </p><p>2613Diffuser plate </p><p>4001Substrate </p><p>4002Pixel </p><p>4003Signal line drive circuit </p><p>4004Scan line drive circuit </p><p>4005Sealing material </p><p>4006Substrate </p><p>4008Liquid crystal layer </p><p>4010Transistor </p><p>4011Transistor </p><p>4013Liquid crystal element </p><p>4015Connecting terminal electrode </p><p>4016Terminal electrode </p><p>4018FPC </p><p>4019Anisotropic conductive film </p><p>4020Protective insulation layer </p><p>4021Insulation layer </p><p>4030Pixel electrode </p><p>4031Counter electrode </p><p>4032Insulation layer </p><p>4040Conductive layer </p><p>4041Insulation layer </p><p>5300Substrate </p><p>5301Pixel </p><p>5302Scan line drive circuit </p><p>5303Scan line drive circuit </p><p>5304Signal line drive circuit </p><p>5305Timing control circuit </p><p>5601Shift register </p><p>5602Switching circuit </p><p>5603Transistor </p><p>5604Wiring </p><p>5605Wiring </p><p>9600TV installation </p><p>9601Frame </p><p>9603Display </p><p>9605Support </p><p>9607Display </p><p>9609Operation keys </p><p>9610Remote control operating machine </p><p>9700Digital Photo Frame </p><p>9701Frame </p><p>9703Display </p><p>9881Frame </p><p>9882Display </p><p>9883Display </p><p>9884Speaker </p><p>9885Operation keys </p><p>9886External memory slot </p><p>9887Connecting terminal </p><p>9888Sensor </p><p>9889Microphone </p><p>9890LED light </p><p>9891Frame </p><p>9893Connecting part </p>

FIGS. 1A to 1E are cross-sectional process diagrams showing an embodiment of the present invention; FIGS. 2A to 2E are cross-sectional process diagrams showing an embodiment of the present invention; FIG. 3 is a cross-sectional view showing an embodiment of the present invention Figures 4A1, 4A2, 4B1 and 4B2 are cross-sectional views and plan views showing an embodiment of the present invention; Figures 5A1, 5A2 and 5B are cross-sectional views and plan views showing an embodiment of the present invention; Figure 6 shows A cross-sectional view of an embodiment of the present invention; FIGS. 7A and 7B are diagrams illustrating a block diagram of a display device; FIGS. 8A and 8B are diagrams illustrating the structure of a signal line driving circuit and a timing diagram illustrating its operation; FIGS. 9A to 9D Is a circuit diagram showing the structure of the shift register; FIGS. 10A and 10B are diagrams illustrating the structure of the shift register and a timing diagram illustrating its operation; 11 is a cross-sectional view illustrating the display device; FIG. 12 is a plan view illustrating the display device; FIG. 13 is a plan view illustrating the display device; FIG. 14 is a diagram illustrating an equivalent circuit of the display device; FIG. 15 is a cross-sectional view illustrating the display device 16 is a plan view illustrating the display device; FIG. 17 is a plan view illustrating the display device; FIG. 18 is a diagram illustrating an equivalent circuit of the display device; FIG. 19 is a cross-sectional view illustrating the display device; 21 is a cross-sectional view illustrating the display device; FIG. 22 is a plan view illustrating the display device; FIG. 23 is a cross-sectional view illustrating the display device; FIG. 24 is a plan view illustrating the display device; Figs. 26A and 26B are diagrams showing electronic devices; Fig. 27 is a diagram showing electronic devices; and Figs. 28A and 28B are cross-sectional views showing one embodiment of the present invention.

Hereinafter, an embodiment mode of the present invention will be described in detail with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the mode and details of the present invention can be transformed into various forms without being limited to the following description. Therefore, the present invention should not be interpreted as being limited to the content described in the embodiment modes shown below. Note that in all the drawings describing the present invention, the same reference numerals are used to denote the same parts or parts having the same functions, and the descriptions thereof are sometimes omitted.

[Embodiment Mode 1]

In this embodiment mode, an embodiment of a display device and a manufacturing method thereof will be described in detail with reference to the drawings. FIG. 1E shows an example of the cross-sectional structure of the transistor of the driving circuit, the transistor of the pixel portion, and the contact portion of the gate wiring (gate electrode) formed on the same substrate.

The transistor 450 is a bottom gate type transistor called a channel etching type. The transistor 460 is a bottom gate type transistor called a bottom contact type (also called an inverted coplanar type).

The transistor 460 disposed in the pixel includes a gate electrode 451a, a gate insulating layer 402, an oxide semiconductor layer 454 including a channel formation region, a source electrode layer 455a, and a drain electrode layer 455b on the substrate 400 with an insulating surface. In addition, an oxide insulating layer 426 covering the transistor 460 and contacting the upper surface and side surfaces of the oxide semiconductor layer 454 is provided.

In addition, an example in which a single-gate structure transistor is used as the transistor 460 arranged in the pixel is described, but a multi-gate structure transistor having a plurality of channel formation regions may also be used as needed.

In addition, the oxide semiconductor layer 454 has light transmittance, and it is formed to overlap a part of the source electrode layer 455a and a part of the drain electrode layer 455b. In addition, the oxide semiconductor layer 454 overlaps with the gate electrode layer 451a via the gate insulating layer 402 having light-transmitting properties. The channel formation region of the transistor 460 arranged in the pixel is the region in the oxide semiconductor layer 454 sandwiched between the side surface of the source electrode layer 455a and the side surface of the drain electrode layer 455b opposite to the side surface, that is, and A region where the gate insulating layer 402 is in contact with and overlaps with the gate insulating layer 451a.

In addition, in order to realize a display device with a high aperture ratio, a translucent conductive film is used as the source electrode layer 455a and the drain electrode layer 455b of the transistor 460.

In addition, as the gate electrode layer 451a of the transistor 460, a translucent conductive film is used.

In addition, the transistor 450 arranged in the driving circuit portion is composed of a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 425a, and a drain electrode layer 425b on the substrate 400 having an insulating surface. . Here, the oxide semiconductor layer 403 includes at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b. In addition, a translucent oxide insulating layer 427 and a protective insulating layer 428 are provided on the channel formation region 423, the source electrode layer 425a, and the drain electrode layer 425b.

In addition, the first region 424c and the second region 424d of the oxide semiconductor layer 403 overlapping with the oxide insulating layer 426 are in the same oxygen excess state as the channel formation region 423, and have the function of reducing leakage current and parasitic capacitance. In addition, when a structure in which the oxide insulating layer 426 does not overlap the oxide semiconductor layer 403 is adopted, the second layer of the oxide semiconductor layer 403 is not formed. The first area 424c, the second area 424d.

Hereinafter, the process of manufacturing the transistor 450 and the transistor 460 on the same substrate will be described with reference to FIGS. 1A, 1B, 1C, 1D, and 1E.

First, a metal film is formed on the substrate 400 with an insulating surface, and then the gate electrode layers 421a and 421b are formed by a first photolithography process and an etching process. Note that the gate electrode layer 421b is equivalent to a gate wiring, but is shown as a gate electrode layer for convenience.

In addition, the resist mask used in the photolithography process can also be formed by an inkjet method. Because the photomask is not used in the inkjet method, the manufacturing cost can be reduced.

As the metal film used for the gate electrode layers 421a and 421b, an element selected from Al, Cr, Ta, Ti, Mo, W, an alloy containing the above element as a component, a laminated film in which the above element is combined, etc. can be mentioned. .

As the substrate 400, for example, aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, or the like can be used. In addition, when the temperature of the subsequent heat treatment is high, it is better to use a substrate with a strain point of 730°C or higher.

In addition, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can also be used.

An insulating layer serving as a base film may be provided between the substrate 400 and the gate electrode layers 421a and 421b. The base film has the function of preventing the diffusion of impurity elements from the substrate 400, and has a single-layer structure of a film selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film, or a plurality of the above-mentioned films. The laminated structure is formed.

Next, after forming a transparent conductive film to cover the gate electrode layers 421a and 421b, the gate electrode layers 451a and 451b are formed by a second photolithography process and an etching process. Note that the gate electrode layer 451b is equivalent to a gate wiring layer, but is shown as a gate electrode layer for convenience. As the light-transmitting conductive film, a conductive material having light-transmitting properties for visible light can be used, such as In-Sn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga -Zn-O type, Al-Ga-Zn-O type, Sn-Al-Zn-O type, In-Zn-O type, Sn-Zn-O type, Al-Zn-O type, In-O type, Metal oxides such as Sn-O and Zn-O. The thickness of the conductive film is appropriately selected within the range of 50 nm or more and 300 nm or less. In addition, when the sputtering method is used, SiO containing 2wt% or more and 10wt% or less can also be used for the above-mentioned conductive material.₂The target material for film formation.

In this embodiment mode, in order to reduce wiring resistance, the same metal film as the gate electrode layers 421a and 421b is used to form part of the gate wiring arranged in the pixel portion.

Next, a gate insulating layer 402 is formed on the gate electrode layers 421a, 421b, 451a, and 451b.

As the gate insulating layer 402, a light-transmitting insulating film such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxynitride layer can be used, and it can be made by a plasma CVD method or a sputtering method. form. In addition, the gate insulating layer 402 is not limited to a single layer of the above-mentioned insulating film, and a stack of different films may also be used. For example, silane (SiH₄), oxygen and nitrogen, and a silicon oxynitride film is formed by a plasma CVD method. The thickness of the gate insulating layer 402 is 100 nm or more and 500 nm or less. When a laminate is used, for example, a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer.

In this embodiment mode, as the gate insulating layer 402, silicon oxynitride (SiON (composition ratio N&lt;0)) formed by a plasma CVD method with a thickness of 100 nm is used.

Next, a light-transmitting conductive film is formed on the gate insulating layer 402, and then a source electrode layer 455a and a drain electrode layer 455b are formed through a third photolithography process and an etching process (refer to FIG. 1A).

For the light-transmitting conductive film, the same material as the gate electrode layers 451a and 451b can be used.

Then, through a fourth photolithography process and an etching process, the gate insulating layer 402 is selectively etched to form a contact hole reaching the gate electrode layer 421b.

Next, a light-transmitting oxide semiconductor film having a thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 20 nm or less, is formed on the gate insulating layer 402 by a sputtering method. In order to make the oxide semiconductor film in an amorphous state even after heat treatment for dehydration or dehydrogenation is performed after the oxide semiconductor film is formed, it is preferable to set the thickness to 50 nm or less. By making the thickness of the oxide semiconductor film thin, it is possible to suppress crystallization that occurs when heat treatment is performed later.

As the oxide semiconductor film, the following oxide semiconductor films can be used: In-Sn-Ga-Zn-O film of quaternary metal oxide, In-Ga-Zn-O film of ternary metal oxide, In-Sn- Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O film, binary metal oxide In-Zn -O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, and In-O film, Sn-O film, Zn-O film, etc. In addition, the above-mentioned oxide semiconductor film may also contain SiO₂。

In addition, as the oxide semiconductor film, it is possible to use InMO₃(ZnO)_m(m&gt;0) film. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, Ga and Co, and the like. In denoted as InMO₃(ZnO)_mIn the oxide semiconductor film of the structure of (m&gt;0), the oxide semiconductor of the structure containing Ga as M is called In-Ga-Zn-O-based oxide semiconductor, and the thin film is called In-Ga-Zn -O type non-single crystal film.

In this embodiment mode, an In-Ga-Zn-O-based oxide semiconductor target is used as the oxide semiconductor film, and an In-Ga-Zn-O-based non-single crystal film with a thickness of 15 nm is formed by a sputtering method.

The In-Ga-Zn-O-based non-single crystal film can be formed under the following conditions: In an oxygen (oxygen flow rate ratio of 100%) atmosphere, an In-Ga-Zn-O-based oxide semiconductor target (In₂O₃: Ga₂O₃: ZnO=1:1:1[molar ratio] (ie, In:Ga:Zn=1:1:0.5[atomic ratio])), the distance between the substrate and the target is set to 100mm, and the pressure is 0.6Pa , Direct current (DC) power is 0.5kW. In addition, a target having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] and In:Ga:Zn=1:1:2 [atomic ratio] can also be used. The filling rate of these targets is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high filling rate, the formed oxide semiconductor film becomes a dense film.

Among the sputtering methods, there are an RF sputtering method and a DC sputtering method that use a high-frequency power source as a sputtering power source, and there is also a pulsed DC sputtering method that applies a bias voltage in a pulsed manner. The RF sputtering method is mainly used for the formation of insulating films, and the DC sputtering method is mainly used for the formation of conductive films.

In addition, in order to reduce dust generated during deposition and improve the uniformity of thickness distribution, it is best to use pulsed direct current (DC) power for sputtering.

In addition, there is also a multi-element sputtering device that can set a plurality of targets whose materials are different from each other. The multi-element sputtering device can not only laminate and form films of different materials in the same processing chamber, but also discharge simultaneously in the same processing chamber to form films of multiple materials.

In addition, there are sputtering apparatuses that use the following sputtering methods: a magnetron sputtering method equipped with a magnet mechanism in the processing chamber; and an ECR sputtering method using plasma generated by microwaves without using glow discharge.

In addition, there is a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted during film formation to form a compound thin film; and a bias sputtering method in which a voltage is also applied to the substrate during film formation Wait.

In addition, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma before forming the oxide semiconductor film by the sputtering method to remove dust adhering to the surface of the gate insulating layer 402. Reverse sputtering refers to a method in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere, and the ionized argon collides with the substrate to change the surface properties. In addition, nitrogen, helium, oxygen, etc. may be used instead of argon.

In addition, before forming the oxide semiconductor film, heat treatment (400°C or higher and lower than the strain point of the substrate) in an inert atmosphere (nitrogen, helium, neon, argon, etc.) may be performed to remove the gate insulating layer 402. Impurities such as hydrogen, water, etc.

Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 403 and 453 by a fifth photolithography process and an etching process (see FIG. 1B). In addition, a resist mask for forming the island-shaped oxide semiconductor layers 403 and 453 may be formed by an inkjet method. By adopting the inkjet method, manufacturing costs can be reduced.

In addition, in this embodiment mode, before forming the oxide semiconductor film, the gate insulating layer is selectively etched by a fourth photolithography process and an etching process to form a contact hole reaching the gate electrode layer 421b . On the other hand, the contact hole may be formed after the island-shaped oxide semiconductor layers 403 and 453 are formed. In this case, it is preferable to perform reverse sputtering to remove resist residues and the like attached to the surfaces of the oxide semiconductor layers 403 and 453 and the gate insulating layer 402.

In addition, after forming an oxide semiconductor film on the gate insulating layer, a contact hole reaching the gate electrode layer 421b is formed, and then the oxide semiconductor film is selectively etched to process it into an island-shaped oxide semiconductor layer 403, 453.

Next, dehydration or dehydrogenation of the oxide semiconductor layers 403 and 453 is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is set to 400°C or higher and lower than the strain point of the substrate, preferably 425°C or higher. Note that when the temperature is 425°C or higher, the heat treatment time is less than one hour. However, when the temperature is lower than 425°C, the heat treatment time is longer than one hour.

Here, the substrate is introduced into an electric furnace, which is a kind of heat treatment device, and the oxide semiconductor layers 403 and 453 are heated in a nitrogen atmosphere. In this embodiment mode, the same furnace is used from the heating temperature T for dehydration or dehydrogenation of the oxide semiconductor layers 403 and 453 to a sufficient temperature at which water no longer enters. Specifically, the same furnace is used until it is lower than the heating temperature T100°C. The above is slow cooling under a nitrogen atmosphere. In addition, the atmosphere is not limited to nitrogen, and helium, neon, argon, etc. can also be used.

Note that in the first heat treatment, it is preferable that water, hydrogen, etc. are not included in nitrogen or a rare gas such as helium, neon, argon, and the like. Here, the purity of the rare gas such as nitrogen or helium, neon, and argon introduced into the heat treatment device is preferably set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher.

The oxide semiconductor layers 403 and 453 are sometimes crystallized by the first heat treatment to become a microcrystalline film or a polycrystalline film. In addition, the oxide semiconductor layers 403 and 453 become oxygen-deficient by the first heat treatment, and the carrier concentration is increased to 1×10.¹⁸/cm³Above, the resistance is therefore reduced. In addition, the gate electrode layers 451a and 451b may also be crystallized by the first heat treatment to become a microcrystalline film or a polycrystalline film. For example, when an indium oxide tin oxide alloy film is used as the gate electrode layers 451a and 451b, the first heat treatment is performed at 450°C for 1 hour to facilitate crystallization. However, when an indium oxide tin oxide alloy film containing silicon oxide is used as the gate electrode layers 451a and 451b, crystallization is not likely to occur.

In addition, the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer may be subjected to the first heat treatment of the oxide semiconductor layer. In this case, a fifth photolithography process is performed after the first heat treatment.

Next, a light-transmitting oxide insulating layer is formed on the gate insulating layer 402 and the oxide semiconductor layers 403 and 453 by a sputtering method. Furthermore, a resist mask is formed by a sixth photolithography process, an oxide insulating layer 426 is selectively formed by an etching process, and then the resist mask is removed. In this step, a structure in which the edges and sides of the oxide semiconductor layers 403 and 453 overlap with the oxide insulating layer 426 is adopted. In addition, through the sixth photolithography process and the etching process, a contact hole reaching the gate electrode layer 421b and a contact hole reaching the drain electrode layer 455b are formed (refer to FIG. 1C).

The oxide insulating layer 426 has a thickness of 1 nm or more, and can be formed by appropriately preventing the mixing of impurities such as water and hydrogen into the oxide insulating layer. In this embodiment mode, the oxide insulating layer 426 is formed using a silicon oxide film formed by a sputtering method.

What is necessary is just to set the substrate temperature during film formation to room temperature or more and 300 degrees C or less. In this embodiment mode, it is set to 100°C. The formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere.

In addition, as the target material, a silicon oxide target material or a silicon target material can be used. For example, in the case of using a silicon target, silicon oxide can be formed by sputtering in an atmosphere of oxygen and a rare gas. An inorganic insulating film is used as the oxide insulating layer formed in contact with the oxide semiconductor layers 403 and 453 with reduced resistance, and the inorganic insulating film does not contain moisture, hydrogen ions, or OH as much as possible^-And other impurities, and can block the above-mentioned impurities intruding from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used.

In this embodiment mode, a boron-added columnar polysilicon target (resistivity of 0.01Ωcm, purity of 6N) is used, and the distance between the substrate and the target (distance between TS) is set to 89mm, and The pressure was set to 0.4 Pa, the direct current (DC) power was set to 6 kW, and the film was formed by pulsed DC sputtering in an oxygen atmosphere (oxygen flow ratio was 100%). The thickness is set to 300 nm.

Next, a metal film is formed on the gate insulating layer 402, the oxide insulating layer 426, and the oxide semiconductor layers 403 and 453, and then a resist mask is formed by the seventh photolithography process, and the source is formed in the etching process. The electrode electrode layer 425a and the drain electrode layer 425b. In addition, a connection electrode layer 429 electrically connected to the gate electrode layer 421b and a connection electrode layer 452 electrically connected to the drain electrode layer 455b are also formed.

As a method for forming the metal film, a sputtering method, a vacuum vapor deposition method (e.g., electron beam vapor deposition method, etc.), an arc discharge ion plating method, or a spraying method can be used. As the metal film, an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta, an alloy containing the above-mentioned elements as a component, an alloy combining the above-mentioned elements, or the like is used. In addition, the metal film is not limited to a single layer of the above-mentioned elements, and a stacked layer of different elements may also be used. In this embodiment mode, a metal film having a three-layer structure of a titanium film (thickness of 100 nm), an aluminum film (thickness of 200 nm), and a titanium film (thickness of 100 nm) is formed. In addition, a titanium nitride film can also be used instead of the titanium film.

In addition, in the etching process after the seventh photolithography process, the metal film contacting the oxide semiconductor layers 403 and 453 needs to be selectively removed. In this case, by using an alkaline etchant (for example, hydrogen peroxide ammonia (31wt% hydrogen peroxide: 28wt% ammonia: water = 5: 2: 2)), etc., you can selectively The metal film is removed, and the oxide semiconductor layers 403 and 453 composed of In-Ga-Zn-O-based oxide semiconductors are left.

In addition, a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. By using the inkjet method, manufacturing costs can be reduced.

Next, a translucent oxide insulating layer 427 is formed on the oxide insulating layer 426, the source electrode layer 425a, the drain electrode layer 425b, the connection electrode layer 429, and the connection electrode layer 452 (see FIG. 1D). As the oxide insulating layer 427, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. In this embodiment mode, the oxide insulating layer 427 is formed using a silicon oxide film formed by a sputtering method.

Next, in an inert gas atmosphere such as nitrogen gas, the second heat treatment is performed at 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

In the second heat treatment, heating is performed in a state where the oxide insulating layer 427 and a part of the oxide semiconductor layer 403 and the oxide insulating layer 426 and the oxide semiconductor layer 453 are in contact. As a result, oxygen is supplied from the oxide insulating layers 427 and 426 to the oxide semiconductor layers 403 and 453 whose resistance is reduced by the first heating treatment, and the oxide semiconductor layers 403 and 453 become oxygen-excessive and increase the resistance. (Proceed to i-shape).

In addition, when the thickness of the oxide semiconductor layer 403 is thinner than 15 nm, in the region of the oxide semiconductor layer 403 that overlaps the source electrode layer 425a and the drain electrode layer 425b made of a metal film, oxygen in this region is likely to move To the metal film side, the entire area is n-typed. In addition, when the thickness of the oxide semiconductor layer 403 is 15 nm or more and 50 nm or less, although the vicinity of the interface between the metal film and the region is n-type, the lower side becomes i-type or n-type.^-The state of stereotypes.

Note that although in this embodiment mode, the second heat treatment is performed after the silicon oxide film is formed, the timing of the heat treatment only needs to be after the silicon oxide film is formed, and is not limited to just after the silicon oxide film is formed.

Next, a protective insulating layer 428 having translucency is formed on the oxide insulating layer 427 (see FIG. 1E). As the protective insulating layer 428, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or the like is used. In this embodiment mode, the protective insulating layer 428 is formed using a silicon nitride film formed by an RF sputtering method.

In addition, although not shown, a flattening insulating layer having translucency may be provided between the oxide insulating layer 427 and the protective insulating layer 428 in the pixel portion. As the planarization insulating layer, an organic material having heat resistance, such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, or epoxy-based resin, can be used. In addition, in addition to the above-mentioned organic materials, low dielectric constant materials (low-k materials), silicone resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, a plurality of insulating layers formed of these materials may be stacked.

Through the above process, the channel etching transistor 450 and the bottom contact transistor 460 can be manufactured on the same substrate. In addition, since in the bottom contact transistor 460, the portion other than the connection electrode layer 452 is made of a material having light transmittance, the aperture ratio can be increased.

The channel etching type such as the transistor 450 is easy to form a short channel length, which is advantageous for the formation of a transistor such as a driving circuit that requires high-speed operation. In other words, it is possible to manufacture a display device that can perform high-speed operation compared to a case where a plurality of circuits formed on the same substrate are all formed using a bottom contact type such as the transistor 460.

In addition, the pixel electrode required by the display device is disposed on the protective insulating layer 428 of the pixel portion, and is electrically connected to the drain electrode layer of the transistor 460. Here, it is sufficient to connect to the connection electrode layer 452. In addition, as the pixel electrode, a transparent conductive film similar to the gate electrode layers 451a and 451b, the source electrode layer 455a, and the drain electrode layer 455b can be used.

The gist of an embodiment of the present invention is that in a display device including a driving circuit and a pixel circuit on the same substrate, in order to easily obtain the electrical characteristics required by the circuit, transistors with different structures are used to form each of the circuits. As in this embodiment mode, by using the channel-etched transistor 450 as the driving circuit and the bottom contact type transistor 460 as the pixel circuit, a display device with superior display characteristics can be manufactured.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 2]

In this embodiment mode, FIGS. 2A to 2E show an example in which a part of the manufacturing process of the transistor is different from that in Embodiment Mode 1. Since the manufacturing process of FIGS. 2A to 2E is the same as the manufacturing process of FIGS. 1A to 1E except for a part thereof, the same reference numerals are used to denote the same parts and detailed descriptions of the same parts are omitted.

First, according to Embodiment Mode 1, the gate electrode layers 421a, 451a and the gate insulating layer 402 are formed on a substrate, and a part of the source electrode layer 455a and the gate electrode layer 451a overlapped with the gate electrode layer 451a via the gate insulating layer 402 are formed. Drain electrode layer 455b. Furthermore, an oxide semiconductor film is formed on the gate insulating layer 402, the source electrode layer 455a, and the drain electrode layer 455b.

Next, dehydration or dehydrogenation of the oxide semiconductor film is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and lower than the strain point of the substrate, preferably 425°C or higher. Note that when the temperature is 425°C or higher, the heat treatment time is less than 1 hour, and when the temperature is lower than 425°C, the heat treatment time is longer than 1 hour. Here, the substrate is placed in an electric furnace, which is one of the heat treatment devices, to heat the oxide semiconductor film in a nitrogen atmosphere, and then the oxide semiconductor film is prevented from being mixed with water and hydrogen again without contacting the atmosphere. Then, introduce high-purity oxygen gas and high-purity N in the same furnace₂O gas or ultra-dry air (the dew point is below -40°C, preferably below -60°C) for cooling. It is best not to use oxygen gas or N₂O gas contains water, hydrogen and so on. Or, the oxygen gas or N₂The purity of O gas is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the oxygen gas or N₂The impurity concentration in O gas is set to 1 ppm or less, preferably 0.1 ppm or less).

In addition, after the first heat treatment of dehydration and dehydrogenation, in oxygen gas or N₂The heat treatment is performed at a temperature of 200°C or more and 400°C or less, preferably at a temperature of 200°C or more and 300°C or less in an O gas atmosphere.

Through the above-mentioned process, the entire oxide semiconductor film is in a state of excess oxygen, so that the resistance of the oxide semiconductor film can be increased, that is, an I-type can be achieved. In this embodiment mode, an example is shown in which the first heat treatment is performed immediately after the oxide semiconductor film is formed, but the first heat treatment is not particularly limited as long as it is performed after the oxide semiconductor film is formed.

Next, a resist mask is formed by a photolithography process, and the oxide semiconductor film and the gate insulating layer 402 are selectively etched by an etching process to form a contact hole reaching the gate electrode layer 421b. Then, the resist mask is removed (refer to FIG. 2A).

Then, a resist mask is formed by a photolithography process, and the oxide semiconductor film is selectively etched by an etching process to be processed into an island shape. Then, the resist mask is removed to form oxide semiconductor layers 404 and 405 on the gate insulating layer 402 (refer to FIG. 2B).

Next, after forming an oxide insulating layer on the gate insulating layer 402 and the oxide semiconductor layers 404 and 405 by a sputtering method, a resist mask is formed by a photolithography process. Furthermore, the oxide insulating layer 426 is formed by an etching process, and the resist mask is removed. In this step, a region where the oxide semiconductor layers 404 and 405 and the oxide insulating layer 426 overlap are formed. In addition, through this process, a contact hole reaching the gate electrode layer 421b and a contact hole reaching the drain electrode layer 455b are formed (refer to FIG. 2C).

It is best to use an inorganic insulating film as the oxide insulating layer, which does not contain moisture, hydrogen or OH as much as possible^-And other impurities, and can block the above-mentioned impurities intruding from the outside. Typically, a silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, or the like can be used.

Next, a stack of an oxide conductive film and a metal film is formed on the gate insulating layer 402, the oxide insulating layer 426, and the oxide semiconductor layers 404 and 405. With the sputtering method, a stack of an oxide conductive film and a metal film can be continuously formed without exposure to the atmosphere.

As the oxide conductive film, it is preferable to use a material containing a zinc oxide component and not containing indium oxide. Examples of such oxide conductive films include zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, and the like. In this embodiment mode, a zinc oxide film is used.

As the metal film, an element selected from the group consisting of Ti, Mo, W, Al, Cr, Cu, and Ta, an alloy containing the aforementioned elements as a component, an alloy combining the aforementioned elements, or the like can be used. In addition, the metal film is not limited to a single layer of the above-mentioned elements, and a stacked layer of different elements may also be used. In this embodiment mode, a three-layer laminated film in which an aluminum film, an aluminum film, and a molybdenum film are laminated is used.

Next, a resist mask is formed by a photolithography process, and the metal film is selectively etched by an etching process to form a source electrode layer 445a, a drain electrode layer 445b, a connection electrode layer 449, and a connection electrode layer 442, Then the resist mask is removed.

In addition, the resist stripping solution used to remove the resist mask is an alkaline solution. When a resist stripping solution is used, the zinc oxide film is also selectively etched using the electrode layer as a mask. Therefore, an oxide conductive layer 446a in contact with the source electrode layer 445a and an oxide conductive layer 446b in contact with the drain electrode layer 445b are formed.

Note that since the oxide semiconductor layer and the oxide conductive layer have different etching speeds, the oxide conductive layer in contact with the oxide semiconductor layer can be removed by time control.

In addition, after the metal film is selectively etched, the resist mask is removed by an oxygen ashing process, and then the source electrode layer 445a, the drain electrode layer 445b, the connection electrode layer 449 and the connection electrode layer 442 is a mask that selectively etches the zinc oxide film.

The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer 404 serves as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer 404 serves as a source region. For the drain area. By providing the oxide conductive layer 446a and the oxide conductive layer 446b, the contact resistance between the oxide semiconductor layer 404 and the source electrode layer 445a and the drain electrode layer 445b can be reduced. In this way, the transistor with the reduced resistance of the current path can operate at high speed, thereby improving the frequency characteristics of the peripheral circuit (drive circuit).

Molybdenum is a material with high contact resistance with an oxide semiconductor. This is because molybdenum is less likely to be oxidized than titanium, and therefore has a weaker effect of extracting oxygen from the oxide semiconductor layer, and the contact interface of the oxide semiconductor layer is not n-typed. In this case, sandwiching the oxide conductive layer between the oxide semiconductor layer and the metal electrode layer is very effective in reducing contact resistance.

In addition, the oxide conductive layer 448 in contact with the connection electrode layer 449 is formed by the same process, and the oxide conductive layer 447 in contact with the connection electrode layer 442 is formed (see FIG. 2D).

Next, the second heating treatment may also be performed under an inert gas atmosphere, such as a nitrogen atmosphere, to reduce the unevenness of the electrical characteristics of the transistor. It is preferable to perform the second heat treatment at 150°C or higher and lower than 350°C, for example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere.

In addition, the second heat treatment allows oxygen to penetrate or diffuse into the oxide semiconductor layers 404 and 454. By allowing oxygen to invade or diffuse into the oxide semiconductor layers 404 and 454, the resistance of the channel formation region can be increased (i-shaped). Thus, it is possible to obtain a transistor whose electrical characteristics become normally off. In addition, by the second heating treatment, the oxide conductive layers 446a, 446b, 447, and 448 can also be crystallized and the conductivity can be improved.

Next, an oxide insulating layer 427 and a protective insulating layer 428 are formed on the oxide insulating layer 426, the source electrode layer 445a, and the drain electrode layer 445b (refer to FIG. 2E). The oxide insulating layer 427 and the protective insulating layer 428 can be formed using the same materials and manufacturing methods as in Embodiment Mode 1.

The transistor 440 and the transistor 460 can be manufactured on the same substrate by the above-mentioned process.

The transistor 440 arranged in the driving circuit is composed of a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 404, an oxide conductive layer 446a, 446b, a source electrode layer 445a and a substrate 400 having an insulating surface. The drain electrode layer 445b is formed. Here, the oxide semiconductor layer 404 includes at least a channel formation region 443, a high-resistance source region 444a, and a high-resistance drain region 444b. In addition, an oxide insulating layer 427 and a protective insulating layer 428 are provided on the channel formation region 443, the source electrode layer 445a, and the drain electrode layer 445b.

An oxide conductive layer 446a serving as a source region is provided between the high resistance source region 444a and the source electrode layer 445a, and a drain region is provided between the high resistance drain region 444b and the drain electrode layer 445b. The oxide conductive layer 446b, thereby reducing the contact resistance.

In addition, the first region 444c and the second region 444d of the oxide semiconductor layer 404 overlapping the oxide insulating layer 426 are in the same oxygen excess state as the channel formation region 443, and have a function of reducing leakage current or parasitic capacitance. In addition, when the oxide insulating layer 426 has a structure that does not overlap with the oxide semiconductor layer 404, the first region 444c and the second region 444d of the oxide semiconductor layer 404 are not formed.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 3]

In this embodiment mode, the active matrix substrate shown in Embodiment Mode 1 or 2 is used to constitute an example of a liquid crystal display device.

FIG. 3 shows an example of the cross-sectional structure of the active matrix substrate.

Although in Embodiment Modes 1 and 2, the transistor of the drive circuit portion, the transistor of the pixel portion, and the contact portion of the gate wiring (gate electrode) are shown on the same substrate, in addition, in this embodiment In the mode, the intersection of the storage capacitor, the gate wiring, and the source wiring can also be illustrated for description.

The capacitors, gate wiring, and source wiring can be formed by the same manufacturing process as the manufacturing process shown in Embodiment Mode 1 or 2, without increasing the number of photomasks and the number of manufacturing processes. In addition, in the portion of the pixel portion that becomes the display area, the gate wiring, the source wiring, and the capacitor wiring layer are formed of a light-transmitting conductive film, thereby achieving a high aperture ratio. In addition, as the source wiring layer of a portion other than the display area, metal wiring may be used to reduce wiring resistance.

In FIG. 3, the transistor 450 is a transistor provided in the driving circuit part, and the transistor 460 electrically connected to the pixel electrode layer 457 is a transistor provided in the pixel part.

In this embodiment mode, as the transistor 460 formed over the substrate 400, the same structure as the transistor 460 of the embodiment mode 1 or 2 is adopted.

The capacitor wiring layer 430 formed using the same transparent material and the same manufacturing process as the gate electrode layer 451a of the transistor 460 overlaps the capacitor electrode 431 with the gate insulating layer 402 as a dielectric to form a storage capacitor. In addition, the capacitor electrode 431 is formed using the same transparent material and the same manufacturing process as the source electrode layer 455a or the drain electrode layer 455b of the transistor 460. Therefore, because the transistor 460 has light transmittance and the storage capacitor also has light transmittance, the aperture ratio can be improved.

In terms of improving the aperture ratio, it is important for the storage capacitor to have light transmittance. In particular, in a small liquid crystal display panel of 10 inches or less, even if the pixel size is miniaturized, a high aperture ratio can be achieved. Since a transparent film is used as a structural member of the transistor 460 and the storage capacitor to achieve a wide viewing angle, even if one pixel is divided into a plurality of sub-pixels, a high aperture ratio can be achieved. For example, when two to four sub-pixels and storage capacitors are included in one pixel, since the transistor has light transmittance and each storage capacitor has light transmittance, the aperture ratio can be improved.

In addition, a storage capacitor is provided under the pixel electrode layer 457, and the capacitor electrode 431 is electrically connected to the pixel electrode layer 457.

Although this embodiment mode shows an example in which the capacitor wiring layer 430, the gate insulating layer 402, and the capacitor electrode 431 are used to form a storage capacitor, there is no particular limitation on the structure of the storage capacitor. For example, instead of providing a capacitor wiring layer, a part of the gate wiring of adjacent pixels may be used as the capacitor wiring layer. In addition, in addition to the gate insulating layer, an insulating layer for the structure of the pixel portion, such as a protective insulating layer and a planarizing insulating layer, can also be used as a dielectric.

In addition, a plurality of gate wiring layers, a plurality of source wiring layers, and a plurality of capacitor wiring layers are provided according to the pixel density. In addition, a plurality of first terminal electrodes having the same potential as the gate wiring, a plurality of second terminal electrodes having the same potential as the source wiring, and a plurality of having the same potential as the capacitor wiring layer are arranged in the terminal portion. The potential of the third terminal electrode and so on. Any number of terminal electrodes may be provided, and the implementer may appropriately determine the number of terminal electrodes.

In the gate wiring contact portion, the gate electrode layer 421b may be formed of a low-resistance metal material. The gate electrode layer 421b is electrically connected to the connection electrode layer 429 through a contact hole reaching the gate wiring.

The gate electrode layer of the transistor 450 of the driving circuit may also adopt a structure that is electrically connected to the conductive layer 417 provided above the oxide semiconductor layer.

In addition, in the wiring intersection, as shown in FIG. 3, a gate insulating layer 402 and an oxide insulating layer 426 are laminated between the gate wiring layer 421c and the source wiring layer 422 to reduce parasitic capacitance. Note that although FIG. 3 shows an example in which a metal film is used as the gate wiring layer 421c, it is also possible to form the gate wiring layer using the same transparent conductive film as the gate electrode layer 451a of the transistor 460. 421c.

In addition, when an active matrix type liquid crystal display device is manufactured, a liquid crystal layer is provided between the active matrix substrate and the counter substrate provided with the counter electrode to fix the active matrix substrate and the counter substrate. In addition, a common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrode electrically connected to the common electrode is provided on the terminal portion. The fourth terminal electrode is a terminal used to set the common electrode to a fixed potential, such as GND, 0V, and so on. The fourth terminal electrode may be formed of the same material having translucency as the pixel electrode layer 457.

By using the same material for the gate electrode, source electrode, drain electrode, pixel electrode, other electrodes, and various wiring layers, a common sputtering target and manufacturing device can be used. In addition, the material cost and the cost required for the etchant and etching gas used during etching can be reduced. As a result, the manufacturing cost can be reduced.

In addition, in the structure of FIG. 3, when a photosensitive resin material is used as the planarization insulating layer 456, the process of forming a resist mask can be omitted.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 4]

In addition, in this embodiment mode, an example of the structure of the terminal portion provided on the same substrate as the transistor will be described with reference to FIGS. 4A1, 4A2, 4B1, and 4B2. Note that the parts in FIGS. 4A1, 4A2, 4B1, and 4B2 that are the same as those in FIG. 3 are described using the same reference numerals.

4A1 and 4A2 respectively show a cross-sectional view and a plan view of the gate wiring terminal portion. Fig. 4A1 corresponds to a cross-sectional view taken along the line C1-C2 in Fig. 4A2.

In FIG. 4A1, the conductive layer 415 formed on the stack of the oxide insulating layer 427 and the protective insulating layer 428 is a connection terminal electrode used as an input terminal. In addition, in the terminal portion of FIG. 4A1, the first terminal 411 formed of the same material as the gate wiring layer 421c and the connection electrode layer 412 formed of the same material as the source wiring layer 422 are interposed by the gate insulating layer 402. They overlap and are conducted by the conductive layer 415. The conductive layer 415 can be formed by using the same transparent material and the same manufacturing process as the pixel electrode layer 457.

4B1 and 4B2 respectively show a cross-sectional view and a plan view of the source wiring terminal portion. Fig. 4B1 corresponds to a cross-sectional view taken along the line C3-C4 in Fig. 4B2.

In FIG. 4B1, the conductive layer 418 formed on the stack of the oxide insulating layer 427 and the protective insulating layer 428 is a connection terminal electrode used as an input terminal. In the terminal portion of FIG. 4B1, the electrode layer 416 formed of the same material as the gate wiring layer 421c overlaps the second terminal 414 electrically connected to the source wiring via the gate insulating layer 402. The electrode layer 416 and the second terminal 414 are not electrically connected, but by setting the electrode layer 416 to a different potential from the second terminal 414, such as a floating state, GND, 0V, etc., it can be used as a capacitor for preventing noise or with For antistatic capacitors. In addition, the second terminal 414 is electrically connected to the conductive layer 418. The conductive layer 418 can be formed by using the same transparent material and the same manufacturing process as the pixel electrode layer 457.

In addition, a plurality of gate wirings, a plurality of source wirings, a plurality of common potential lines, and a plurality of power supply lines are provided according to the pixel density. In addition, a plurality of first terminals having the same potential as the gate wiring, a plurality of second terminals having the same potential as the source wiring, and a plurality of having the same potential as the power supply line are arranged in the terminal portion. The third terminal electrode, a plurality of fourth terminals having the same potential as the common potential line, and the like. Arbitrary number of terminals are provided, and the implementer decides the number of terminals appropriately.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 5]

In this embodiment mode, an example of the structure and manufacturing method of a liquid crystal display device will be described.

Although a display device including a liquid crystal element (also referred to as a liquid crystal display element) is described in this embodiment mode, it is not limited to this, and a display medium whose contrast changes due to electrical action, such as electronic ink, can be applied.

In addition, the display device described in the present invention includes a panel in which a display element is sealed, an IC (Integrated Circuit) for operating the panel, and the like. In addition, each pixel of the element substrate on which the display element is formed includes a unit for supplying current to the display element. In addition, the display device also includes: a module mounted with connectors such as FPC (Flexible Printed Circuit), TAB (Tape Automated Bonding) tape, or TCP (Tape Carrier Package) ; A module with a printed circuit board is arranged on the end of the TAB tape or TCP; a module in which the IC is directly mounted on the display element by the COG (Chip On Glass) method.

The appearance and cross section of a liquid crystal display panel corresponding to an embodiment of the display device will be described with reference to FIGS. 5A1, 5A2, and 5B. 5A1 and 5A2 are plan views of a panel in which a sealing material 4005 is used to seal the transistors 4010, 4011 and the liquid crystal element 4013 between the first substrate 4001 and the second substrate 4006. Fig. 5B corresponds to a cross-sectional view of MN along Figs. 5A1 and 5A2.

A sealing material 4005 is provided in a manner to surround the pixel portion 4002 and the scan line driving circuit 4004 provided on the first substrate 4001. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scan line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed by the first substrate 4001, the sealing material 4005, and the second substrate 4006 together with the liquid crystal layer 4008. In addition, a signal line driver circuit 4003 is mounted on the first substrate 4001 in a region different from the region surrounded by the sealing material 4005. The signal line driver circuit 4003 is formed using a single crystal semiconductor film or a polycrystalline semiconductor film in a separately prepared area. On the substrate.

Note that there is no particular limitation on the connection method of the separately formed drive circuit, and the COG method, wire bonding method, TAB method, or the like can be used. FIG. 5A1 is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 5A2 is an example of mounting the signal line driving circuit 4003 by the TAB method.

In addition, the pixel portion 4002 and the scan line driving circuit 4004 provided on the first substrate 4001 include a plurality of transistors. FIG. 5B illustrates a transistor 4010 included in the pixel portion 4002 and a transistor 4011 included in the scan line driving circuit 4004. Insulating layers 4041, 4020, and 4021 are provided on the transistors 4010 and 4011.

The highly reliable transistor including the oxide semiconductor layer shown in Embodiment Mode 1 or 2 can be applied to the transistors 4010 and 4011. As the transistor 4011 for the driving circuit, the transistor 450 shown in Embodiment Mode 1 or 2 can be used, and as the transistor 4010 for the pixel, the transistor 460 shown in Embodiment Mode 1 or 2 can be used. In this embodiment mode, the transistors 4010 and 4011 are n-channel type transistors.

A conductive layer 4040 is provided on the insulating layer 4021 at a position overlapping the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By disposing the conductive layer 4040 at a position overlapping the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 can be reduced. In addition, the potential of the conductive layer 4040 may be the same as the potential of the gate electrode layer of the transistor 4011 or different from the potential of the gate electrode layer of the transistor 4011. Also, the conductive layer 4040 may be used as the second gate electrode layer. In addition, the potential of the conductive layer 4040 may also be GND, 0V, or a floating state.

In addition, the pixel electrode 4030 included in the liquid crystal element 4013 is electrically connected to the transistor 4010. Furthermore, the counter electrode 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The overlapping portion of the pixel electrode 4030, the counter electrode 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. In addition, the pixel electrode 4030 and the counter electrode 4031 are respectively provided with insulating layers 4032 and 4033 serving as alignment films.

In addition, as the first substrate 4001 and the second substrate 4006, light-transmitting substrates such as glass, ceramics, and plastics can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics; glass fiber reinforced plastic) board, PVF (polyvinyl fluoride) film, polyester film, or acrylic resin film can be used.

In addition, reference numeral 4035 denotes a columnar spacer obtained by selectively etching the insulating layer, and it is provided for controlling the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. In addition, spherical spacers can also be used.

In addition, the counter electrode 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. The common connection portion may be used to electrically connect the counter electrode 4031 and the common potential line through conductive particles arranged between a pair of substrates. In addition, conductive particles are included in the sealing material 4005.

In addition, it is also possible to use a liquid crystal exhibiting a blue phase without using an alignment film. The blue phase is a type of liquid crystal phase, and refers to the phase that appears before the cholesteric phase changes to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase only appears in a narrow temperature range, when used in the liquid crystal layer 4008, in order to improve the temperature range, a liquid crystal composition mixed with a chiral agent in an amount of 5 wt% or more is used. Since the liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has the following characteristics: the response speed is short, that is, 1 msec or less, and it is optically isotropic, so alignment processing is not required, and the viewing angle dependence is low.

In the transistor 4011, an insulating layer 4041 is formed in contact with the oxide semiconductor layer. The insulating layer 4041 can be formed using the same material and method as the oxide insulating layer 427 shown in Embodiment Mode 1. Here, a silicon oxide film formed by a sputtering method is used.

In addition, a protective insulating layer 4020 is formed on the insulating layer 4041. The insulating layer 4020 may be formed using the same material and method as the protective insulating layer 428 shown in Embodiment Mode 1. Here, a silicon oxide film formed by a plasma CVD method is used as the protective insulating layer 4020.

In addition, an insulating layer 4021 is formed as a planarizing insulating layer. As the insulating layer 4021, an organic material having heat resistance, such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, epoxy-based resin, etc., can be used. In addition, in addition to the above-mentioned organic materials, low dielectric constant materials (low-k materials), silicone resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, the insulating layer 4021 may be formed by stacking a plurality of insulating layers formed of these materials.

In addition, the silicone-based resin is equivalent to a resin containing Si-O-Si bonds formed from a silicone-based material as a starting material. As the substituent of the silicone resin, an organic group (for example, an alkyl group, an aryl group) and a fluorine group can also be used. In addition, the organic group may have a fluorine group.

In addition, the method of forming the insulating layer 4021 is not particularly limited, and according to its material, sputtering, SOG, spin coating, dipping, spraying, inkjet, screen printing, offset printing, etc. can be used, and a doctor blade, Roll coater, curtain coater, knife coater, etc. are formed. The firing process and the annealing of the semiconductor layer are also used as the insulating layer 4021, so that the process can be reduced.

As the pixel electrode 4030 and the counter electrode 4031, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium containing titanium oxide can be used. Tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and the like.

In addition, the pixel electrode 4030 and the counter electrode 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The sheet resistance of the pixel electrode formed using the conductive composition is preferably 10000 Ω/ or less, and the light transmittance at a wavelength of 550 nm is preferably 70% or more. In addition, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1Ω. cm below.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of the above-mentioned materials, and the like can be mentioned.

In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003, scanning line driving circuit 4004, or pixel portion 4002 are supplied by the FPC 4018.

The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode 4030, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the transistor 4011.

The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

In addition, although FIGS. 5A1, 5A2, and 5B show an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001, it is not limited to this structure. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

FIG. 6 shows an example of a liquid crystal display module configured as a display device using a transistor substrate 2600 manufactured according to the manufacturing method disclosed in the description of the present invention.

The transistor substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a transistor, etc., a display element 2604 including a liquid crystal layer, and a colored layer 2605 are disposed therebetween to form a display area.

The colored layer 2605 is required when performing color display. When the RGB method is adopted, a coloring layer corresponding to each color of red, green, and blue is provided for each pixel. Polarizing plates 2606 and 2607 and a diffusion sheet 2613 are arranged outside the transistor substrate 2600 and the counter substrate 2601.

The light source is composed of a cold cathode tube 2610 and a reflecting plate 2611. The circuit board 2612 incorporates peripheral circuits such as a control circuit and a power supply circuit, and is connected to the wiring circuit portion 2608 of the transistor substrate 2600 via a flexible wiring board 2609. In addition, a phase difference plate may be provided between the polarizing plate and the liquid crystal layer.

As a liquid crystal display module, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (multi-domain vertical Alignment; Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optical Compensated) Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc.

Through the above process, a liquid crystal display panel with high reliability as a display device can be manufactured.

In addition, this embodiment mode can be appropriately combined with other embodiment modes.

[Embodiment Mode 6]

In this embodiment mode, an example of operating a driving circuit and a pixel portion composed of a transistor manufactured on the same substrate will be described.

In this embodiment mode, the method for manufacturing a transistor according to Embodiment Mode 1 is used to form the pixel portion and the driving circuit portion on the same substrate. Note that the transistor shown in Embodiment Mode 1 is an n-channel type transistor, and the drive circuit section is limited to a part of the circuit that can be composed of only the n-channel type transistor.

FIG. 7A shows an example of a block diagram of an active matrix display device. Disposed on the substrate 5300 of the display device are: a pixel portion 5301; a first scanning line driving circuit 5302; a second scanning line driving circuit 5303; and a signal line driving circuit 5304. A plurality of signal lines extending from the signal line driver circuit 5304 and a plurality of scan lines extending from the first scan line driver circuit 5302 and the second scan line driver circuit 5303 are arranged in the pixel portion 5301. In addition, pixels with display elements are arranged in a matrix in the intersection area of the scan line and the signal line. In addition, the substrate 5300 of the display device is connected to the timing control circuit 5305 (also referred to as a controller or a control IC) through a connection portion such as FPC (Flexible Printed Circuit).

The first scan line driver circuit 5302, the second scan line driver circuit 5303, and the signal line driver circuit 5304 shown in FIG. 7A are formed on the same substrate 5300 as the pixel portion 5301. As a result, the number of components such as a drive circuit provided outside is reduced, so that cost reduction can be achieved. In addition, since the connection portion (FPC, etc.) between the substrate 5300 and an external drive circuit can be reduced, reliability and yield can be improved.

In addition, the timing control circuit 5305 supplies the first scan line driver circuit start signal (GSP1), the scan line driver circuit clock signal (GCLK1), and the like to the first scan line driver circuit 5302. In addition, the timing control circuit 5305 supplies a second scan line driver circuit start signal (GSP2) (also referred to as a start pulse), a scan line driver circuit clock signal (GCLK2), and the like to the second scan line driver circuit 5303.

In addition, the timing control circuit 5305 supplies the signal line driver circuit start signal (SSP), the signal line driver circuit clock signal (SCLK), the video signal data (DATA) (also simply referred to as the video signal) and the lock signal to the signal line driver circuit 5304. Save the signal (LAT) and so on. In addition, each clock signal may be a plurality of clock signals whose periods are shifted or a signal supplied together with a signal (CKB) that inverts the clock signal. In addition, one of the first scan line driver circuit 5302 or the second scan line driver circuit 5303 may be omitted.

FIG. 7B shows a structure in which a circuit with a low driving frequency (for example, the first scan line driver circuit 5302, the second scan line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and is different from the pixel portion 5301. A signal line driver circuit 5304 is formed on the substrate. By adopting this structure, even if a transistor with low field-effect mobility is used, a part of the driving circuit can be formed on the same substrate as the pixel portion. Thus, it is possible to achieve cost reduction or yield improvement.

Next, an example of the structure and operation of a signal line driver circuit composed of n-channel transistors will be described with reference to FIGS. 8A and 8B.

The signal line driving circuit has a shift register 5601 and a switch circuit 5602. The switch circuit 5602 is composed of off circuits 5602_1 to 5602_N (N is a natural number). In addition, the switch circuits 5602_1 to 5602_N are respectively composed of transistors 5603_1 to 5603_k (k is a natural number). Here, the transistors 5603_1 to 5603_k are n-channel type TFTs.

Take the switch circuit 5602_1 as an example to illustrate the connection relationship of the signal line driving circuit. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. The gates of the transistors 5603_1 to 5603_k are connected to the wiring 5605_1.

The shift register 5601 has the function of sequentially outputting signals of H level (also referred to as H signal, high power supply potential level) to the wirings 5605_1 to 5605_N, and sequentially selecting switch circuits 5602_1 to 5602_N.

The switch circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) of the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, whether the potentials of the wirings 5604_1 to 5604_k are supplied or not to the signal lines S1 to S1. The function of Sk. In this way, the switch circuit 5602_1 has a function as a selector. In addition, the transistors 5603_1 to 5603_k respectively have the function of controlling the conduction state of the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, the function of supplying the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. In this way, the transistors 5603_1 to 5603_k each have a function as a switch.

In addition, video signal data (DATA) are input to the wirings 5604_1 to 5604_k, respectively. In many cases, the video signal data (DATA) is an analog signal based on image information or video signals.

Next, the operation of the signal line driver circuit of FIG. 8A will be described with reference to the timing chart of FIG. 8B. FIG. 8B shows an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, and the signals Vdata_1 to Vdata_k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. In addition, one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. As an example, one gate selection period is divided into a period T1 to a period TN. The period T1 to the period TN are respectively the periods for writing the video signal data (DATA) to the pixels belonging to the selected column.

In the drawings shown in this embodiment mode, the distortion of the signal waveform of each structure may be exaggerated for clarity. Therefore, it is not limited to the dimensions shown.

In the period T1 to the period TN, the shift register 5601 sequentially outputs signals of the H level to the wirings 5605_1 to 5605_N. For example, in the period T1, the shift register 5601 outputs a high-level signal to the wiring 5605_1. At this time, the transistors 5603_1 to 5603_k are turned on, and the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state. Then, Data (S1) to Data (Sk) are input to the wirings 5604_1 to 5604_k. Data (S1) to Data (Sk) are written into the pixels of the first row to the k-th row among the pixels belonging to the selected column by the transistors 5603_1 to 5603_k, respectively. Through the above steps, in the periods T1 to TN, the video signal data (DATA) is sequentially written to every k rows of pixels belonging to the selected column.

As described above, by writing the data (DATA) for the video signal to the pixels of each plurality of rows, the number of the data (DATA) for the video signal or the number of wirings can be reduced. Therefore, the number of connections with external circuits can be reduced. In addition, by writing the video signal to the pixels of each of the multiple rows, the writing time can be extended, and therefore, insufficient writing of the video signal can be prevented.

In addition, as the shift register 5601 and the switch circuit 5602, a circuit composed of the transistor shown in Embodiment Mode 1 or 2 can be used. At this time, the polarities of all the transistors of the shift register 5601 can be made of unipolar transistors.

Next, the structure of the scanning line drive circuit will be described. The scan line driving circuit has a shift register. In addition, a level shifter, a buffer, etc. may also be provided in some cases. In the scan line driving circuit, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register. The generated selection signal is buffered and amplified in the buffer and supplied to the corresponding scan line. The scan line is connected to the gate electrode of the transistor of the pixel of a row. Furthermore, since the transistors of the pixels of a row need to be turned on at the same time, a buffer capable of flowing a large current is used.

An embodiment of a shift register that is a part of the scan line driver circuit and/or the signal line driver circuit will be described with reference to FIGS. 9A to 9D and FIGS. 10A and 10B.

The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number greater than 3) (refer to FIG. 9A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register are supplied with a first clock signal CK1 from the first wiring 11, a second clock signal CK2 from the second wiring 12, and a third wiring 13 The third clock signal CK3 is supplied with the fourth clock signal CK4 from the fourth wiring 14.

In addition, a start pulse SP1 (first start pulse) from the fifth wiring 15 is input to the first pulse output circuit 10_1. In addition, a signal from the pulse output circuit of the previous stage (referred to as the previous-stage signal OUT(n-1)) is input to the n-th pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than N) in the second and subsequent stages.

In addition, a signal from the third pulse output circuit 10_3 of the latter stage is input to the first pulse output circuit 10_1. Similarly, the signal from the (n+2)th pulse output circuit 10_(n+2) of the latter stage (the latter-stage signal OUT(n+2)) is input to the n-th pulse output circuit 10_n after the second stage.

Thus, the first output signal (OUT(1)(SR) to OUT(N)(SR)) and electrical output are output from the pulse output circuit of each stage for input to the pulse output circuit of the subsequent stage and/or the previous stage. The second output signals OUT(1) to OUT(N) input to other circuits and the like. In addition, as shown in FIG. 9A, since the rear-stage signal OUT(n+2) is not input to the last two stages of the shift register, as an example, separately input the second start pulse SP2 and the third stage signal OUT(n+2). The structure of the start pulse SP3 is sufficient.

In addition, the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at a certain interval. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1/4 cycle (that is, the phases are shifted by 90°). In this embodiment mode, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal is sometimes referred to as GCK or SCK depending on the input drive circuit, and it is referred to as CK here.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 9A, in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected To the third wiring 13. Furthermore, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. .

The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N respectively include a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, and a first output terminal 26. , The second output terminal 27 (refer to FIG. 9B).

In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third clock signal CK3 is input to the third input terminal 23. The four input terminal 24 inputs the start pulse, the fifth input terminal 25 inputs the subsequent stage signal OUT(3), the first output signal OUT(1)(SR) is output from the first output terminal 26, and the second output terminal 27 is output The second output signal OUT(1).

In addition, as the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N, a four-terminal transistor 28 may be used in addition to the three-terminal transistor (refer to FIG. 9C). In addition, in the description of the present invention, when the transistor has two gate electrodes across the semiconductor layer, the gate electrode located below the semiconductor layer is also referred to as the lower gate electrode, and the gate electrode located above the semiconductor layer The gate electrode is also called the upper gate electrode. The transistor 28 is an element that can electrically control between the In terminal and the Out terminal by the first control signal G1 input to the lower gate electrode and the second control signal G2 input to the upper gate electrode.

When an oxide semiconductor is used for the semiconductor layer of the transistor including the channel formation region, the threshold voltage sometimes shifts to the negative side or the positive side due to the manufacturing process. Therefore, in a transistor that uses an oxide semiconductor for the semiconductor layer including the channel formation region, it is preferable to adopt a structure capable of controlling the threshold voltage. In the transistor 28 shown in FIG. 9C, gate electrodes are provided above and below the channel formation area via a gate insulating layer, and by controlling the potential of the upper and/or lower gate electrodes, the threshold voltage can be controlled Is the desired value.

Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 9D.

The pulse output circuit shown in FIG. 9D has a first transistor 31 to a thirteenth transistor 43. In addition, in addition to the first input terminal 21 to the fifth output terminal 25, the first output terminal 26, and the second output terminal 27, it also includes a power supply line 51 supplied with a first high power supply potential VDD, and a second high power supply The power supply line 52 of the potential VCC and the power supply line 53 supplied with the low power supply potential VSS, and supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43 connected to them, respectively.

Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 9D is shown: the first power supply potential VDD is a potential greater than or equal to the second power supply potential VCC, and the second power supply potential VCC is a potential greater than the third power supply potential VSS. In addition, the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H-level and the L-level at a certain interval, for example, when the H-level is punctual, the potential is VDD, and when the L-level is punctual, the potential is VSS.

In addition, by making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be kept low without affecting the operation, and the shift of the threshold value of the transistor can be reduced. , And the deterioration can be suppressed.

In addition, as shown in FIG. 9D, as the first transistor 31 and the sixth transistor 36 to the ninth transistor 39 among the first transistor 31 to the thirteenth transistor 43, it is preferable to use the four transistors shown in FIG. 9C. Terminal transistor 28.

The operation of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 requires the use of a control signal of the gate electrode to switch the potential of the node connected to one of the source and drain electrodes. In addition, the first transistor 31, the sixth transistor 36 to the ninth transistor are preferably the following transistors, that is, the faster the response to the control signal input to the gate electrode (the steep rise of the conduction current), the more it can be reduced Wrong operation of the pulse output circuit. Therefore, by using the four-terminal transistor 28, the threshold voltage can be controlled, so that a pulse output circuit that can further reduce erroneous operation can be obtained. In addition, although the first control signal G1 and the second control signal G2 are the same control signal in FIG. 9D, a structure in which different control signals are input may also be adopted.

In the first transistor 31 of FIG. 9C, the first terminal is electrically connected to the power line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate The pole electrode) is electrically connected to the fourth input terminal 24.

In the second transistor 32, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34.

In the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26.

In the fourth transistor 34, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26.

In the fifth transistor 35, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is electrically connected to The fourth input terminal 24.

In the sixth transistor 36, the first terminal is electrically connected to the power line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode (lower The gate electrode and the upper gate electrode) are electrically connected to the fifth input terminal 25.

In the seventh transistor 37, the first terminal is electrically connected to the power line 52, and the second terminal is electrically connected to the second terminal of the eighth transistor 38, the gate electrode (the lower gate electrode and the upper gate electrode) It is electrically connected to the third input terminal 23.

In the eighth transistor 38, the first terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) It is electrically connected to the second input terminal 22.

In the ninth transistor 39, the first terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and the second terminal is electrically connected to the gate electrode of the third transistor 33 and The gate electrode of the tenth transistor 40 and the gate electrode (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 52.

In the tenth transistor 40, the first terminal is electrically connected to the first input terminal 21, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39.

In the eleventh transistor 41, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor. Gate electrode of crystal 34.

In the twelfth transistor 42, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 (the lower gate And the upper gate electrode).

In the thirteenth transistor 43, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 (the lower gate And the upper gate electrode).

In FIG. 9D, the connection part of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is the node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, and the second terminal of the eighth transistor 38 The connection part between one terminal and the gate electrode of the eleventh transistor 41 is node B (refer to FIG. 10A).

10A shows the following signals, that is, when the pulse output circuit illustrated in FIG. 9D is applied to the first pulse output circuit 10_1, the signal input to the first input terminal 21 to the fifth input terminal 25 or from the first output terminal 26 and The signal output from the second output terminal 27.

Specifically, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, the third clock signal CK3 is input to the third input terminal 23, and the fourth input terminal 24 is input The start pulse, the second output signal OUT(3) is input to the fifth input terminal 25, the first output signal OUT(1) (SR) is output from the first output terminal 26, and the second output signal is output from the second output terminal 27 OUT(1).

In addition, a transistor refers to an element having at least three terminals including a gate, a drain, and a source. There is a channel region between the drain region and the source region. The zone allows current to flow. Here, since the source and drain vary according to the structure or operating conditions of the transistor, it is difficult to define which is the source and which is the drain. Therefore, sometimes the regions used as source and drain are not called source or drain. In this case, as an example, the regions used as the source and drain are sometimes referred to as the first terminal and the second terminal, respectively.

In addition, in FIG. 10A, a capacitor element for boosting operation by making the node A in a floating state may be separately provided. In addition, a capacitor element that electrically connects one of the electrodes to the node B may be separately provided to maintain the potential of the node B.

Here, FIG. 10B shows a timing chart of the shift register including a plurality of pulse output circuits shown in FIG. 10A. In addition, when the shift register is a scan line driver circuit, the period 61 in FIG. 10B corresponds to the vertical retrace period, and the period 62 corresponds to the gate selection period.

In addition, as shown in FIG. 10A, by providing the ninth transistor 39 whose gate is applied with the second power supply potential VCC, there are the following advantages before and after the boosting operation.

Without the ninth transistor 39 whose gate electrode is applied with the second power supply potential VCC, when the potential of the node A rises due to the boosting operation, the source potential of the second terminal of the first transistor 31 rises , And the source potential becomes greater than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power line 51 side. Therefore, in the first transistor 31, because a relatively large bias is applied between the gate and the source and between the gate and the drain, between the gate and the source and between the gate and the drain Under greater pressure, this will lead to the deterioration of the transistor.

Therefore, by pre-installing the ninth transistor 39 whose gate electrode is applied with the second power supply potential VCC, although the potential of the node A rises due to the boosting operation, it is not necessary to make the second terminal of the first transistor 31 The potential rises. In other words, by providing the ninth transistor 39, the value of the negative bias applied between the gate and the source of the first transistor 31 can be set to be small. Therefore, since the negative bias voltage applied between the gate and source of the first transistor 31 can be set small by adopting the circuit structure of this embodiment mode, it is possible to suppress the first bias caused by the pressure. Deterioration of transistor 31.

In addition, it suffices to provide the ninth transistor 39 between the second terminal of the first transistor 31 and the gate of the third transistor 33 in a manner of being connected by the first terminal and the second terminal. In addition, when a shift register having a plurality of pulse output circuits of this embodiment mode is used, the ninth transistor 39 can also be omitted in a signal line driver circuit whose number of stages is greater than that of the scan line driver circuit. , And has the advantage of reducing the number of transistors.

In addition, by using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off current of the transistors can be reduced, the on current and the field effect mobility can be improved, and the degree of deterioration can also be reduced. Therefore, the error operation in the circuit can be reduced. In addition, the degree of deterioration of the transistor caused by applying a high potential to its gate electrode is smaller than that of a transistor using amorphous silicon. Thus, even if the first power supply potential VDD is supplied to the power supply line supplying the second power supply potential VCC, the same operation can be obtained, and the number of power supply lines between the lead circuits can be reduced, so that the circuit can be miniaturized.

In addition, even if the clock signal supplied to the gate electrode of the seventh transistor 37 through the third input terminal 23, and the clock signal supplied to the gate electrode of the eighth transistor 38 through the second input terminal 22 becomes the opposite The gate electrode of the seven transistor 37 uses the clock signal supplied from the second input terminal 22, and the gate electrode of the eighth transistor 38 uses the clock signal supplied from the third input terminal 23 to replace the wiring relationship. The role of.

In addition, in the shift register shown in FIG. 10A, by changing from both the seventh transistor 37 and the eighth transistor 38 in the on state to the state in which the seventh transistor 37 is off and the eighth transistor 38 is on , Then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, and the potential of the node B is reduced by the potential drop of the second input terminal 22 (CK2) and the third input terminal 23 (CK3) This occurs twice, and the drop in the potential of the node B is caused by the drop in the potential of the gate electrode of the seventh transistor 37 and the drop in the potential of the gate electrode of the eighth transistor 38.

On the other hand, in the shift register shown in FIG. 10A, by changing from both the seventh transistor 37 and the eighth transistor 38 in the on state to the seventh transistor 37 being turned on and the eighth transistor 38 being turned off Then becomes the state where the seventh transistor 37 is off and the eighth transistor 38 is off, and the second input terminal 22 (CK2) and the third input terminal 23 (CK3) drop in the potential of the node B generated The drop in the potential occurs only once, and the drop in the potential of the node B is caused by the drop in the potential of the gate electrode of the eighth transistor 38.

Therefore, it is preferable to adopt the following connection relationship: the clock signal CK3 is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and the clock signal CK3 is supplied to the eighth transistor 38 The gate electrode (the lower gate electrode and the upper gate electrode) of the clock signal CK2 is supplied from the second input terminal 22. This is because the number of changes in the potential of the node B can be reduced to reduce noise.

In this way, by adopting a structure in which the H-level signal is periodically supplied to the node B while the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level, the erroneous operation of the pulse output circuit can be suppressed .

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 7]

In this embodiment mode, as an embodiment of the display device, an example of a liquid crystal display device including the transistor shown in Embodiment Mode 1 or 2 and using a liquid crystal element as a display element will be described with reference to FIGS. 11 to 24.

First, a VA (Vertical Alignment) type liquid crystal display device will be described. VA refers to a way to control the arrangement of liquid crystal molecules of a liquid crystal display panel. The VA-type liquid crystal display device has a manner in which liquid crystal molecules are aligned in a direction perpendicular to the surface of the panel when no voltage is applied. In this embodiment mode, in particular, the pixel is divided into a plurality of regions (for example, two to four sub-pixels), and the molecules are pushed in different directions, respectively. This is called multi-domain (multi-domain), or multi-quadrant design. In the following description, a liquid crystal display device considering a multi-quadrant design will be described.

12 and 13 show the pixel electrode and the counter electrode, respectively. FIG. 12 is a plan view of the side of the substrate where the pixel electrode is formed, and the cross-sectional structure along the cutting line EF shown in the figure is shown in FIG. 11. In addition, FIG. 13 is a plan view of the side of the substrate where the counter electrode is formed. Hereinafter, description will be made with reference to these drawings.

FIG. 22 shows a state where the substrate 600 and the counter substrate 601 are overlapped and liquid crystals are implanted. On the substrate 600, a transistor 628, a pixel electrode layer 624 connected to the transistor 628, and a storage capacitor 630 are formed. A counter electrode layer 640 and the like are formed on the counter substrate 601.

A color film 636 and a counter electrode layer 640 are formed on the counter substrate 601, and protrusions 644 are formed on the counter electrode layer 640. An alignment film 648 is formed on the pixel electrode layer 624, and an alignment film 646 is similarly formed on the counter electrode layer 640 and the protrusion 644. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601.

The transistor 628 and the pixel electrode layer 624 and the storage capacitor portion 630 connected thereto are formed on the substrate 600. The pixel electrode layer 624 is connected to the wiring 618 through the contact hole 623 formed in the insulating film 20, the insulating film 621, and the insulating film 622. As the transistor 628, the transistors shown in Embodiment Modes 1 and 2 are appropriately used. In addition, the storage capacitor portion 630 is composed of a first capacitor wiring 604 formed at the same time as the gate wiring 602 of the transistor 628, a gate insulating layer 606, and a second capacitor wiring 617 formed at the same time as the wirings 616 and 618.

The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap to form a liquid crystal element.

FIG. 12 shows the planar structure on the substrate 600. The pixel electrode layer 624 is formed using the material shown in Embodiment Mode 1. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is used to control the alignment of the liquid crystal.

The transistor 629 shown in FIG. 12, the pixel electrode layer 626 connected to the transistor 629, and the storage capacitor portion 631 can be formed in the same manner as the transistor 628, the pixel electrode layer 624, and the storage capacitor portion 630, respectively. Both the transistor 628 and the transistor 629 are connected to the wiring 616. The pixels of the liquid crystal panel are composed of a pixel electrode layer 624 and a pixel electrode layer 626. In other words, the pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels. In this embodiment, the pixel is composed of two sub-pixels, but it can also be composed of more sub-pixels.

Fig. 13 shows a planar structure on the side of the counter substrate. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. A protrusion 644 for controlling the alignment of the liquid crystal is formed on the opposite electrode layer 640. Note that in FIG. 13, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are represented by dotted lines, and the case where the counter electrode layer 640, the pixel electrode layer 624 and the pixel electrode layer 626 are arranged to overlap each other is shown. .

Fig. 14 shows an equivalent circuit of this pixel structure. Both the transistor 628 and the transistor 629 are connected to the gate wiring 602 and the wiring 616. In this case, by making the potential of the capacitor wiring 604 and the potential of the capacitor wiring 605 different, it is possible to make the liquid crystal element 651 and the liquid crystal element 652 perform different operations. That is, by separately controlling the potentials of the capacitor wiring 604 and the capacitor wiring 605, the alignment of the liquid crystal can be precisely controlled and the viewing angle can be enlarged.

When a voltage is applied to the pixel electrode layer 624 provided with the slit 625, a distortion of the electric field (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slits 625 and the protrusions 644 on the side of the opposite substrate 601 to engage with each other, an inclined electric field is effectively generated to control the alignment of the liquid crystals, so that the liquid crystals have different alignment directions according to their positions. In other words, the viewing angle of the liquid crystal display panel is enlarged by multi-quadrant.

Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 15 to 18.

26 and 27 show the pixel structure of the VA type liquid crystal display panel. FIG. 27 is a plan view of the substrate 600, and FIG. 26 shows a cross-sectional structure along the cutting line YZ shown in the figure.

In this pixel structure, one pixel has a plurality of pixel electrodes, and each pixel electrode is connected to a transistor. Each transistor is driven by a different gate signal. That is, in a pixel designed in a multi-quadrant manner, the signal applied to each pixel electrode is independently controlled.

The pixel electrode layer 624 is connected to the transistor 628 using a wiring 618 in the contact hole 623. In addition, the pixel electrode layer 626 is connected to the transistor 629 using a wiring 619 in the contact hole 627.

As the transistor 628 and the transistor 629, the transistors shown in Embodiment Mode 1 or 2 can be suitably used. The gate wiring 602 of the transistor 628 and the gate wiring 603 of the transistor 629 are separated from each other to be able to provide different gate signals. On the other hand, the transistor 628 and the transistor 629 share the wiring 616 used as a data line. In addition, a capacitor wiring 690 is provided under the wirings 618 and 619 with a gate insulating layer 606 interposed therebetween.

The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes, and are separated from each other by the slit 625. The pixel electrode layer 626 is formed to surround the outside of the pixel electrode layer 624 extending in a V shape. By using the transistor 628 and the transistor 629 to make the voltages applied to the pixel electrode layer 624 and the pixel electrode layer 626 different, the alignment of the liquid crystal is controlled. Fig. 18 shows an equivalent circuit of this pixel structure. The transistor 628 is connected to the gate wiring 602, and the transistor 629 is connected to the gate wiring 603. In addition, both the transistor 628 and the transistor 629 are connected to the wiring 616. By providing different gate signals to the gate wiring 602 and the gate wiring 603, the operating timings of the liquid crystal element 651 and the liquid crystal element 652 can be different from each other. In other words, by separately controlling the operations of the transistor 628 and the transistor 629, the liquid crystal alignment of the liquid crystal element 651 and the liquid crystal element 652 can be precisely controlled, and the viewing angle can be enlarged.

A color film 636 and a counter electrode layer 640 are formed on the counter substrate 601. In addition, a planarization film 637 is formed between the color film 636 and the counter electrode layer 640 to prevent misalignment of the liquid crystal. Fig. 17 shows a planar structure on the side of the counter substrate. The counter electrode layer 640 is commonly used between different pixels, and the counter electrode layer 640 is formed with a slit 641. By arranging the slit 641 and the pixel electrode layer 624 and the slit 625 on the side of the pixel electrode layer 626 in a mutually biting manner, an inclined electric field can be effectively generated to control the alignment of the liquid crystal. As a result, the liquid crystals can have different alignment directions according to their positions, thereby expanding the viewing angle. In addition, in FIG. 17, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are shown by dotted lines, and the case where the counter electrode layer 640, the pixel electrode layer 624 and the pixel electrode layer 626 are arranged to overlap each other is shown. .

The alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and the alignment film 646 is also formed on the counter electrode layer 640 in the same manner. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601. In addition, by overlapping the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640, the first liquid crystal element 651 is formed. In addition, by overlapping the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640, the second liquid crystal element 652 is formed. The pixel structure of the display panel illustrated in FIGS. 15 to 18 adopts a multi-quadrant structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel.

Next, a liquid crystal display device of the lateral electric field method will be described. The lateral electric field method refers to a method in which an electric field is applied to the liquid crystal molecules in a cell in a horizontal direction to drive the liquid crystal to display gray scales. With the lateral electric field method, the viewing angle can be increased to approximately 180°. Hereinafter, a liquid crystal display device adopting a lateral electric field method will be described.

FIG. 19 shows a state in which the substrate 600 and the counter substrate 601 are overlapped and liquid crystals are implanted. On the substrate 600, an electrode layer 607, a transistor 628, and a pixel electrode layer 624 are formed. A color film 636, a planarizing film 637, and the like are formed on the counter substrate 601. In addition, since the pixel electrode is present on the side of the substrate 600, the counter electrode is not provided on the side of the counter substrate 601. In addition, a liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601 with the alignment film 646 and the alignment film 648 interposed therebetween.

On the substrate 600, an electrode layer 607, a capacitor wiring 604 and a transistor 628 connected to the electrode layer 607 are formed. The capacitor wiring 604 may be formed at the same time as the gate wiring 602 of the transistor 628. The transistor 628 can use the transistors shown in Embodiment Modes 1 to 5. The electrode layer 607 can use the same material as the pixel electrode layer shown in Embodiment Mode 1 or 2. In addition, the electrode layer 607 is formed into a shape roughly divided into pixel shapes. In addition, a gate insulating layer 606 is formed on the electrode layer 607 and the capacitor wiring 604.

Wirings 616 and 618 of the transistor 628 are formed on the gate insulating layer 606. The wiring 616 is a data line that transmits video signals in the liquid crystal display panel, and is a wiring extending in one direction, and the wiring 616 is connected to the source region or the drain region of the transistor 628 to become one of the source and drain Of electrodes. The wiring 618 is a wiring that becomes the other electrode of the source region and the drain region and is connected to the pixel electrode layer 624.

An insulating film 620 and an insulating film 621 are formed on the wiring 616 and the wiring 618. In addition, the pixel electrode layer 624 connected to the wiring 618 through the contact holes 623 formed in the insulating films 620 and 621 is formed on the insulating film 621. The pixel electrode layer 624 is formed using the same material as the pixel electrode layer 457 shown in Embodiment Mode 3.

As described above, the transistor 628 and the pixel electrode layer 624 connected to the transistor 628 are formed on the substrate 600. Furthermore, a storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

Fig. 20 is a plan view illustrating the structure of a pixel electrode. FIG. 19 shows a cross-sectional structure corresponding to the cut line OP shown in FIG. 20. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is used to control the alignment of the liquid crystal.

In this case, an electric field occurs between the electrode layer 607 and the pixel electrode layer 624. A gate insulating layer 606 is provided between the electrode layer 607 and the pixel electrode layer 624, but the thickness of the gate insulating layer 606 is 50 nm to 200 nm, which is sufficiently thinner than the thickness of the liquid crystal layer of 2 μm to 10 μm. An electric field actually occurs in a direction parallel to the substrate 600 (horizontal direction). The electric field controls the alignment of the liquid crystal, and the liquid crystal molecules are rotated horizontally by using the electric field substantially parallel to the direction of the substrate. In this case, since the liquid crystal molecules are horizontal in any state, there is no change in contrast or the like due to the viewing angle, thereby expanding the viewing angle. Moreover, the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes, so the aperture ratio can be improved.

Next, another example of a liquid crystal display device of the lateral electric field method will be described.

21 and 22 show the pixel structure of an IPS type liquid crystal display device. FIG. 22 is a plan view, and FIG. 21 shows a cross-sectional structure along the cutting line VW shown in FIG. 22.

FIG. 21 shows a state where the substrate 600 overlaps the counter substrate 601 and liquid crystals are implanted, and a transistor 628 and a pixel electrode layer 624 connected to the transistor 628 are formed on the substrate 600. A color film 636, a planarizing film 637, and the like are formed on the counter substrate 601. In addition, no counter electrode layer is provided on the counter substrate 601 side. In addition, a liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601 with the alignment film 646 and the alignment film 648 interposed therebetween.

A common potential line 609 and a transistor 628 are formed on the substrate 600. The common potential line 609 may be formed simultaneously with the gate wiring 602 of the transistor 628. The transistor 628 uses the transistors shown in Embodiment Modes 1 to 5.

The wiring 616 and the wiring 618 of the transistor 628 are formed on the gate insulating layer 606. The wiring 616 is a data line used to supply video signals in the liquid crystal panel, and is connected to the source region or the drain region of the transistor 628 and also serves as one of the source and drain electrodes. The wiring 618 is a wiring connected to the pixel electrode layer 624, and also serves as the other electrode of the source and drain of the transistor 628.

An insulating film 620 and an insulating film 621 are formed on the wiring 616 and the wiring 618. In addition, the pixel electrode layer 624 connected to the wiring 618 through the contact hole 623 is formed on the insulating films 620 and 621. The pixel electrode layer 624 can be formed using the same material as the pixel electrode layer 457 shown in Embodiment Mode 3. As shown in FIG. 22, the pixel electrode layer 624 is formed in such a way that a lateral electric field is formed between comb-shaped electrodes formed at the same time as the common potential line 609. In addition, the comb-tooth portion of the pixel electrode layer 624 and the comb-shaped electrode formed at the same time as the common potential line 609 is formed to mesh with each other.

When an electric field is generated between the pixel electrode layer 624 and the common potential line 609, the electric field controls the alignment of the liquid crystal. Therefore, the liquid crystal molecules can be rotated horizontally by using an electric field substantially parallel to the direction of the substrate. In this case, since the liquid crystal molecules are also horizontal in any state, there is no change in contrast or the like due to the viewing angle, and the viewing angle is expanded.

As described above, the transistor 628 and the pixel electrode layer 624 connected to the transistor 628 are formed on the substrate 600. In addition, the storage capacitor is formed by a common potential line 609, a gate insulating layer 606, and a capacitor electrode 615. In addition, the capacitor electrode 615 and the pixel electrode layer 624 are connected through a contact hole 633.

Next, the mode of the TN type liquid crystal display device is shown.

23 and 24 show the pixel structure of a TN type liquid crystal display device. FIG. 24 is a plan view, and FIG. 23 shows a cross-sectional structure along the KL line shown in FIG. 24.

The pixel electrode layer 624 is connected to the transistor 628 through the wiring 618 in the contact hole 623. The wiring 616 used as a data line is connected to the transistor 628. The transistor 628 can use any of the transistors shown in Embodiment Mode 1 or 2.

The pixel electrode layer 624 can be formed using the same material as the pixel electrode layer shown in Embodiment Mode 3.

A colored layer 636 and a counter electrode layer 640 are formed on the counter substrate 601. Furthermore, between the color film 636 and the counter electrode layer 640, a planarization film 637 is formed to prevent misalignment of the liquid crystal. The liquid crystal layer 650 is formed by sandwiching the alignment film 648 and the alignment film 646 between the pixel electrode layer 624 and the counter electrode layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap to form a liquid crystal element.

In addition, the color film 636 may be formed on the side of the substrate 600. In addition, a polarizing plate was attached to the surface of the substrate 600 on the opposite side to the surface on which the transistor was formed and on the surface of the counter substrate 601 on the opposite side to the surface on which the counter electrode layer 640 was formed.

Through the above process, a liquid crystal display device with a high aperture ratio can be manufactured.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 8]

The display device disclosed in the description of the present invention can be applied to various electronic devices (including game consoles). Examples of electronic equipment include: television devices (also called televisions or television receivers); monitors used in computers, etc.; image capturing devices such as digital cameras and digital cameras; digital photo frames, mobile phones (also called Mobile phones, mobile phone devices); portable game machines; portable information terminals; sound reproduction devices; large game machines such as pachinko machines, etc.

Fig. 25A shows an example of a mobile phone. In addition to the display unit 1102 assembled in the housing 1101, the mobile phone 1100 also includes operation buttons 1103, an external port 1104, a speaker 1105, a microphone 1106, and the like.

The mobile phone 1100 shown in FIG. 25A can input information by touching the display portion 1102 with a finger or the like. In addition, the display unit 1102 can be touched with a finger or the like to perform operations such as calling or sending and receiving emails.

The screen of the display unit 1102 mainly has the following three modes: the first is a display mode based on the display of images; the second is an input mode based on the input of information such as text; the third is a display mode and an input mode. The display + input mode is a mixture of modes.

For example, in the case of making a call or creating an e-mail, the display unit 1102 may be set to a character input mode mainly for character input, and the character input operation displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons in the middle of the display portion 1102 with high recognizability.

In addition, by installing a detection device with a sensor that detects the inclination of the mobile phone 1100, such as a gyroscope, an acceleration sensor, etc., it is possible to determine the direction of the mobile phone 1100 (vertical or horizontal), and thus the screen of the display unit 1102 The display switches automatically.

The screen mode is switched by touching the display portion 1102 or operating the operation buttons 1103 of the housing 1101. It is also possible to switch the screen mode according to the type of image displayed on the display unit 1102. For example, when the video signal displayed on the display unit is data of a moving image, the screen mode is switched to the display mode, and when the video signal displayed on the display unit is text data, the screen mode is switched to the input mode.

In addition, when the signal detected by the light sensor of the display unit 1102 is detected in the input mode and it is known that there is no touch operation input on the display unit 842 within a certain period of time, it can also be controlled to change the screen mode from the input mode. Switch to display mode.

The display part 1102 can also be used as an image sensor. For example, by photographing palm prints, fingerprints, etc. on the display unit 1102, identity recognition can be performed. In addition, by using a light source that emits near-infrared light, it is also possible to photograph finger veins, palm veins, etc. Here, a plurality of transistors 460 shown in Embodiment Mode 1 or 2 are arranged on the display portion 1102. Since the transistor 460 is light-transmissive, a light sensor can be disposed under the transistor 460. In addition, since a light source emitting near-infrared light is not blocked by the transistor 460, it is possible to irradiate an object with near-infrared light with a sufficient amount of light.

Fig. 25B is also an example of a mobile phone. The portable information terminal shown in FIG. 25B as an example may have multiple functions. For example, in addition to the telephone function, a computer can also be incorporated to have various data processing functions.

The portable information terminal shown in FIG. 25B is composed of two frames of a frame 1800 and a frame 1801. The housing 1800 includes a display panel 1802, a speaker 1803, a microphone 1804, a pointing device 1806, an image capturing device 1807, an external connection terminal 1808, etc., and the housing 1801 includes a keyboard 1810, an external memory slot 1811, and the like. In addition, an antenna is incorporated in the housing 1801.

In addition, the display panel 1802 includes a touch screen, and FIG. 25B shows a plurality of displayed operation keys 1805 with broken lines.

In addition, in addition to the above-mentioned structure, a non-contact IC chip, a small recording device, etc. may be mounted.

The display device can be used for the display panel 1802, and the display direction thereof is appropriately changed according to the manner of use. In addition, since the image capturing device 1807 is provided on the same surface as the display panel 1802, a video phone can be performed. The speaker 1803 and the microphone 1804 are not limited to audio calls, and can also be used for recording, reproduction, and the like. Furthermore, the frame body 1800 and the frame body 1801 can be placed in the expanded state and overlapped state as shown in FIG. 25B by sliding, and the miniaturization suitable for carrying can be achieved.

The external connection terminal 1808 is an input and output terminal for power input and information communication, and can be used for charging and data communication with a personal computer. In addition, by inserting the recording medium into the external memory slot 1811, it can correspond to the storage and movement of a larger amount of data.

In addition, in addition to the above-mentioned functions, an infrared communication function, a TV receiving function, etc. may also be provided.

Fig. 26A shows an example of a television device. In the television device 9600, a display portion 9603 is incorporated in a housing 9601. The display unit 9603 can display images. In addition, the structure in which the frame 9601 is supported by the bracket 9605 is shown here.

The television device 9600 can be operated by using the operation switches provided in the housing 9601 and the remote operation machine 9610. By using the operation keys 9609 provided in the remote operating machine 9610, it is possible to perform channel switching and volume operations, and to operate the image displayed on the display portion 9603. In addition, it is also possible to adopt a configuration in which the remote operating machine 9610 is provided with a display portion 9607 that displays the information output from the remote operating machine 9610.

In addition, the television device 9600 adopts a structure including a receiver, a modem, and the like. By using the receiver, general TV broadcasts can be received. Furthermore, by connecting a modem to a wired or wireless communication network, it can also be one-way (from sender to receiver) or two-way (between sender and receiver or between receivers, etc.) Information communication.

Fig. 26B shows an example of a digital photo frame. In the digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display various images. For example, by displaying image data taken with a digital camera or the like, it can perform the same functions as a general photo frame.

In addition, the digital photo frame 9700 adopts a structure including an operating unit, external connection terminals (USB terminals, etc.), an external memory slot, and the like. This structure can also be assembled on the same surface as the display part, but it is best to improve the design by installing it on the side or back. For example, a memory storing image data taken by a digital camera can be inserted into the external memory slot of the digital photo frame 9700 and the image data can be extracted, and then the extracted image data can be displayed on the display portion 9703.

In addition, the digital photo frame 9700 can also adopt a structure for sending and receiving information wirelessly. It is also possible to adopt a structure in which the desired image data is extracted and displayed wirelessly.

FIG. 27 shows a portable game machine, which is composed of two frames of a frame 9881 and a frame 9891, and can be connected in an open and closed manner by a connecting portion 9893. The housing 9881 is equipped with a display portion 9882, and the housing 9891 is equipped with a display portion 9883.

In addition, the portable game machine shown in FIG. 27 has a speaker unit 9884, an external memory slot 9886, an LED light 9890, an input unit (operation keys 9885, connection terminals 9887, and a sensor 9888 (including functions for measuring the following factors) : Force, displacement, position, speed, acceleration, angular velocity, speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, tilt Temperature, vibration, smell or infrared) and microphone 9889) and so on. Of course, the structure of the portable game machine is not limited to the above-mentioned structure, as long as the structure is equipped with at least the display device disclosed in the description of the present invention, and a structure in which other accessory equipment is appropriately provided may be adopted. The portable game machine shown in FIG. 27 has the following functions: read out the program or data stored in the recording medium and display it on the display unit; and realize information by wireless communication with other portable game machines Shared. In addition, the functions of the portable game machine shown in FIG. 27 are not limited to these, and may have various functions.

As described above, the display devices shown in other embodiment modes can be arranged in the display sections of various electronic devices as described above.

In addition, this embodiment mode can be freely combined with other embodiment modes.

[Embodiment Mode 9]

In this embodiment mode, a structure example of a storage capacitor different from that in Embodiment Mode 3 will be described with reference to FIGS. 28A and 28B. 28A and 28B are cross-sectional views of the pixel transistor 460 and the storage capacitor. Note that since the structures of FIGS. 28A, 28B and FIG. 3 are the same except for the structure of the storage capacitor, the same reference numerals are used to denote the same parts, and detailed descriptions of the same parts are omitted.

28A is an example in which the oxide insulating layers 426 and 427, the protective insulating layer 428, and the planarizing insulating layer 456 are used as a dielectric, and the pixel electrode layer 457 and the capacitor wiring layer 432 are used to form a storage capacitor. Since the capacitor wiring layer 432 is formed of the same transparent material and process as the source electrode layer of the transistor 460 of the pixel portion, it is laid out without overlapping the source wiring layer of the transistor 460.

In the storage capacitor shown in FIG. 28A, the pair of electrodes and the dielectric have light-transmitting properties, so that the entire storage capacitor has light-transmitting properties.

In addition, FIG. 28B is a structural example of a storage capacitor different from that of FIG. 28A.

28B is an example in which the gate insulating layer 402 is used as a dielectric, and the capacitor wiring layer 430, the capacitor electrode 431, and the oxide semiconductor layer 405 are used to form a storage capacitor. Here, the oxide semiconductor layer 405 formed in contact with the capacitor electrode 431 is used as one electrode of the storage capacitor. In addition, the oxide semiconductor layer 405 is formed using the same transparent material and the same manufacturing process as the source electrode layer or the drain electrode layer of the transistor 460. In addition, since the capacitor wiring layer 430 is formed of the same light-transmitting material and the same manufacturing process as the gate electrode layer of the transistor 460, it is laid out without overlapping the gate wiring layer of the transistor 460.

In addition, although not shown, the capacitor electrode 431 is electrically connected to the pixel electrode layer 457.

In the storage capacitor shown in FIG. 28B, the pair of electrodes and the dielectric have light-transmitting properties, so that the entire storage capacitor has light-transmitting properties.

The storage capacitor shown in FIGS. 28A and 28B has light transmittance. Even if the pixel size is miniaturized in order to achieve high-definition display images, sufficient capacitance can be obtained and a high aperture ratio can be achieved.

In addition, this embodiment mode can be freely combined with other embodiment modes.