Selective deposition utilizing masks and directional plasma treatment

Selective deposition using mask and directional plasma treatment

SELECTIVE DEPOSITION UTILIZING MASKS AND DIRECTIONAL PLASMA TREATMENT

The embodiments described herein generally relate to methods of depositing materials on semiconductor substrates. More specifically, the embodiments described herein are about selective deposition methods using masks and precision material engineering techniques.

Reliable production of sub-half micron and smaller features is one of the key technical challenges for the next generation of very large integrated circuits (VLSI) and ultra-large integrated circuits (ULSI) of semiconductor components. However, as the limits of circuit technology have been pushed forward, the shrinking size of VLSI and ULSI technologies has placed additional demands on processing capabilities. Reliable formation of the gate structure on the substrate is very important to the success of VLSI and ULSI and to continuous efforts to improve circuit density.

As the circuit density of next-generation devices increases, the width of interconnects such as vias, trenches, contacts, gate structures, and other features, and the dielectric material between these interconnects, is reduced to 45nm And 32nm and smaller sizes. In order to be able to manufacture next-generation components and structures, the features of three-dimensional (3D) stacking in semiconductor wafers are often utilized. In particular, FinFETs are often used to form three-dimensional (3D) structures of semiconductor wafers. By arranging the transistors in three In the two-dimensional space, instead of the traditional two-dimensional space, multiple transistors can be placed very close to each other in integrated circuits (ICs).

FIG. 1 (Prior Art) shows a FinFET 150 located on the substrate 100. As shown in FIG. The substrate 100 includes a plurality of semiconductor fins 102 formed thereon and separated by a shallow trench isolation (STI) structure 104. The shallow trench isolation (STI) structure 104 may be formed of an insulating material.

The substrate 100 may be included in the part of the NMOS element region 101 and the part of the PMOS element region 103 as necessary, and each semiconductor fin 102 may be alternately formed in the NMOS element region 101 and the PMOS element region 103 of the substrate 100 in sequence. The semiconductor fin 102 is formed to protrude above the top surface of the shallow trench isolation (STI) structure 104. Subsequently, the gate structure 106 (usually including a gate electrode layer located on the gate dielectric layer) is deposited on the NMOS device region 101 and the PMOS device region 103 and is higher than the semiconductor fin 102.

The gate structure 106 may be patterned to expose the portions 148 and 168 of the semiconductor fin 102 that are not covered by the gate structure 106. Then, the exposed portions 148, 168 of the semiconductor fin 102 can be doped with dopants using a planting process to form lightly doped source and drain (LDD) regions. The patterning process usually uses lithography technology to form a two-dimensional pattern and form a 3D structure from the two-dimensional pattern. Different surface characteristics in the two-dimensional pattern tend to increase the complexity of the subsequent deposition process.

Selective deposition processes have been developed to selectively deposit materials on substrates. Can perform traditional selective deposition methods to only A material layer is partially formed on a plane surface made of a material different from the substrate material on the substrate. Figures 2A-2C (prior art) show an exemplary process for performing the deposition process. The process uses self-assembled monolayers (SAMs) as the surface modification layer to selectively modify the surface properties of different surface materials exposed on the substrate. For example, the substrate 202 may include a feature 204 formed of a first material (such as a silicon oxide layer) on a substrate 202 formed of a second material (such as silicon), as shown in FIG. 2A. An opening 208 is defined in the feature 204, and the opening 208 exposes the surface 206 of the substrate 202. The SAMs 210 can then be formed on the substrate 202 by the solution-based precursor, as shown in FIG. 2B. Generally speaking, a self-assembled monolayer (SAM) 210 is formed on a surface that has the ability to chemically react with molecules from the SAM 210. In the embodiment depicted in FIG. 2B, the precursor used to form the SAM 210 is selected to be chemically related to the surface 212 (such as silicon oxide material) of the feature 204, rather than to the surface 206 (such as silicon material) of the substrate 202. react. By doing so, the SAM 210 can be mainly formed on the features 204 of the substrate 202, and the surface 206 of the substrate 202 is free of SAM. 210. Subsequently, an atomic layer deposition (ALD) process (a process that is highly sensitive to surface conditions) is performed to selectively form a structure 214 on the designated surface 206 of the substrate 202, as shown in FIG. 2C.

With the SAM 210 configured on the feature 204, the structure 214 can be selectively formed only on the designated surface 206 of the substrate 202. However, in the case where the substrate contains only one type of material, the SAM 210 may be fully formed on the entire surface of the substrate Therefore, selective material deposition is difficult to achieve. In other words, in the case where the structure on the substrate is formed of a single type of material, selective deposition via the use of SAM may not be successfully enabled because the self-assembled monolayer SAM is applied non-selectively across the board. For example, the fin structure 102 depicted in Figure 1 may be formed of one type of material. However, when only one type of material needs to be selectively formed or a specific amount of material is required, the use of SAM may not be successful because SAM may not be selectively formed on the entire outer surface 120 of the fin structure 102.

Therefore, there is a need for improved methods of selective deposition processes.

In one embodiment, a selective deposition method is provided. The method includes the following steps: depositing a mask material on a substrate and patterning the mask material to form a patterned mask. After the patterning, multiple regions of the substrate can be exposed, and ions can be implanted into the patterned mask and the exposed regions of the substrate. The exposed areas are planted areas, and materials can be deposited on the substrate. The material can be selectively deposited on the desired area of the substrate in response to the surface modification of the exposed areas.

In another embodiment, a selective deposition method is provided. The method includes the steps of depositing a mask material on a substrate, and patterning the mask material to form a patterned mask. After the patterning of the mask, multiple regions of the substrate may be exposed through the patterned mask. Ions can be implanted into the patterned mask and the exposed area of the substrate. The patterned mask can be removed from the substrate to expose the unplanted area of the substrate, and the material may be selectively deposited on the planted area or any area of the unplanted area of the substrate.

In yet another embodiment, a selective deposition method is provided. The method includes the following steps: implanting fluorine ions into a patterned mask and a first region where the substrate is exposed through the patterned mask. The fluoride ions can be reduced to less than about 5×10¹⁶(Ion/cm²) Ion dose implantation. The patterned mask can be removed from the substrate to expose the second region of the substrate. During the process of planting the fluoride ions in the first zone, the second zone can avoid the planting of fluoride ions. An ALD process can be used to deposit materials while maintaining the substrate at a temperature below about 500°C. The ALD process can selectively deposit the material on one of the first or second regions.

<p>100Substrate</p><p>101NMOS device area</p><p>102Semiconductor Fin</p><p>103PMOS component area</p><p>104Shallow trench isolation (STI) structure</p><p>106Gate structure</p><p>Part 148</p><p>150FinFET</p><p>Part 168</p><p>202Substrate</p><p>204Features</p><p>206surface</p><p>208Open</p><p>210Self-assembled single layer (SAM)</p><p>212surface</p><p>214Structure</p><p>300Processing room</p><p>301 Chamber body</p><p>302ion</p><p>306RF Plasma Source</p><p>308Plasma sheath regulator</p><p>309Internal processing area</p><p>312Regulator</p><p>314Regulator</p><p>316Gap</p><p>334Substrate support</p><p>338Substrate</p><p>340Plasma</p><p>341Border</p><p>342Plasma sheath</p><p>344Features</p><p>347Sidewall</p><p>349Top surface</p><p>351Plane</p><p>369Trajectory path</p><p>370Trajectory path</p><p>371Trajectory path</p><p>388Air source</p><p>390bias voltage source</p><p>400Ion treatment room</p><p>402Ion source</p><p>403 side wall</p><p>406ion</p><p>410Extraction hole</p><p>414Suppression electrode</p><p>416Ground electrode</p><p>418Ion beam</p><p>420Plasma sheath regulator</p><p>423Plane</p><p>430Regulator</p><p>432Regulator</p><p>440Plasma</p><p>441Border</p><p>442Plasma sheath</p><p>450Gap</p><p>500Ion implantation treatment room</p><p>502Ion source</p><p>504Extraction electrode</p><p>506Magnet analyzer</p><p>508First deceleration (D1) station</p><p>510Magnet analyzer</p><p>512Second deceleration (D2) station</p><p>614Lift</p><p>616Lift board</p><p>618Lift plate actuator</p><p>620pin</p><p>622Cleaning Ring</p><p>624Clean the passage</p><p>629 Chamber body</p><p>630Gas delivery equipment</p><p>631 side wall</p><p>632Bottom/chamber cover</p><p>633Flow valve channel</p><p>634Atomic layer deposition (ALD) processing chamber</p><p>636AAir Inlet</p><p>636BAir Inlet</p><p>637Expansion pipeline</p><p>637AAir Inlet</p><p>637BAir Inlet</p><p>638Reactant gas source</p><p>639Reactant gas source</p><p>640Purifying air source</p><p>642AValve</p><p>642BValve</p><p>643ATransmission pipeline</p><p>643BTransportation pipeline</p><p>644AValve seat assembly</p><p>644BValve seat assembly</p><p>645APurification pipeline</p><p>645BPurification pipeline</p><p>646AValve seat assembly</p><p>646BValve seat assembly</p><p>648AProgrammable logic controller</p><p>648BProgrammable logic controller</p><p>660Bottom surface</p><p>662Choke</p><p>666Pumping area</p><p>672Hat</p><p>678Pumping System</p><p>679Pumping channel</p><p>680Control Unit</p><p>682CPU</p><p>683Related control software</p><p>684Support circuit</p><p>686Memory</p><p>688Signal Bus</p><p>690Expansion pipeline</p><p>692Substrate support</p><p>700Method</p><p>710Operation</p><p>720Operation</p><p>730Operation</p><p>740Operation</p><p>750Operation</p><p>Line 802</p><p>Line 804</p><p>Line 806</p><p>1400Regulator</p><p>1402Regulator</p><p>1404Regulator</p><p>G1Horizontal spacing</p><p>G2Horizontal spacing</p><p>ZaDistance</p>

In order to understand the features of the present disclosure in detail, reference may be made to the embodiments (some of which are illustrated in the accompanying drawings) to make a more specific description of the above briefly summarized disclosure. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure, and therefore should not be regarded as limiting the scope of the present disclosure, because the present disclosure may recognize other equally effective embodiments.

Figure 1 (Prior Art) shows an exemplary schematic three-dimensional view of a substrate on which a FinFET structure is formed.

Figures 2A-2C (prior art) show an exemplary flow chart of a selective deposition process using self-assembled monolayers (SAMs).

Figure 3A schematically illustrates an apparatus that can be used to implant dopants into a substrate.

Figure 3B schematically illustrates another embodiment of an apparatus that can be used to implant dopants into a substrate.

Figure 4 schematically illustrates another embodiment of an apparatus that can be used to implant dopants into a substrate.

Figure 5 illustrates a schematic plan view of another embodiment of an apparatus that can be used to implant dopants into a substrate.

Figure 6 schematically illustrates a cross-sectional view of an equipment that can be used for an atomic layer deposition (ALD) process.

Figure 7 schematically shows a method for performing a selective deposition process.

Figure 8 is a graph schematically illustrating the nucleation delay of the ALD process versus the ion dose implanted in the substrate.

For ease of understanding, the same element symbols have been used where possible to refer to elements with the same drawings. It is conceived that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further elaboration. However, it should be noted that the drawings only illustrate exemplary embodiments of the present disclosure, and therefore should not be construed as limiting the scope of the present disclosure, because the present disclosure may recognize other equally effective embodiments.

Provides a method for selectively depositing different materials at different locations on the substrate. The substrate may include any suitable structure of a fin structure, a gate structure, a contact structure, or a semiconductor element. In one embodiment, The selective deposition process can form different materials on different surfaces (for example, different parts of the substrate), depending on the material properties of the lower layer deposited on it. For example, the described method may use an ion-assisted oriented plasma processing process or other appropriate ion implantation process to modify the material disposed on the substrate. Ions modify the surface properties of the substrate to enable subsequent selective deposition processes. That is, a selective deposition process in which materials are deposited preferentially on one of the modified surface or the unmodified surface relative to the other surface. In one embodiment, the substrate on which the mask is disposed may undergo an ion implantation process to modify the mask and the surface of the substrate exposed by the mask. The mask can be removed, which causes the substrate to have areas of planted and unplanted material. A subsequent deposition process can be performed to selectively deposit on the implanted or unplanted area of the substrate.

Figure 3A schematically illustrates an embodiment of a processing chamber 300 suitable for implanting dopants into a substrate. In addition to the processing chamber 300 described below, an ion implantation device such as a plasma immersion ion implantation device may be used to perform the method described herein. The processing chamber 300 described herein can be used as a plasma doping device. However, the processing chamber 300 may also include, but is not limited to, an etching and deposition system. In addition, the plasma doping equipment can perform many different material modification processes on the substrate. One such process involves doping a substrate, such as a semiconductor substrate, with the desired dopant material.

The processing chamber 300 may include a chamber body 301 that defines an internal processing area 309. The substrate holder 334 is arranged in the processing chamber 300. During the directional plasma process, the substrate 338 with the features 344 formed thereon may be disposed on the substrate support 334. Substrate 338 can be packaged Including, but not limited to, semiconductor wafers, flat panels, solar panels, and polymer substrates. The substrate may include or be made of various materials, and the materials include silicon materials, silicon nitride materials, silicon oxide materials, metal materials, metal oxide materials, and the like. The semiconductor substrate may have the shape of a disc as needed, and have a diameter of 200 millimeters (mm), 300 millimeters (mm), or 450 millimeters (mm) or other sizes.

The RF plasma source 306 is coupled to the chamber body 301 and provided to generate plasma 340 in the processing chamber 300. In the embodiment of FIG. 3A, the plasma sheath regulator 308 is disposed in the internal processing area 309. The plasma sheath regulator 308 includes a pair of regulators 312 and 314 defining a gap 316 in the middle. The gap 316 defines the horizontal spacing (G). In some embodiments, the plasma sheath regulator 308 may include an insulator, a conductor, or a semiconductor. The pair of adjusters 312, 314 may be a pair of sheets having a thin, flat shape. In other embodiments, the pair of adjusters 312 and 314 may have other shapes, such as a tube shape, a wedge shape, and/or a beveled edge near the gap 316. In one embodiment, the regulators 312, 314 may be made of quartz, alumina, boron nitride, glass, polysilicon, silicon nitride, silicon carbide, graphite, and the like.

The horizontal spacing of the gap 316 defined by the pair of adjusters 312 and 314 may be about 6.0 millimeters (mm). The pair of adjusters 312, 314 can also be positioned to define a vertical distance (Z) above the plane 351. The plane 351 is defined by the front surface of the substrate 338 or the surface of the substrate support 334. In one embodiment, the vertical spacing (Z) may be about 3.0 mm.

The gas source 388 is coupled to the processing chamber 300 to supply ionizable process gas to the internal processing area 309. Examples of ionizable process gases include, but are not limited to BF₃, BI₃N₂, Ar, PH₃, AsH₃, B₂H₆, H₂, Xe, Kr, Ne, He, SiH₄, SiF₄, SF₆, C₂F₆, CHF₃, GeH₄, GeF₄, CH₄, CF₄, AsF₅, PF₃And PF₅. The plasma source 306 can generate the plasma 340 by exciting and ionizing the process gas provided to the processing chamber 300. The ions in the plasma 340 can be attracted through the plasma sheath 342 by different mechanisms. In the embodiment of FIG. 3A, the bias voltage source 390 is coupled to the substrate support 334, and the substrate support 334 is configured to bias the substrate 338 to attract ions 302 from the plasma 340 through the plasma sheath 342. The bias source 390 may be a DC power source that provides a DC voltage bias signal or an RF power source that provides an RF bias signal. In one embodiment, the bias signal may be between about 1 MHz and about 5 MHz, such as about 2 MHz.

It is believed that the plasma sheath regulator 308 can modify the electric field in the plasma sheath 342 to control the shape of the boundary 341 between the plasma 340 and the plasma sheath 342. The boundary 341 between the plasma 340 and the plasma sheath 342 may have a convex shape with respect to the plane 351. When the bias source 390 biases the substrate 338, the ions 302 are attracted through the plasma sheath 342 and pass through the gap 316 defined between the regulators 312 and 314 at a wide range of incident angles. For example, the ions 302 following the trajectory path 371 may strike the substrate 338 at an angle of positive θ (+θ) relative to the plane 351. The ions following the trajectory path 370 can impinge perpendicularly on the substrate 338 at an angle of about 90 degrees with respect to the same plane 351. Follow trajectory path The ions of 369 can strike the substrate 338 at a negative θ (-θ) angle with respect to the plane 351. Therefore, the range of the incident angle may be between about positive θ (+θ) and about negative θ (-θ), centered at about 90 degrees. In addition, some ion trajectory paths, such as paths 369 and 371, may cross each other. Therefore, in addition to the more traditional ion implantation process, the processing chamber 300 can also be configured to perform a directional implantation process.

Depends on many factors, including, but not limited to, the horizontal spacing (G) between the regulators 312 and 314, the vertical spacing (Z) of the plasma sheath regulator 308 above the plane 351, and the dielectric of the regulators 312 and 314 For constants, and other plasma process parameters, the angle of incidence (θ) can range between +60 degrees and -60 degrees, centered at about 0 degrees. Therefore, the surface of the substrate 338, such as the three-dimensional structure on the substrate 338, can be uniformly processed by the ions 302. In addition, if a mask is formed on the substrate 338, the ion 302 can also process the mask. It is conceived that the mask can be a two-dimensional mask or a three-dimensional mask, depending on the required patterning technique. In one example, the sidewalls 347 of the features 344 (with exaggerated dimensions for clarity) that can be used to form the fin structure of the FINFET device can be treated more uniformly by the ions 302 instead of only the top surface 349. Likewise, the three-dimensional mask can also be processed more uniformly.

Referring to FIG. 3B, instead of the pair of regulators 312 and 314 shown in FIG. 3A, at least three regulators 1400, 1402, 1404 are used to control the ions to reach the substrate 338 at a desired angular distribution. By arranging the two outer regulators 1400 and 1404 on a common plane (the same vertical plane (Za)) at equal intervals from Za above the substrate 338 And keep the same horizontal spacing G1 and G2 between the regulators 1400, 1402, and 1404 to obtain ions dispersed at a symmetrical bimodal angle centered at +/-θ (+θ and -θ) degrees.

As described above, the incident angle of the ions implanted into the substrate 338 can be modified by changing the vertical spacing between the outer adjusters 1400, 1404 and the middle adjuster 1402, so as to change the gap angle. The angular ion dispersion can be modified by changing the horizontal spacing (G1, G2) between the regulators 1400, 1402, 1404, so as to change the gap width defined by the horizontal spacing (G1, G2). An asymmetric distribution can be formed by making Za and Zb different, by selecting G1 that is different from G2, or a combination of the above two actions. In one embodiment, the angled ion dispersion can be modified to have an angle between about 0 degrees and about 30 degrees from the center to process or implant ions to only one side of the structure. Similarly, an asymmetrical distribution can be used to dope the mask so that a part smaller than the entire mask is implanted. In another embodiment, one or more of the regulators 1400, 1402, 1404 (for example, the intermediate regulator 1402) may have holes formed therein through which ions can pass. The idea is to allow a variety of regulator configurations to provide the required angular ion distribution.

Figure 4 shows another embodiment of an ion processing chamber 400 that can be used to implant ions into a substrate at a desired and variable angle of incidence. The processing chamber 400 includes an ion source 402 having a side wall 403 with an extraction hole 410. The processing chamber 400 further includes a plasma sheath regulator 420 to control the shape of the boundary 441 between the plasma 440 and the plasma sheath 442 near the extraction hole 410. Extraction electrode assembly is extracted from Plasma 440 The ions 406 are accelerated through the plasma sheath 442 to form a well-defined ion beam 418. The extraction electrode assembly may include sidewalls 403 serving as arc-shaped slit electrodes, suppression electrodes 414, and ground electrodes 416. The suppression electrode 414 and the ground electrode 416 each have a hole aligned with the extraction hole 410 for extracting a well-defined ion beam 418. To help illustrate, a Cartesian coordinate system is defined in which ion beam 418 travels in the Z direction. The XY plane is perpendicular to the Z direction, and the Z direction can be changed depending on the direction of the ion beam 418.

In the embodiment of FIG. 4, the plasma sheath regulator 420 includes a pair of regulators 430, 432 positioned in the ion source 402. In other embodiments, the regulator 420 may include a regulator. The regulators 430, 432 can be made of quartz, alumina, boron nitride, silicon, silicon carbide, graphite, glass, porcelain, silicon nitride, and the like. The pair of adjusters 430, 432 may be a pair of thin, flat sheets. In other embodiments, the pair of adjusters 430 and 432 may have other shapes, such as a tube shape, a wedge shape, and/or a beveled edge. A gap 450 with a gap (G) is defined between the pair of adjusters 430 and 432. The pair of adjusters 430 and 432 can also be positioned at a vertical distance (S) above the plane 423, which is defined by the inner surface of the side wall 403 with the extraction hole 410.

In operation, process gas (not shown) is supplied to the ion source 402. Examples of process gases include, but are not limited to BF₃, BI₃N₂, Ar, PH₃, AsH₃, B₂H₆, H₂, Xe, SF₆, C₂F₆, CHF₃, Kr, Ne, He, SiH₄, SiF₄, GeH₄, GeF₄, CH₄, CF₄, AsF₅, PF₃And PF₅. The process gas can be derived from a gas source or can be vaporized from a solid source, depending on the species required. The process gas is ionized in the ion source 402 to generate plasma. Other ion source types that generate plasma include indirect heated cathode (IHC) sources, Bernas sources, RF sources, microwave sources, spiral sources, and electron cyclotron resonance (ECR) sources. The IHC source usually includes a filament positioned close to the cathode and also includes an associated power source. The cathode (not shown) is positioned in the ion source 402. When the filament is heated, the electrons emitted by the filament are accelerated to the cathode to provide heating for the cathode. The heated cathode then provides electrons into the arc chamber, and these electrons collide with the gas molecules of the process gas to generate plasma.

The extraction electrode assembly including the sidewall 403, the suppression electrode 414, and the ground electrode 416 extracts ions 406 from the plasma 440 in the ion source 402 into a well-defined ion beam 418. The ions 406 are accelerated through the boundary 441 and the plasma sheath 442 and pass through the gap 450 between the pair of regulators 430 and 432. The ion source 402 can be biased using DC, pulsed DC, RF current, and/or pulsed RF current, while the substrate is maintained at ground potential. Alternatively, the ion source 402 may be at ground potential, and the substrate may be biased using DC or pulsed DC. The suppression electrode 414 may be biased to a moderately negative voltage to prevent electrons from entering and returning to the ion source 402. The ground electrode 416 may be at ground potential. The intensity of the electric field generated by the electrode assembly can be adjusted to achieve the desired beam current and energy.

Advantageously, the plasma sheath regulator 420 controls the boundary 441 between the plasma 440 and the plasma sheath 442 close to the extraction hole 410 The shape. In order to control the shape of the boundary 441, the plasma sheath modifier 420 modifies or affects the electric field in the plasma sheath 442. When the plasma sheath regulator 420 includes the pair of regulators 430 and 432, the boundary 441 may have a concave shape with respect to the plasma 440, as shown in FIG. 4. Depends on several factors, including, but not limited to, the horizontal distance (G) between the adjusters 430, 432, the vertical distance (S) between the adjusters 430, 432 above the plane of the substrate or the substrate support, and the adjusters 430, 432 The material and thickness of the material, and other process parameters of the ion source, the shape of the boundary 441 can be controlled.

The shape of the boundary 441 between the plasma 440 and the plasma sheath 442 and the electric field gradient in the plasma sheath 442 control the parameters of the ion beam. For example, the angular dispersion of ions 406 can be controlled to assist ion beam focusing. For example, when the boundary 441 has a concave shape with respect to the plasma, large-angle ion dispersion is accelerated across the boundary to assist ion beam focusing. In addition, the ion beam current density of the ion beam 418 can also be controlled. For example, compared to the boundary 441 of a conventional ion source, the boundary 441 has a larger area to extract additional ions. Therefore, the additional extracted ions help increase the ion beam current density. Therefore, under all other parameters being the same, the shape of the boundary 441 can provide a focused ion beam with a high ion beam current density. In addition, the emissivity of the ion beam can also be controlled by controlling the shape of the boundary 441. Therefore, for a given particle density and angular distribution, the beam quality of the extracted ion beam can be well defined.

FIG. 5 shows an ion implantation processing chamber 500, for example, a beam implant device that can be used to implant ions into certain areas of a substrate. Can be used An example of a wire harness device for carrying out the embodiments described herein is VARIAN VIISTA available from Applied Materials, Inc. of Santa Clara, California, USA^® TRIDENT system. It is conceived that other appropriate setting systems from other manufacturers can also benefit from the embodiments disclosed herein. Other equipment, such as plasma immersion ion implantation (P3i) and plasma doping (PLAD) equipment, can also be used to perform the embodiments described herein.

The ion implantation processing chamber 500 includes an ion source 502, an extraction electrode 504, a 90-degree magnet analyzer 506, a first deceleration (D1) station 508, a magnet analyzer 510, and a second deceleration (D2) station 512. The deceleration stations D1 and D2 (also referred to as "deceleration lenses") each consist of multiple electrodes and have defined holes to allow ion beams to pass through. By applying different combinations of voltage potentials to the plurality of electrodes, the decelerating lenses D1 and D2 can manipulate the ion energy, and make the ion beam hit the target wafer with the required energy to implant the ions into the substrate. The aforementioned deceleration lenses D1 and D2 are usually electrostatic triode (or quadrupole) deceleration lenses.

It is conceived that any of the aforementioned devices 300, 400, 500 can be used to implant ions into a substrate and/or a mask located on the substrate. The ions can be implanted at a desired angle of incidence using a suitably set device, or the ions can be implanted along a direction perpendicular to the surface of the substrate and/or the mask. Such an implantation process can be selected to implant the required dopant species at the required dosage.

FIG. 6 is a schematic cross-sectional view of an embodiment of an atomic layer deposition (ALD) processing chamber 634. The ALD processing chamber 634 includes a gas delivery device 630 suitable for cyclic deposition, such as ALD or chemical vapor deposition (CVD). The terms ALD and CVD as used herein refer to the sequential or simultaneous introduction of reactants to deposit thin layers on the substrate structure. The reactants can be sequentially introduced repeatedly to deposit multiple thin layers to form a conformal layer with a desired thickness. The chamber 634 can also be applied to other deposition techniques accompanying the lithography process, such as the 193nm immersion lithography process. The idea is that a separate device can also be used for the lithography process.

The chamber 634 includes a chamber main body 629 having a side wall 631 and a bottom 632. The flow valve channel 633 formed through the chamber body 629 provides a passage for a robot (not shown) to deliver and retrieve a substrate 338 from the chamber 634, such as a 200mm, 300mm, or 450mm semiconductor substrate or glass substrate.

The substrate support 692 is disposed in the chamber 634 and supports the substrate 338 during processing. The substrate support 692 is installed to the lifter 614 to raise and lower the substrate support 692 and the substrate 338 on the substrate support 692. The lifting plate 616 is connected to a lifting plate actuator 618, and the lifting plate actuator 618 controls the raising of the lifting plate 616. The lifting plate 616 may be raised and lowered to raise and lower the pin 620 configured to movably pass through the substrate support 692. The pins 620 are used to raise and lower the substrate 338 above the surface of the substrate support 692. The substrate support 692 may include a vacuum chuck, an electrostatic chuck, or a clamping ring for fixing the substrate 338 to the surface of the substrate support 692 during processing.

The substrate support 692 may be heated to heat the substrate 338 disposed on the substrate support 692. For example, the substrate support 692 may be heated using an embedded heating element, such as a resistance heater, or the substrate support 692 may be heated using radiant heat, such as a heater lamp disposed above the substrate support 692. In some embodiments, the substrate 338 may be heated to a temperature less than about 500°C during the deposition process, for example, between about 125°C and about 450°C. The purge ring 622 may be configured on the substrate support 692 to define a purge channel 624 that provides purge gas to the peripheral portion of the substrate 338 to prevent deposition on the peripheral portion.

The gas delivery device 630 is disposed on the upper part of the chamber body 629 to provide gas (for example, process gas and/or purge gas) to the chamber 634. The pumping system 678 communicates with the pumping channel 679 to evacuate any desired gas from the chamber 634 and help maintain a desired pressure or a desired pressure range inside the pumping zone 666 of the chamber 634.

In one embodiment, the gas delivery device 630 includes a chamber cover 632. The chamber cover 632 includes an expansion pipe 637 extending from the central portion of the chamber cover 632 and a bottom surface 660 extending from the expansion pipe 637 to the peripheral portion of the chamber cover 632. The size and shape of the bottom surface 660 may substantially cover the substrate 338 disposed on the substrate support 692. The chamber cover 632 may have a choke 662 in a peripheral portion of the chamber cover 632 adjacent to the periphery of the substrate 338. The cap 672 includes part of the expansion duct 637 and air inlets 636A, 636B. The expansion duct 637 has an air inlet 636A, 636B to provide air flow from two similar valves 642A, 642B. The air flows from the valves 642A, 642B may be provided together and/or individually.

In one configuration, valve 642A and valve 642B are coupled to separate reactant gas sources, but are coupled to the same purge gas source. For example, the valve 642A is coupled to the reactant gas source 638, the valve 642B is coupled to the reactant gas source 639, and both valves 642A and 642B are coupled to the purge gas source 640. Each valve 642A, 642B includes a delivery line 643A, 643B with a valve seat assembly 644A, 644B, and includes a purge line 645A, 645B with a valve seat assembly 646A, 646B. The conveying pipelines 643A and 643B are in communication with the reactant gas sources 638 and 639 and are in communication with the air inlets 637A and 637B of the expansion pipe 690. The valve seat assemblies 644A, 644B of the transfer lines 643A, 643B control the reactant gas flow from the reactant gas sources 638, 639 to the expansion pipe 690. The purification pipelines 645A and 645B are in communication with the purification gas source 640 and intersect with the delivery pipelines 643A and 643B downstream of the valve seat assemblies 644A and 644B of the delivery pipelines 643A and 643B. The valve seat components 646A and 646B of the purification lines 645A and 645B control the purification air flow from the purification gas source 640 to the delivery lines 643A and 643B. If a carrier gas is used to transport the reactant gas from the reactant gas sources 638, 639, the same gas can be used as the carrier gas and the purge gas (that is, argon can be used as the carrier gas and the purge gas at the same time).

When the valve seat assembly 644A, 644B of the valve is closed, each valve 642A, 642B can be a zero dead volume valve to be able to flush the reactant gas from the delivery line 643A, 643B. For example, the purification line 645A, 645B may be located adjacent to the valve seat assemblies 644A, 644B of the delivery lines 643A, 643B. When the valve seat assemblies 644A and 644B are closed, the purge lines 645A and 645B can provide purge gas to flush the delivery lines 643A and 643B. In the illustrated embodiment, the purge lines 645A, 645B are positioned to be slightly separated from the valve seat assemblies 644A, 644B of the delivery lines 643A, 643B, so that when the purge lines 645A, 645B are opened, the purge gas will not be directly input Valve seat components 644A, 644B. The zero dead volume valve used herein is defined as a valve with a negligible dead volume (that is, not necessarily a zero dead volume). Each valve 642A, 642B can be adapted to provide a combined gas flow of reactant gas 638, 639 and purge gas 640 and/or individual gas flow. The purge gas pulse can be provided by opening and closing the diaphragm of the valve seat assembly 646A of the purge line 645A. The reactant gas pulse from the reactant gas source 638 can be provided by opening and closing the diaphragm valve seat 644A of the transfer line 643A.

The control unit 680 may be coupled to the chamber 634 to control the processing conditions. The control unit 680 includes a central processing unit (CPU) 682, a support circuit 684, and a memory 686 including related control software 683. The control unit 680 may be any type of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The CPU 682 can use any appropriate memory 686, such as random access memory, read-only memory, floppy disk drive, optical disk drive, hard disk, or any other form of local or remote digital storage. Various support circuits can be coupled to the CPU 682 for Support chamber 634. The control unit 680 may be coupled to another controller positioned adjacent to the individual chamber element, such as the programmable logic controllers 648A, 648B of the valves 642A, 642B. The two-way communication between the control unit 680 and various other components of the chamber 634 is handled by a large number of signal cables collectively referred to as the signal bus 688, some of which are shown in FIG. 6. In addition to the programmable logic controllers 648A, 648B from the valves 642A, 642B to control the process gas and purge gas from the gas sources 638, 639, 640, the control unit 680 can also be set to be responsible for other activities used in substrate processing. Automated control, such activities as substrate transport, temperature control, chamber emptying, etc. Some of these activities are described elsewhere in this article.

FIG. 7 is a method of performing a selective deposition process, which can be performed to form different materials on different positions of the substrate. It is conceived that various structures extending outward from the substrate may be formed on the substrate, such as a fin structure, a gate structure, a contact structure, or any other suitable structure used in semiconductor applications.

The method 700 begins at operation 710 by depositing a mask on a substrate, such as the substrate 338 depicted in FIGS. 3-6. In one embodiment, the substrate may be such as crystalline silicon (such as Si&lt;100&gt; or Si&lt;111&gt;), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped Silicon substrates, patterned or unpatterned silicon-on-insulator (SOI) substrates, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire materials. The substrate can have various sizes, such as 200mm, 300mm, 450mm or Other diameters are rectangular or square panels. Unless otherwise stated, the embodiments and examples described herein are performed on a substrate having a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm. In embodiments where an SOI structure is used for the substrate, the substrate may include a deep buried dielectric layer on a crystalline silicon substrate. The substrate can also be any polygonal, square, rectangular, curved or other non-circular workpiece, such as a polygonal glass substrate used in the manufacture of flat panel displays.

The mask can be formed on the substrate by any suitable method. For example, the mask can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin coating process, or the like. The mask may be formed of a material that can be patterned, such as a hard mask material or a photoresist material. Photoresist materials suitable for use as masks include polymeric materials, carbon-based materials, and nanowires, and so on. Appropriate hard mask materials include SiON, SiN, SiO₂, Amorphous carbon, TiN, and TaN, etc. In one embodiment, the mask can be deposited in a desired pattern during the deposition process, which can eliminate the need for a subsequent patterning process. Alternatively, the patterning process may be performed after the mask has been deposited on the substrate.

In operation 720, if the mask has not been patterned during the deposition process, the mask may be patterned. The patterning process can be selected based on the type of material used as the mask, such as a photolithography process. Examples of patterning processes include exposing the mask to x-rays, electron beams, or ultraviolet radiation/light (including deep ultraviolet light and extreme ultraviolet light, and other radiation energy sources. In one example, 248 nm lithography, 193nm lithography Patterned photosensitive masks with technology, 157nm lithography, EUV lithography, electron beam lithography, and similar technologies.

The pattern developed on the mask can be any ideal pattern suitable for subsequent integrated circuit design, such as lines, squares, etc. The patterning of the mask may include removing part of the mask to expose an area of the underlying substrate. After operation 720, the patterned mask may remain on the substrate such that certain areas of the substrate (e.g., the first area) are exposed and other areas of the substrate (e.g., the second area) are covered by the mask.

In operation 730, an ion implantation process may be performed to dope, coat, process, implant, insert or modify certain film/surface properties of both the mask and the exposed area of the substrate (such as the first or implanted area) . As a result, the mask and the exposed area of the substrate can be modified, while the area of the substrate covered by the mask (for example, the second or unplanted area) can remain unmodified. For example, the mask can shield the second region from implantation.

Operation 730 may use the aforementioned device configured to implant ions on the substrate. A suitable ion implantation process (such as the above-mentioned oriented plasma process) can modify the surface properties of the exposed area of the substrate. The ions (including atoms of the desired type) implanted in the exposed region of the substrate may be selected to respond to a certain type of material to be subsequently deposited, which will be described in more detail with reference to operation 750. In one example, the required atomic species can be reduced to less than about 5×10¹⁶(Ion/cm²) (E.g. between about 1×10¹⁴(Ion/cm²) And about 5×10¹⁶(Ion/cm²The dose between )) is implanted into the exposed area of the patterned mask and the substrate.

Several process parameters can be controlled during the ion implantation process. In an exemplary ion implantation process, a plasma process can be performed by supplying a gas mixture into a processing chamber (eg, chambers 300, 400, 500). The dopant gas mixture may be supplied into the processing chamber at a flow rate between about 10 sccm and about 200 sccm. Suitable gas for supplying ion doping gas mixture includes AsH₃, GaH₃, SiH₄, SiF₄, GeH₄, GeF₄, CH₄, CF₄, AsF₅, PF₃, PF₅, B₂H₆, BH₃And similar gases. Inert gas such as Ar, He, Kr, Ne, or similar, or inert gas such as H₂, N₂, N₂O, NO₂, Or similar carrier gas is supplied to the gas mixture. The chamber pressure is generally maintained between about 0.1 millitorr and about 100 millitorr, for example about 10 millitorr. RF power such as capacitive or induced RF power, DC power, electromagnetic energy, or magnetron sputtering can be supplied into the processing chamber to help dissociate the gas mixture during the processing.

The electric field generated by applying a DC or RF electrical bias to the substrate support or to the air inlet above the substrate support, or both, can be used to accelerate the ions generated by the dissociation energy to the substrate. In some embodiments, the ions may undergo a mass selection or mass filtration process, which may include passing the ions through a magnetic field aligned orthogonal to the desired direction of movement. For the purpose of ionizing atoms, the electric field provided by the RF power can be capacitively or inductively coupled, and can be a DC discharge field or an alternating field, such as an RF field. Alternatively, microwave energy can be applied to an ion implantation gas mixture containing any of these elements to produce ion. In some embodiments, the gas containing high-energy ions may be plasma.

Apply an electrical bias (peak-to-peak voltage) between about 50V and about 10,000V (for example, about 1000V) to the substrate support, the gas distributor, or both to accelerate the ions with the required energy Go to the substrate surface. In some embodiments, an electrical bias is also used to ionize the process gas. In other embodiments, a second electric field is used to ionize the process gas. In one embodiment, an RF field with a frequency of about 2 MHz is provided to ionize the process gas, and the substrate support is biased at a power level between about 100 W and about 10,000 W (for example, about 200 W). Generally, the generated ions are accelerated to the substrate by biasing the above-mentioned substrate or gas distributor.

In some embodiments, the power used to generate ions can be pulsed. You can apply power to the plasma source for the required time and then stop for the required time. The power cycle can be repeated for the required number of cycles at the required frequency and non-empty factor. In some embodiments, the plasma may be pulsed at a frequency between about 1 Hz and about 50,000 Hz (e.g., between about 1000 Hz and about 5000 Hz). In other embodiments, the non-empty factor (the ratio of the power supply time per cycle to the non-power supply time) of the plasma pulse may be between about 10% and about 90%, for example, between about 25% and about 50%. between. In one embodiment, RF power between about 100 watts to about 5000 watts can be supplied, and a bias voltage between about 50 watts and about 11,000 watts can be supplied power. The process temperature can be controlled between about -100 degrees Celsius and about 650 degrees Celsius.

In operation 740, the patterned mask may be removed. A suitable mask removal process (such as a wet cleaning or plasma ashing process) can be used to remove the mask. The idea is that the type of mask removal process used can be determined at least in part by the type of mask located on the substrate. In one example, if a photoresist is used as a mask, a piranha stripping process (sulfuric acid and hydrogen peroxide/buffered hydrofluoric acid) can be used to remove the mask. The idea is that the mask removal process can be performed so that the exposed area of the substrate and the area covered by the mask are not modified before the mask is removed, so as to maintain the implanted (exposed area) and undistributed areas of the substrate. The doping distribution of the plant (coverage area) area. Due to the mask removal process, the substrate may exhibit implanted and non-implanted regions with different surface properties as a result of the ion implantation operation 730.

In operation 750, a material may be selectively deposited on the implanted or non-implanted area of the substrate. Various material deposition processes (such as an ALD process) can be used to deposit materials on the desired area of the substrate. The material selected for deposition can be affected by the surface properties of the substrate (ie, implanted vs. unplanted area). The implanted area of the substrate can absorb the molecules supplied during the ALD process and react with these molecules so as to incorporate atoms from each pulse of the ALD process, so that the deposited material can grow and be continuously deposited. Alternatively, the non-implanted area of the substrate can absorb the molecules supplied during the ALD process and react with these molecules to incorporate the original from each pulse of the ALD process. Sub, and able to deposit the required materials. Therefore, the desired area of the substrate may include implanted or unplanted areas.

Since the ALD process is sensitive to surface conditions, the method 700 is suitable for selectively depositing materials on specific areas of the substrate. The ALD process is a CVD process with self-terminating/restricted growth. The ALD process yields only a few angstroms or a single layer thickness. The ALD process is controlled by dividing the chemical reaction into two independent and repeating half reactions. The thickness of the material formed by the ALD process depends on the number of reaction cycles. The first reaction provides the first atomic layer of the molecular layer absorbed on the substrate, and the second reaction provides the second atomic layer of the molecular layer absorbed on the first atomic layer. In this way, the ordered material structure can serve as a template for the growth of the material layer.

Depending on the type of implanted ions and the type of deposited material, the implanted or non-implanted area can prevent the ALD material from being deposited on either the implanted or non-implanted area. Or, again depending on the type of implanted ions and the type of material being deposited, the implanted and non-implanted areas of the substrate can be used as the starting seed/nucleation surface to allow the ALD material to form at the nucleation site. Nucleus and growth. In this way, the selective deposition process can selectively deposit different materials at different locations on the substrate.

During the ALD process, the first reactant gas mixture can be supplied into the processing chamber simultaneously, sequentially, or without the reducing gas mixture during the thermal ALD process or the plasma ALD process as needed. 634, the reducing gas mixture such as hydrogen (H₂) Or NH₃gas. Can be supplied to the processing chamber 634 A suitable first reactant gas mixture may include a silicon-containing gas (e.g. SiH₄, Si₂H₆), or other appropriate silicon-containing compounds, and/or tantalum-containing gas, titanium-containing gas, platinum-containing gas, cobalt-containing gas, tungsten-containing gas, aluminum-containing gas, nickel-containing gas, copper-containing gas, silver-containing gas, Gold gas, hafnium-containing gas, ruthenium-containing gas, boron-containing gas, phosphorus-containing gas, nitrogen-containing gas, oxygen-containing gas, combinations and mixtures of the above gases, or other materials that can deposit a single layer on the surface of a substrate suitable for semiconductor devices One or more of the appropriate gases. Examples of alternative reagents described herein (i.e., reducing agents used with reactant gases to form a monolayer during the deposition process) may include hydrogen (e.g., H₂Or atom H), nitrogen (e.g. N₂Or atom N), ammonia (NH₃), hydrazine (N₂H₄), a mixture of hydrogen and ammonia (H₂/NH₃), borane (BH₃), diborane (B₂H₆), triethylborane (Et₃B), Silane (SiH₄), Ethylsilane (Si₂H₆), Propylsilane (Si₃H₈), Butane (Si₄H₁₀), methyl silane (SiCH₆), dimethyl silane (SiC₂H₈), phosphine (PH₃), derivatives of the above reagents, plasma of the above reagents, or a combination of the above reagents.

The pulse of the first reactant gas mixture lasts for a predetermined time interval. The term pulse as used herein refers to the dose of material injected into the processing chamber. Between each pulse of the first reactant gas mixture or the first and second reactant gas mixtures (discussed further below), there may be each or more of the first and/or second reactant gas mixtures Between pulses, the purge gas mixture is pulsed into the processing chamber to remove unreacted/unabsorbed impurities or residual gas mixtures (such as Unreacted impurities from the reactant gas mixture or others) so that the impurities or residual gas mixture can be pumped out of the processing chamber.

During the pulsing of the first reactant gas mixture, several process parameters are also controlled. In one embodiment, the process pressure is controlled between about 7 Torr and about 30 Torr. The treatment temperature is between about 100°C and about 450°C. The RF power can be controlled between about 100 watts and about 2000 watts. The reactant gas supplied in the first reactant gas mixture may be controlled between about 5 sccm and about 10 sccm. The reducing gas may be supplied between about 100 sccm and about 700 sccm.

After the pulse of the first reactant gas is terminated, the pulse of the second reactant gas mixture is supplied into the processing chamber 634 to form a second monolayer of the desired material on the desired area of the substrate. The second reactant gas mixture can be supplied into the processing chamber 634 at the same time as the reducing gas mixture (or reagent) during the thermal ALD process or the plasma ALD process, or sequentially, or without the reducing gas mixture. Mixtures such as hydrogen (H₂) Or NH₃gas. It is believed that the second monolayer is absorbed onto the first monolayer by a chemical reaction to allow atoms from the second monolayer to be firmly adhered to the atoms of the first monolayer.

In one embodiment, a suitable second reactant gas mixture that can be supplied to the processing chamber 634 can include a silicon-containing gas (e.g., SiH₄, Si₂H₆), or other appropriate silicon-containing compounds, and oxygen-containing gases (such as H₂O, O₂, Or O₃), tantalum-containing gas, titanium-containing gas, platinum-containing gas, cobalt-containing gas, tungsten-containing gas, aluminum-containing gas, nickel-containing gas, copper-containing gas, silver-containing gas, gold-containing gas, hafnium-containing gas, ruthenium-containing gas, One or more of boron-containing gas, phosphorus-containing gas, nitrogen-containing gas, oxygen-containing gas, combinations and mixtures of the above-mentioned gases, or other suitable gases that can deposit a single layer on the surface of a substrate suitable for semiconductor devices. Examples of alternative reagents described herein (i.e., reducing agents used with reactant gases to form a monolayer during the deposition process) may include hydrogen (e.g., H₂Or atom H), nitrogen (e.g. N₂Or atom N), ammonia (NH₃), hydrazine (N₂H₄), a mixture of hydrogen and ammonia (H₂/NH₃), borane (BH₃), diborane (B₂H₆), triethylborane (Et₃B), Silane (SiH₄), Ethylsilane (Si₂H₆), Propylsilane (Si₃H₈), Butane (Si₄H₁₀), methyl silane (SiCH₆), dimethyl silane (SiC₂H₈), phosphine (PH₃), derivatives of the above reagents, plasma of the above reagents, or a combination of the above reagents.

The pulse of the second reactant gas mixture lasts for a predetermined time interval. Between each pulse or several pulses of the second reactant gas mixture or the first and second reactant gas mixtures, the purge gas mixture can be pulsed into the processing chamber to remove unreacted/not absorbed by the substrate surface Impurities or residual gas mixtures (for example, unreacted impurities from reactant gas mixtures or others).

During the pulsing of the second reactant gas mixture, several process parameters are also controlled. In one embodiment, the process pressure is controlled between about 5 Torr and about 30 Torr. The treatment temperature is between about 125°C and about 450°C. The RF power can be controlled between about 100 watts and about 800 watts. The reactant gas supplied in the second reactant gas mixture can be It is controlled between about 5sccm and about 20sccm. The reducing gas may be supplied between about 100 sccm and about 700 sccm.

Between each pulse of the reactant gas mixture or after several pulses, the purge gas mixture is then supplied to the processing chamber 634 to remove residues and impurities from the processing chamber. Several process parameters are also controlled during the pulsing process of the purified gas mixture. In one embodiment, the process pressure is controlled between about 1 Torr and about 100 Torr. The treatment temperature is between about 125°C and about 450°C. The RF power can be controlled between about 100 watts and about 800 watts. Ar or N₂The gas can be supplied between about 200 sccm and about 1000 sccm.

After the pulse of the purge gas mixture, an additional cycle starting with the pulse of the first and/or second reactant gas mixture followed by the pulse of the purge gas mixture can then be repeated until the desired material thickness is obtained. When the pulsed first reactant gas mixture of the subsequent cycle begins, the process pressure and other process parameters can be adjusted to a predetermined level to assist the deposition of subsequent material monolayers.

FIG. 8 is a graph 800 schematically illustrating the nucleation delay of the ALD process versus the ion dose implanted in the substrate. The X-axis of the graph represents the number of ALD cycles performed, and the Y-axis represents the deposition thickness of the deposited layer. Line 802 illustrates the nucleation and growth of a material layer deposited on the surface of a substrate that has not been processed or modified (for example, by ion implantation). As can be seen, nucleation is at or near the first ALD cycle.

Line 804 illustrates the nucleation and growth of a layer of material deposited on the surface of the substrate that has been modified with the implant dose x. Here, due to being mixed The ion dose into the substrate surface, the nucleation of the material is delayed as a result of the surface modification of the substrate. Line 806 illustrates the nucleation and growth of the material layer deposited on the surface of the substrate that has been modified with the implant dose y (where y&gt;x). Here, as the dose of ions incorporated into the surface of the substrate increases, the nucleation of the material is further delayed as a result of the modification of the substrate.

Therefore, it can be seen that the amount of nucleation delay can depend on the implantation dose. Using the nucleation delay benefit of the method 700, after a certain number of ALD cycles, the film thickness of the implanted and non-implanted regions of the substrate is different. Therefore, the material can be selectively deposited mainly on a desired area of the substrate, such as an unplanted area formed after removing the mask. It should be noted that appropriate ion doses and ALD deposition parameters should be used to achieve the nucleation delay benefits observed between the implanted and non-implanted areas of the substrate.

In summary, ion implantation of a substrate with a patterned mask on it and subsequent mask removal can be used to produce implanted and unplanted areas on the substrate. The combination of the nucleation delay phenomenon and the selection of ion dose parameters and material deposition parameters can be used to selectively deposit material on a desired area of the substrate while exhibiting little or no material deposition in other areas of the substrate. Therefore, the selective deposition of materials on the substrate can be improved using the methods described herein.

Although the foregoing is directed to the embodiments of the present disclosure, other and further embodiments of the present disclosure can be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the scope of subsequent patent applications.