Method for wafer inspection, wafer inspection tool, and non-transitory computer-readable medium

Method for wafer inspection, wafer inspection tool and non-transitory computer readable medium

METHOD FOR WAFER INSPECTION, WAFER INSPECTION TOOL, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM

The present invention generally relates to dynamic design attributes for wafer inspection.

The following description and examples will not be recognized as prior art because they are included in this paragraph.

A method or system (such as electronic design automation (EDA), computer-aided design (CAD), and other integrated circuit (IC) design software) can be used to develop an integrated circuit design. These methods and systems can be used to generate a circuit pattern database from the IC design. The circuit pattern database contains data representing a plurality of layouts for various layers of the IC. The data in the circuit pattern database can be used to determine the layout of a plurality of marking lines. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to manufacture one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlayer dielectric, and a metallization layer. One of the interconnect patterns.

The term "design data" (as used herein) generally refers to the physical design (layout) of an IC and the data derived from the physical design through complex simulation or simple geometric and Boolean operations.

Manufacturing semiconductor devices (such as logic and memory devices) usually involves using a number of semiconductor manufacturing processes to process a substrate (such as a semiconductor wafer) to form various features and multiple stages of the semiconductor devices. The lithography department involves the transfer of a pattern from a marking to the matching A semiconductor manufacturing process for a photoresist placed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices can be fabricated in a configuration on a single semiconductor wafer and then divided into individual semiconductor devices.

The inspection process is used in various steps during a semiconductor manufacturing process to detect defects on the wafer to promote higher yields and therefore higher profits in the manufacturing process. Inspection has always been an important part of manufacturing semiconductor devices (such as IC). However, as the size of semiconductor devices decreases, inspection becomes even more important for the successful manufacture of acceptable semiconductor devices, because smaller defects can cause these devices to fail.

However, as design rules shrink, semiconductor manufacturing processes can operate closer to the limits of the execution capabilities of these processes. In addition, as design rules shrink, smaller defects can have an impact on the electrical parameters of the device, which forces more sensitive inspections. Therefore, as the design rules shrink, the number of defects potentially related to yield detected by inspections has increased significantly, and the number of interfering defects detected by inspections has also increased significantly. Therefore, more and more defects can be detected on the wafers, and it can be difficult and expensive to correct the procedures to eliminate all of these defects.

In an effort to maximize the sensitivity of the inspection system to capture subtle spatial systemic "design for manufacturability" (DFM) defects caused by the interdependence of design and procedures, the system may be affected by areas that are not of interest (such as CMP-filled areas). ) Overwhelmed by millions of events. For many reasons, detecting such interfering defects is disadvantageous. For example, these interfering events need to be filtered from the detection results by the subsequent processing of the detection data. In addition, the detection of interference events limits the ultimate achievable sensitivity of the detection system for DFM applications. A high rate of interfering defect data will also overload the data processing capacity of the detection system during operation, thereby reducing the output of data and/or causing data loss.

Correspondingly, the development of a device that does not have one or more of the above-mentioned shortcomings is used in comparison with wafer inspection. The methods and/or systems related to the application may be advantageous.

The following description of the various embodiments should not be interpreted in any way that limits the scope of the attached patent application.

An embodiment relates to a method for wafer inspection. The method includes: during the operation of a wafer inspection process, prompting a user of a wafer inspection tool on which a wafer inspection tool of the wafer inspection process is executed with information for a design classification procedure. The information includes one or more formulas used to calculate design attributes from a wafer design. The method also includes: receiving information from the user and updating the wafer inspection process based on the received information. In addition, the method includes: performing inspection of the wafer according to the updated wafer inspection process. Performing the inspection includes: scanning at least a part of the wafer using the wafer inspection basis, thereby generating an output in response to light from at least a part of the wafer. Performing the inspection also includes detecting defects on the wafer based on the output. In addition, performing the inspection includes: classifying the defects detected on the wafer according to the designed classification procedure in the updated wafer inspection process. The steps of prompting, receiving, updating, executing, scanning, detecting, and classifying are executed by the wafer inspection tool.

The above method can be performed according to the further description herein. Furthermore, the above method may include any other steps of any other method described herein. In addition, the above methods can be executed by any of the systems described herein.

Another embodiment relates to a non-transitory computer-readable medium that stores program instructions executable on a computer system for executing a computer-implemented method for wafer inspection, a wafer inspection tool. The computer-implemented method includes the steps of the above-mentioned method. The computer-readable medium can be further configured as described herein. The steps of the computer-implemented method can be executed according to the description herein. In addition, the computer-implemented method for executing the program instructions may include any other steps of any other method described herein.

An additional embodiment relates to a wafer inspection tool. The wafer inspection mechanism includes an optical subsystem configured to scan at least a portion of a wafer, thereby generating output in response to light from at least a portion of the wafer. The wafer inspection tool also includes a computer subsystem, which is configured to prompt information for a design-based classification process during the operation of a wafer inspection process to perform one of the wafer inspection processes on it A user of wafer inspection tools. The information includes one or more formulas used to calculate the design attributes from the wafer design. These design attributes are used to classify the defects in the design classification process. The computer subsystem is also configured to receive information from the user and update the wafer inspection process based on the received information. In addition, the computer subsystem is configured to detect defects on the wafer based on the output and classify the inspected on the wafer according to the designed classification procedure in the updated wafer inspection process And other defects. The wafer inspection tool can be further configured as described herein.

<p>100step</p><p>102Step</p><p>104Step</p><p>106Step</p><p>200Design editing</p><p>202Solid Polygon/Polygon</p><p>204Polygon</p><p>206Result</p><p>208Polygon</p><p>210Result</p><p>212Union</p><p>214Result</p><p>216Result</p><p>218Polygon</p><p>300Polygon</p><p>302Polygon</p><p>400Step</p><p>402Step</p><p>404Step</p><p>406Step</p><p>408Step</p><p>410Step</p><p>412Step</p><p>414Step</p><p>416Step</p><p>418Step</p><p>420Step</p><p>422Step</p><p>424Step</p><p>426Step</p><p>428Step</p><p>430Step</p><p>432Step</p><p>434Step</p><p>436Step</p><p>438Step</p><p>440Step</p><p>442step</p><p>444step</p><p>446Step</p><p>448Step</p><p>450Step</p><p>452Step</p><p>454Step</p><p>500Non-transitory computer readable media</p><p>502Program command</p><p>504Computer System</p><p>600Optical Subsystem</p><p>604Light source</p><p>606Beam Splitter</p><p>608Refracting optics</p><p>610wafer</p><p>612Detector</p><p>614Computer System</p>

When reading the following [Embodiments] and referring to the drawings, you will understand the other objectives and advantages of the present invention. Among them: FIG. 1 shows a flowchart of an embodiment of a method for calculating a design attribute; 2 is a schematic diagram showing an example of a polygon used in a one-of-two-layer design clip of a wafer design and the result of an embodiment of the layer logic operation between the layers; FIG. 3 is a response to a A schematic diagram of an example of a polygon in the one-of-two-layer design editing of a wafer design; FIGS. 4a to 4c show a flowchart of an embodiment of a method for wafer inspection; FIG. 5 shows a storage An embodiment of a non-transitory computer-readable medium that can be executed on a computer system of a computer system of a wafer inspection tool for executing one or more of the computer-implemented methods described herein Block diagram; and FIG. 6 is a schematic diagram showing a side view of an embodiment of a wafer inspection tool.

Although the present invention is susceptible to various modifications and alternative forms, specific embodiments of the present invention are shown in the drawings through examples and will be described in detail herein. However, it should be understood that the detailed description of the drawings here does not intend to limit the present invention to the specific form disclosed. On the contrary, the present invention will fall within the spirit and scope of the present invention (such as the scope of the attached patent application). (Defined) all modifications, equivalents and replacements.

Turning to these diagrams, it should be noted that these diagrams are not drawn to scale. In particular, the proportions of some of the elements in the drawings are greatly enlarged to emphasize the characteristics of the elements. It should also be noted that these drawings are not drawn to the same scale. The same reference numbers are used to indicate elements that can be similarly configured and shown in more than one drawing. Unless otherwise stated herein, any of the elements described and shown can include any suitable commercially available elements.

The classification by design (DBB) is a feature, which is part of some wafer inspection tools. This feature enables the location of defects based on chip design data to be correlated with each other. This technology has made the following use cases of detection tools possible: a) the ability to remove systemic interfering defects; b) systemic defect discovery; and c) systemic defect classification and monitoring.

For example, basic design attributes (such as pattern density and intersection area) calculated based on specific mathematical operations performed on polygon data are enhanced to have a rich set of existing defect attribute examples based on design information. This design information helps to easily classify new disturbing defect types. A "interfering" or "interfering defect" is a term commonly used in this technology. It refers to the detection of a potential defect on a wafer, but it is not a fact that a user regards as important defect. In this way, an "interfering defect" can only be noise on the wafer detected by inspection, which does not mean any actual defect on the wafer or an actual defect that the user does not pay attention to.

The only shortcoming today is that these operations are implemented in the code as functions. For example, currently, all of these attribute definitions are implemented in software as functions. The system can implement a set of design-by-design attributes based on predefined operations for one or more layers. If any new attribute needs to be supported by a new formula, the code has to be modified to introduce a new function. In other words, if new attributes involving operations are required, the code must be changed and new calculation logic must be introduced into the software. This requires new software to be released to the field to introduce the new attribute(s). The user of the wafer inspection tool cannot change the formula after the attribute calculation. Customers of the testing tool are required to use electronic design automation (EDA) to generate the combined data. But this is also difficult because of the need to interface between the design and the defect team.

An embodiment relates to a method for wafer inspection. The embodiments described in this article can be used to enhance wafer inspection tools with a new concept of "dynamic design attributes", which can provide the ability to define attribute formulas during operation and use them as processes and other defects Part of classification and/or classification methods and products (such as iDO, which can be purchased from KLA-Tencor, Milpitas, Calif). For example, the method includes: during the operation of a wafer inspection process, prompting information for a sorting procedure according to the design to a user on which a wafer inspection tool of the wafer inspection process is executed. A dynamic design attribute is an extension of an existing design attribute. In addition, the dynamic design attributes described in this article can be combined with any existing DBB feature set. In one embodiment, the wafer inspection tool is configured as a broadband plasma tool, which is a further embodiment herein.

The information includes one or more formulas used to calculate design attributes from a wafer design. These design attributes are used to classify the defects in the design classification process. In this way, the embodiments enable users to define formulas for calculating design attributes. Therefore, the logic after the calculation of a dynamic design attribute can be obtained from a user of the wafer inspection tool. In this way, customers and application engineers can come up with their own formulas based on the interaction between the multiple layers of the polygon. These formulas can lead to differences in the customer's test results. "Dynamic Design attributes". The user can add any number of dynamic design attributes. In addition, these embodiments provide users with flexibility to derive design attribute formulas based on learning in the field. Attributes can be generated dynamically and quickly. The embodiments described herein are therefore dynamic and have multi-user control.

This formula can be applied to "design editing". A "design clip" (as the term is used in this document) is defined as a relatively small part of the entire design data for the wafer. For example, in one embodiment, the one or more formulas include one or more of the design attributes used to calculate the part of the design data from the design around the location of the defects detected on the wafer Formulas. The part of the design data around the location of the defects detected on the wafer can be a design clip extracted from the entire design data based on the design space coordinates of the defects, which can be based on August 2009 It was determined as described in US Patent Application No. 7,570,796 granted to Zafar et al. on the 4th, which is incorporated herein by reference as described in its entirety. In this way, the attributes of the design clips around the defect location used to effectively classify the defect can be calculated.

The information used for a dynamic design attribute (some or all of the information that can be provided by a user) can include an attribute name, an attribute description, an attribute internal name, and a calculation formula (which can be one of the further descriptions in this article or Multiple formulas), an attribute data type, and an attribute value. In one embodiment, the information used for the DBB program includes a flag for each of the design attributes indicating that the design attributes are type attributes or measurement attributes. A type attribute defines an attribute of a type of the defect and can be expressed as an alphanumeric string. For example, a type attribute may be a defect type such as a bridge defect, a particle defect, and the like. A measurement attribute can be an attribute that defines a size of the defect and can be expressed by a measurement value or a range of the measurement value. For example, a measurement attribute can be a range of the width of the defects. In another embodiment, the classification step is based on the part of the design data of the wafers around the location of the defects detected on the wafer to separate the defects, and the information includes specific information for the design. Each of the attributes indicates the design used to calculate the design attributes A flag indicating a degree of part of the data. In one embodiment, the extent of the parts of the design data is the whole of the parts of the design data or the area of interest of one of the parts of the design data. For example, the dynamic design attribute may have a flag indicating that the attribute is used for the entire clip or one of the extended bounding boxes (EBB) in the clip. The EBB can represent the area of interest in the design clip. The aforementioned flags can include any suitable tags that can be used to identify these dynamic design attributes as described above.

One of the important aspects of the dynamic design attributes described in this article is the calculation formulas, and these calculation formulas are now further described. A dynamic design attribute formula can have inputs including the input layer(s). The input layer(s) may include one or more of the designs for the wafer. A design clip is captured for use in these layers, and the polygons in the clip are used for attribute calculations. In one embodiment, the information includes one or more operators for the one or more formulas, and the one or more operators are used for one or more of the two or more polygons in the design. Logical operators. For example, a dynamic design attribute formula can also have an input that includes one level of operator, and is applied to the logical operator between two levels. In another embodiment, the information includes one or more calculations for performing the one or more formulas on the polygon caused by the one or more logical operators, and the result of the one or more calculations These are the calculated design attributes. For example, a dynamic design attribute formula may have an input including a result calculator. When a layer operator is applied to the input layer of a design clip, a set of polygons can be generated. A result calculator is then applied to these polygons to arrive at an attribute value. In this way, the dynamic design attributes described herein provide the ability to use logical operators to combine data from multiple layers and link it to the attribute definition.

In an example of a dynamic design attribute, a design data file may include M1 and M2 layers (metal layer 1 and metal layer 2 of the wafer, respectively). The user can define a dynamic attribute called "MergeCount". MergeCount=POLYGONCOUNT (M1 or M2). The dynamic attribute M ergeCount calculation is shown in Figure 1. Specifically, as shown in Figure 1 As shown in step 100 of, the calculation includes: capturing one of the design clips for the M1 and M2 layers, and can be performed as described further herein. The calculation also includes: calculating the M1 polygons or M2 polygons (as shown in step 102 of FIG. 1). As shown in step 104 of FIG. 1, calculating the dynamic attribute further includes calculating PolygonCount. As further shown in step 106, the calculation includes specifying an attribute value, which is performed based on the result of the PolygonCount.

In one embodiment, the one or more logical operators include one or more of logical AND, OR, XOR, and NOT operators. For example, in these layers of logical operations, the part of the calculation formula is a logical operation formula between the layers that use logical AND, OR, XOR, and NOT operators.

FIG. 2 shows the input and output of various logical operators that roughly represent an example of a polygon that can be included in the design data for a general wafer. In the design clip 200, a solid polygon 202 represents layer 1, and a diagonal polygon 204 formed therein represents layer 2. The polygon 204 includes two vertically oriented lines or grooves that overlap a portion of the solid polygon 202.

Figure 2 also shows the results of layer logic operations between these layers. For example, result 206 is the result of performing an AND operator for polygons 202 and 204. The result includes: intersecting the polygon 208 between the two layers. The result 210 is the result of performing an OR operator for the polygons 202 and 204. The result 210 contains the union 212 of the polygons between the two layers. The result 214 is the result of executing one of the NOT operators for the polygons 202 and 204. This result is produced by merging polygons 202 and 204 and applying an inversion to the polygons. The result 216 is the result of executing one of the XOR operators for the polygons 202 and 204. This result is generated by finding the polygons 218 that are specific to the regions in the layers. The above-mentioned layers of logical operators can be applied to one or more layers. A design attribute formula can also be based on a combination of layers, such as "My new attribute"=COUNT(POLY OR ETCH OR STI), where POLY, ETCH, and STI are the polysilicon and etching of the wafer. Carve and shallow trench isolation layer.

The dynamic design attribute formula also contains a "result calculator". These calculators are basically performed by mathematical calculations on groups of synthetic polygons of layered logic operations. The result of applying the "calculator" is basically the attribute value. In one embodiment, the one or more calculations include one or more of the following: counting the number of one of the polygons generated by the one or more logical operators; counting the number of polygons generated by the one or more logical operators The number of vertices in each of the polygons; sum up the area of all the polygons generated by the one or more logical operators; determine the number of the vertices generated by the one or more logical operators One of the smallest areas of all areas of the polygons; and one of the largest areas of all the polygons generated by the one or more logical operators is determined. For example, the following result calculator can be used for these dynamic design attributes. These calculators can also be extended to support any new calculators produced in the future.

a) Polygon counting calculator-the number of polygons in the counting result

b) Vertex count calculator-count the number of vertices in each polygon

c) Polygon area calculator-the sum of the area of all polygons

d) Minimum area calculator-the minimum area of all polygon areas in the result set

e) Maximum area-the maximum area of all polygon areas in the result set

In one embodiment, the calculated design attributes include the pattern density of the polygons in the design. For example, based on the above, one of the EBB pattern density attributes in DBB can be expressed as: POLYGONAREA (LAYER1 OR LAYER2 OR LAYER3 OR LAYER...). In another embodiment, the calculated design attributes include the overlap ratio of polygons in two or more layers of the design. For example, an overlap ratio attribute can be expressed as: POLYGONAREA (LAYER1 AND LAYER2 AND LAYER3).

The dynamic design attributes described in this article can be used to separate interfering defects from other defects detected on the wafer. For example, these properties can be used to eliminate disturbing defects in free areas where no patterns are printed. This can be performed by defining an OR operation on Achieved by a dynamic design attribute on all layers. In addition, the attributes described in this article can be used to identify virtual related interference defects. For example, in the design shown in FIG. 3, polygon 300 is a polygon in the polysilicon layer, and polygon 302 is a polygon in the diffusion layer. If a defect falls on an area where polysilicon and diffusion overlap and if the overlap area is greater than 90%, then the defect can be regarded as an interfering defect. If the defect falls in a non-overlapping area, it is regarded as a real defect. As in this case, it is possible to define a new dynamic design attribute with an AND operator between the layers.

The dynamic design attributes described in this article can also be used for systemic defects that span multiple products. For example, most systematic defects in a foundry are repeated across multiple products with some variations in pattern size and the same design rules surrounding the patterns. Most defect types have common rules, such as maximum line width, layer combination, spacing between polygons, etc., and these rules can be transferred from one device to another to monitor or find the defect type concerned. Semiconductor IC manufacturers can generate these rules, store them in a database, and use them when they need to spread a new device. The above-mentioned logical operators are possible and can be applied based on different user scenarios. Providing software flexibility to quickly come up with these definitions will improve feature flexibility for application manipulation and also identify new use cases for application DBB.

The user is prompted that the information used for the DBB program can be executed in any suitable way. For example, a user can provide input to the wafer inspection tool on which a wafer inspection process is run. In this example, a user can select a wafer inspection process from a list of available wafer inspection processes and select a run option. The list of processes and the operating options can be displayed to the user by any display device coupled to the wafer inspection tool. After the user has selected a wafer inspection process to allow, a prompt may be displayed to the user on the display device, the prompt asking the user whether to provide new information for a DBB process of the process. If the user selects one of the options for inputting new information, the display device can display various information about the sorting process to be run for the wafer inspection process The DBB program allows the user to change, delete or add information to the existing program.

The method also includes: receiving information from the user and updating the wafer inspection process based on the received information. The information from the user can be received via any suitable input device. The wafer inspection process can be updated in any suitable way. In this way, the software uses a formula defined by the user (rather than a hard-coded function in the code).

The method further includes: performing a wafer inspection according to the updated wafer inspection process. Performing the inspection includes scanning at least a portion of the wafer with the wafer inspection tool, thereby generating an output in response to the light from the at least a portion of the wafer, which can be performed in any suitable manner. In addition, performing the inspection includes: detecting defects on the wafer based on the output, which can be performed in any suitable manner. Performing the inspection further includes: classifying the defects detected on the wafer according to the DBB program in the updated wafer inspection process, which can be executed as described further herein. The steps of prompting, receiving, updating, executing, scanning, detecting, and classifying are performed by the wafer inspection tool, which can be configured according to the further description herein.

The DBB attributes can be calculated in the main user interface (UI) during a test run. For example, given a defect location, the detector software has the ability to retrieve design information or design editing, which basically revolves around the design background of a given defect. These DBB attributes can be used in the DBB process to use design context information to isolate concerns or sample shape defects (DOI). For example, in one embodiment, the classification step divides the interfering defects in the defects into one or more first groups and the DOI in the defects into one or more second groups. In another embodiment, the classification step shapes a sample of the DOI among the defects by dividing the different types of the DOI into different groups.

In some embodiments, the information includes one or more layers of the wafer, where the design is used to calculate the design attributes for one or more layers of the wafer. For example, the design clip information described above can be retrieved for a specific layer. In one embodiment, one or more parameters of the DBB program are based on multi-level design rules. For example, dynamic design attributes can be based on multi-layer design rules It makes possible better classification or sample shaping defects. The classification process may also include: applying design rule checking rules to the clips to better classify or to separate defects based on pattern failure critical conditions. In one embodiment, the classification step divides the defects into patterns by applying a design rule check to the part of the design data of the wafer around the location of the defects detected on the wafer Different groups of failures with different critical conditions.

Figure 4 shows an embodiment of the method described herein. It should be noted that not all of the steps shown in Figure 4 are necessary for the practice of the method. Some steps can be omitted and added, and the method is still practiced within the scope of the embodiments described herein. In addition, those skilled in the art will understand that all of these steps do not have to be executed in the order shown in FIG. 4.

As shown in Figure 4A, the method starts at the beginning 400. The method includes: activating the detector client software (as shown in step 402). The detector client software is only the software on the wafer inspection tool, which is used by a user to interact with and control the inspection tool. This software can be activated in any suitable way. The method also includes loading a wafer (as shown in step 404). The wafer can be loaded in any suitable way. For example, a wafer container or cassette can be loaded into the wafer inspection tool automatically or by a user, and the user can control the wafer inspection tool to load one of the wafers from the container to the tool One on stage.

The method further includes: defining the wafer layout (as shown in step 406). Defining the wafer layout may include: defining the layout of the die on the wafer in the coordinates that can be used by the wafer inspection tool. The user can use the above-mentioned software to input the wafer layout. In addition, the method includes: aligning the wafer (as shown in step 408). For example, the wafer inspection tool can be configured to align the wafer in the wafer inspection tool after receiving an instruction from the user to align.

The method may also include: selecting a design data file (as shown in step 410). For example, a user of the wafer inspection tool can use the above software to select the wafer inspection The tool can access one of the design data files. The design data file can be stored on the wafer inspection tool or can be accessed from another storage medium (such as a fab database remotely coupled to the inspection tool). The design data file may contain information for one or more layers formed or to be formed on the wafer. In addition, as shown in step 412, the method includes alignment to the design. Aligning to the design may include: aligning the wafer or the output (such as an image) of the wafer with the coordinates of the design. The alignment to the design can be further performed as described in the patent owned by Zafar et al., which is incorporated by reference above.

The method can then continue (as shown in Figure 4b). For example, the method may include: activating the DBB process setting in the wafer post-processing (as shown in step 414). The DBB process setting can be executed by a user via the above-mentioned client software. Step 416 of the method includes determining whether a new dynamic design attribute is needed. This step can be performed by automatically asking the user whether there are any new dynamic design attributes when starting the DBB process setting.

If the user indicates that there is a new dynamic design attribute, the method includes: defining the dynamic design attribute name and description (as shown in step 418). This step can include: prompting the user to enter this information. The method may also include: identifying the process layer(s) for the dynamic design attribute (as shown in step 420), and it may also prompt the user to select or input the process layer(s) implement. In addition, the method includes identifying the layer of logical operations (as shown in step 422), which can be executed by prompting the user to select or input the layer of logical operators. The method further includes defining a formula (as shown in step 424) for the design attribute of the combination layer and operator. This step can be performed automatically by the user or by the wafer inspection tool based on input from the user.

The method may then include: activating a design data viewer (as shown in step 426), which may be executed by the client software after receiving all the relevant information about the new design attribute from the user. The design data viewer can display the relevant part or parts of the design data associated with the new design attribute to the user. For example, the design data viewer can display the information for each of the layer(s) associated with the new design attribute Those who design and edit each. In addition, the design data viewer can display the result of the logic operation at the level generated for the new design attribute.

The method further includes: verifying the attribute result (as shown in step 428). The verification of the attribute result can be performed by prompting the user with an indication of whether the attribute result is satisfactory. The attribute result can be visually verified in the design data viewer on a sample area of the design data. In addition, the method includes: saving the attribute definition (as shown in step 430). When a user selects one of the save options in the client software, the attribute definition can be saved. The method also includes: determining whether more dynamic attributes need to be defined (as shown in step 432). If there are more new dynamic design attributes, the method can return to step 418 and repeat these steps between steps 418 and 432 as needed.

If it is determined or indicated that there is no new dynamic design attribute in step 416, the method includes: defining other parameters for the DBB (as shown in step 434 of FIG. 4b). Other parameters for DBB can be input by the user via the above-mentioned client software. After other parameters for the DBB have been provided in step 434 and/or determined or indicated: there are no more new dynamic design attributes in step 432, the method may then include: saving the detection process (as in step 436 Shown). The detection process can be saved in any suitable way and in any suitable format. The inspection process may be stored in a storage medium provided in the wafer inspection tool and/or may be stored in a storage medium (such as a fab database) located remotely from the wafer inspection tool.

The method then continues (as shown in Figure 4c). For example, after the detection process has been saved, the method includes: running the detection (as shown in step 438), which can be executed in any suitable manner. The method also includes: loading the area for viewing (as shown in step 440). Loading the area for inspection may include: loading the inspection result into the wafer inspection tool or a separate defect inspection tool (such as a scanning electron microscope (SEM)) for one of the inspection type applications. In addition, the method includes: viewing the dynamic attribute result (as shown in step 442). Viewing the dynamic attribute results can include: inspecting without using the physical wafer Depending on the result in the software. However, viewing the dynamic attribute results such as can include: using a defect inspection tool to revisit the locations on the physical wafer included in the dynamic attribute results to further inspect the defects detected at these locations. In either way, the dynamic attribute results can be reviewed to determine whether any new dynamic design attributes produce the desired result.

The method may also include: activating Impact, which is a defect classification software available from KLA-Tencor (as shown in step 444). Any other suitable defect classifier software can be activated in step 444 to replace Impact. The defect classifier can be activated by the defect inspection tool or the wafer inspection tool. As shown in step 446, the method includes using the dynamic properties to define and tune the classifier. Defining and tuning the classifier may include: changing any one or more parameters of the classifier used in the wafer inspection process. For example, defining and tuning the classifier may include: defining and tuning a decision tree used in the classifier. The method also includes: saving the classifier (as shown in step 448). The classifier can be stored in any suitable way and in any suitable format. The classifier can also be stored in any of the storage media described herein (such as included in the wafer inspection tool or one of the storage media in a fab database).

The method may further include: linking the classifier to the wafer inspection process (as shown in step 450). This step can be performed in any suitable way. For example, a link to the classifier may be included in the wafer inspection process stored in step 436. The method also includes verifying the results (as shown in step 452), which can be performed in any suitable way. In addition, the method includes the final decision on the production process (as shown in step 454), which can also be executed in any suitable manner.

Each of the embodiments of the methods described above can include any other steps of any of the other methods described herein. In addition, each of the embodiments of the methods described above can be executed by any of the systems described herein.

All of the methods described herein may include: storing the results of one or more steps of the method embodiments in a non-transitory computer-readable storage medium. These results Any of the results described herein can be included and can be stored in any way known in the art. The storage medium may include any storage medium described herein or any other suitable storage medium known in the art. After the results are stored, the results can be accessed in the storage medium and used by any of the methods or system embodiments described herein, formatted for display to a user , Used by another software module, method or system, etc. For example, after the method detects the defects, the method may include: storing information about the detected defects in a storage medium.

An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a computer system of a wafer inspection tool for executing a computer-implemented method for wafer inspection. An example of this is shown in FIG. 5. In particular, as shown in FIG. 5, the non-transitory computer-readable medium 500 includes program instructions 502 executable on the computer system 504. The computer-implemented method includes the steps of the above-mentioned method. The computer-implemented method that can execute the program instructions can include any of the other steps described herein.

The program instructions 502 for implementing methods (such as those described herein) can be stored on the computer-readable medium 500. The computer-readable medium can be a storage medium, such as a magnetic or optical disk, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.

These program instructions can be implemented in any of a variety of ways (including program-based technology, component-based technology, and/or object-oriented technology, among others). For example, ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Class Library ("MFC"), or other technologies or methods can be used to implement these program instructions as needed.

The computer system can take various forms, including a personal computer system, a video computer, a host computer system, a workstation, a network tool, an Internet tool, or other devices. Generally speaking, the term "computer system" can be broadly defined to cover any device with one or more processors that executes instructions from a memory medium. The computer system may also include any suitable processor known in the art, such as a parallel processor. In addition, the computer system may include a computer platform with high-speed processing and software, such as an independent or a network interconnection tool.

Another embodiment relates to a wafer inspection tool. An example of this tool is shown in FIG. 6. The wafer inspection tool includes an optical subsystem configured to scan at least a portion of a wafer, thereby generating output in response to light from the at least a portion of the wafer. For example, as shown in FIG. 6, the wafer inspection tool includes an optical subsystem 600.

As shown in FIG. 6, the optical subsystem includes a light source 604. The light source 604 may include any suitable light source known in the art, such as a broadband plasma light source. In this way, the detection system can be configured as a broadband plasma detection system. The light source 604 is configured to direct light to the beam splitter 606, which is configured to reflect the light from the light source 604 to the refractive optical element 608. The refractive optical element 608 is configured to focus the light from the beam splitter 606 to the wafer 610. The beam splitter 606 may comprise any suitable beam splitter, such as a 50/50 beam splitter. The refractive optical element 608 may include any suitable refractive optical element, and although the refractive optical element 608 is shown as a single refractive optical element in FIG. 6, it may be one or more refractive optical elements and/or one or more reflective optical elements To replace.

The light source 604, the beam splitter 606, and the refractive optical element 608 can thus form an illumination channel for the optical subsystem. The illumination channel may include any other suitable elements (not shown in Figure 6), such as one or more polarizing components and one or more filters (such as spectral filters). As shown in Figure 6, the light source, beam splitter, and refractive optical element are configured so that the light is guided to the wafer along a normal or substantially normal incident angle. However, the light can be directed to the wafer along any other suitable angle of incidence.

The optical subsystem can be configured to scan the light on the wafer in any suitable manner.

The light reflected from the wafer 610 due to the illumination can be collected by the refractive optical element 608 and guided through the beam splitter 606 to the detector 612. Therefore, the refractive optical element, beam splitter and detector can form a detection channel of the optical subsystem. The detector can include Any suitable image detector known in the art, such as a charge coupled device (CCD). The detection channel may also include one or more additional components (not shown in FIG. 6), such as one or more polarizing components, one or more spatial filters, one or more spectral filters, and the like. The detector 612 is configured to generate an output in response to the reflected light detected by the detector. The output can include signal, signal data, image, image data and any other suitable output.

As described above, the detector included in the optical subsystem can be configured to detect light reflected from the wafer. Therefore, the detection channel included in the optical subsystem can be configured as a bright field (BF) channel. However, the optical subsystem may include one or more detection channels (not shown) that can be used to detect light scattered from the wafer due to the illumination of the wafer. In addition, one or more parameters of the detection channel shown in FIG. 6 can be changed so that the detection channel can detect light scattered from the wafer. In this way, the optical subsystem can be configured as a dark field (DF) tool and/or a BF tool.

The wafer inspection tool also includes a computer subsystem coupled to the optical subsystem. For example, the computer subsystem can be coupled to a detector of the optical subsystem. In one example, as shown in FIG. 6, the computer system 614 is coupled to the detector 612 of the optical subsystem 600 (for example, one or more transmission media is shown by the dashed line in FIG. 6, which may include this technology Any suitable transmission media known in ). The computer system can be coupled to the detector in any suitable way. The computer system can be coupled to the optical subsystem in any other suitable manner, so that the image and any other information for the wafer generated by the optical subsystem can be selectively sent to the computer system, and the computer system can send Commands to the optical subsystem also perform one or more steps described herein.

The computer system 614 is configured for: during the operation of a wafer inspection process, prompting information for a DBB process to a user on which a wafer inspection tool of the wafer inspection process is executed. The information includes one or more formulas used to calculate the design attributes from the wafer design. These design attributes can be used to classify the deficiencies in the DBB program trap. The computer system is also configured to receive information from the user. In addition, the computer system is configured to update the wafer inspection process based on the received information. The computer system is further configured to detect defects on the wafer based on the output and classify the defects detected on the wafer according to the DBB program in the updated wafer inspection process. Each of these steps can be performed as described further herein. In addition, the computer system can be configured to perform any other steps described herein. The wafer inspection tool shown in Figure 6 can be further configured as described herein.

It should be noted that FIG. 6 is provided herein to generally illustrate a configuration of an optical subsystem that can be included in the wafer inspection tool embodiments described herein. Obviously, the configuration of the optical subsystem described in this article can be changed to optimize the performance of the tool, as it normally performs when designing a commercial inspection tool. In addition, an existing optical subsystem can be used (for example, by adding the functions described in this article to an existing inspection tool) (such as 28XX, 29XX, and Puma, which are commercially available tools from KLA-Tencor, Milpitas, and Calif). 9XXX series) to implement the wafer inspection tools described in this article. For some of these tools, the methods described herein can be used as a selection function of the tool (for example, in addition to other functions of the tool). Alternatively, the wafer inspection tools described herein can be designed to "self-scratch" to provide a completely new tool.

Those skilled in the art will understand further modifications and alternative embodiments of various aspects of the present invention based on this description. For example, the present invention provides a method and system for dynamically designing attributes for wafer inspection. Correspondingly, this description is interpreted as having only illustrative meaning and is intended to teach those skilled in the art the general way to implement the present invention. It should be understood that the forms of the present invention shown and described herein will be regarded as the presently preferred embodiments. Those skilled in the art will understand after having the advantages of this description of the present invention: elements and materials can be replaced by the elements and materials depicted and described herein, parts and procedures can be reversed, and certain features of the present invention can be changed Use independently. Changes can be made to the elements described herein (as described in the scope of the patent application below) without departing from the spirit and scope of the present invention.