Body-contacted partially depleted silicon on insulator transistor
Abstract
Embodiments include an apparatus, system, and method related to a body-contacted partially depleted silicon on insulator (PDSOI) transistor that may be used in a switch circuit. In some embodiments, the switch circuit may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed.

Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
20 claims: 20 independent, 0 dependent
- 1一種開關電路,包括:具有閘極、源極、汲極和本體接觸之一開關電晶體;第一和第二電阻,其彼此串聯耦合,並進一步與該源極接觸和該汲極接觸耦合並介於兩者之間;以及一放電電晶體,其具有與該開關電晶體之該本體接觸耦合之一第一接觸,與該開關電晶體之該閘極接觸耦合之一第二接觸,和與該第一和該第二電阻耦合之一閘極接觸。
- 2如申請專利範圍第1項之開關電路,其中該閘極接觸與介於該第一和第二電阻間之一第一節點耦合。
- 3如申請專利範圍第1項之開關電路,其中該第一節點是一虛擬接地。
- 4如申請專利範圍第1項之開關電路,其中該電路是一絕緣層上覆矽(SOI)裝置。
- 5如申請專利範圍第4項之開關電路,其中該絕緣層上覆矽(SOI)裝置包括一部分空乏絕緣層上覆矽(SOI)裝置。
- 6如申請專利範圍第1項之開關電路,其中該電路是一n-通道金屬氧化物半導體(NMOS)場效應電晶體開關,其被配置為傳送一負直流電壓。
- 7如申請專利範圍第1項之開關電路,其中該電路是一p-通道金屬氧化物半導體(PMOS)場效應電晶體開關,其被配置為傳送一正直流電壓。
- 8如申請專利範圍第1項之開關電路,其中該第一電阻和該第二電阻是相同大小的。
- 9如申請專利範圍第1項之開關電路,其中該放電電晶體之該第一接觸係該放電電晶體之一源極接觸,以及該放電電晶體之該第二接觸係該放電電晶體之一汲極接觸。
- 10如申請專利範圍第1項之開關電路,其中該電路包括一共閘極放大器。
- 11一種部分空乏絕緣層上覆矽(PDSOI)裝置,包括:一第一電晶體,其被配置為在開啟時,讓一信號通過,而在關閉時,防止該信號通過;一節點,其被配置為提供一虛擬接地;以及一第二電晶體,其具有與該節點耦合之一第一接觸,和與該第一電晶體本體耦合之一第二接觸,當該第一電晶體於關閉時,將提供一放電通路至該本體。
- 12如申請專利範圍第11項之部分空乏絕緣層上覆矽(PDSOI)裝置,其中該第一接觸係一閘極接觸,以及該第二接觸係一源極接觸。
- 13如申請專利範圍第11項之部分空乏絕緣層上覆矽(PDSOI)裝置,更進一步包括:一第一電阻與一第二電阻彼此串聯耦合,其中該節點設置於該第一與第二電阻之間。
- 14如申請專利範圍第11項之部分空乏絕緣層上覆矽(PDSOI)裝置,其中該第一電晶體包括與該第一電阻耦合之一源極接觸和與該第二電阻耦合之一汲極接觸。
- 15如申請專利範圍第11項之部分空乏絕緣層上覆矽(PDSOI)裝置,其中當該第一電晶體開啟時,該第二電電晶體將被設置為關閉。
- 16如申請專利範圍第15項之部分空乏絕緣層上覆矽(PDSOI)裝置,其中當該第一電晶體關閉時,該第二電電晶體進一步被設置為開啟。
- 17一種收發器系統,包括:一收發器,其被配置為提供一信號;一功率放大模組,其被配置為接收由該收發器送出之該信號,並放大該信號以用於傳輸;以及一開關電路,其設置於該收發器或該功率放大器模組,該開關電路包含一部分空乏絕緣層上覆矽(PDSOI)裝置,其具有:一開關電晶體,其被配置為開關該信號;一對電阻,其被配置於提供一虛擬接地於一第一節點;以及一放電電晶體,其與該開關電晶體和該第一節點耦合,並被配置為提供一放電通路,以在該開關電晶體的一本體中將電荷放電。
- 18如申請專利範圍第17項之收發器系統,其中當該開關電晶體關閉時,該放電電晶體被配置為提供該放電通路。
- 19如申請專利範圍第17項之收發器系統,其中該信號以32dBM或更大之一功率被傳輸,而且具有1800百萬赫茲或更高之一頻率。
- 20如申請專利範圍第17項之收發器系統,其中該信號以34dBM或更大之一功率被傳輸,並且具有在800一915百萬赫茲之一頻率。
Independent claims20
42 paragraphs, as filed
The body contact part is covered with silicon transistor on the depleted insulating layer
Body-Contacted Partially Depleted Silicon on Insulator Transistor
The embodiments of the present disclosure generally relate to the field of circuits, and particularly relate to silicon transistors on the depleted insulating layer of the body contact portion.
For low-power radio frequency (RF) switching devices, PDSOI transistors are the best choice, especially in mobile phone applications where price, performance and power consumption are the main key elements. However, PDSOI transistors face challenges when processing larger signals. Especially the large signal performance in the PDSOI switch will be affected by the charge accumulation in the quasi-neutral region of the PDSOI transistor body. The accumulation of charge may lead to accumulation of hot carriers, excessive gate induced leakage current (GIDL), negative transconductance, loss of gate control, hysteresis, etc. These problems can be widely referred to as the floating body effect (FBE).
In an n-channel metal oxide semiconductor field effect transistor (NMOS) device, the most common way to suppress the accumulation of hot carriers related to FBE is to establish a discharge path for the accumulated charge. When the body remains floating, a negative DC voltage is applied to the gate of the NMOS to turn it off. Therefore, in order to discharge the accumulated charge and turn off the parasitic bipolar junction transistor (BJT) formed across the NMOS, the negative DC voltage needs to be transmitted to the body.
Some techniques to perform this task have been developed. These technologies include connecting the body to using diodes or connecting into diode-connected FETs. The gate, or even a negative DC voltage that uses a large resistance (referred to as "resistive body contact") and is equal to the gate voltage is applied. Although these technologies may be able to discharge the thermal charges, turn off the parasitic BJT, and help suppress the harmonics generated by turning off the field effect transistors; but they may also adversely affect the operation of the device and in other aspects. .
For example, the field effect transistor connected in the form of a diode may transmit the applied negative DC voltage plus a DC threshold voltage Vth to the gate, Vth corresponding to the threshold voltage of the device. This may impair the efficiency of the charge discharge mechanism.
For another example, the body contact impedance can apply an appropriate negative DC voltage to the body of the device; however, the resistance may be related to additional insertion loss, and performance degradation relative to intermodulation distortion (IMD) and the second harmonic. All related.
According to one aspect of the present invention, a circuit includes: a switching transistor having a gate, a source, a drain, and a body contact; first and second resistors, which are coupled in series with each other, and are further in contact with the source The drain is contact-coupled and interposed between the two; and a discharge transistor having a first contact coupled in contact with the body of the switching transistor, and a second contact coupled with the gate of the switching transistor The contact is in contact with a gate electrode coupled with the first and the second resistance.
According to another aspect of the present invention, a part of a silicon-on-depleted insulating layer (PDSOI) device includes: a first transistor configured to allow a signal to pass when it is turned on, and to prevent the signal from passing when it is turned off A node, which is configured to provide a virtual ground; and a second transistor, which has a first contact coupled with the node and a second contact coupled with the body of the first transistor, when the first electrical When the crystal is closed, it will provide a discharge path to the body.
According to another aspect of the present invention, a system includes: a system configured to provide a letter No. transceiver; a power amplifier module configured to receive the signal sent by the transceiver, and amplify the signal for transmission; and a switch circuit, which is provided in the transceiver or the power amplifier module , The switching circuit includes a part of a silicon-on-depleted insulating layer (PDSOI) device, which has: a switching transistor configured to switch the signal; a pair of resistors configured to provide a virtual ground to a first node; And a discharge transistor, which is coupled with the switching transistor and the first node, and is configured to provide a discharge path to discharge electric charges in a body of the switching transistor.
<p>100Switching circuit</p><p>104Switching Transistor</p><p>108Gate contact</p><p>112Source contact</p><p>116Dip pole contact</p><p>120Body contact</p><p>124Resistor</p><p>128Resistor</p><p>130Resistor</p><p>132Discharge Transistor</p><p>136Gate contact</p><p>140Source contact</p><p>144Dip pole contact</p><p>148node</p><p>200Switch operation</p><p>204Block Diagram</p><p>208Block Diagram</p><p>300Sample system</p><p>302Power Amplifier (PA) Module</p><p>304Transceiver</p><p>306Antenna Switch Module (ASM)</p><p>308antenna structure</p>
The embodiments are described by way of example, and should not be limited to the illustrations in the drawings, wherein the same symbols represent similar components, and among them: FIG. 1 illustrates a switch circuit according to various embodiments.
Figure 2 illustrates a flow chart of a switch operation according to one of the various embodiments.
Fig. 3 is a block diagram of an exemplary wireless communication device according to one of various embodiments.
The various viewpoints of these illustrative embodiments will be described in terms commonly used by those who are familiar with the technology, which are used to express the essence of their work to others who are familiar with the technology. However, for those who are familiar with the technology, it will be obvious that alternative embodiments using only some of the described viewpoints can also be implemented. For the purpose of explanation, the specific devices and configurations are proposed to provide a thorough understanding of the illustrative embodiments. However, for those familiar with the technology, it will be obvious that alternative embodiments without specific details can also be implemented. In other embodiments, well-known features are omitted or simplified to avoid obscuring the embodiments.
In addition, various operations will be described as multiple discrete operations, in other words, The most helpful way to understand the present invention; however, the order of description should not be interpreted as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the order of description.
The phrase "in an embodiment" is used repeatedly. The phrase generally does not refer to the same embodiment; however, it may be. The terms "including", "having" and "including" are synonymous, unless the context dictates otherwise
Provide some words to clarify the context, which can be used in various related embodiments. The phrases "A/B" and "A and/or B" refer to (A), (B) or (A and B); the phrase "A" , B and/or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).
The term "coupled with" and its derivative terms can be used here. "Coupled" can mean one or more following it. "Coupled" can mean that two or more elements are in direct physical or electrical contact. "Coupled" can also mean that two or more elements are indirectly in contact with each other, but still cooperate or interact with each other, and it can also mean that one or more other elements are coupled or connected between these elements, which is called To be coupled to each other.
Figure 1 illustrates a switching circuit 100 according to one of various embodiments. The switch circuit 100 can be a silicon-on-insulator (SOI) device, which has a silicon layer disposed on an insulating layer, and can also be referred to as a buried oxide (BOX) layer. In some embodiments, an additional silicon layer may be provided under the insulating layer.
In various embodiments, the top silicon layer may have a thickness of about 50-90 nanometers (nm), and the insulating layer may be a silicon dioxide or a sapphire layer, which may be about 100 to Thickness of 200 nanometers (nm). In some embodiments, the switch circuit 100 may be a partial depleted SOI (PDSOI) device, in which the silicon is located under a doped channel, It can be a partial depletion of mobile charge carriers. This part of the depleted area can be referred to as a quasi-neutral area.
The switching circuit 100 may include a switching transistor 104. In an embodiment, the switching circuit 100 is a PDSOI, and the switching transistor 104 may have a tendency to accumulate charge in a quasi-neutral region. The embodiment described here provides the discharge of the accumulated charges while at least alleviating some of the above-mentioned problems, which is related to the design of other technologies to solve the FBE problem.
The switching transistor 104 may include a gate contact 108, a source contact 112, a drain contact 116 and a body contact 120. The switching circuit 100 may further include resistors 124 and 128 connected in series with each other, and as shown in the figure, they are coupled to the source contact 112 and the drain contact 116 and are interposed therebetween. In some embodiments, the resistors 124 and 128 may be the same size. The switching circuit 100 may further include a resistor 130 coupled with the gate contact 108.
Although the switching transistor 104 shown in FIG. 1 is usually an NMOS, in other embodiments, the switching transistor 104 may also be a PMOS.
The switch circuit 100 may further include a discharge transistor 132. The discharge transistor 132 can generate a discharge path to discharge the charge accumulated in the quasi-neutral region of the switching transistor 104. The discharge transistor 132 may include a gate contact 136, a source contact 140, and a drain contact 144. The gate contact 136 is coupled with a node 148 between the resistors 124 and 128; the source contact 140 can be coupled with the body contact 120; the drain contact 144 can be coupled with the gate contact 108.
The resistors 124 and 128 can provide a virtual ground, for example, at the node 148 is in contact with the gate electrode 136 at a fixed potential. Use the discharge transistor 132 to connect the body contact 120, the drain contact 116 and the source contact 112 to the fixed potential of the node 148, which facilitates the removal of the gap between the gate contact 108 and the body contact 120 The potential difference of, therefore discharges the charge from the quasi-neutral region.
Figure 2 shows a flowchart of a switching operation 200 according to one of various embodiments. According to some embodiments, the switching operation 200 can be implemented by a switching circuit, such as the switching circuit 100.
In block 204, the switching operation 200 may include turning on the switching circuit. In some embodiments, the switching circuit can be turned on by turning on a switching transistor, such as the switching transistor 104, to transmit a signal, such as a radio frequency (RF) signal, between the source and drain contacts .
In some embodiments, the switching transistor can be turned on by applying a positive DC voltage, for example, 2.5 volts (V), to the gate contact of the switching transistor. The drain contact of the discharge transistor, for example, the drain contact 144, will also see the positive DC voltage. The gate contact of the discharge transistor, for example, the gate contact 136, can see a 0 volt at the virtual ground. This can cause the gate-source voltage of the discharge transistor, V_gs, to be -2.5V, and the discharge transistor is turned off, and, in fact, the discharge transistor is removed from the switching circuit.
In block diagram 208, the switching operation 200 may include closing the switching circuit and providing a discharge path between the gate and the substrate of the switching transistor. In some embodiments, the switching circuit can be turned off by turning off the switching transistor to prevent the passage of a signal, for example, the RF signal. In some embodiments, the switching transistor can be turned off by applying a negative DC voltage, for example, -2.5V, to the gate contact of the switching transistor. The discharge When the drain of the transistor is in contact, the negative DC voltage will also be seen. This will cause the V_gs of the discharge transistor to be 2.5V. This will turn on the discharge transistor 132, by coupling the gate body contact of the switching transistor to the body contact of the switching transistor, thereby creating a discharge path. This can be done without providing voltage space, and there is no Vth voltage drop.
When the switching operation 200 using an NMOS transistor as the switching transistor (also referred to as "NMOS switch") is widely discussed, the switching operation can also be performed by using a PMOS transistor as the switching circuit (also referred to as "PMOS switch"). ) Example implementation. In various embodiments, in a switching circuit that transmits a negative DC voltage to the body of the switching circuit transistor, the NMOS transistor can be used as the discharge transistor, and a PMOS transistor can be used for transmission A positive DC voltage is applied to a switching circuit of the body of the switching transistor.
The use of the switch circuit 100 as described above to provide a discharge path does not suffer the same damage related to the voltage critical space, which is related to a FET switch circuit connected in the form of a diode. The example simulation has shown that, compared to a FET switch circuit connected in the form of a diode, the switch circuit 100 has a 3 dB improvement relative to IMD, a 2.5 dB improvement relative to the third harmonic, and a 2.5 dB improvement relative to the second harmonic. 1.5 dB improvement.
The use of the switch circuit 100 as described above to provide a discharge path does not suffer the same damage related to the insertion loss, which is related to a body contact (BC) impedance switch circuit. The example simulation has shown that, relative to a BC impedance switch circuit, the switch circuit 100 has an improvement of 40 millibels (dBM) or more relative to the insertion loss, 1 dB relative to the IMD, and 3.5 relative to the second harmonic. dB improvement, and 0.5 dB improvement relative to the third-order harmonic.
The switch circuit 100 can be a common gate amplifier, and can be combined with many applications, including but not limited to, complementary metal oxide semiconductor (CMOS) switches, power amplifiers Amplifiers, low-noise amplifiers (LNAs), buffers, duplexers, etc.
The switch circuit 100 can be combined with various systems. A block diagram of an example system 300 is illustrated in FIG. 3. As shown in the figure, the system 300 includes a power amplifier (PA) module 302, which may be a radio frequency (RF) power amplifier module in some embodiments. The system 300 as illustrated in the figure may include a transceiver 304 coupled to the PA module 302. The PA module 302 may include any of the various operations performed by the switch circuit 100, such as amplification, switching, and mixing. In various embodiments, a switch circuit (for example: switch circuit 100) may be additionally/alternatively included in the transceiver 304 and provided, for example: up conversion, or an antenna switch module (ASM) 306 It provides various switch functions.
The PA module 302 can receive an RF input signal, RFin, which is transmitted by the transceiver 304. The PA module 302 can amplify the RF input signal, RFin, and provide the RF output signal, RFout. The RF input signal, RFin, and the RF output signal, RFout, both may be part of a transmission chain, as illustrated by Tx-RFin and Tx-RFout in FIG. 3 respectively.
The amplified RF output signal, RFout, can be provided to the ASM 306, which performs an over-the-air (OTA) transmission via the antenna structure 308. The ASM 306 can also receive RF signals via the antenna structure 308, and couple the received RF signal, Rx, to the transceiver 304 along a receiving chain.
In various embodiments, the antenna structure 308 may include one or more directional and/or omnidirectional antennas, including, for example, a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, and a microstrip antenna. Antenna or any other type of antenna suitable for OTA RF signal transmission/reception.
The system 300 can be any system that includes power amplification. In various embodiments When the system 300 is used for high RF power and frequency power amplification, it may be particularly useful to use the switching circuit 100 included in the system 300 to switch the RF signal. For example, if the switching circuit 100 is included in the system 300, for a Global System for Mobile Communications (GSM) signal with a power of about 32 dBm or more and a frequency of about 1800 megahertz (MHz) or higher , And lower-band GSM signals, for example, 800MHz-915MHz, and have a power of about 34 dBM or higher transmission may be particularly helpful.
The system 300 can be applied to any one or more of terrestrial and satellite communications, radar systems, and various industrial and medical applications. More specifically, in various embodiments, the system 300 may be a radar device, a satellite communication device, a mobile computing device (for example, a phone, a tablet computer, a laptop computer, etc.), a base station, A radio broadcast, or a TV amplifier system, the chosen one.
Although the present invention has been described in accordance with the above illustrative embodiment, those skilled in the art should understand that there are numerous alternative and/or equivalent schemes used to achieve the same purpose without departing from the scope of the present invention. The painting implementation can replace the specific embodiments shown and described. Those familiar with the technology can easily understand that the teaching of the present invention can be implemented in numerous embodiments. This description is intended to be regarded as illustrative and not restrictive.
3 sheets
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Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| WO0227920A1 | Cites | World Intellectual Property Organization (WIPO) | Examiner |
| EP0385641A2 | Cites | European Patent Office (EPO) | Examiner |
| EP1006584A2 | Cites | European Patent Office (EPO) | Examiner |
| CN1256521A | Cites | China | Examiner |
| WO2007008934A1 | Cites | World Intellectual Property Organization (WIPO) | Examiner |
| WO2007035610A2 | Cites | World Intellectual Property Organization (WIPO) | Examiner |
| WO9523460A1 | Cites | World Intellectual Property Organization (WIPO) | Examiner |
| WO0227920A1 | Cites | World Intellectual Property Organization (WIPO) | – |
| WO9523460A1 | Cites | World Intellectual Property Organization (WIPO) | – |
| WO2007008934A1 | Cites | World Intellectual Property Organization (WIPO) | – |
| WO2007035610A2 | Cites | World Intellectual Property Organization (WIPO) | – |
7 members in 4 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 13535203 | United States of America | – | |
| 201213535203 | United States of America | A | |
| 201213535203 | United States of America | A | |
| 13535203 | – | – | – |
| US201213535203 | – | – | – |
Members7
| Document | Office | Kind | |
|---|---|---|---|
| US2014002171A1 | United States of America | A1 | |
| KR20140001145A | Republic of Korea | A | |
| CN103516342A | China | A | |
| TW201409955A | Taiwan Province of China | A | |
| US8829967B2 | United States of America | B2 | |
| TWI595751BThis record | Taiwan Province of China | B | |
| CN103516342B | China | B |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Annulment or lapse of patent due to non-payment of feesLapsedMM4A | MM4A |
Numbers
- Publication
- I595751
- Publication, DOCDB
- I595751
- Publication, EPODOC
- TWI595751B
- Application
- 102122337
- Application, DOCDB
- 102122337
- Application, EPODOC
- TW20130122337
Titles2
- English
- BODY-CONTACTED PARTIALLY DEPLETED SILICON ON INSULATOR TRANSISTOR
- Chinese
- 本體接觸部分空乏絕緣層上覆矽電晶體
Classification
- CPC, 4
- H03K17/687
- H03K2017/6875
- H03K2217/0018
- H10D30/63
- IPC, 1
- H04B1 40