Analog to digital converter with dual integrating capacitor systems

Analog-to-digital converter with double integrating capacitor system

ANALOG TO DIGITAL CONVERTER WITH DUAL INTEGRATING CAPACITOR SYSTEMS

The present invention generally relates to analog-to-digital converters.

An analog-to-digital converter (ADC) is a device that converts a continuous quantity into a discrete time digital representation. For example, an ADC can be an electronic device that converts an input analog voltage or current into a digital value proportional to the magnitude of the voltage or current. Generally, an input voltage can be stored on one or more sampling capacitors of the ADC before it is converted into a digital number. An ADC can use any suitable coding scheme for its output, such as a two's complement binary number or a Gray code.

FIG. 1 illustrates an example of a system 100 including a capacitive touch sensor 105 coupled to a control unit 150. The capacitive touch sensor 105 of the system 100 may include a screen including an insulator coated with a transparent conductor in a specific pattern. When a finger or other object touches the surface of the screen, one of the capacitances changes. A signal indicating this change in capacitance can be sent to the control unit 150 for processing to determine the position of the touch. In various embodiments, the system 100 is operable to handle the measurement of any suitable type of capacitance (such as surface capacitance, projected capacitance, mutual capacitance, and self capacitance or absolute capacitance).

As shown, the capacitive touch sensor 105 includes a sensing area 105A. The driving electrode 103(x) and the sensing electrode 103(y) may be formed in the sensing area 105A on one or more substrates. As shown, the driving electrode 103(x) is in a horizontal direction It continues upward, and the sensing electrode 103 (y) continues in a vertical direction. However, the sensing and driving electrodes can have any suitable shape and configuration. The capacitive sensing channel 104 can be formed in the sensing area where the edges of the driving electrode 103 (x) and the sensing electrode 103 (y) are adjacent to each other. In some embodiments, the driving electrode 103 (x) and the sensing electrode 103 (y) are configured to be electrically isolated from each other. For example, the driving electrode 103(x) and the sensing electrode 103(y) of the capacitive touch sensor 105 can be arranged on the opposite surface of an insulating substrate so that the substrate provides a gap between the driving electrode and the sensing electrode. Electrical isolation.

The control unit 150 of the system 100 can communicate with the capacitive touch sensor 105. As shown, the control unit 150 includes a driving unit 110, a sensing unit 120, a storage device 130, and a processor unit 140. The storage device 130 may store in a computer-readable storage medium for programming executed by the processor unit 140 and data used in the operation of the processor unit 140 or generated by the operation of the processor unit 140. In some embodiments, the control unit 150 is an integrated circuit chip, such as a general-purpose microprocessor, a microcontroller, a programmable logic device/array, an application-specific integrated circuit (ASIC) or its A combination. In other embodiments, the driving unit 110, the sensing unit 120, and/or the processor unit 140 may be provided in a separate control unit.

The processor unit 140 controls the driving unit 110 to supply a driving signal (such as an electric pulse) to the driving electrode 103 (x) so as to induce charges on the sensing electrode 103 (y) intersecting the driving electrode 103 (x). The sensing unit 120 senses the charge at each intersection 104 via the sensing electrode 103 (y), and the sensing unit 120 provides a measurement signal representing the node capacitance to the processor unit 140. At the place In the illustrated embodiment, the sensing unit 120 includes one or more analog-to-digital converters (ADC) 180 operable to convert a signal representing the node capacitance into a digital value sent to the processor unit 140.

In the illustrated embodiment, the driving electrode 103(x) is connected to the driving unit 110 through one or more first switching elements 170, and the sensing electrode 103(y) is connected through one or more second switching elements 160 To the sensing unit 120. The switching elements 160 and 170 are controlled by the processor unit 140. In a specific embodiment, the processor unit 140 controls the switching elements 160 and 170 and the driving unit 110 and the sensing unit 120 to perform sensing at all intersection points 104 on the sensing area 105A and provide a full sensing resolution. Each driving electrode 103(x) can be driven, and a signal from each sensing electrode 103(y) can be sensed. In a different embodiment, the processor unit 140 controls the switching elements 160 and 170 and the driving unit 110 and the sensing unit 120 to drive and sense through a smaller number of channels. Selected subsets of drive electrodes and sense electrodes can be used. In this example, the driving signal is applied to the group of driving electrodes 103(x) forming a smaller number of driving channels, and the group of sensing electrodes 103(y) forming a smaller number of sensing channels is sensed. Test signal.

In a specific embodiment, the processor unit 140 can process the data received from the sensing unit 120 and determine the existence and location of a touch on the capacitive touch sensor 105. In a specific embodiment, the presence and position of a touch on the capacitive touch sensor 105 can be detected by detecting the capacitance of one or more capacitive sensing channels 104 of the capacitive touch sensor. One change to determine. In some embodiments, the capacitance of one or more capacitive sensing channels 104 can be sampled periodically to determine whether the capacitance of the channels has changed. Change. In some embodiments, the capacitance of one or more capacitive sensing channels 104 is sampled by ADC 180.

In a typical ADC system, one or more sampling capacitors of the ADC are operable to receive charge from one or more integrating capacitors coupled to the ADC. The one or more integrating capacitors measure the value by storing a charge corresponding to a value in a time period. After the end of the time period, the charge on the integrating capacitors is transferred to one or more sampling capacitors of the ADC. Then, the charge in the sampling capacitor of the ADC is converted into a digital value. In some systems, the integrating capacitor can measure a new value while the ADC is converting the charge stored on the sampling capacitors. These typical systems have various shortcomings, including: the added area for the individual integrating capacitor and the sampling capacitor, the charge redistribution error caused by the charge transfer from the integrating capacitor to the sampling capacitor, and the relatively slow operation. The ADC can transfer the charge from the integrating capacitor to the sampling capacitor before starting the conversion process.

In some embodiments, the ADC 180 includes a first capacitor system and a second capacitor system. The first capacitor system and the second capacitor system each include one or more capacitors. Each capacitor system is detachably coupled to the same part of the ADC 180 and the same sensing circuit. Each capacitor system is configured to store a charge received through the sensing circuit when coupled to the sensing circuit and provide the charge received through the sensing circuit to the ADC 180 when coupled to the portion of the ADC 180 For conversion into a digital value. The ADC 180 may further include a timing circuit configured to generate one or more control signals and a switching circuit configured to receive the one or more control signals. When the one or more control signals are in a first state, The switching circuit couples the first capacitor system to the sensing circuit to receive charge through the sensing circuit and at the same time couples the second capacitor system to the portion of the ADC 180. When the one or more control signals are in a second state, the switching circuit couples the second capacitor system to the sensing circuit to receive charge through the sensing circuit and at the same time couples the first capacitor system to the ADC 180 part.

FIG. 2A illustrates an exemplary embodiment of the ADC 180. 2B to 2C illustrate exemplary operating states of the ADC 180. FIG. 3 illustrates an example method for alternating between the capacitor systems of the ADC 180, and FIG. 4 illustrates an additional example embodiment of the ADC 180.

FIG. 2A illustrates an exemplary system 200 which is an exemplary embodiment of the ADC 180. As shown in FIG. The system 200 includes an ADC having a double integrating capacitor system 206 and 208. In some embodiments, all or part of the system 200 may reside in a capacitive touch sensor control unit (such as the control unit 150 of FIG. 1). In certain embodiments, at least a part of the system 200 resides in a sensing unit of a capacitive touch sensor control unit (such as the sensing unit 120 of the control unit 150). In a particular embodiment, the ADC of the system 200 is configured to receive a signal indicating a capacitance of a capacitive sensing channel 104 of a capacitive touch sensor 105 and convert the signal into a digital value.

The system 200 includes: a sensing circuit 202, a timing circuit 204, two capacitor systems 206 and 208, a series of switches 210 to 213, a comparator 214, ADC logic 222 and a digital-to-analog converter (DAC) 224 . The two capacitor systems 206 and 208 are each operable to act as an integrating capacitor and sampling Capacitor. In some embodiments, the capacitor system 206 can act as a sampling capacitor when the capacitor 208 acts as an integrating capacitor and as an integrating capacitor when the capacitor 208 acts as a sampling capacitor. Therefore, the ADC of the system 200 includes a double integrating capacitor that also serves as the sampling capacitor of the ADC. Therefore, certain embodiments of the present invention can avoid the various disadvantages associated with separate integrating capacitors and sampling capacitors.

The sensing circuit 202 may include any suitable circuit for transmitting a signal to the capacitor systems 206 and 208 via the switches 210 and 212, respectively. For example, the sensing circuit 202 may include one or more receiving pads, amplifiers, inverters, transmission lines, or other suitable circuits. In a particular embodiment, the sensing circuit 202 is coupled to a capacitive sensing channel 104 of a capacitive touch sensor 105 and is configured to indicate a region of the capacitive touch sensor 105 (such as, A signal of one of the capacitances of the capacitive sensing channel 104) is transmitted to the capacitor systems 206 and 208.

The capacitor systems 206 and 208 each include one or more capacitors operable to receive and store a signal from the sensing circuit 202. In some embodiments, the capacitor systems 206 and 208 may each include a plurality of capacitors coupled together in parallel. The capacitor systems 206 and 208 are each detachably coupled to the sensing circuit via the switches 210 and 212, respectively. The capacitor systems 206 and 208 are each configured to store a signal received from the sensing circuit 202 and provide the stored signal to a specific part of the ADC for converting the stored signal into a digital value. In some embodiments, a signal from the sensing circuit 202 may include a charge amount. In a specific embodiment, the amount of charge may indicate a capacitance sensed by the sensing circuit 202.

In some embodiments, the capacitor systems 206 and 208 are each detachably coupled to a specific part of the ADC. In the illustrated embodiment, the capacitor systems 206 and 208 are each detachably coupled to the comparator 214, and more specifically to the inverting input of the comparator 214. As shown, switches 211 and 213 are directly connected to comparator 214 and couple capacitor systems 206 and 208 to comparator 214, respectively.

The timing circuit 204 is coupled to the switches 210 to 213 and is configured to generate one or more control signals sent to the switches 210 to 213. For example, the timing circuit 204 may send a signal S which is operable to close the switches 210 and 213 when S is high and to open the switches when S is low. The timing circuit 204 can also send a signal<img file="TWI577136B_D0001.tif" wi="43" he="79" img-format="tif" img-content="character" orientation="portrait" inline="no" />,Signal<img file="TWI577136B_D0002.tif" wi="45" he="76" img-format="tif" img-content="character" orientation="portrait" inline="no" />Can be operated in<img file="TWI577136B_D0003.tif" wi="45" he="74" img-format="tif" img-content="character" orientation="portrait" inline="no" />When it is high, disconnect switches 211 and 212 and<img file="TWI577136B_D0004.tif" wi="43" he="79" img-format="tif" img-content="character" orientation="portrait" inline="no" />When it is low, close the switches. In some embodiments,<img file="TWI577136B_D0005.tif" wi="43" he="79" img-format="tif" img-content="character" orientation="portrait" inline="no" />One of the signal S is an inverted version.

The switches 210 to 213 may collectively constitute a switching circuit operable to receive one or more control signals from the timing circuit 204. Based on the value of the received control signal, the switching circuit can couple the capacitor systems 206 and 208 to the appropriate components of the system 200. When the control signal received by the self-timer circuit 204 is in a first state, the switching circuit can couple the capacitor system 206 to the sensing circuit 202 and at the same time couple the capacitor system 208 to the comparator 214. For example, as shown in FIG. 2B, when the control signal S is high and the control signal<img file="TWI577136B_D0006.tif" wi="43" he="67" img-format="tif" img-content="character" orientation="portrait" inline="no" />When it is low, the capacitor system 206 is coupled to the sensing circuit 202 through the switch 210 and the capacitor system 208 is coupled to the comparator 214 through the switch 213. When the control signal received by the self-timer circuit 204 is in a second state, the switching circuit can couple the capacitor system 208 to the sensing circuit 202 and simultaneously The capacitor system 206 is coupled to the comparator 214. For example, as shown in FIG. 2C, when the control signal S is low and the control signal<img file="TWI577136B_D0007.tif" wi="43" he="69" img-format="tif" img-content="character" orientation="portrait" inline="no" />When high, the capacitor system 208 is coupled to the sensing circuit 202 through the switch 212 and the capacitor system 206 is coupled to the comparator 214 through the switch 211. In some embodiments, the switching circuit may include a plurality of switches that temporarily couple one of the capacitor systems 206 or 208 to the sensing circuit 202 and the other capacitor system to the comparator 214.

Figures 2B to 2C are further explained in conjunction with an exemplary method 300 for alternating between the capacitor systems of the ADC 180. The method starts at step 302. At step 304, a first capacitor system is coupled to a sensing circuit and a second capacitor system is decoupled from the sensing circuit. For example, in FIG. 2B, the capacitor system 206 is coupled to the sensing circuit 202 by the closed switch 210, and the capacitor system 208 is decoupled from the sensing circuit by the open switch 212. At step 306, the second capacitor system is coupled to a portion of an ADC, and the first capacitor system is decoupled from the portion of the ADC. For example, the capacitor system 208 is coupled to the comparator 214 via the closed switch 213, and the capacitor system 206 is decoupled from the comparator 214 via the open switch 211.

At step 308, charge is transferred between the sensing circuit and the first capacitor system, and at the same time, the charge stored on one of the second capacitor systems is converted into a digital value by the ADC. For example, the charge can be transferred between the sensing circuit 202 and the capacitor system 206, and at the same time, a charge stored in the capacitor system 208 can be converted into a digital value by the ADC of the system 200.

At step 310, a second capacitor system is coupled to a sensing circuit And decouple a first capacitor system from the sensing circuit. For example, in FIG. 2C, the capacitor system 208 is coupled to the sensing circuit 202 by the closed switch 212, and the capacitor system 206 is decoupled from the sensing circuit by the open switch 210. At step 312, the first capacitor system is coupled to a portion of an ADC, and the second capacitor system is decoupled from the portion of the ADC. For example, the capacitor system 206 is coupled to the comparator 214 via the closed switch 211, and the capacitor system 208 is decoupled from the ADC via the open switch 213.

At step 314, the charge is transferred from the sensing circuit to the second capacitor system, and at the same time, the charge stored in one of the first capacitor systems is converted into a digital value by the ADC. For example, charge can be transferred between the sensing circuit 202 and the capacitor system 208, and at the same time, a charge stored in the capacitor system 206 is converted into a digital value by the ADC of the system 200. The method ends at step 316.

During step 308 and step 314, any suitable ADC can convert the charge stored at capacitor systems 206 and 208 into digital values. For example, in FIG. 2, the ADC of the system 200 is shown as a successive approximation ADC. As another example, in FIG. 4, an algorithm ADC is shown.

Referring again to FIG. 2B, the ADC of the system 200 includes a comparator 214, an ADC logic 222, and a DAC 224. The capacitor system 208 is coupled to the comparator 214, and the ADC is operable to convert the amount of charge stored by the capacitor system 208 into a digital value. For example, the amount of charge stored by the capacitor system 208 can generate a voltage drop across the capacitor system 208, which is converted into a digital value. The comparator 214 is operable to receive a voltage from the DAC 224 and compare Compare it with a voltage stored in the capacitor system 208. The comparator output 220 feeds the result of this comparison to the ADC logic 222. The ADC logic 222 is operable to store an n-bit binary value 223 provided to the DAC 224. DAC 224 is based on a reference voltage V_ref 228 and convert the n-bit binary value into an analog voltage. This analog voltage is then provided to the comparator 214 for comparison with a voltage from the capacitor system 208.

In a particular embodiment, in the first iteration of the analog to digital conversion, the ADC logic will first output a binary value 223, where the most significant bit is set to a digit 1 and every other bit is set to a digit 0. Therefore, if the ADC is an 8-bit ADC, the first digit value will be 1000000 (which corresponds to the decimal value 64). DAC 224 receives this value and bases it on V_ref 228 and convert it into an analog voltage. In this case, the analog voltage will be V_refAbout 1/2, because the analog voltage is equal to V_refMultiply the decimal value (64) of the binary value 223 and divide the maximum decimal value (127) of the binary value 223=Vref*64/127. The analog voltage is compared with the voltage stored by the capacitor system 208. If the analog voltage from the DAC 224 is higher than the voltage stored by the capacitor system 208, the most significant bit of the binary value 223 is reset to 0, otherwise it remains set to 1. The most significant bit under the binary value 223 is set to 1, a corresponding analog voltage is generated by the DAC, a comparison is made, and the ADC logic 222 records the result. This process is repeated for each bit of the signal 223 until the result 230 is obtained. The result 230 corresponds to the digital value of the voltage stored in the capacitor system 208. A similar procedure can be executed by the ADC to convert a value stored in the capacitor system 206 into a digital value.

Certain embodiments may provide one or more of the following technical advantages or none Provides any of the following technical advantages. Certain embodiments may provide an analog-to-digital converter with double integrating capacitors. In certain embodiments, each integrating capacitor can also serve as a sampling capacitor of the analog-to-digital converter. Certain embodiments can reduce the area required for sensing voltage and converting the voltage into a digital value. Certain embodiments reduce the charge redistribution error caused by the transfer of charge from the integrating capacitor to the sampling capacitor. Certain embodiments speed up the operation of sampling and conversion or increase the number of samples that can be converted in a given time.

FIG. 4 illustrates an exemplary system 400 which is an exemplary embodiment of the ADC 180. As shown in FIG. The system 400 includes an ADC with a double integrating capacitor system 446 and 448. In some embodiments, all or part of the system 400 may reside in a capacitive touch sensor control unit (such as the control unit 150). In certain embodiments, at least a part of the system 400 resides in a sensing unit of a capacitive touch sensor control unit (such as the sensing unit 120 of the control unit 150). In a particular embodiment, the ADC of the system 400 is configured to receive a signal indicative of a capacitance of a capacitive sensing channel 104 of a capacitive touch sensor 105 and convert the signal into a digital value.

The system 400 includes: a sensing circuit 402, a timing circuit 404, two capacitor systems 446 and 448, switches 410 to 413, 420 to 422, 426 to 429 and 434 to 438, capacitors 423 to 424, and a differential amplifier 440, ADC logic 430 and digital-to-analog converters (DAC) 432, 433(A) and 433(B). The sensing circuit 402 may include any suitable circuit for transmitting a signal to the capacitor systems 446 and 448 via the switches 410 to 413. For example In other words, the sensing circuit 402 may include one or more receiving pads, amplifiers, inverters, transmission lines, or other suitable circuits. In a particular embodiment, the sensing circuit 402 is coupled to a capacitive sensing channel 104 of a capacitive touch sensor 105 and is configured to indicate a region of the capacitive touch sensor 105 (such as, A signal of one of the capacitances of the capacitive sensing channel 104) is transmitted to the capacitor systems 446 and 448. In a specific embodiment, the sensing circuit 402 is operable to transmit a positive (ie, rising) edge of an electrical pulse sent by the control unit 150 to the capacitive sensing channel 104 to sense a signal on the lines 406 and 408 Vin1. The sensing circuit 402 can also be operated to transmit a negative (ie, falling) edge of the electrical pulse sent by the control unit 150 to the capacitive sensing channel 104 on the lines 407 and 409 to sense a signal Vin2. The sensing circuit 402 may include an inverter coupled to the connections 407 and 409 so that the negative edge generates a charge that is transferred to the capacitor system 446 or 448.

In the illustrated embodiment, the capacitor systems 446 and 448 each include two capacitors operable to receive and store one or more signals received from the sensing circuit 402. The capacitor system 446 is detachably coupled to the sensing circuit 402 via the switches 410 and 411, and the capacitor system 448 is detachably coupled to the sensing circuit via the switches 412 and 413. The capacitor systems 446 and 448 are each configured to store one or more signals received from the sensing circuit 402 and provide the one or more stored signals to a specific part of the ADC of the system 400 for converting the stored signals Into a digital value. In some embodiments, a signal from the sensing circuit 402 may include an amount of charge. In a specific embodiment, the amount of charge may indicate a capacitance sensed by the sensing circuit 402.

In some embodiments, the capacitor systems 446 and 448 are each detachably coupled to a specific part of the ADC. In the illustrated embodiment, the capacitor systems 446 and 448 are detachably coupled to the differential amplifier 440, and more specifically, to the inverting input of the differential amplifier 440 via the switches 421 and 422, respectively. The capacitor systems 446 and 448 are also detachably coupled to the output 425 of the differential amplifier 440 via the switches 428 and 429, respectively.

The timing circuit 404 is coupled to the switches 410 to 413, 421 to 422, 428 to 429, and 437 to 438 and is configured to generate one or more control signals sent to these switches. The timing circuit 404 is operable to generate a control signal having at least a first state and a second state. In the first state, the signal from the timing circuit 404 turns on the switches 410 and 411 to couple the capacitor system 446 to the sensing circuit 402 and turns off the switches 412 and 413 so that the second capacitor system 448 is not coupled to the sensing circuit 402. At the same time, the switches 421 and 426 are kept open by the signal from the timing circuit 404 so that the capacitor system 446 is not coupled to the differential amplifier 440 of the ADC and the switches 422 and 427 are kept closed to couple the capacitor system 448 to the differential amplifier. Move the amplifier. In some embodiments, the switches 421, 422, 426 and 427 also depend on a clock signal CK coupled to the switch 420. In certain embodiments, unless the clock signal CK is not active (or the complement of the clock signal CK is active), these switches are not closed.

When the control signal from the timing circuit 404 is in the first state, the charge can be transferred between the sensing circuit 202 and the capacitor system 446, and at the same time, a charge stored by the capacitor system 448 is converted into a charge by the ADC of the system 400 Digital value. When the control signal from the timing circuit 404 is in a second state, the signal from the timing circuit 404 opens the switches 410 and 411 to decouple the capacitor system 446 from the sensing circuit 402 and closes the switches 412 and 413 to The second capacitor system 448 is coupled to the sensing circuit 402. At the same time, the switches 421 and 426 (depending on the value of the clock signal CK) can be closed to couple the capacitor system 446 to the differential amplifier 440 of the ADC, and the switches 422 and 427 can be kept open to connect the capacitor system 448 to the differential amplifier 440. The dynamic amplifier 440 is decoupled. In the second state, charge can be transferred between the sensing circuit 402 and the capacitor system 448, and at the same time, a charge stored by the capacitor system 446 is converted into a digital value by the ADC of the system 400.

The ADC of the system 400 is operable to convert the amount of charge stored by the capacitor system 446 or 448 into a digital value. This operation will be explained with respect to the capacitor system 446. The ADC utilizes two stages to perform the conversion. When the capacitor system 446 is selected for conversion, stages 443 and 442 are used. When the capacitor system 448 is selected for conversion, stages 444 and 442 are used.

The amount of charge stored by the capacitor system 446 can generate a voltage drop across the capacitors 416 and 417, which is converted into a digital value by the ADC. When a CK signal is applied, the switch 421 is closed and the differential amplifier 440 is operable to amplify the voltage across the capacitors 416 and 417. This amplified voltage can be referred to as an intermediate result of the analog-to-digital conversion and is stored in capacitors 423 and 424 of stage 442. Based on this amplified value, the ADC logic 430 will determine a current result 431 and a part of the composite result. When CK is active, the switch 421 will open and the switch 420 will close. The current result 431 is fed to the DAC 432 of the stage 442. Then, the DAC 432 is based on the value of the current result 431 A voltage selected from 434, 435, and 436 is applied. The differential amplifier 440 amplifies this voltage and the voltage stored in the capacitors 423 and 424. The resulting voltage (a second intermediate result) is stored in the capacitor system 446 of stage 443. The ADC logic 430 will determine a new current result 431 and an additional part of the composite result based on the resulting voltage. This new current result 431 is fed to the DAC 433 (A) of level 443. Then, the DAC 433(A) applies a voltage selected from 434(A), 435(A), and 436(A) based on the value of the current result 431. Then, the differential amplifier 440 amplifies the voltage applied by the DAC 433 (A) together with the voltage stored in the capacitor system 446, and stores the resulting voltage in the capacitors 423 and 424. The ADC logic 430 determines a new current result 431 and the extra part of the composite result. The system 400 continues in this manner, switching between stage 442 and stage 443 until the conversion is completed and a composite result indicating a digital value of the initial voltage level stored in the capacitor system 446 is obtained.

In some embodiments, one of DACs 433(A) and 433(B) can be eliminated by sharing another DAC between stage 443 and stage 444. For example, DAC 433(A) can be shared by stage 443 and stage 444 as follows. When the ADC is converting a value stored by the capacitor system 446 of the stage 443, the DAC 433(A) can be selected to be used by the stage 443. When the ADC is converting a value stored by the capacitor system 448 of the stage 444, the DAC 433(B) can be used by the stage 444.

In this article, the reference to a computer-readable storage medium includes one or more non-transitory tangible computer-readable storage media having a structure. As an example and not by way of limitation, a computer-readable storage medium may include: a semiconductor-based IC or other ICs (such as, for example, a programmable gate array (FPGA) or an ASIC), a hard disk, a HDD, a hybrid hard disk drive (HHD), an optical disk, an optical disk drive (ODD), a magneto-optical disk, a magneto-optical disk drive, a floppy disk, A floppy disk drive (FDD), magnetic tape, a holographic storage medium, a solid state drive (SSD), a RAM drive, a secure digital card, a secure digital drive or another suitable computer readable storage The media or, where appropriate, two or a combination of two or more of these items. In this article, the reference to a computer-readable storage medium does not include any medium that is not eligible for patent protection under 35 USC§ 101. In this article, the reference to a computer-readable storage medium does not include a temporary form of signal transmission (such as a propagated electric or electromagnetic signal itself), so it does not qualify for patent protection under 35 USC§ 101. A computer-readable non-transitory storage medium can be volatile, non-volatile, or a combination of volatile and non-volatile where appropriate.

In this article, unless the context clearly indicates or indicates otherwise, "or" is inclusive and not mutually exclusive. Therefore, in this article, unless the context clearly indicates or otherwise indicates otherwise, "A or B" means "A, B, or both." In addition, unless the context clearly dictates or otherwise indicates otherwise, "and" refers to the combined and respective two. Therefore, in this article, unless the context clearly indicates or otherwise indicates otherwise, "A and B" means "A and B, jointly or separately."

The present invention includes all changes, substitutions, changes, alterations and modifications to the exemplary embodiments herein that those familiar with the art will understand. In addition, in the scope of the attached patent application, one of the following is adapted, configured, capable, configured, enabled, operable, or operated to perform a specific function The reference to a device or system or a component of a device or system includes that device, system or component, regardless of whether it or its specific function is activated, turned on, or unlocked, provided that the device, system or component is so adapted and operated. So configured, able to be so, so configured, so enabled, so to operate, or so to operate.

<p>100System</p><p>103(x)Drive electrode</p><p>103(y)sensing electrode</p><p>104Capacitance sensing channel/intersection point</p><p>105ASensing area</p><p>105Capacitive touch sensor</p><p>110Drive unit</p><p>120Sensing unit</p><p>130Storage device</p><p>140Processor Unit</p><p>150Control Unit</p><p>160Second switching element/switching element</p><p>170First switching element/switching element</p><p>180Analog to Digital Converter</p><p>200System</p><p>202Sensing circuit</p><p>204Timing circuit</p><p>206Double Integral Capacitor System/Capacitor System</p><p>208Double Integral Capacitor System/Capacitor System/Capacitor</p><p>210Switch</p><p>211Switch</p><p>212Switch</p><p>213Switch</p><p>214Comparator</p><p>220Comparator output</p><p>222Analog-to-digital converter logic</p><p>223n-bit binary value/binary value/signal</p><p>224Digital to Analog Converter</p><p>228Reference voltage</p><p>230Result</p><p>400System</p><p>402Sensing circuit</p><p>404Timing circuit</p><p>Line 406</p><p>407line/connection</p><p>Line 408</p><p>409line/connection</p><p>410Switch</p><p>411Switch</p><p>412Switch</p><p>413Switch</p><p>416Capacitor</p><p>417Capacitor</p><p>420Switch</p><p>421Switch</p><p>422Switch</p><p>423Capacitor</p><p>424Capacitor</p><p>425output</p><p>426Switch</p><p>427Switch</p><p>428Switch</p><p>429Switch</p><p>430Analog-to-digital converter logic</p><p>431Current Result/New Current Result</p><p>432Digital to Analog Converter</p><p>433(A)Digital to Analog Converter</p><p>433(B)Digital to Analog Converter</p><p>434Switch</p><p>434(a)Switch</p><p>434(b)Switch</p><p>435Switch</p><p>435(a)Switch</p><p>435(b)Switch</p><p>436Switch</p><p>436(a)Switch</p><p>436(b)Switch</p><p>437Switch</p><p>438Switch</p><p>440Differential Amplifier</p><p>442level</p><p>Class 443</p><p>444level</p><p>446Double Integral Capacitor System/Capacitor System</p><p>448Double Integral Capacitor System/Capacitor System/Second Capacitor System</p><p>CKclock signal</p><p>SSignal/Control signal</p><p><img file="TWI577136B_D0008.tif" wi="42" he="78" img-format="tif" img-content="character" orientation="portrait" inline="no" />Signal/Control signal</p><p>VinSignal</p><p>Vin1signal</p><p>Vin2signal</p><p>VrefReference voltage</p>

Figure 1 illustrates an exemplary system including a capacitive touch sensor coupled to a control unit including an analog-to-digital converter (ADC).

FIG. 2A illustrates an exemplary embodiment of the ADC of FIG. 1. FIG.

2B to 2C illustrate exemplary operating states of the ADC of FIG. 2A.

FIG. 3 illustrates an exemplary method for alternating between the capacitor systems of the ADC of FIG. 1. FIG.

FIG. 4 illustrates an additional exemplary embodiment of the ADC of FIG. 1. FIG.