Bumpless build-up layer package with a pre-stacked microelectronic devices

Bumpless build-up layer package with pre-stacked microelectronic device (2)

BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES

The present invention relates to a package, and more particularly to a bumpless build-up package with pre-stacked microelectronic devices.

Background of the invention

The several embodiments of the present invention described herein are generally related to the field of microelectronic device package design, and more particularly to a bumpless build-up (BBUL) design with pre-stacked micro Microelectronic device package for electronic device.

According to an embodiment of the present invention, a microelectronic package is specially proposed, which includes: a first microelectronic device having an active surface with a plurality of active contact land blocks thereon, an opposite back surface, and At least one side, wherein the first microelectronic device includes at least one through-silicon via, which extends from the back surface of the first microelectronic device into the first microelectronic device but does not pass through the active surface of the first microelectronic device The plurality of active surfaces contact the land block, the at least one through silicon via is in electrical communication with the integrated circuit of the active surface of the first microelectronic device; a second microelectronic device has an active surface, An opposite back surface, and at least one Side; at least one interconnection, which electrically connects the active surface of the second microelectronic device and the at least one first microelectronic device through silicon via adjacent to the back surface of the first microelectronic device, wherein the first The active surface of the microelectronic device and the active surface of the second microelectronic device face the same direction; a layer of underfill material is disposed between the first microelectronic device and the second microelectronic device, and the underfill The material is in direct contact with the at least one side of the second microelectronic die; an encapsulation material that surrounds at least a part of the first microelectronic device and the second microelectronic device, and the encapsulation material contacts and surrounds the At least a part of the underfill material layer on the side of the second microelectronic device; and a build-up layer which is electrically connected to the plurality of active surface contact land blocks of the active surface of the first microelectronic device.

<p>102The first microelectronic device</p><p>104,124Active surface</p><p>105Active part</p><p>106, 126, 156back surface</p><p>107Matrix part</p><p>108, 128side</p><p>112Through Silicon Via</p><p>114Active surface contact land block</p><p>116,132Contact land block</p><p>122Second Microelectronic Device</p><p>136Interconnection</p><p>138Filling materials</p><p>140Stacked structure</p><p>150Carrier</p><p>152Packaging materials</p><p>154Front surface</p><p>160Matrix</p><p>162Through hole</p><p>164,176Through hole</p><p>170Layer increase</p><p>172,178Conduction trajectory</p><p>174Dielectric layer</p><p>180Solder Mask Material</p><p>182Open</p><p>184External interconnection</p><p>190,192Microelectronic package</p>

The subject of this publication is specifically pointed out and clearly requested at the end of this manual. From the description in the following text and the scope of patent application attached, together with the accompanying drawings, the aforementioned and other features of this publication can be more fully and clearly seen. It should be understood that the accompanying drawings only depict several embodiments based on this publication, and therefore should not be considered as limiting the scope of this publication. The following text will use the accompanying drawings to describe the content of this publication in additional detail and detail, so as to make it easier to establish the advantages of the content. In these accompanying drawings:

Figures 1-9 illustrate a side cross-sectional view of a process for forming a microelectronic device package with pre-stacked microelectronic devices in a bumpless build-up design.

Figure 10 illustrates another embodiment of a microelectronic device package A side cross-sectional view of the microelectronic device package with pre-stacked microelectronic devices in a bumpless build-up design.

Detailed description of the preferred embodiment

In the following detailed description, reference is made to the accompanying drawings showing several specific embodiments by way of illustration, in which the subject matter requested in the scope of the patent application of this application can be implemented in these embodiments. The text describes these embodiments with a level of detail sufficient to enable those skilled in the art to implement the requested subject. It should be understood that although the various embodiments in the text are different from each other, they are not necessarily mutually exclusive. For example, a specific feature, structure, or characteristic described in conjunction with one embodiment can be implemented in other embodiments without departing from the spirit and scope of the requested subject matter. In addition, it should be understood that the position or arrangement of individual elements in the disclosed embodiments can be modified without departing from the spirit and scope of the requested subject matter. Therefore, the detailed description in the following text should not be regarded as a restrictive form, and the scope of the requested subject matter is only based on the appropriate interpretation of the appended patent scope and the full range of equivalents endowed by the appended patent scope. Define. In the accompanying drawings, similar reference numerals refer to the same or similar elements or functions in these drawings, and the elements depicted therein are not necessarily drawn in proportion to each other. On the contrary, individual elements may be Enlarged or reduced, so that the elements described in the content of this specification can be more easily understood.

The embodiments in this detailed description are related to the field of manufacturing microelectronic packages, where a first microelectronic device with through-silicon vias can be stacked with a second microelectronic device and used in In a bump build-up package.

Figures 1-8 illustrate cross-sectional views of an embodiment of the process for forming a bumpless build-up layer coreless (BBUL-C) microelectronic package. As shown in Figure 1, a first microelectronic device 102 can be provided, wherein the first microelectronic device 102 includes an active surface 104, and an opposite one substantially parallel to the active surface 104 of the first microelectronic device. The back surface 106 and at least one side 108 extending from the active surface 104 of the first microelectronic device to the back surface 106 of the first microelectronic device. The first microelectronic device 102 may have an active portion 105 adjacent to the active surface 104 of the first microelectronic device and a base portion 107 extending from the active portion 105 of the first microelectronic device to the back surface 106 of the first microelectronic device . As those skilled in the art will understand, the first microelectronic device active part 105 includes a number of integrated circuits and interconnections of the first microelectronic device 102 (not shown in the figure). The first microelectronic device 102 can be any suitable integrated circuit device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, and an application-specific integrated circuit Circuits, or other things like that. In one embodiment, the first microelectronic device 102 is a microprocessor.

The first microelectronic device 102 may have at least one via extending from the back surface 106 of the first microelectronic device through the first microelectronic device base portion 107 to the first microelectronic device active portion 105. Such a via type is called a TSV 112. The through silicon via 112 of the first microelectronic device can be electrically connected to an integrated circuit (not shown in the figure) in the active part 105 of the first microelectronic device. Each through-silicon via 112 of the first microelectronic device may have a contact land 116 on the back surface 106 of the first microelectronic device. Although the figure shows the contact land on the back surface of the first microelectronic device as directly adjacent to the through silicon via 112 of the first microelectronic device, it should be understood that it may also be provided on the back surface of the first microelectronic die. Use the track to form an electrical contact between them at a suitable location. The through-silicon via 112 of the first microelectronic device and the back surface contact land 116 of the first microelectronic device can be manufactured by any technique known in the art, including but not limited to drilling (laser and ion ), lithography, electroplating and deposition, and can be made of any suitable conductive metal, including but not limited to copper, aluminum, silver, gold or alloys thereof.

As shown in FIG. 2, a second microelectronic device 122 can be aligned with the first microelectronic device 102. The second microelectronic device 122 may have a back surface 126 that is substantially parallel to the second microelectronic device active surface 124, and at least one extending from the second microelectronic device active surface 124 to the second microelectronic device back surface 126 One side 128. The second microelectronic device 122 may further include at least one contact land 132 adjacent to the active surface 124 of the microelectronic device, wherein the second microelectronic device contact land 132 may be connected to the second microelectronic device 122 The integrated circuit (not shown in the figure). The second microelectronic device 122 can be any suitable integrated circuit device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, and an application-specific integrated circuit. Circuits, or other things like that. In one embodiment, the second microelectronic device 122 is a memory device. The second microelectronic device contact land 132 can be any suitable conductive metal, including but not limited to copper, aluminum, silver, gold, or alloys thereof.

As further shown in Figure 2, the second microelectronic device The device 122 can be attached to the first microelectronic device by connecting the second microelectronic device contact land 132 to the plurality of interconnections 136 (shown as solder balls in the figure) of the first microelectronic device back surface contact land 116. The device 102 thus forms a stacked structure 140. An underfill material 138, such as an epoxy material, can be arranged between the first microelectronic device back surface 106 and the second microelectronic device active surface 124 and around the plurality of interconnections 136. The underfill material 138 can improve the structural integrity of the stacked structure 140.

As shown in Figure 3, the back surface 126 of the second microelectronic device can be, as known by those skilled in the art, by such as DBF (die tested film) or adhesive (not shown in the figure). ), and is attached to a carrier 150. An encapsulating material 152 may be arranged adjacent to the second microelectronic device side 128, the first microelectronic device side 108, and at the first microelectronic device including the first microelectronic device active surface contact land 114. On the active surface 104 of the device, a front surface 154 of the packaging material 152 is thus formed, as shown in FIG. 4. Placing the second microelectronic device back surface 126 on the carrier 150 can cause a back surface 156 of the packaging material 152 to be formed to be substantially flat with the second microelectronic device back surface 126, thereby forming the base 160.

The packaging material 152 can be arranged by any process known in the art, including a lamination process, as those skilled in the art will recognize, and can be any suitable dielectric material, including But it is not limited to silica-filled epoxy, such as available from Ajinomoto Fine-Techno Co., Inc., 210-0801 Suzukicho, Kawasaki District, Kawasaki City, Japan 2 (1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi, 210-0801, Japan) purchaser (Ajinomoto GX13, Ajinomoto GX92 and others).

A plurality of through holes 162 may be formed through the front surface 154 of the packaging material to expose at least a portion of the active surface contact land 114 of each first microelectronic device, as shown in FIG. 5. The through hole 162 in Figure 5 can be formed by any technique known in this art, including but not limited to laser drilling, ion drilling, and lithography. Recognizable. A patterning and electroplating process can be used to fill the through holes 162 to form the via holes 164 and at the same time to form the first layer of conductive traces 172, as those skilled in the art will recognize, as shown in Figure 6. Shown.

As shown in Figure 7, a build-up layer 170 may be formed on the front surface 154 of the packaging material. The build-up layer 170 may include a plurality of dielectric layers having conductive traces formed on each dielectric layer, and conductive traces of different layers are connected by via holes extending through each dielectric layer. Please refer to FIG. 7, the build-up layer 170 may include a first layer of conductive traces 172 and has a dielectric layer 174 formed adjacent to the first layer of conductive traces 172 and the front surface 154 of the packaging material. At least one track-to-track via 176 may extend through the dielectric layer 174 to connect at least one first-layer conductive track 172 to one second-layer conductive track 178. A solder resist material 180 can be patterned on the dielectric layer 174 and the second layer conductive trace 178 so that at least one opening 182 exposes at least a part of the second layer conductive trace 178.

As shown in FIG. 8, at least one external interconnection 184 can be formed on the second-level conductive trace 178 through the patterned opening 182 in the solder resist material 180. These external interconnects 184 can be a soldering material and can be used to connect the build-up layer 170 to external components (not shown in the figure).

It should be understood that although only one dielectric layer and two conductive trace layers are shown in the figure, the build-up layer 170 may be any suitable number of dielectric layers and conductive trace layers. The dielectric layer(s), such as the dielectric layer 174, etc., can be formed by any technique known in the art, and can be any suitable dielectric material. The conductive trace layer, such as the first conductive trace 172 and the second conductive trace 178, and the via 176, can be manufactured by any technique known in this art, including but not limited to electroplating and micro It can be made of any suitable conductive material, including but not limited to copper, aluminum, silver, gold or alloys thereof.

The carrier 150 can be removed to produce a microelectronic package 190, as shown in FIG. 9. The stacking and packaging of the first microelectronic device 102 and the second microelectronic device 122 causes the microelectronic package 190 to have a sufficient thickness to avoid warpage in the microelectronic package 190, as those skilled in the art will understand, This can result in reduced yield loss due to solder ball bridging and/or non-contact openings.

Another embodiment of the microelectronic package 192 is shown in FIG. 10. In this embodiment, the first microelectronic device active surface 104 can be connected to the first microelectronic device active surface contact land 114 and the second microelectronic device contact land 132 through the interconnection 136 extending between the The active surfaces 124 of the two microelectronic devices are in electrical communication. The build-up layer 170 can be formed adjacently on the back surface of the first microelectronic device, and can be electrically connected to the through silicon via 112 of the first microelectronic device.

It can also be understood that the subject matter of this description is not necessarily limited to the specific applications illustrated in Figures 1-10. The subject of the content of this description is applicable Used in other stacking device applications. In addition, the subject matter of this description can also be used in any suitable application outside the field of microelectronic device manufacturing. In addition, the subject of this description can be part of a large bumpless build-up package, which can include a plurality of stacked microelectronic dies that can be formed at the wafer level, or any number of suitable changes, such as Those who are familiar with this skill will understand.

This detailed description has discussed various embodiments of these devices and/or processing procedures by using example diagrams, block diagrams, flowcharts, and/or examples. In the case where these example diagrams, block diagrams, flowcharts and/or examples in the preceding paragraphs contain one or more functions and/or operations, those skilled in this will be able to understand that in each example diagram, block diagram, flow Each function and/or operation system in the figures and/or examples can be implemented independently and/or collectively by a wide variety of hardware, software, firmware, or any combination of them.

The subject matter discussed above sometimes describes different components contained in or connected to other different components. It should be understood that these descriptions are only exemplary, and there are many alternative structures that can be implemented to achieve the same function. Conceptually, any configuration method of components used to achieve the same function is effectively "connected" to achieve the desired function. Therefore, leaving aside the structure or intermediate components, combining any two components in this article to achieve a specific function can be regarded as "connecting" with each other to achieve the desired function. Similarly, any two components so connected can also be regarded as being "operably connected" or "operably coupled" to each other to achieve the desired function, and any two components that can be so connected can be viewed To be "operably coupled" to each other to achieve the desired function. Detailed examples of operability coupling include but are not limited to Physically adaptable and/or physically interactive components and/or wirelessly interactive and/or wireless interactive components and/or logically interactive and/or logically interactive components.

Those who are familiar with this technology will understand that the terms used in this article, especially in the scope of the attached patent application, are generally intended to be "open" terms. Generally speaking, words such as "including" or "including" should be interpreted as "including but not limited to" or "including but not limited to", respectively. In addition, the word "has" should be interpreted as "have at least".

When appropriate for the context and/or application, the use of plural and/or singular words in the detailed description can be interpreted from the plural to the singular and/or from the singular to the plural.

Those who are familiar with this technology will be able to further understand that if there is an indication of the number of components in the request item, the intention to limit the request item in this way will be clearly recorded in this request item, and there is no such request. In the case of this record, there is no such intention. In addition, if there is a clear record of a specific quantity of the requested item presented, it will be recognized by those who are familiar with this technique, and such record should typically be interpreted as meaning "at least" the stated quantity.

The use of terms such as "one embodiment", "one embodiment", "some embodiments", "another embodiment", or "other embodiments" in this specification can mean that it is used in conjunction with one or more embodiments. A particular feature, structure, or characteristic described may be included in at least some embodiments, but not necessarily in all embodiments. The use of terms such as "one embodiment", "one embodiment", "another embodiment" or "other embodiment" in the detailed description does not necessarily all refer to the same embodiment.

Although a variety of methods and systems have been used in this article to illustrate and Some exemplary techniques are shown, but those familiar with this technique should understand that many other variants can be made without departing from the subject matter requested herein or its spirit, and can be replaced by equivalents. In addition, without departing from the central concept described in this article, many modifications can be made to the requested subject to suit specific circumstances. Therefore, it is intended that the requested subject matter is not limited to the specific examples disclosed, and that the requested subject matter may also include all implementations and their equivalents falling within the scope of the appended patent application.