Semiconductor device and method of forming the same

Semiconductor device and its forming method

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

This application claims that the title of the application on November 30, 2012 is "Metal Oxide Semiconductor Device and Method of Forming the Same; Three-Dimensional Decoupled Package for Highly Distributed LDMOS Power Switches for Use in Switch-Mode DC-DC Power Converters; Three -Dimensional Mixed Pillar Routing for Highly Distributed LDMOS Power Switches for Use in Switch-Mode Power Converters; Semiconductor Device Formed with Plural Metallic Layers" U.S. Provisional Application No. 61/732,208, which is incorporated by reference This article.

The present invention is generally directed to semiconductor devices, and more specifically directed to a metal oxide semiconductor device and a method of forming the same.

A customized high-speed laterally diffused metal oxide semiconductor ("LDMOS") process can be used to fabricate a lateral power switch/transistor on a silicon wafer. The lateral power-on relationship is formed by wiring in and out of the very many units of the device terminal allowed on the top side of a wafer. Unlike traditional vertical and trench-style devices, back-side wiring is usually not used. In addition, in the case of deep submicron lithography, the pitch (or half pitch) of a unit drops below 5 microns (one millionth of a meter ("μm")), which makes the source and drain The plating metal is relatively tight so that there is not much available space to couple to the upper metal contacts. The upper metal contacts are routed to An external package pin located at a periphery of a semiconductor package. This difficulty illustrates two unfavorable challenges.

A first challenge is the reduced metal width, which leads to an increase in the resistance between the high current drain terminal and the source terminal of the switch and external package pins. A second challenge is the large amount of overlap between the drain and source metals of the switch, which leads to an increase in the output capacitance of the switch (commonly referred to as "Coss").

In signal or digital applications, the size reduction does not hinder the wiring. However, if the application is a power management device, the segments of the switch should ideally be routed to external pins with extremely low impedance and also have the same impedance measured from a common reference point. This situation is difficult to achieve because the internal parts of the units are inherently farther away from the periphery than the peripheral parts of the units, resulting in voltage and power loss of the internal connections to the external package pins (such as the above two challenges) Reflected).

A distributed transmission line problem occurs when the source, drain, and gate lines are electrically far away from their respective single-point input signal generators. In the absence of remedial measures, the live long connector actually becomes a delay line, which causes problems with the turn-on or turn-off of a switch with a relatively large fine pitch. This effect is a gradual and slow turn-on (or turn-off) behavior, which propagates from the input signal generator to an effective current tank from one end of a transmission line to the other end, resulting in part of the lateral power switch being turned off while the other part Still conducting, or vice versa. This causes a lateral power switch to produce a potentially destructive condition called "through", because this condition causes a power rail to be temporarily shorted to the local circuit ground, thereby generating a potential destructive current. Usually in circuit design, this problem is eliminated by delaying the speed of turning on or turning off these switches of the driver circuit. Although this solution is feasible, it also makes it impossible to achieve the purpose of using high-speed LDMOS devices with deep sub-micron fine pitch structures. Therefore, a high-speed interconnect configuration of large deep sub-micron switches and a corresponding program for forming these switches would be advantageous.

Therefore, what this technology needs is a switch including switches (for example, an LDMOS device) A semiconductor device and its forming method overcome the limitation of switching speed, layout defects and switching device structure in the prior art. In addition, there is a need for a compact LDMOS device that can switch at a high speed and can be used to construct a power converter or a part of it.

With the advantageous embodiments of the present invention (including a semiconductor device and its forming method), these and other problems can be substantially solved or avoided, and technical advantages can be substantially achieved. In one embodiment, the semiconductor device includes using a plurality of laterally diffused metal oxide semiconductor ("LDMOS") units to form a semiconductor die. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metal pillars distributed over the redistribution layer and electrically coupled to the redistribution layer.

The foregoing has fairly broadly summarized the features and technical advantages of the present invention so that the following detailed description of the present invention can be better understood. In the following, additional features and advantages of the present invention will be described, which form the subject of the patent application scope of the present invention. Those familiar with the art should understand that the concepts and specific embodiments disclosed can be easily used as a basis for modifying or designing other structures or programs for carrying out the same purpose of the present invention. Those familiar with the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present invention as stated in the scope of the attached patent application.

<p>110Power System</p><p>120Controller</p><p>130Drive</p><p>210Conductive substrate/lead frame</p><p>215Wire frame fingers</p><p>216Wire frame fingers</p><p>220Surface Mount Components</p><p>225area</p><p>230Magnetic material rod</p><p>240Semiconductor die</p><p>250Conductive clamp</p><p>260area</p><p>265First wire bonding</p><p>266Second wire bonding</p><p>310Shallow trench isolation area</p><p>315Substrate</p><p>316Epitaxial layer</p><p>320N-type buried layer</p><p>325N type well</p><p>330P type well</p><p>335Gate Dielectric Layer</p><p>340Gate</p><p>345N-type lightly doped area</p><p>350P-type lightly doped area</p><p>355Gate sidewall spacer</p><p>360N-type heavily doped area</p><p>362N-type heavily doped area</p><p>365P-type heavily doped area</p><p>367P-type heavily doped region</p><p>370Access area</p><p>372P-type doped area</p><p>375Silicon layer</p><p>380Dielectric area</p><p>385Metal contacts</p><p>405Power semiconductor device</p><p>410Semiconductor die</p><p>420Conductive patterned lead frame</p><p>421Conductive patterned lead frame</p><p>430Printed Circuit Board</p><p>440Decoupling Capacitor/Chip Capacitor</p><p>441Decoupling Capacitor/Chip Capacitor</p><p>445Decoupling Capacitor/Chip Capacitor</p><p>450Low inductance area</p><p>455area</p><p>461Through hole</p><p>462Solder bump</p><p>463Solder bump</p><p>470Radiator</p><p>480Adhesive</p><p>490Metal Pillar/Copper Pillar</p><p>495Plastic</p><p>510N gate drive final stage</p><p>520P gate drive final stage</p><p>530N-Lateral diffusion metal oxide semiconductor device</p><p>531P-Lateral diffusion metal oxide semiconductor device</p><p>610small circle</p><p>620small circle</p><p>630small circle</p><p>640small circle</p><p>650small circle</p><p>800path</p><p>805path</p><p>810path</p><p>820path</p><p>830path</p><p>840path</p><p>910Gate Polycrystalline Silicon Tape</p><p>1010First inverter</p><p>1011P-type metal oxide semiconductor device</p><p>1012N-type metal oxide semiconductor device</p><p>1020Second inverter</p><p>1021P-type metal oxide semiconductor device</p><p>1022N-type metal oxide semiconductor device</p><p>1030Third inverter</p><p>1040Fourth inverter</p><p>1105Lightly doped P substrate</p><p>1108P well</p><p>1111Source Metal Belt</p><p>1112Source Metal Belt</p><p>1113Source Metal Belt</p><p>1114Source Metal Belt</p><p>1121Dip metal belt</p><p>1122Dip metal belt</p><p>1123Dip metal belt</p><p>1124Dip metal belt</p><p>1130Gate Metal Strip</p><p>1131Gate Metal Strip</p><p>1140Gate oxide tape</p><p>1150Gate Polycrystalline Silicon Tape</p><p>1160Source Metal Belt</p><p>1161Dip Metal Belt</p><p>1162Source Metal Strip</p><p>1163Dip metal belt</p><p>1164Source Metal Belt</p><p>1165Dip metal belt</p><p>1170N- Lateral Diffusion Metal Oxide Semiconductor Device Source Contact</p><p>1171N-lateral diffusion metal oxide semiconductor device/P-lateral diffusion metal oxide semiconductor device drain contact</p><p>1172P- Lateral Diffusion Metal Oxide Semiconductor Device Source Contact</p><p>1173Logic circuit element contacts</p><p>1174Copper Through Hole</p><p>1175Through hole</p><p>1176Through hole</p><p>1177Redistribution layer</p><p>1178Copper Pillar</p><p>1179Wire frame</p><p>1180Through hole</p><p>1181Through hole</p><p>1182Through hole</p><p>1184P- Lateral Diffusion Metal Oxide Semiconductor Device Source Metal Strip</p><p>1185P- lateral diffusion metal oxide semiconductor device drain metal strip</p><p>1186P-Lateral diffusion metal oxide semiconductor device source metal strip</p><p>1187P- lateral diffusion metal oxide semiconductor device drain metal strip</p><p>1188P-Lateral diffusion metal oxide semiconductor device source metal strip</p><p>1189P- lateral diffusion metal oxide semiconductor device drain metal strip</p><p>1191N Gate Driver</p><p>1192P Gate Driver</p><p>1193Logic circuit components</p><p>1194N-lateral diffusion metal oxide semiconductor device/P-lateral diffusion metal oxide semiconductor device drain contact</p><p>1195N- Lateral Diffusion Metal Oxide Semiconductor Device Source Contact</p><p>1196P- Lateral diffusion metal oxide semiconductor device source contact</p><p>1197Logic circuit components</p><p>1905Lightly doped substrate/semiconductor die</p><p>1910well</p><p>1915Insulation layer/Silicon oxynitride layer</p><p>1920Through hole</p><p>1925Through hole</p><p>1930Copper through hole</p><p>1935The first polyimide layer</p><p>1940Copper Redistribution Layer</p><p>1945Bronze Pillar</p><p>1950The second polyimide layer</p><p>1955Copper wire frame</p><p>2001N-Lateral Diffusion Metal Oxide Semiconductor Unit</p><p>2003Access area</p><p>2005P-doped semiconductor substrate</p><p>2010Shallow trench isolation area</p><p>2015P type well</p><p>2020Gate oxide layer</p><p>2025Gate polysilicon layer</p><p>2030Overlay gate oxide layer</p><p>2035Silicon Nitride</p><p>2040Sidewall spacer</p><p>2045Photoresist</p><p>2050Gate width</p><p>2055P type area</p><p>2060Heavy doped N-type region</p><p>2065Photoresist</p><p>2070Lightly doped N-type region</p><p>2075Photoresist</p><p>2080Heavy doped N-type region</p><p>2085Photoresist</p><p>2090Heavy doped P-type region</p><p>2095Silica layer</p><p>2100Photoresist</p><p>2105Silica area</p><p>2110Non-reactive refractory metal</p><p>2115Silicide layer</p><p>2120Amorphous silicon oxynitride layer</p><p>2125Photoresist layer</p><p>2130Etching stop refractory layer</p><p>2135Photoresist layer</p><p>2140Silicon oxynitride layer</p><p>2145Photoresist layer</p><p>2150Etching stop refractory layer</p><p>2155Photoresist layer</p><p>2160Silicon oxynitride layer</p><p>2165Photoresist layer</p><p>2170Silicon oxynitride layer</p><p>2175Photoresist layer</p><p>2180Polyimide coating</p><p>2185Photoresist layer</p><p>2190Refractory barrier layer</p><p>2195Copper seed layer</p><p>2200Copper layer</p><p>2205Polyimide coating</p><p>2210Photoresist layer</p><p>2215Copper seed layer</p><p>2220Copper Pillar/Metal Pillar</p><p>2225Encapsulant</p><p>2230Pattern wire frame</p><p>8001P-Lateral diffusion metal oxide semiconductor unit unit</p><p>8003Aisle area</p><p>8005P-doped semiconductor substrate</p><p>8010Shallow trench isolation area</p><p>8015Lightly doped N-type well</p><p>8017N type well</p><p>8020Gate oxide layer</p><p>8025Gate polysilicon layer</p><p>8030Overlay gate oxide layer</p><p>8040Side wall spacer</p><p>8055N type area</p><p>8060Heavy doped P-type region</p><p>8070Lightly doped P-type region</p><p>8080Heavy doped P-type region</p><p>8090Heavy doped N-type region</p><p>8105Silica area</p><p>8115Silicide layer</p><p>8120Amorphous silicon oxynitride layer</p><p>8130Etching stop refractory layer</p><p>8140Silicon oxynitride layer</p><p>8150Etching stop refractory layer</p><p>8160Silicon oxynitride layer</p><p>8170Silicon oxynitride layer</p><p>8180Polyimide coating</p><p>8190Refractory barrier layer</p><p>8200copper layer</p><p>8215Copper seed layer</p><p>8220Metal Pillar/Copper Pillar</p><p>8225Encapsulant</p><p>8230Patterned wire frame</p>

For a more complete understanding of the present invention, refer to the following description in conjunction with the accompanying drawings, in which: FIG. 1 illustrates a block diagram of an embodiment of a power converter including a semiconductor device; FIGS. 2A and 2B illustrate the capsule An isometric view of an embodiment of an electronic device/power converter before sealing; Figure 3 illustrates a cross-sectional view of an embodiment of a part of a semiconductor device; FIG. 4 illustrates a front view of an embodiment of a semiconductor device showing inverted semiconductor die coupled to one of a plurality of decoupling devices by a metal pillar; FIG. 5 illustrates the formation of a semiconductor device using a circumferential ring distribution system A plan view of an embodiment; FIG. 6 illustrates a plan view of an embodiment of a redistribution layer formed as a deposit on a semiconductor die; FIG. 7 illustrates the redistribution layer illustrated in FIG. 6 A plan view with an overlay showing an outline of an N-LDMOS device and a P-LDMOS device; FIGS. 8 and 9 illustrate enlarged plan views of the redistribution layer illustrated in FIG. 6; FIG. 10 illustrates The configuration is to generate a pulse-width modulation ("PWM") signal. The diagram in Figure 1 illustrates a large-amplitude gate drive signal for an N-LDMOS device, an N-type metal oxide semiconductor ("NMOS") inverted signal. A schematic diagram of an embodiment of a device chain; FIG. 11 illustrates a simplified three-dimensional view of an embodiment of a part of a semiconductor device or part of the implementation of a part of an N-LDMOS device; FIG. 12 illustrates the formation of a substance A simplified three-dimensional view of a part of the partially constructed N-LDMOS device after the flat second metal layer is applied; FIG. 13 illustrates a simplified plan view of a part of the partially constructed N-LDMOS device after the second metal layer is formed; FIG. 14 Illustrates a simplified three-dimensional view of a portion of the partially constructed N-LDMOS device after forming a substantially flat third metal layer; FIG. 15 illustrates the partially constructed portion of the N-LDMOS device after forming the third metal layer A simplified plan view; FIG. 16 illustrates a simplified three-dimensional view of an embodiment of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices, which illustrates the partially constructed source in a second metal layer of the semiconductor device A geometric shape of the metal strip and the drain metal strip; Figure 17 illustrates a partially constructed semiconductor including N-LDMOS and P-LDMOS devices A simplified three-dimensional view of the device, which illustrates a geometric shape of the source and drain contacts in the third metal layer; FIG. 17A illustrates a simplified part of a semiconductor device including N-LDMOS and P-LDMOS devices A three-dimensional view illustrating a geometry of a through hole of a redistribution layer; FIG. 17B illustrates a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices, which illustrates a geometry of a redistribution layer Shape; Figure 17C illustrates a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices, which illustrates a geometric shape of the pillars of the redistribution layer; Figure 17D illustrates the inclusion of N-LDMOS and P -A simplified three-dimensional view of a partially constructed semiconductor device of the LDMOS device, which illustrates a geometric shape of a conductive patterned wire frame; FIG. 18 illustrates an embodiment of a semiconductor device including N-LDMOS and P-LDMOS devices. Fig. 19 illustrates a front view of an embodiment of a part of a semiconductor device including an N-LDMOS and/or P-LDMOS device; Fig. 20 illustrates a specific implementation of a semiconductor device or part thereof A cross-sectional view of an embodiment of an N-LDMOS device; FIGS. 21 to 87 illustrate a cross-sectional view of an embodiment of an N-LDMOS device that is implemented in a semiconductor device or a portion thereof; FIG. 88 illustrates A cross-sectional view of an embodiment of a P-LDMOS device embodied in a semiconductor device or part thereof; and FIG. 89 illustrates an embodiment of a P-LDMOS device embodied in a semiconductor device or part thereof A cross-sectional view.

Unless otherwise indicated, the corresponding numbers and symbols in different drawings generally refer to Corresponding part. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiment and are not necessarily drawn to scale.

The making and use of the current preferred embodiment are discussed in detail below. However, it should be understood that these embodiments provide many applicable inventive concepts that can be implemented in many specific contexts. The specific embodiments discussed only illustrate specific ways to make and use the invention, and do not limit the scope of the invention.

The embodiment will be described in a specific context (ie, a switch (e.g., embodied in an LDMOS device), a semiconductor device incorporating an LDMOS device and a method of forming the same). Although the principle of the present invention will be described in the context of a power converter using an LDMOS device, any application or related semiconductor technology that can benefit from a device that can switch at a high speed on a semiconductor substrate is entirely within the scope of the present invention. Within the scope.

Referring initially to FIG. 1, a block diagram of an embodiment of a power converter including a semiconductor device is illustrated. The power converter includes a power system 110, a controller 120, and a driver 130, and supplies power to a system such as a microprocessor. Although the power system 110 uses a buck converter topology in the illustrated embodiment, those skilled in the art should understand that other converter topologies such as a forward converter topology are fully within the broad scope of the present invention.

The power system 110 of the power converter receives an input voltage V from the power source (represented by a battery) at one of its inputs_in, And provide a regulated output voltage V at the output of one of the power converters_outTo power (for example) a microprocessor. In order to comply with the principle of a buck converter topology, the output voltage V_outGenerally less than the input voltage V_inMakes one of the switching operations of the power converter adjustable output voltage V_ont. A main switch Q_mn[For example, a P-channel metal oxide semiconductor field effect transistor ("MOSFET") implemented in a P-type laterally diffused metal oxide semiconductor ("P-LDMOS") device] is activated for a major time interval ( Basically with the main switch Q_mnOne of the main working cycles "D" coexist) conducts electricity and reduces the input voltage V_inCoupled to an output filter Wave inductor L_out. During the main time interval, flows through the output filter inductor L_outOne of the inductor current I_LoutAs the current flows from the input of the power system 110 to the output of the power system 110, it increases. Output filter capacitor C_outFilter inductor current I_LoutOne of the ac components.

In a complementary time interval (substantially with the main switch Q_mnDuring one complementary duty cycle "1-D" coexistence), the main switch Q_mnTransformed into a non-conducting state and an auxiliary switch Q_aux[For example, an N-channel MOSFET implemented in an N-type laterally diffused metal oxide semiconductor ("N-LDMOS") device) is enabled to conduct electricity. Auxiliary switch Q_auxProvide sustain inductor current I_LoutContinuous flow through output filter inductor L_outOne of the paths. During the complementary time interval, through the output filter inductor L_outThe inductor current I_Loutreduce. Generally speaking, the main switch Q_mnAnd auxiliary switch Q_auxThe respective duty cycles can be adjusted to maintain the output voltage V of the regulated power converter_out. However, those familiar with this technology should understand that the main switch Q_mnAnd auxiliary switch Q_auxThe conduction periods can be separated by a short time interval to avoid transconductance between the conduction periods and advantageously reduce the switching loss associated with the power converter.

The controller 120 of the power converter receives a desired power converter characteristic, such as a desired system voltage V from an internal or external source that can be associated with the microprocessor_system, And the output voltage of the power converter V_out. According to the aforementioned characteristics, the controller 120 provides a signal (for example, a pulse width modulation ("PWM") signal S_PWM) To control the main switch Q of the power system 110_mnAnd auxiliary switch Q_auxA duty cycle and a frequency to adjust its output voltage V_out. Any controller adapted to control at least one switch of the power converter is fully within the broad scope of the present invention.

The power converter also includes a driver 130, which is configured to be based on the PWM signal S provided by the controller 120_PWMRespectively on the main switch Q_mnAnd auxiliary switch Q_auxProvide drive signal S_DRV1, S_DRV2. There are many known and feasible alternative techniques for implementing a driver 130, including techniques that provide a sufficiently large signal delay to prevent cross currents when controlling multiple switches in the power converter. The driver 130 usually contains and cooperates with the main switch Q_mnAnd auxiliary switch Q_auxProvide drive signal S_DRV1, S_DRV2Of multiple drive switches Switching circuit. Of course, the drive signal S can be provided_DRV1, S_DRV2Any driver 130 that controls a switch is fully within the broad scope of the present invention.

In one embodiment, the main switch Q_mnAnd auxiliary switch Q_auxIt can be incorporated into a power switch in a semiconductor device that is closest to the control function of the controller 120 that executes the power converter or a signal processing device. Control and signal processing devices are usually complementary metal oxide semiconductor ("CMOS") devices, such as P-type metal oxide semiconductor ("PMOS") devices and N-type metal oxide semiconductor ("NMOS") devices. PMOS and NMOS devices can also be referred to as P-channel and N-channel MOSFETs, respectively. The control and signal processing device uses low voltage (for example, 2.5 volts) (hence, also called "low voltage device") to prevent flashover between its thin wire structures. Main switch Q of power system 110_mnAnd auxiliary switch Q_auxAnd one of the plurality of driver switches of the driver 130 can be formed by an LDMOS device that handles a higher voltage (for example, 10 volts) and is therefore referred to as a higher voltage device. Integrating control and signal processing devices, power switches, and driver switches on a semiconductor substrate can greatly reduce the cost and size of power converters or other equipment using similar devices.

Therefore, as illustrated in FIG. 1, one of the inputs of the controller 120 is coupled to the output voltage V of a power converter_outOr receive the output voltage V of a power converter_outTo adjust the output voltage V_out. A controller 120 may use an inverting input coupled to the output voltage V of the power converter_outAn analog operational amplifier constructs an error amplifier. A non-inverting input of the error amplifier is coupled to a reference voltage representing the output voltage of one of the power converters to be regulated. A working cycle of a power switch of a power converter is initiated by a clock signal. To terminate the duty cycle, an analog comparator compares the output of the error amplifier with a ramp voltage waveform. The ramp voltage waveform is usually a periodic ramp voltage waveform or a periodic ramp voltage waveform with a proportionally superimposed switch or inductor current. . When the output of the error amplifier exceeds the ramp voltage waveform, the working cycle of the power switch is terminated by the analog comparator. The result of this controller structure is a feedback configuration in which the analog comparator continuously makes a decision to terminate one of the power switch duty cycles during the time interval during which the power switch is enabled to conduct. The analogous controller architecture can terminate a power switch duty cycle with a fine time granularity that does not depend on a clock frequency or a calculation rate of the digital logic. Digital circuits can also be used to construct a controller.

Referring now to FIGS. 2A and 2B, an isometric view of an embodiment of an electronic device/power converter (eg, a power module) before encapsulation is illustrated. The power converter includes a magnetic device (for example, an inductor), an integrated circuit, and surface mount components. The power converter may include a power conversion circuit, which includes at least one of a magnetic device, an integrated circuit, and a surface mount component, or may be embodied in at least one of a magnetic device, an integrated circuit, and a surface mount component. The power conversion circuit may form a power converter that usually includes a switching regulator or a power converter such as a step-down switching regulator having an integrated control circuit for reducing the component count and for Synchronous rectifier with high power conversion efficiency. Of course, an embodiment is not limited to a power module, power converter or the like, and can be applied to other electronic devices.

A conductive substrate (or lead frame) 210 is patterned and etched to form a conductive interconnection layer for a lower part of a winding of an inductor and electrical interconnections between surface mount components, integrated circuits, and the inductor. A typical thickness of the lead frame 210 is about 8 mils (thousandths of an inch). Although the lead frame 210 is usually constructed of copper, alternative conductive materials can also be used. The lead frame 210 provides an external connection for the power module and a support base of a magnetic material for the inductor. The external connector is formed as a finger of the wire frame 210, and the reference is a finger of the wire frame (two of them are designated as 215 and 216).

The lead frame 210 is generally constructed using a one-piece metal tape surrounding the conductive pattern to provide mechanical support during the manufacturing steps, and the metal tape is then discarded during the manufacturing process. After the electronic device is constructed, the surrounding metal strips are generally cut to, for example, provide unconnected traces. The lead frame 210 is generally generated in an array of repeating patterns (not shown) such as a 16x16 array to, for example, form 256 substantially identical electronic devices. Forming an array of lead frames 210 is known in the art to reduce the manufacturing cost of an electronic device. One program.

A thin layer of solder paste is selectively applied to the lead frame 210 to the area (designated 225) used for the masking process to electrically and mechanically attach the surface mount components. Surface mount components such as capacitors (one of them designated 220) are placed so that their conductive ends are in the solder paste. The solder paste can be composed of lead-based and lead-free ingredients. The array of lead frame 210 with surface mount components 220 is reflowed in an oven to mechanically and electrically attach the surface mount components 220 to the lead frame 210.

The steps described above generally do not need to be performed in a highly controlled environment in a clean room. However, the following steps are preferably performed in a clean room environment such as a molded plastic package that is generally known in the art for assembling integrated circuits.

An adhesive (for example, a die attach adhesive such as Abletherm 2600AT produced by Ablestik of Rancho Dominguez, California) is applied to the lead frame 210 to hold a magnetic core (for example, a rod of a magnetic material) 230 And an integrated circuit in the form of a semiconductor die 240. The rod body 230 of magnetic material and the semiconductor die 240 are positioned above the die attaching adhesive on the lead frame 210. Therefore, a lower surface of the rod body 230 of magnetic material faces and is preferably adhered to the lead frame 210. The rod 230 that includes a magnetic material to enhance the magnetic properties of the inductor and can be about 250 micrometers ("μm") thick, 4 mils wide, and 7.5 mils long. The adhesive is usually cured in a controlled thermal process to secure the rod 230 of the magnetic material and the semiconductor die 240 to the lead frame 210.

The solder paste is applied to the areas of the lead frame 210 (generally designated as 260), where the ends of the conductive clamp 250 are placed in these areas. In addition, the solder paste can be composed of lead-based and lead-free ingredients. A conductive clamp 250 (for example, about 8 mils to 12 mils thick) is placed above the rod 230 of magnetic material on the lead frame 210 with its equal ends in the solder paste. The conductive clamp 250 is formed so that its equal ends are bent toward the lead frame 210 around the end of the rod 230 of magnetic material without mechanical interference. Therefore, an upper surface of the rod body 230 of magnetic material faces the conductive clamp 250. Therefore, the upper surface of the rod 230 of magnetic material and the lower surface of the conductive clamp 250 are better. An insulating gap, for example, about a 5 mil air gap, remains between the surfaces, which gap can then be filled with an encapsulant. The conductive clamp 250 provides a part of the conductive inductor winding above each rod 230 of magnetic material. The lead frame 210 is heated in a reflow oven to mechanically and electrically bond the conductive clamp 250 to the lead frame 210.

Wire bonds such as gold wires (such as a first wire bond 265) are attached to each semiconductor die 240 and the lead frame 210 to electrically couple the pads on the semiconductor die 240 to the bonding area of the lead frame 210, thereby Provide circuit connections between them. Wire bonds such as a second wire bond 266 can also be used to selectively electrically couple portions of the lead frame 210 to provide circuit interconnections that cannot be easily wired in a single plane layout, thus creating a double-layer printed circuit board (also known as "Printed wiring board") or the topological layout functionality of the lead frame 210 of the substrate.

When an electronic device is formed in an array as mentioned above, the array is placed in a mold and an encapsulant such as a molding material (preferably, ring) is deposited on the array as known in the art. Oxygen resin) to provide environmental and mechanical protection and a thermally conductive cover to promote heat dissipation during operation. Other molding materials and procedures and electronic devices constructed without an encapsulant are fully within the broad scope of the present invention.

Turning now to FIG. 3, a cross-sectional view of an embodiment of a portion of a semiconductor device is illustrated. Since the process steps used to construct the semiconductor device illustrated in Figure 3 are similar to those described by the following patent: Lotfi et al. filed on January 29, 2004 entitled "Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming The Same" U.S. Patent 7,230,302, Lotfi et al., filed on August 28, 2009, entitled "Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same" U.S. Patent No. 8,212,315, Lotfi et al. U.S. Patent Application Publication No. 2007/0284658 entitled "Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same" filed on August 20, 2007 No., Lotfi et al. filed on August 15, 2012, the U.S. Patent Application Publication No. 2012/0306011 entitled "Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same" (these cases are Incorporated into this article by reference); the steps in this procedure will not be described in detail at this time. However, the procedure steps used to construct a similar device will be described later in this article.

The cross-sectional view illustrated in FIG. 3 illustrates the individual LDMOS cells of P-LDMOS and N-LDMOS devices that are constructed using a very large number of these individual cells. In one embodiment, a mirror image is used to repeat the pattern of the individual cells illustrated in FIG. 3 as necessary to generate a P-LDMOS or N-LDMOS device with a suitable current rating for an application. In this way, for example, a plurality of heavily doped source regions and heavily doped drain regions are used to form a substrate.

A semiconductor device is formed in a semiconductor die including a shallow trench isolation region 310 within a substrate 315 (eg, a P-type substrate) to provide dielectric separation between PMOS, NMOS, P-LDMOS, and N-LDMOS devices . An epitaxial layer 316 (for example, a P-type epitaxial layer) grown on a surface of the substrate 315 and partially diffused therein is preferably doped between 1.10¹⁴Atoms/cm³And 1.10¹⁶Atoms/cm³between. A buried layer (for example, an N-type buried layer) 320 is recessed in the substrate 315 in the area where the P-LDMOS device and the N-LDMOS device are housed.

The semiconductor device also includes wells (for example, N-type wells) formed in the area of the substrate 315 for accommodating PMOS devices and P-LDMOS devices and under the shallow trench isolation area 310 and on the N-type buried layer 320 (of P-LDMOS). )325. The N-type well 325 is formed to provide electrical isolation for the PMOS device and the P-LDMOS device and to cooperate with the N-type buried layer 320 (in the case of the P-LDMOS device) and the shallow trench isolation region 310 to provide isolation. As illustrated in the figure, the N-type well 325 on the N-type buried layer 320 does not cover the entire area of the substrate 315 between the shallow trench isolation regions 310 to accommodate the P-LDMOS device. Therefore, the N-type well 325 of the P-LDMOS is constructed for the reasons as stated herein.

The semiconductor device includes an additional well (for example, a P-type well) 330 formed in the substrate 315 between the shallow trench isolation regions 310, which is substantially located in the region that houses the NMOS device and the N-LDMOS device. Although the P-type well 330 on the N-type buried layer 320 covers the entire area of the substrate 315 that accommodates N-LDMOS devices between its shallow trench isolation regions 310, the P-type well 330 is defined as covering the substrate 315 to accommodate N-LDMOS devices. A part of the area of the LDMOS device is also completely within the broad scope of the present invention. Semiconductor devices also include gates 340 of PMOS, NMOS, P-LDMOS, and N-LDMOS devices, which are located above a gate dielectric layer 335 and include gate sidewall spacers 355 surrounding the gates 340 of these devices .

The N-LDMOS device includes a lightly doped withstand voltage enhancement region (for example, an N-type lightly doped region) 345 for its drain. The P-LDMOS device also includes a lightly doped withstand voltage enhancement region (for example, a P-type lightly doped region) 350 for its drain. In this embodiment and for similar reasons as stated above, the N-type lightly doped region 345 and the P-type lightly doped region 350 provide higher voltage ratings for N-LDMOS and P-LDMOS devices, respectively. Therefore, N-LDMOS and P-LDMOS devices can not only handle the higher voltage from their drain-source, but also when the source has more positive charge than the gate 340, these devices can also handle the higher voltage from one of them. One of the source-gate has a higher voltage. It should be realized that the width of the N-type lightly doped region 345 and the P-type lightly doped region 350 can be individually changed to change the breakdown voltage characteristics of the respective N-LDMOS and P-LDMOS devices without departing from the scope of the present invention. . In addition, the N-type lightly doped region 345 and the P-type lightly doped region 350 may be similar to the respective N-LDMOS and P-LDMOS and P-LDMOS illustrated and described with respect to FIGS. 2 to 15 in the previously cited U.S. Patent No. 7,230,302. LDMOS device is formed in one way.

The semiconductor device also includes heavily doped regions (for example, N-type heavily doped regions) 360 of the source and drain of the NMOS device, which preferably have a heavily doped source and drain different from that of the N-LDMOS device One of the doped regions (for example, N-type heavily doped regions) 362 has a dopant concentration distribution. The N-type heavily doped region 360 of the NMOS device is formed in the P-type well 330 of the NMOS device, and the source and drain of the NMOS device are formed as described above. In addition, N- The N-type heavily doped region 362 of the LDMOS device is formed in the P-type well 330 of the N-LDMOS device. In addition, the N-type heavily doped region 362 of the drain of the N-LDMOS device is adjacent to the N-type lightly doped region 345 of the N-LDMOS device.

The semiconductor device also includes heavily doped regions of the source and drain of the PMOS device (for example, a P-type heavily doped region) 365, which preferably has a heavily doped source and drain that is different from the source and drain of the P-LDMOS device. The doping concentration distribution of one of the impurity regions (for example, the P-type heavily doped region) 367. The P-type heavily doped region 365 of the PMOS device is formed in the N-type well 325 of the PMOS device, and the source and drain of the PMOS device are formed as described above. In addition, the P-type heavily doped region 367 of the P-LDMOS device is formed in the N-type well 325 or in the region adjacent to the N-type well 325 of the P-LDMOS device, and forms the source and drain of the P-LDMOS device. Part of it. In addition, the P-type heavily doped region 367 of the drain of the P-LDMOS device is adjacent to the P-type lightly doped region 350 of the P-LDMOS device.

In the illustrated embodiment, the N-type well 325 on the N-type buried layer 320 does not cover the entire area of the substrate 315 that accommodates the P-LDMOS device between the shallow trench isolation regions 310 of the P-LDMOS device. In particular, the N-type well 325 is located under a channel region 370 and in the channel region 370. Compared with the P-type lightly doped region 350 and the heavily doped region 367, the N-type well 325 and the N-type well are doped oppositely. Burying layer 320. Therefore, a doped region (for example, a P-type doped region) 372 of the same doping type as the lightly doped region 350 is between the P-type heavily doped region 367 of the drain of the P-LDMOS device and the N-type well 325 It extends between the regions and has a doping concentration distribution that is smaller than the doping concentration distribution of the P-type heavily doped region 367. Although the P-type heavily doped region 367 preferably has the same doping concentration distribution, the P-type heavily doped region 367 of the source has a doping concentration distribution different from that of the corresponding part of the drain. Within the scope. The same principle applies to other similar device areas of semiconductor devices. The P-type doped region 372 of the same doping type as the lightly doped region 350 together separates the heavily doped region 367 of the drain from the channel region 370 formed in the oppositely doped N-type well 325.

The P-type doped region 372 can be implemented exactly in the substrate 315, and the substrate 315 has an intermediate At 1.10¹⁴Atoms/cm³And 1.10¹⁶Atoms/cm³Doping concentration distribution among one. The use of the substrate 315 as the P-type doped region 372 can provide an opportunity to omit a mask and a processing step when manufacturing a semiconductor device. In yet another alternative embodiment, the P-type doped region 372 may be formed by an ion implantation process before implanting the P-type heavily doped region 367 of the source and drain of the P-LDMOS device. Of course, the P-type doped region 372 can be formed to have any doping concentration distribution smaller than that of the P-type heavily doped region 367.

Incorporating the P-type doped region 372 into the P-LDMOS device can further increase a breakdown voltage between the P-type heavily doped region 367 and the N-type well 325 of the P-LDMOS device. Therefore, the P-LDMOS device exhibits a higher drain-source voltage handling capability due to its higher breakdown voltage and also provides a higher source-gate when the source has more positive charges than the gate 340 Extreme voltage handling capability. It should be understood that although the doped regions have been described with respect to P-LDMOS devices, the principles are equally applicable to N-LDMOS devices, and in this regard, are applicable to other transistors of similar construction.

The P-LDMOS and N-LDMOS devices illustrated and described with respect to FIG. 3 are referred to as asymmetric devices. In other words, the asymmetric nature of the source and drain of the semiconductor device of FIG. 3 provides an asymmetric device. Of course, those skilled in the art should understand that the size of the source and drain (including their lightly doped regions and heavily doped regions) can be changed and still fall within the broad scope of the present invention. The semiconductor device also includes a dielectric region 380 formed on the gate, source, and drain silicon layers (one of which is designated as 375) of the PMOS, NMOS, P-LDMOS, and N-LDMOS devices. Metal contact 385.

As described in this article, a semiconductor device (also called a "power semiconductor device") includes a device placed in an LDMOS device (also called a "power MOSFET" or "enhanced type"), which is preferably implemented in a distributed manner. One or more decoupling capacitors under one of the semiconductor die of one of the MOSFETs in "MOSFET") to reduce the impedance of one of the voltage sources used for the driver. The drivers can be distributed on the periphery of the semiconductor die to substantially equalize the driving signals of the individual MOS cells coupled to the MOS device and the LDMOS cells of the LDMOS device. Timing. In general, it should be understood that an LDMOS device is formed by coupling the source and drain of a very large number of small LDMOS cells (for example, 100,000 or more cells) in parallel in a common die and driving from a common circuit node It is formed by connecting individual gates of LDMOS cells in parallel. One design challenge is to match the timing of the signals coupled to the individual gates so that the LDMOS cells are turned on or off at substantially the same time. Failure to maintain synchronization between the signal and individual gates can lead to failure of the semiconductor device. In the conventional design, the high frequency characteristic of the gate signal is suppressed so that the obtained low frequency signal arrives substantially at the same time.

An embodiment of a structure for efficiently routing signals into and out of an LDMOS device formed in a semiconductor die will now be described. In one embodiment, a plurality of LDMOS cells are formed in the semiconductor die. Distributed three-dimensional decoupling is performed using metal pillars (e.g., elongated copper pillars) that can be formed to have an aspect ratio (e.g., equal to or greater than 1 to 1) to form a distributed circular signal path in the semiconductor die to extract from The current from the drain or source contact (or emitter or collector contact) of the LDMOS device to the distributed decoupling device. This structure does not rely on conventional package pins and solder joints in the middle of a circuit board with a single decoupling point. The drain contact is in contact with the source contact, but it does not need to be wired through the conventional top chip electroplating metal as used in conventional integrated circuit devices. In reality, a conductive pattern is used to contact a conductive patterned lead frame (such as a conductive pattern formed on an upper surface of a printed circuit board at one of a plurality of locations with a plurality of small decoupling devices (for example, decoupling capacitors)) A grid of metal pillars of the lead frame). The decoupling devices are distributed and placed in a third dimension below the printed circuit board. The decoupling device is placed on a conductive patterned lead frame under the semiconductor die on a lower surface of the printed circuit board. The conductive patterned lead frame on the upper surface of the printed circuit board is coupled to the conductive patterned lead frame on the lower surface of the printed circuit board through a plurality of through holes. The influence of the charged long transmission line is therefore eliminated by using a plurality of distributed decoupling devices placed in the third dimension through the lead frame and through holes under the grid of the metal pillars. Alternatively, a conductive patterned lead frame can be packaged using a semiconductor die and then placed on a printed circuit board.

An alternative convex structure with a bump bottom electroplating solution would allow bumps to be placed in various locations. A bump is usually formed by using deposition methods (such as vapor deposition of solder material) or by ball collision using wire bonding equipment. As described in US Patent No. 7,989,963 entitled "Transistor Circuit Formation Substrate" filed by Simon Tam on March 14, 2008, the manufacturing meaning of this manufacturing process may be too expensive to be considered practical. As described in one of the following patents, the use of the post in the package and the connector to a lead frame is a widely established and cost-effective manufacturing process that can achieve a practical solution to the distributed wiring problem: Tung in 2002 U.S. Patent No. 6,681,982, filed on June 12, 2001, entitled "Pillar Connections for Semiconductor Chips and Method of Manufacture", Hwee filed on May 18, 2001, entitled "Method for Forming a Flip Chip Semiconductor Package" U.S. Patent No. 6,510,976, Chew filed on August 21, 2001, entitled "Method for Forming a Flip Chip on Leadframe Semiconductor Package" U.S. Patent No. 6,550,666, Tung's U.S. Patent No. 6,578,754 filed on April 27, 2000 and titled "Pillar Connections for Semiconductor Chips and Method of Manufacture" and Tung's U.S. Patent No. 6,578,754 on April 27, 2000 U.S. Patent No. 6,592,019 entitled "Pillar Connections for Semiconductor Chips and Method of Manufacture" filed on the 26th. Each of these patents is incorporated herein by reference.

An embodiment of a power semiconductor device will now be described. In one aspect, a plurality of drivers (eg, gate drivers) are located on the periphery of the power semiconductor die to equalize the gate timing and provide a driver with low gate driving impedance. Create physical structures on metal strips and semiconductor dies to improve the redistribution layer ("RDL") and switch output capacitor C_oss. A metal strip such as aluminum strip is formed and positioned to route gate signals to individual LDMOS cells to reduce gate resistance and improve timing equalization of gate drive signals. A gate drive bias voltage "VDDG" bus and ground ("GND" or "PGND") rails are convex to reduce Gate drive supply impedance.

This structure enables the gate drive signals to actually reach the respective gates of the LDMOS cells at the same time. The decoupling device of the gate drive bias voltage bus is placed in a distributed manner in the path directly under the semiconductor die. As a result, the signal conducted along the gate drive transmission line formed as a metal strip exhibits low impedance.

In one embodiment, the metal strip of the gate drive signal extends from the periphery of the connector to the LDMOS cell in one of the central regions on the semiconductor die. The metal strip is used to connect the gate drive from the periphery of the die to the LDMOS cell. The metal pillar is formed as an electroplated metal (for example, copper) pillar to couple an external decoupling device located under the semiconductor die to a point on the semiconductor die. In one embodiment, at least one decoupling device is located directly under the semiconductor die. A column and a decoupling device are coupled to one end of one of the metal strips of the gate drive signal. In one embodiment, potting is formed above to provide structural support and protection to the metal pillars.

Turning now to FIG. 4, a front view of an embodiment of a semiconductor device 405 is illustrated, which shows coupling to a plurality of decoupling devices (for example, decoupling or One of the chip capacitors 440, 441) inverts the semiconductor die 410. Partial decoupling is achieved by using metal pillars 490 and decoupling capacitors 440 and 441 at locations where decoupling is required (such as the peripheral location of the semiconductor die 410). One or more decoupling capacitors 440, 441 can be placed substantially below a corresponding pillar 490, directly above or directly below the semiconductor die 410 to reduce circuit path inductance. Placing a decoupling device (e.g., decoupling or chip capacitor 445) outside of a low-inductance area 450 that is substantially below the semiconductor die 410 (e.g., in an area 455 outside the semiconductor die area) will produce reduced One of the performances of the decoupling capacitor 445 is higher inductance. In the low inductance area 450, the decoupling capacitors 440, 441 are completely located under the semiconductor die area of the semiconductor device 405. The metal pillar 490 can also be used to couple to the high current source and drain terminals of an LDMOS cell of an LDMOS device located in a more central area of the semiconductor die 410.

In FIG. 4, a photoresist (for example, a half-mil (~12 μm) photoresist) is spin-coated on a top surface of the semiconductor die 410 and etched to form a hole in which a metal pillar 490 is formed. The photoresist is then removed so that the cantilevered conductive pillar remains. On the semiconductor die 410, aluminum is deposited first, followed by a tin-copper or scintillation layer/seed layer copper deposition and electroplating. In order to provide mechanical stability, a plastic 495 (for example, an encapsulant such as epoxy resin or polyimide) is used to surround the metal pillars 490 so that one end of each metal pillar 490 is exposed on a surface of the plastic 495. The metal pillars 490 may be formed in the polyimide layer and may extend from the polyimide layer. The metal pillars 490 contact the islands of a conductive patterned lead frame 420 defined on an upper surface of a printed circuit board 430 according to the original drawing. The metal pillars 490 are reflow soldered to the conductive patterned lead frame 420. Construct a through hole in the printed circuit board 430 (for example, one of them is designated as 461) so that the metal post 490 is coupled to a conductive patterned lead frame 421 on a lower surface of the printed circuit board 430 and coupled to the decoupling Terminals of capacitors 440, 441, 445. The decoupling capacitors 440, 441, 445 are reflow soldered to the islands of the conductive patterned lead frame 421 on the lower surface of the printed circuit board 430 using an array of solder bumps (for example, one of them is designated as 463). The islands are small geometric structures, such as patterned lead frames, which are useful for a reflow soldering operation to attach a component to a circular area. An array of solder bumps (for example, one of them is designated as 462) is located on the islands of the conductive patterned lead frame 420 on the upper surface of the printed circuit board 430. Therefore, the decoupling capacitors 440, 441, 445 are placed on the island with a short vertical distance from the nodes on the periphery of the semiconductor die 410 to generate low impedance to the local circuit grounding of these nodes. The metal pillars 490 are coupled to the conductive patterned lead frame 420 by solder bumps 462.

The semiconductor die 410 is turned over as illustrated in FIG. 4 before being attached to the printed circuit board 430, and therefore the metal pillars 490 under the semiconductor die 410 are in electrical contact with its "top" side. Because the device is a high-power device, a heat sink 470 is mounted (via an adhesive 480) on the "lower" surface of the semiconductor die 410 (which illustrates the semiconductor die 410 in the top of FIG. 4). Above), so that the decoupling capacitors 440, 441, 445 can be installed It is mounted on the printed circuit board 430 and under the top side of the flipped semiconductor die 410. The heat sink 470 therefore contacts the lower surface of the semiconductor die 410. Therefore, the metal pillar 490 enables the decoupling capacitors 440, 441, 445 to be placed on the printed circuit board 430 close to the top side of the semiconductor die 410, and a through hole 461 passing through the printed circuit board 430 is formed to transfer the semiconductor die 410 is coupled to the array of decoupling capacitors 440, 441, 445 under the printed circuit board 430. In this way, a distributed decoupling function is provided for the power semiconductor device 405. In one embodiment, the same or a different lead frame can be used to couple to the grid of solder bumps or pillars or other circuit elements. An exemplary lead frame is 6 millimeters ("mm") x 6mm. The structure illustrated in FIG. 4 can be filled/encapsulated (for example, with epoxy), and the resulting assembly can be coupled to a lead frame using, for example, a clamp inductor as described in the following patents: Lotfi, etc. US Patent No. 7,688,172 entitled "Magnetic Device Having a Conductive Clip" filed on October 5, 2005, is incorporated herein by reference.

Therefore, an inverted semiconductor (eg, silicon) die is coupled to a printed wiring or an upper surface of a circuit board through an elongated metal pillar, and a decoupling device is coupled to a lower surface of the printed circuit board below the semiconductor die. In an embodiment, at least one of the plurality of decoupling devices is coupled to a lower surface of the printed circuit board directly below the semiconductor die. With this structure, a metal path between the semiconductor die and at least one decoupling device generates a reduced circuit impedance. The inverted semiconductor die, printed circuit board and at least one decoupling chip device can be easily assembled in a cost-effective reflow soldering process. This structure avoids the need to produce a plurality of alternate small metal source and drain pads on the exposed surface of the semiconductor die structure, otherwise it will be necessary to provide a low inductance connection to the printed circuit board of the semiconductor die. To promote the layout of the printed circuit board. Alternatively, as illustrated and described below, the conductive patterned lead frame 420 can be packaged with the semiconductor die 410 and the metal pillars 490 in a packaged semiconductor device, and then placed on a printed circuit board 430 such that the decoupling capacitors 440, The arrays of 441 and 445 are located under the conductive patterned lead frame 420 (see, for example, FIG. 18, packaged semiconductor device).

Turning now to FIG. 5, a plan view of an embodiment of a semiconductor device formed using a circumferential ring distribution system is illustrated. An N-LDMOS device 530 and a P-LDMOS device 531 represent a pair of LDMOS devices forming, for example, a power stage of a buck or boost dc-dc power converter. As previously stated above, each LDMOS device is formed by a very large number of individual LDMOS cells. FIG. 5 shows the N-LDMOS device 530 and the P-LDMOS device 531 and the final drive stages, such as the N-gate drive final stage 510 and the P-gate drive final stage 520 located on the periphery of the semiconductor die (of the power semiconductor device). A conventional design uses only one structure of the N gate drive final stage 510 and only one structure of the P gate drive final stage 520 located on one end of the semiconductor die. Distributing a plurality of driving final stages around one of the semiconductor dies of each of the N-LDMOS device 530 and the P-LDMOS device 531 substantially improves the timing of the driving signals coupled to the individual LDMOS cells. In each driving final stage, there is a totem-pole configuration that is coupled in series with a P-MOS unit and an N-MOS unit driven by a cascade buffer. The drive final stage is electrically coupled in parallel.

In the very many (for example, thousands) LDMOS cells that make up each LDMOS device, the gate drive signals on the control or gate terminals should arrive at substantially the same time and with substantially the same amplitude. Using a capacitor to attenuate the high-frequency characteristics of the gate drive signal to improve relative simultaneity can compromise the efficiency of high-frequency operation. The design includes a plurality of decoupling devices to provide low impedance to the gate driver's gate drive bias voltage VDDG bus, but it will not slow down the gate driver. The decoupling device reduces the impedance of the gate drive bias voltage VDDG bus supplied to the distributed driver. The gate drive signal still retains a certain propagation delay variation, but the largest part of this variation is eliminated by the distributed gate drive structure.

Turning now to FIG. 6, a plan view illustrating an embodiment of a redistribution layer formed as a deposit on a semiconductor die. The redistribution layer (for example, a copper redistribution layer) distributes power and ground nodes across the surface of the semiconductor die and distributes coupling to other circuit nodes of the LDMOS cell. The redistribution layer is also used to distribute the control and monitoring signals to the gate drivers.

The small circles (labeled "SW", "PGND", "PVIN", etc.) couple LDMOS cells and other circuit nodes to one of the conductive (for example, copper) patterned lead frames 420 described above with reference to FIG. 4 or below The position of the elongated metal (for example, copper) post of a lead frame 1179 is described with reference to FIG. 17D. The small circle marked "SW" (one of them is designated 610) is formed to couple the drain of the P-LDMOS cell and the drain of the N-LDMOS cell together and couple these drains to such as in Figure 1 The illustrated output inductor Lout is a circuit node of an external output inductor. The small circle labeled "PVIN" (one of them is designated 620) provides a positive bias voltage to the source of the LDMOS cell forming the high-side P-LDMOS device, and the small circle labeled "PGND" (its One of the others is designated as 630) to provide a local circuit ground for the source of the LDMOS cell forming the low-side N-LDMOS device. At the periphery of the redistribution layer, a small circle labeled "VDDG" (one of which is designated as 640) is used to drive the gate drive inverter of the LDMOS cell (also called "gate driver" or "Driver") supplies a positive bias voltage, and a small circle labeled "PGND" (one of which is designated as 650) grounds the gate drive inverter supply local circuit.

Turning now to FIG. 7, a plan view of the redistribution layer illustrated in FIG. 6 is illustrated, which has an overlay showing an outline of the N-LDMOS device 530 and the P-LDMOS device 531 (see FIG. 5). In addition, the outlines showing the positions of the N gate drive final stage 510 and the P gate drive final stage 520 are also shown. In one embodiment, 220,000 ribbons are used to form the N-LDMOS device 530, each ribbon representing an N-LDMOS cell with a width of about 20 microns and a channel length of about 2 to 3 microns. In one embodiment, 120,000 strips of approximately the same size are used to form the P-LDMOS device 531.

Turning now to FIGS. 8 and 9, an enlarged plan view of the redistribution layer illustrated in FIG. 6 is illustrated. Around the periphery are three paths for gate drive inverters that drive the gates of N-LDMOS cells and P-LDMOS cells. A path 800 provides a positive gate drive bias voltage VDDG bus to the gate drive inverter, and a path 805 provides a local circuit ground for the inverter. A path N_Drv 810 is the gate drive signal generated by the gate drive inverter No. A path N_Drv 830 is on another copper/metal layer and is in electrical communication with path N_Drv 810. The path N_Drv 830 is coupled to the gate of the N-LDMOS cell. Path 820 is further electroplated metal (for example, 20 μm electroplated metal) under the redistribution layer, and path 840 represents 20 μm electroplated metal coupled to the gate polysilicon layer or tape (generally called "gate") of the N-LDMOS cell . Figure 9 illustrates the gate polysilicon ribbon 910 of the N-LDMOS cell. It should be understood that the gate may be formed of other materials such as a conductive metal material.

Turning now to FIG. 10, a schematic diagram illustrating an embodiment of an NMOS inverter chain configured to generate a PWM signal S_PWMGenerate a large amplitude gate drive signal S illustrated in Figure 1 for an N-LDMOS device_DRV2. The even number (for example, four) inverter sequences as illustrated in Fig. 10 are composed of a low-amplitude duty cycle signal S_PWMGenerate a large amplitude gate drive signal S with the same direction_DRV2. The NMOS inverter chain is marked as "N-Gate Drive Final Stage" in Figures 5 and 7, and is distributed around the periphery of the device.

The output stage of the inverter chain is formed by a parallel driving configuration of one of the first inverter 1010 and the second inverter 1020. The first inverter 1010 is formed using a PMOS device 1011 and an NMOS device 1012. The second inverter 1020 is formed using a PMOS device 1021 and an NMOS device 1022. The first inverter 1010 is driven by a third inverter 1030 formed using a smaller MOS device (usually about one third of the size of the MOS device in the first inverter 1010). Similarly, the third inverter 1030 is driven by a fourth inverter 1040 formed using MOS devices (approximately one third of the size of the MOS devices in the third inverter 1030). In this way, the low-level input signal (PWM signal S_PWM) Is continuously amplified in a stage formed using a continuously increasing MOS device to generate the gate drive signal S having a sufficiently large amplitude illustrated in FIG. 1_DRV2To drive the auxiliary switch Q illustrated in Figure 1_aux。

A PMOS inverter chain corresponding to the NMOS inverter chain illustrated in FIG. 10 can be constructed using an even number of inverter stages to input signals from a P-LDMOS device with low amplitude S_PWMGenerate a large amplitude and same-directed gate drive signal. The PMOS inverter chain will therefore operate in a time period that is complementary to the NMOS inverter chain, and the time interval is large enough to avoid illustrating a main switch Q in FIG. 1_mnAnd auxiliary switch Q_auxThe series circuit configuration produces a through current. Although NMOS and PMOS inverter chains using NMOS and PMOS devices have been described, it should be understood that N-LDMOS and P-LDMOS devices can also be used to benefit.

Therefore, as illustrated and described above with reference to the accompanying drawings, a semiconductor device and a method of forming the same have been introduced. In one embodiment, the semiconductor device includes a semiconductor die using a plurality of LDMOS cells, a redistribution layer electrically coupled to the plurality of LDMOS cells, distributed over the redistribution layer and electrically coupled to the redistribution layer A plurality of metal pillars (for example, copper pillars formed as electroplated pillars) and a conductive patterned lead frame of the redistribution layer are electrically coupled by the plurality of metal pillars. The semiconductor device further includes a gate driver electrically coupled to the redistribution layer and to the gates of the plurality of LDMOS cells through the redistribution layer. The semiconductor device is filled with an encapsulant so that part of the conductive patterned lead frame is exposed for use as an external contact of the semiconductor device. The number of external contacts is coupled to a printed circuit board and the number of external contacts (for example, through a through hole on an opposite surface of the printed circuit board) is coupled to a plurality of decoupling devices. At least one of the plurality of decoupling devices is located under the semiconductor die. The number of the external contacts is coupled to the gate driver, the others are electrically coupled to the redistribution layer and through the redistribution layer to the gates of the plurality of LDMOS cells, and the number of the external contacts is coupled to the redistribution layer The drain or source of the plurality of LDMOS cells.

Turning now to FIG. 11, a simplified three-dimensional view of an embodiment of a part of a semiconductor device or part of an implementation of a part of an N-LDMOS device is illustrated. According to standard practices in the semiconductor industry, the various features in these drawings and subsequent drawings are not drawn to scale. In order to make the discussion in this text clear, the size of various features may be increased or decreased arbitrarily, and similar reference numbers may be used for similar features of different devices constituting the semiconductor device. Character.

The N-LDMOS device is formed in a semiconductor die including a lightly doped P substrate 1105 and a P well 1108 implanted in the lightly doped P substrate 1105. The P well 1108 includes doped source regions "s" and drain regions "d" in a sequence of alternating patterns, which are arranged in parallel in the P well 1108 or directly located when the P well 1108 is not implanted. Above the lightly doped P substrate 1105. The source metal (for example, aluminum) strip (one of which is designated as 1111, 1112) is formed in a substantially flat first metal (for example, aluminum) layer M1 and is located above the doped source region "s" and The doped source regions "s" are in electrical contact but are not in contact with each other. Correspondingly, a drain metal (for example, aluminum) strip (one of which is designated as 1121, 1122) is also formed in the first metal layer M1 and is located above the doped drain region "d" and electrically contacts the doped drain. The polar regions "d" are not in contact with each other. Therefore, a plurality of alternating source and drain metal strips are formed on the lightly doped P substrate 1105 in the first metal layer M1, and they are equal to each of the plurality of source and drain regions and (for example, through The silicide layer forms an electrical contact with each of the plurality of source and drain regions. The gate oxide strip (one of them designated as 1140) isolates the gate polysilicon strip (one of them designated as 1150) from the underlying P-well 1108 or with lightly doped P-well 1108 when the optional P-well 1108 is not implanted The miscellaneous P substrate 1105 is isolated. Therefore, a plurality of gate polysilicon ribbons 1150 are formed above the lightly doped P substrate 1105 between one of the plurality of source and drain regions and parallel to one of the plurality of source and drain regions. One gate polysilicon strip 1150 is oriented parallel to the plurality of alternating source and drain metal strips. Figure 11 does not show the additional and different dopants formed in the P well 1108 or the lightly doped P substrate 1105 between the doped source region "s" and the doped drain region "d" and separate them equally. Miscellaneous belt. One of the gate metal (for example, aluminum) strips 1130 in the first metal layer M1 is located above the gate polysilicon strip 1150, is aligned perpendicular to the gate polysilicon strip 1150, and is electrically coupled to the gate polysilicon strip 1150.

Turning now to FIG. 12, there is illustrated a simplified three-dimensional view of a part of the partially constructed N-LDMOS device after forming a substantially flat second metal (e.g., aluminum) layer M2. The second metal layer M2 is formed on the respective source metal formed in the first metal layer M1 Strip 1111, 1112 and the strip above the drain metal strip 1121, 1122 (such as a source metal (e.g., aluminum) strip (one of which is designated as 1160) and a drain metal (e.g., aluminum) strip (these, etc.) One is designated as 1161)). An isolation or insulating layer of silicon oxynitride (see, for example, FIG. 19) separates and electrically isolates the first metal layer from the second metal layer. The source metal strips 1160 in the second metal layer M2 located above the source metal strips 1111 and 1112 in the first metal layer M1 are coupled to the source metal strips 1111 and 1112 by conductive vias. Similarly, the drain metal strips 1161 in the second metal layer M2 located above the drain metal strips 1121 and 1122 in the first metal layer M1 are coupled to the drain metal strips 1121 and 1122 through conductive vias. Therefore, a second plurality of alternating source and drain metal strips are formed on the first metal layer M1 in the second metal layer M2, which are overlying and parallel to the first plurality of alternating source and drain metal strips One of them. The first plurality of source and drain metal strips are electrically coupled to each of the second plurality of alternating source and drain metal strips through vias. The source metal strip 1160 and the drain metal strip 1161 in the second metal layer M2 are not coupled to the gate metal strip 1130 in the first metal layer M1, and the gate metal strip 1130 and the gate polysilicon strip 1150 intersect and are electrically coupled To the gate polysilicon tape 1150.

Turning now to FIG. 13, a simplified plan view of a part of the partially constructed N-LDMOS device after the formation of the second metal layer M2 is illustrated. FIG. 13 illustrates that the source metal strips 1111, 1112, 1113, 1114 in the first metal layer M1 are electrically coupled to the through holes of the source metal strips 1160, 1162 in the second metal layer M2 (one of them is designated 1175). Similarly, vias (one of them designated as 1176) electrically couple the drain metal strips 1121, 1122, 1123, 1124 in the first metal layer M1 to the drain metal strips 1161 in the second metal layer M2. 1163. The through holes 1175, 1176 penetrate an isolation or insulating layer (see (for example) the insulating layer 1915 in FIG. 19), which separates and electrically isolates the first metal layer M1 from the second metal layer M2 (insulation) . It should be noted that in one embodiment, the vias do not electrically couple the gate metal strip 1130 in the first metal layer M1 to the source metal strips 1160, 1162 or the drain metal strip 1161 in the second metal layer M2. 1163.

Turning now to FIG. 14, it is illustrated that the formation of a substantially flat third metal (e.g., After the Al) layer M3, this part constructs a simplified three-dimensional view of one of the parts of the N-LDMOS device. The third metal layer M3 covers the second metal layer M2. FIG. 14 illustrates the N-LDMOS device source contact 1170 formed in the third metal layer M3 and the N-LDMOS device drain contact 1171 also formed in the third metal layer M3. An isolation or insulating layer of silicon oxynitride (see, for example, FIG. 19) separates and electrically isolates the second metal layer from the third metal layer. The N-LDMOS device drain contact 1171 is commonly used for a P-LDMOS device drain contact (also referred to as an "N-LDMOS/P-LDMOS device drain contact" 1171) formed on the same die. The N-LDMOS device source contact 1170 is electrically coupled to the source metal strip (one of them designated as 1160) in the second metal layer M2 by a through hole (for example, an aluminum through hole not shown in FIG. 14). The drain contact 1171 of the N-LDMOS/P-LDMOS device is electrically coupled by a through hole (for example, an aluminum through hole not shown in FIG. 14) to the drain metal strip in the second metal layer M2 (one of which is designated As 1161). Therefore, the source and drain contacts formed in the third metal layer M3 are electrically coupled to one of the second plurality of alternating source and drain metal strips in the second metal layer M2 through the through hole and substantially Cover the plurality of source and drain regions.

Turning now to FIG. 15, a simplified plan view of a part of the partially constructed N-LDMOS device after the formation of the third metal layer M3 is illustrated. FIG. 15 illustrates electrically coupling the source contact 1170 of the N-LDMOS device formed in the third metal layer M3 to the via holes (one of them) of the source metal strips 1160, 1162, 1164 in the second metal layer M2 The person designated as 1180). FIG. 15 also illustrates the connection between the drain contact 1171 of the N-LDMOS/P-LDMOS device formed in the third metal layer M3 and the drain metal strips 1161, 1163, 1165 in the second metal layer M2. Hole (one of them is designated as 1181). It is also shown that the N-LDMOS/P-LDMOS device drain contact 1171 formed in the third metal layer M3 is electrically coupled to the P-LDMOS device drain metal strip 1185 in the second metal layer M2 of a P-LDMOS device. , 1187, 1189 through holes (one of them is designated as 1182). The P-LDMOS source metal strips 1184, 1186, 1188 in the second metal layer M2 of the P-LDMOS device are electrically coupled to one of the P-LDMOS device source contacts in the third metal layer M3 by a through hole (Figure 15 Zhongwei Exhibition Show). The through holes 1180, 1181, 1182 penetrate an isolation or insulating layer (see, for example, the insulating layer 1915 in FIG. 19), which separates and electrically isolates the second metal layer M2 from the third metal layer M3 ( insulation). FIG. 15 also illustrates the gate metal strip 1130 in the first metal layer M1 that intersects with the gate polysilicon strip 1150 (see FIG. 14) and is electrically coupled to the gate polysilicon strip 1150 (see FIG. 14).

Turning now to FIG. 16, a simplified three-dimensional view of an embodiment of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated, which illustrates the source metal in the second metal layer M2 of the partially constructed semiconductor device A geometric shape of belt and drain metal belt. 16 illustrates gate drivers coupled to N-LDMOS and P-LDMOS devices at the periphery of the semiconductor die, such as an N-gate driver 1191 and P-gate driver 1192. Therefore, around the periphery of the semiconductor die, the N-LDMOS device has a plurality of N gate drivers (such as the N gate driver 1191) and the P-LDMOS device has a plurality of P gate drivers (such as the P gate driver 1192). FIG. 16 also illustrates a logic circuit element located at the periphery of the semiconductor die, such as a logic circuit element 1193. The electroplated metal on the second metal layer M2 is overlaid by the through hole as previously described above and is electrically coupled to the respective electroplated metal on the first metal layer M1. To simplify the illustration, the portion of the first metal layer M1 underlying the second metal layer M2 is not illustrated in FIG. 16. Also shown in FIG. 16 is the gate metal strips 1130, 1131 that intersect the gate polysilicon strips (not shown) of the N-LDMOS and P-LDMOS devices in the first metal layer M1 and are electrically coupled to the gate polysilicon strips. For the purpose of the previous drawings, the source metal strip 1160 and the drain metal strip 1161 in the second metal layer M2 of the N-LDMOS device and the source electrode in the second metal layer M2 of the P-LDMOS device are specified in FIG. 16 Metal belt 1184 and drain metal belt 1185.

Turning now to FIG. 17, a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated, which illustrates the source and drain contacts (ie, conductive regions) in the third metal layer M3 One of geometric shapes. The light P-doped substrate 1105 is illustrated in FIG. 17, but the optional P-well located in the upper part of one of it is not shown. N- The LDMOS/P-LDMOS device drain contact 1171 is located between the N-LDMOS device source contact 1170 and a P-LDMOS device source contact 1172 in the third metal layer M3. FIG. 17 also illustrates gate drivers and logic circuit element contacts (one of which is designated as 1173) located at the periphery of the semiconductor device in the third metal layer M3.

Turning now to FIG. 17A, a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated. Hole, one of them is designated as 1174) one of geometric shapes. The copper via 1174 provides electrical contact between the third metal layer M3 and the redistribution layer. The copper via 1174 penetrates an isolation or insulating layer (see, for example, the first polyimide layer 1935 in FIG. 19), which separates and electrically isolates (insulates) the third metal layer M3 from the redistribution layer.

Turning now to FIG. 17B, a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated, which illustrates a geometry of a redistribution layer (eg, a copper redistribution layer) 1177. The redistribution layer 1177 is shown as the electroplated metal patterned on the respective electroplated metal on the third metal layer M3 and electrically coupled to the third metal layer M3 by the copper via 1174 (see FIG. 17A). In addition, the redistribution layer 1177 is separated from the third metal layer M3 by an isolation layer or insulating layer (see FIG. 19).

Turning now to FIG. 17C, a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated, which illustrates the pillars of the redistribution layer 1177 (eg, copper pillars, one of which is designated 1178 ) Is a geometric shape. Copper pillars 1178 provide electrical contact between the redistribution layer 1177 and a conductive patterned lead frame.

Turning now to FIG. 17D, a simplified three-dimensional view of a partially constructed semiconductor device including N-LDMOS and P-LDMOS devices is illustrated, which illustrates a geometric shape of a conductive patterned lead frame 1179. The lead frame 1179 is shown as being patterned over the redistribution layer 1177 and electrically coupled to the redistribution layer 1177 by copper pillars 1178 (see FIG. 17C).

Turning now to FIG. 18, it illustrates the three-dimensional exterior of an embodiment of a semiconductor device (filled with an encapsulant such as epoxy) including one of N-LDMOS and P-LDMOS devices Department view. A portion of the lead frame 1179 (see FIG. 17D) is exposed for use as an external contact of the semiconductor device. An external N-LDMOS/P-LDMOS device drain contact 1194 is located between an external N-LDMOS device source contact 1195 and an external P-LDMOS device source contact 1196, and an external gate driver and logic circuit Element contacts (one of them designated as 1197) is located around the periphery of one of the semiconductor devices. In one embodiment, a usable filling material is an encapsulant such as epoxy resin, but other filling materials including filling materials with enhanced thermal properties are expected to be within the broad scope of the present invention. The external electrical contact surface of the semiconductor device can be coated with a copper scintillation layer/seed layer and then electroplated with copper to form a metal surface that can be easily soldered. The outer surface can also be plated with a thin gold layer or other inert metal or alloy layer to provide a further passivation level for welding or other adhesion procedures. As illustrated and described with respect to FIG. 4, the filled or packaged semiconductor device of FIG. 18 can be placed on a printed circuit board closest to a decoupling device to provide the advantages as stated above.

Turning now to FIG. 19, a front view of an embodiment of a portion of a semiconductor device including an N-LDMOS and/or P-LDMOS device is illustrated. N-LDMOS and/or P-LDMOS devices are formed in a semiconductor die including a well 1910 located above a lightly doped substrate 1905, and doped source regions "s" and drain regions " d" is located in it. The first metal layer M1, the second metal layer M2, and the third metal layer M3 are separated and insulated from each other by a silicon oxynitride layer (generally designated as 1915), and are located in the doped source region "s" and the doped drain Above area "d" and isoelectric contact with it. Vias (one of them designated 1920) provide electrical contact between the plated metal on the first metal layer M1 and the second metal layer M2. Vias (one of them designated 1925) provide electrical contact between the plated metal on the second metal layer M2 and the third metal layer M3. Copper vias (one of them designated as 1930) are formed in a first polyimide layer 1935 to form a copper redistribution layer on the third metal layer M3 and the first polyimide layer 1935 Provide electrical contact between 1940. Copper pillars (one of them designated as 1945) are formed in a second polyimide layer 1950 to be between the copper redistribution layer 1940 and a copper lead frame 1955 formed on the second polyimide layer 1950 Provide electrical contact between. It should be understood that the specific materials of the respective layers are only examples and other materials with similar properties can be used to benefit.

Therefore, as illustrated and described above with reference to the accompanying drawings, a semiconductor device and a method of forming the same have been introduced. In one embodiment, the semiconductor device includes using a plurality of LDMOS cells to form a semiconductor die, a metal layer electrically coupled to the plurality of LDMOS cells (for example, a plurality of copper layers forming a redistribution layer), and a semiconductor die along the semiconductor crystal. One of the dies is located peripherally and electrically coupled to the gate driver of the plurality of LDMOS cells through the metal layer (e.g., includes one of the gate drivers formed as the driver switch of the MOS device). The metal layer is used to couple one of the gate drivers to a gate driving bias voltage and to control and monitor signals. The semiconductor device also includes a plurality of metal pillars distributed over the metal layer and electrically coupled to the metal layer; and a conductive patterned lead frame electrically coupled to the plurality of metal pillars. The semiconductor device is filled with an encapsulant so that part of the conductive patterned lead frame is exposed for use as an external contact of the semiconductor device. One of the external contacts is coupled to a plurality of decoupling devices through a through hole on an opposite surface of a printed circuit board. One of the external contacts is coupled to the gate driver through the metal layer, and one of the external contacts is coupled to the drain or source of the plurality of LDMOS cells through the metal layer.

Turning now to FIG. 20, a cross-sectional view of an embodiment of an N-LDMOS device embodied in a semiconductor device or part thereof is illustrated. Although some layers of the N-LDMOS device will be described with respect to FIG. 20, one of the procedures for constructing these layers will also be explained in more detail with respect to FIG. 21 and other drawings. An N-LDMOS device is formed in a semiconductor die containing a P-doped semiconductor substrate (also referred to as a "substrate") 2005, and an optional epitaxial layer (for example, a light Doped P-type epitaxial layer, not shown). Although the substrate 2005 is a P-type substrate in the illustrated embodiment, those skilled in the art should understand that the substrate 2005 may be an N-type substrate without departing from the scope of the present invention.

The N-LDMOS device is composed of a plurality of N-LDMOS cells (such as illustrated in Figure 20 The N-LDMOS cell 2001) is formed. The N-LDMOS device includes a P-type well 2015 and a heavily doped P-type region 2090 formed above the P-type well 2015. A heavily doped N-type region 2060, 2080 is formed on either side of or on the heavily doped P-type region 2090. The heavily doped N-type region 2060 is formed to have a lower doping density than the heavily doped N-type region 2080, especially in a lateral direction away from the heavily doped N-type region 2080. The heavily doped N-type regions 2060 and 2080 provide an ohmic junction through the silicide layer 2115 formed thereon. The silicide layer 2115 provides a strongly conductive junction between the heavily doped N-type regions 2060, 2080 and a first metal (e.g., aluminum) layer M1 to ultimately provide a source contact (designated as " Bond the source (contact)"). The heavily doped N-type region 2080 above the heavily doped P-type region 2090 is relatively thin (for example, about 10 Å to 100 Å) so that it is formed between the heavily doped N-type region 2080 and the heavily doped P-type region 2090 The resulting PN junction will essentially be an ohmic junction that is strongly conductive in both directions. Therefore, the PN junction formed between them cannot be used as a diode. Similarly, the silicide layer 2115 provides a strongly conductive junction between the heavily doped N-type region 2080 and the first metal layer M1 to finally provide a drain contact for the N-LDMOS device (designated as "bonding drain (contact Pieces)"). The source and drain of the first metal layer M1 is made of, for example, amorphous silicon silicon oxynitride ("Si_xO_yN_z") One of the insulating layers of the layer 2120 is separated.

A P-type region 2055 is formed near the heavily doped N-type region 2060 and the heavily doped P-type region 2090 in the P-type well 2015. A channel region 2003 is formed under the gate between the heavily doped N-type region 2060 and the lightly doped N-type region 2070. The P-type region 2055 is formed in the P-type well 2015 by ion implantation at an angle deviated from the vertical under the gate formed on the channel region 2003, and the P-type region 2055 is used to control the N-LDMOS One of the threshold voltages of the device.

The gate system is formed with a gate polysilicon layer 2025, which has an underlying gate oxide layer 2020 and an overlying gate oxide layer 2030 and sidewall spacers (one of which is designated as 2040). The gate polysilicon layer 2025 on the channel region 2003 controls the conductivity level therein. The underlying gate oxide layer 2020 is on the gate polysilicon layer 2025 An isolation layer is formed between the P-type well 2015 and the P-type region 2055. A portion of the overlying gate oxide layer 2030 above the gate polysilicon layer 2025 is removed and a silicide layer 2115 is formed above the portion to reduce the gate resistance.

Therefore, the gate polysilicon layer 2025 (together with the silicide layer 2115) forms a gate polysilicon strip 1150 across many N-LDMOS cells of the N-LDMOS device and is coupled to the gate metal strip 1130 in the first metal layer M1 (see (eg ) Figure 11). The gate metal tape 1130 is routed to a plurality of gate drivers located at the periphery of the semiconductor device (see, for example, FIG. 16). By coupling the gate metal strip 1130 (which has a conductivity substantially greater than that of the gate polysilicon strip 1150) in the first metal layer M1 to the plurality of gate drivers, the gate of the N-LDMOS unit Extremely enables a substantially time-aligned switching signal.

In view of the large amount of effective capacitance generated between the gate, source and drain, it is an important design consideration to provide a time-aligned switching signal to the plurality of gates of individual N-LDMOS cells. This capacitance requires a large number of gates. Extremely drive current to achieve a fast switching transition. Failure to generate a time-aligned gate drive signal for the gates of individual N-LDMOS cells can enable other N-LDMOS cells to be turned on before turning on some N-LDMOS cells, which forces the cells that were switched early to be shifted in time during the switching transition. Conduct high current pulses. Dislocation of high current pulses in time exposes the N-LDMOS cell to device failure.

The illustrated structure also enables the use of substantially the same structure in a common semiconductor die to form N-LDMOS and P-LDMOS devices, and enables the use of a low inductance, high current path to couple each LDMOS type to an external circuit. Each LDMOS is formed to have a single large source contact and a single large and shared drain contact (see, for example, FIG. 17), which can simplify the circuit board layout and adhesion problems of an external circuit. Large source and drain contacts are easily overlaid with a copper redistribution layer that has substantially the same area as the large source and drain contacts (see (for example) Figure 17B), and finally overlaid with a wire Block (see (for example) FIG. 17D), which further improves conductivity and couples a packaged semiconductor device (see (for example) FIG. 18) to an external circuit. The source contact and the common drain contact are covered with N- The substantially entire active area of the LDMOS and P-LDMOS devices makes the high-current contacts that are not overlying the active switching area waste less die area.

Regarding the N-LDMOS cell 2001, the source (or source region) is specifically implemented in at least the heavily doped N-type region 2060, and the drain (or drain region) is specifically implemented in the lightly doped N-type region 2070 (for example, a lightly doped drain ("LDD") region) and an adjacent heavily doped N-type region 2080 opposite to the channel region 2003. The gate resides on the channel area 2003 with the layer as described in this article. The LDD region provides the N-LDMOS device with a breakdown voltage higher than that of the conventional design. These regions are formed in the order of "heavy doped source region", "gate", "lightly doped drain region" and "heavy doped drain region". A structure similar to the structure described with respect to FIG. 88 and other drawings is adopted in the P-LDMOS device.

Turning now to FIGS. 21 to 87, cross-sectional views illustrating an embodiment of an N-LDMOS device embodied in a semiconductor device or part thereof are illustrated. Starting in FIG. 21, an N-LDMOS device is formed in a semiconductor die containing a P-doped semiconductor substrate (also referred to as a "substrate") 2005, and an optional epitaxial layer can be grown on a surface of the substrate (For example, a lightly doped P-type epitaxial layer, not shown). The substrate 2005 is preferably lightly doped with P (for example, boron) between 1.10¹⁴Atoms/cm³And 1.10¹⁶Atoms/cm³between. Especially when the substrate 2005 is a lightly doped P-type substrate, it is not necessary to grow an optional epitaxial layer on the substrate 2005. Although the substrate 2005 is a P-type substrate in the illustrated embodiment, those skilled in the art should understand that the substrate 2005 may be an N-type substrate without departing from the scope of the present invention.

The substrate 2005 is formed with isolation regions (for example, shallow trench isolation regions 2010). The shallow trench isolation region 2010 can also be formed in a substrate or grown in an epitaxial layer on the substrate to provide dielectric isolation between devices implemented on the substrate or on the epitaxial layer. The shallow trench isolation regions 2010 are formed by coating, patterning and etching the substrate 2005 using a photoresist to define respective regions therein. An exemplary photoresist is an AZ electronic material photoresist. Then etch and use a combination such as silicon dioxide, silicon nitride, or any other suitable The dielectric, one of the dielectric materials, backfills the shallow trench isolation region 2010. Then, the epitaxial layer of the substrate 2005 and the shallow trench isolation region 2010 are planarized by a thinning process such as a chemical mechanical planarization ("CMP") thinning process to planarize the device while constraining the surface of the die destroy. The steps of masking, etching, dielectric backfilling, and thinning are widely known in the art and will not be described in further detail below.

The P-type substrate 2005 is divided into dielectric separation regions by the shallow trench isolation region 2010 to accommodate a plurality of N-LDMOS and P-LDMOS devices and gate drivers in the illustrated embodiment and embedded on the P-type substrate 2005 Other PMOS and NMOS devices used as low-voltage devices in control circuits. The low-voltage device may be operated in, for example, a controller of a power converter (for example, in a control and signal processing device that may be formed on the surface of a semiconductor device). Further, P-type substrate 2005 may be used to accommodate (for example) a power system and a power converter (i.e., the power switch and the driver switch) within one of the higher power drive N-LDMOS means of pressure and the P-LDMOS device.

Turning now to FIG. 22, the P-type well 2015 is formed by coating and patterning a photoresist mask (not shown) and then etching the photoresist mask to define the area occupied by the P-type well 2015. (For example, at a control energy of about 100 kiloelectron volts ("keV") to 300 keV) the P-type well 2015 is formed by an ion implantation process of an appropriate P-type dopant species such as boron, and results in relatively high The best place is about 1.10¹⁷Atoms/cm³To 2.10¹⁹Atoms/cm³A doping concentration distribution in a range.

Turning now to FIG. 23, a gate oxide layer 2020 (an insulating layer) is formed on the surface of the semiconductor device that meets a thickness of the expected operating voltage of the gate. The gate oxide layer 2020 is usually silicon dioxide formed by, for example, placing a wafer on which silicon devices are formed in an oven; and using a feature size of about 0.25 microns ("μm") A device operating at a low gate voltage (for example, 2.5 volts) causes the exposed surface of the wafer to interact with oxygen or other suitable materials with a thickness of about 30 Angstroms ("Å") to 50 Å at 500°C to 900°C The reaction lasts from 10 minutes to 100 minutes (such as to produce a high κ (dielectric constant) Stacked). Assuming that the gate-source voltage limit of N-LDMOS and P-LDMOS devices is limited to a voltage (for example, about 2.5 volts), a gate dielectric layer thickness as stated above can be used to form a gate oxide layer 2020. Preferably, the gate oxide layer 2020 is constructed to have a uniform thickness to provide the devices with a gate-source rated voltage of approximately 2.5 volts that fully or almost completely saturates the forward conductive properties of the devices. Of course, the aforementioned gate voltage ranges of these devices are provided for illustrative purposes only, and other voltage ranges are expected to fall within the broad scope of the present invention.

Turning now to FIG. 24, a gate polysilicon layer 2025 is deposited over a surface of the gate oxide layer 2020 and used in a subsequent processing step such as having a thickness of about 1.10¹⁹To 5.10²⁰A suitable doping species (such as arsenic) of a doping density in a range performs N-type (or P-type) doping on the gate polysilicon layer 2025 to obtain an appropriate level of conductivity. Anneal the gate polysilicon layer 2025 at a high temperature in an oven (for example, at a temperature ranging from 800 degrees Celsius ("°C") to 1000°C for 2 minutes to 60 minutes) to properly diffuse and activate the dopants . The gate polysilicon layer 2025 may have a thickness ranging from about 100 nanometers to about 500 nanometers, but may have a smaller or larger thickness range depending on an application.

Turning now to FIG. 25, an overlying gate oxide layer 2030 (an insulating layer) is formed on one of the upper surfaces of the gate polysilicon layer 2025 by the following operations: a wafer on which silicon devices are formed is placed in an oven; And make the exposed surface of the gate polysilicon layer 2025 react with oxygen at a high temperature (for example, at a temperature of 500°C to 900°C for 1 minute to 60 minutes). The overlying gate oxide layer 2030 may be formed to have a thickness of about 50 Å to 500 Å.

Turning now to FIG. 26, the gate oxide layer 2020, the gate polysilicon layer 2025, and the overlying gate oxide layer 2030 are patterned and etched to define and form their horizontal dimensions. A photoresist mask is used with an etching to define the lateral dimensions of the gate polysilicon layer 2025, the gate oxide layer 2020, and the overlying gate oxide layer 2030. In the following figures, only reference numerals are used to designate one of the gate polysilicon layer 2025 and the gates of the underlying and overlying gate oxide layers 2020 and 2030. An exemplary photoresist is AZ electronic material photoresist. Patterned and etched to define and The steps of forming the horizontal dimensions of the gate polysilicon layer 2025 and the underlying and overlying gate oxide layers 2020 and 2030 are well known in the art and will not be described in further detail below. In an alternative embodiment, the gate polysilicon layer 2025 may include or be formed in other ways to have a variety of materials, including various metals, other doped semiconductors, or other conductive materials. It should be noted that the horizontal dimensions of the gate polysilicon layer 2025 and the underlying and overlying gate oxide layers 2020 and 2030 can be masked and etched in the same processing steps, and one of N-LDMOS and P-LDMOS formed on the same silicon Various other structures of both devices.

Turning now to Figure 27, silicon nitride ("Si₃N₄") An overlying layer of 2035 (an insulating layer). The deposition of a cladding layer on silicon nitride 2035 over the semiconductor device is a conventional process in the art and will not be described further herein.

Now turning to FIG. 28, almost everywhere (except for the silicon nitride layer 2035 and the sidewall adjacent to the gate polysilicon layer 2025, the underlying oxide layer 2020 and the overlying oxide layer 2030, which are adjacent to the vertical thick portion), the nitrogen is etched back. Overlay on silicon 2035. In this way, in a self-aligned process without masking and etching a photoresist, the silicon nitride layer 2035 adjacent to the gate polysilicon layer 2025 and the underlying oxide layer 2020 and the overlying oxide layer 2030 A sidewall spacer (one of them is designated as 2040) is formed.

Turning now to FIG. 29, a photoresist 2045 is coated, patterned, and etched in a subsequent processing step to define the source region of the N-LDMOS device so that P-type ions such as boron ions can be implanted into selected regions of the semiconductor device middle. The photoresist is etched to expose half of the width of a gate, which is about 0.2μm (designated as 2050) to meet the tolerance issues when patterning and etching the photoresist. Therefore, the lateral position of the P-type ion implantation is controlled by using a photoresist mask, one of the techniques known in the art. The steps of coating, patterning, and etching a photoresist are widely known in the art and will not be described in further detail herein.

Turning now to Figure 30, implant P-type ions (for example, about 5.10 at a control energy of about 20 keV to 100 keV)¹⁷Atoms/cm³To 1.10¹⁹Atoms/cm³) To form a P-type region 2055. The P-type region 2055 is ion-implanted by a suitable atomic species (such as boron) to Make the formed N-LDMOS device reach an available gate threshold voltage.

Turning now to FIG. 31, N-type ions (for example, arsenic) are implanted to form a heavily doped N-type region 2060. The heavily doped N-type region 2060 is implanted (for example, under a control energy of about 5 keV to 50 keV) with a preferably 5.10¹⁸Atoms/cm³To 1.10²⁰Atoms/cm³A doping concentration distribution in a range to enable the formed N-LDMOS device to achieve a low source resistance. After the photoresist 2045 is stripped off as illustrated in FIG. 32, (for example, in an oven at a temperature of 700°C to 1000°C for 1 minute to 60 minutes) the semiconductor device is annealed to reshape the P-type region 2055 and The doped N-type region 2060 is converted into an active substrate site.

Turning now to FIG. 33, a photoresist 2065 is coated, patterned, and etched so that a gate polysilicon layer 2025 and an underlying oxide layer 2020 and an overlying oxide layer 2030 can be formed at a subsequent processing step. N-type ions are selectively implanted in the intermediate region. As illustrated in FIG. 34, N-type ions (eg, arsenic ions) are implanted between the gates to form a lightly doped N-type region 2070. In one embodiment, the implantation density of the lightly doped N-type region 2070 is preferably 1.10¹⁷Atoms/cm³To 1.10¹⁹Atoms/cm³It is implanted in the range of 10keV to 200keV at a controlled energy.

After stripping off the photoresist 2065 as illustrated in FIG. 35, the semiconductor device is annealed in an oven to convert the lightly doped N-type region 2070 into the active substrate site (for example, continuous at a temperature of 700°C to 1000°C) 1 minute to 60 minutes). Turning now to FIG. 36, a photoresist 2075 is coated, patterned, and etched for subsequent use in the area between the gate formed by the gate polysilicon layer 2025 and the underlying oxide layer 2020 and the overlying oxide layer 2030 Selective implantation of ions.

Turning now to FIG. 37, a heavily doped N-type region 2080 is implanted into the semiconductor device. In one embodiment, the heavily doped N-type region 2080 is doped to about 1.10 using, for example, arsenic.¹⁹Atoms/cm^-3To 5.10²⁰Atoms/cm^-3A density in a range, and implantation is performed under a control energy of 10 keV to 100 keV. At the same time, similar use has about 1.10¹⁹To 5.10²⁰Arsenic with a doping density in a range is N-type doped to the gate polysilicon layer 2025 to obtain Get an appropriate level of gate conductivity. After stripping off the photoresist 2075 as illustrated in FIG. 38, the semiconductor device is annealed in an oven (for example, at a temperature of 700°C to 1000°C for 1 minute to 60 minutes) to remove the heavily doped N-type region The 2080 is converted to the role of the substrate.

Turning now to FIG. 39, a photoresist 2085 is coated, patterned, and etched in a subsequent step for subsequent selective implantation in a selected region between the source region and the drain region of the N-LDMOS device P-type ion. As illustrated in FIG. 40, ion implantation using boron, for example, forms a heavily doped P-type region 2090. In one embodiment, the heavily doped P-type region 2090 is doped to about 1.10¹⁹Atoms/cm^-3To 5.10²⁰Atoms/cm^-3One density, and implantation is performed under a control energy of 5keV to 50keV. After stripping off the photoresist 2085 as illustrated in FIG. 41, the semiconductor device is annealed in an oven (for example, at a temperature of 700° C. to 1000° C. for 1 minute to 60 minutes) to add the heavily doped P-type The area 2090 is converted into an active substrate site. The heavily doped N-type region 2080 on the heavily doped P-type region 2090 is relatively thin (for example, about 10 Å to 100 Å).

Turning now to Fig. 42, in (for example) a chamber with oxygen and silicon source gas at 550°C to 900°C for 30 minutes to 90 minutes, a low-temperature silicon dioxide ("SiO₂") Layer 2095 (an insulating layer). To avoid silicidation of the N-type area on the surface, a low-temperature silicon dioxide layer 2095 is deposited and then the photoresist is coated and processed to use a self-aligned block ("SAB", a self-aligned silicide/self-aligned silicide) Object block) defines the area where silicide will be formed. Silicide is formed only on exposed silicon. In which silicon is covered by a layer of SiO₂In the covered area, no silicide layer will be formed.

Turning now to FIG. 43, a photoresist 2100 is patterned and etched to enable the formation of silicide regions over selected areas of the semiconductor device (illustrated half of the gate width 2050 for subsequent processing). After etching the low temperature silicon dioxide layer 2095 as illustrated in FIG. 44, the silicon dioxide region 2105 remains. The overlying gate oxide layer 2030 is also partially removed as illustrated in FIG. 44. As illustrated in FIG. 45, a non-reactive refractory metal 2110 is coated on the surface of the semiconductor device. Exemplary refractory metals include tungsten, titanium, and cobalt. use A low temperature baking (for example, at a temperature of 400°C to 550°C for 1 minute to 20 minutes), followed by a high temperature annealing (for example, at a temperature of 600°C to 800°C for 1 minute to 20 minutes), A silicide (for example, having a thickness preferably in the range of 100 angstroms ("Å") to 800 Å) is formed over the exposed silicon and polysilicon surfaces to reduce the resistance of the silicide sheet.

Turning now to FIG. 46, a wet etch is used to etch the non-reactive refractory metal 2110, leaving the silicide layer 2115. The portion of the silicide layer 2115 formed above the exposed area of silicon and polysilicon is substantially non-responsive to wet etching and will not be removed by wet etching. An exemplary wet etching system is aqua regia (a mixture of nitric acid and hydrochloric acid). In one embodiment, the silicide layer 2115 of the overlying gate polysilicon layer 2025 is electrically coupled to the gate metal strip 1130 formed in a first metal layer M1 (as discussed with respect to FIG. 11 and other figures).

Turning now to FIG. 47, a plasma deposition process is used to deposit an amorphous silicon silicon oxynitride ("Si_xO_yN_z") Layer 2120 (an insulating layer). The use of a plasma deposition process to form an amorphous silicon silicon oxynitride layer 2120 is well known in the art and will not be described further herein. As illustrated in FIG. 48, a photoresist layer 2125 is deposited on the amorphous silicon silicon oxynitride layer 2120. In a subsequent processing step, the photoresist layer 2125 is patterned and etched to expose portions of the silicide layer 2115.

Turning now to FIG. 49, a suitable etch such as a reactive ion etching ("RIE") is used to etch the amorphous silicon silicon oxynitride layer 2120 to expose portions of the silicide layer 2115. As illustrated in FIG. 50, the remaining portion of the photoresist layer 2125 is stripped off. Next, a first metal (for example, aluminum) layer M1 is vacuum deposited over the surface of the semiconductor device as illustrated in FIG. 51.

Turning now to FIG. 52, an etch stop refractory layer 2130 is deposited on the first metal layer M1. In one embodiment, the etch stop refractory layer 2130 is made of titanium nitride, cobalt nitride, or tungsten nitride. The procedure for depositing an etch stop refractory layer over an aluminum layer is well known in the art and will not be described further herein. As illustrated in FIG. 53, a photoresist layer 2135 is deposited over the semiconductor device, and then the photoresist layer 2135 is patterned and etched to cover the first An area of the metal layer M1 to be retained. Thereafter, a suitable etch such as an RIE is used to remove the exposed area of the etch stop refractory layer 2130 and the exposed area of the first metal layer M1 as illustrated in FIG. 54. In addition, the remaining portion of the photoresist layer 2135 is stripped, thereby exposing the remaining portions of the etch stop refractory layer 2130 and the amorphous silicon oxynitride layer 2120 as illustrated in FIG. 55.

Turning now to FIG. 56, another silicon oxynitride layer 2140 (an insulating layer) is deposited over the semiconductor device and planarized by chemical mechanical planarization. As illustrated in FIG. 57, a photoresist layer 2145 is deposited and patterned over the silicon oxynitride layer 2140 to enable the formation of low resistance metal source and drain contacts of N-LDMOS in a series of processing steps. Thereafter, the silicon oxynitride layer 2140 is etched down to the etch stop refractory layer 2130 as illustrated in FIG. 58. An exemplary silicon oxynitride etchant device uses hexafluoroethane (``C₂F₆")gas.

Turning now to FIG. 59, the photoresist layer 2145 is stripped off. Thereafter, a second metal (for example, aluminum) layer M2 is vacuum deposited over the surface of the semiconductor device as illustrated in FIG. 60. An etch stop refractory layer 2150 is deposited on the second metal layer M2 as illustrated in FIG. 61. In one embodiment, the etch stop refractory layer 2150 is made of titanium nitride, cobalt nitride, or tungsten nitride. As illustrated in FIG. 62, a photoresist layer 2155 is deposited and patterned over the etch stop refractory layer 2150 to cover the area to be retained in the second metal layer M2. Thereafter, as illustrated in FIG. 63, a suitable etch such as an RIE is used to remove the exposed area of the etch stop refractory layer 2150 and the exposed area of the second metal layer M2. In addition, the remaining portion of the photoresist layer 2155 is stripped, thereby exposing the remaining portions of the etch stop refractory layer 2150 and the silicon oxynitride layer 2140 as illustrated in FIG. 64.

Turning now to FIG. 65, another silicon oxynitride layer 2160 (an insulating layer) is deposited over the semiconductor device and planarized by chemical mechanical planarization. As illustrated in FIG. 66, a photoresist layer 2165 is deposited and patterned over the silicon oxynitride layer 2160 to cover the area of the silicon oxynitride layer 2160 to be retained. FIG. 67 illustrates the process of etching the silicon oxynitride layer 2160 until the etching stops. The part after the refractory layer 2150 completes the semiconductor device. Thereafter, the photoresist layer 2165 is stripped off as illustrated in FIG. 68.

Turning now to FIG. 69, a third metal (e.g., aluminum) layer M3 is then vacuum deposited over the surface of the semiconductor device. As illustrated in FIG. 70, a photoresist layer 2165 is deposited and patterned to cover the area to be retained in the third metal layer M3. Thereafter, as illustrated in FIG. 71, a suitable etching such as an RIE is used to remove the exposed area of the third metal layer M3. In addition, the remaining part of the photoresist layer 2165 is stripped, thereby exposing the remaining part of the third metal layer M3 and the silicon oxynitride layer 2160 as illustrated in FIG. 72.

Turning now to FIG. 73, a final silicon oxynitride layer 2170 (an insulating layer) is deposited over the semiconductor device and planarized by chemical mechanical planarization. As illustrated in FIG. 74, a photoresist layer 2175 is deposited and patterned over the silicon oxynitride layer 2170 to cover the area to be retained. Thereafter, a suitable etching such as an RIE is used to remove the exposed area of the silicon oxynitride layer 2170, thereby exposing the remaining part of the third metal layer M3 as illustrated in FIG. 75. In addition, the remaining part of the photoresist layer 2175 is stripped, thereby exposing the remaining part of the silicon oxynitride layer 2170 as illustrated in FIG. 76.

Turning now to FIG. 77, a polyimide coating 2180 (an insulating layer) is deposited over the semiconductor device. As illustrated in FIG. 78, a photoresist layer 2185 is deposited and patterned over the polyimide coating 2180 to cover the area of the third metal layer M3 above the drain of the N-LDMOS device. Thereafter, a suitable etching is used to remove the exposed area of the polyimide coating 2180, thereby exposing the remaining part of the third metal layer M3 on the source of the N-LDMOS device as illustrated in FIG. 79. In addition, the remaining part of the photoresist layer 2185 is stripped off, thereby exposing the remaining part of the polyimide coating 2180.

Turning now to FIG. 80, a refractory barrier layer 2190 (for example, titanium nitride, tantalum nitride, or cobalt nitride) is deposited over the semiconductor device. Next, a thin metal (for example, copper) seed layer 2195 is deposited over the refractory barrier layer 2190 as illustrated in FIG. 81. Then, the copper seed layer 2195 is electroplated as illustrated in FIG. 82 to form an electroplated copper layer 2200. After that, as shown in Figure 83 Illustratively, another polyimide coating 2205 (an insulating layer) is deposited over the copper layer 2200.

Turning now to FIG. 84, a photoresist layer 2210 is deposited and patterned over the polyimide coating 2205. The photoresist layer 2210 is etched and the underlying polyimide coating 2205 is etched to expose the underlying copper layer 2200 above the source of the N-LDMOS device. Thereafter, another thin metal (for example, copper) seed layer 2215 is deposited over the semiconductor device. Depositing the copper seed layer 2215 is used to create a new surface for the subsequent electrodeposition of metal (eg, copper) pillars as an optional step. Thereafter, the photoresist layer 2210 is peeled off from the semiconductor device as illustrated in FIG. 86 (in which a part of the copper seed layer 2215 is covered with the photoresist layer 2210).

Turning now to FIG. 87, metal (eg, copper) pillars 2220 are formed by an electroplating process using an acid solution. As illustrated and described above with reference to FIG. 4, the copper pillars 2220 are used as low-resistance source contacts to a conductive patterned lead frame to complete the traces to which the terminals of the semiconductor device can be soldered. Corresponding steps can be used in conjunction with the steps described above for constructing source contacts to form low-resistance drain contacts of N-LDMOS devices. In addition, an encapsulant (for example, an epoxy resin) 2225 can be selectively deposited between the copper pillar 2220 and a patterned lead frame 2230 placed above the copper pillar 2220 to produce an exterior for an encapsulated semiconductor device Contact (e.g. (see) Figure 18).

Turning now to FIG. 88, a cross-sectional view of an embodiment of a P-LDMOS device embodied in a semiconductor device or part thereof is illustrated. Although some layers of the P-LDMOS device will be described with respect to FIG. 88, one of these layers will also be described with respect to FIG. 89 for more detailed explanation. In addition, because many of the process steps for building a semiconductor device including a P-LDMOS device are similar to the process steps for building a semiconductor device including the N-LDMOS device stated above, the following discussion will be limited to forming the layers of the P-LDMOS device.

A P-LDMOS device is formed in a semiconductor die containing a P-doped semiconductor substrate (also referred to as a "substrate") 8005, and an optional epitaxial layer (for example, a light Doped P-type epitaxial layer, not shown). Although the substrate 8005 is a P-type substrate in the illustrated embodiment, those skilled in the art should understand that Without the scope of the present invention, the substrate 8005 may be an N-type substrate.

The P-LDMOS device is formed by a plurality of P-LDMOS cells (such as the P-LDMOS cell 8001 illustrated in FIG. 88). The P-LDMOS device includes a lightly doped N-type well 8015 on which an N-type well 8017 is formed. The N-type well 8017 has a heavily doped N-type region 8090 formed therein. A heavily doped P-type region 8060, 8080 is formed on either side of or above the heavily doped N-type region 8090. The heavily doped P-type region 8060 is formed to have a lower doping density than the heavily doped P-type region 8080, especially in a lateral direction away from the heavily doped P-type region 8080. The heavily doped P-type regions 8060 and 8080 provide an ohmic junction through the silicide layer 8115 formed thereon. The silicide layer 8115 provides a strong conductive junction between the heavily doped P-type regions 8060, 8080 and a first metal (e.g., aluminum) layer M1 to ultimately provide source contacts (designated as " Bond the source (contact)"). The heavily doped P-type region 8080 above the heavily doped N-type region 8090 is relatively thin (for example, about 10 Å to 100 Å) so that it is formed between the heavily doped P-type region 8080 and the heavily doped N-type region 8090. The resulting PN junction will essentially be an ohmic junction that is highly conductive in both directions. Therefore, the PN junction formed between them cannot be used as a diode. Similarly, the silicide layer 8115 provides a strongly conductive junction between the heavily doped P-type region 8080 and the first metal layer M1 to finally provide a drain contact for the P-LDMOS device (designated as "bonding drain (contact Pieces)"). The source and drain of the first metal layer M1 is made of, for example, amorphous silicon silicon oxynitride ("Si_xO_yN_z") The insulating layer of layer 8120 is separated.

An N-type region 8055 is formed in the N-type well 8017 near the heavily doped P-type region 2060 and the heavily doped N-type region 8090. A channel region 8003 is formed under the gate between the heavily doped P-type region 8060 and the lightly doped P-type region 8070. The N-type region 8055 is formed in the N-type well 8017 by ion implantation under the gate formed on the channel region 8003 at an angle deviated from the vertical plane, and is used to control a threshold of the P-LDMOS device Voltage.

These gates are formed with a gate polysilicon layer 8025. The gate polysilicon layer 8025 has an underlying gate oxide layer 8020 and an overlying gate oxide layer 8030 on the periphery, as well as between the sidewalls. Spacer (one of them is designated as 8040). The gate polysilicon layer 8025 above the channel region 8003 controls the conductivity level therein. The underlying gate oxide layer 8020 forms an isolation layer between the gate polysilicon layer 8025 and the N-type well 8017 and the N-type region 8055. A portion of the overlying gate oxide layer 8030 above the gate polysilicon layer 8025 is removed and a silicide layer 8115 is formed above the portion to reduce the gate resistance.

Therefore, the gate polysilicon layer 8025 (together with the silicide layer 8115) forms a gate polysilicon strip across many P-LDMOS cells of the P-LDMOS device and is coupled to the gate metal strip 1131 in the first metal layer M1 (see (for example) Figure 16). The gate metal tape 1131 is routed to a plurality of gate drivers located at the periphery of the semiconductor device (see, for example, FIG. 16). The gate of the P-LDMOS cell is activated by coupling the gate metal strip 1131 (which has a conductivity substantially greater than that of the gate polysilicon strip) in the first metal layer M1 to the plurality of gate drivers The switching signal is substantially time aligned.

In view of the large amount of effective capacitance generated between the gate, source and drain, it is an important design consideration to provide a time-aligned switching signal to the plurality of gates of individual P-LDMOS cells. This capacitance requires a large number of gates. Extremely drive current to achieve a fast switching transition. Failure to generate a time-aligned gate drive signal for the gates of individual P-LDMOS cells will enable other P-LDMOS cells to be turned on before turning on some P-LDMOS cells, which forces the cells that were switched early to shift in time during the switching transition. Conduct high current pulses. Dislocation of high current pulses in time exposes the P-LDMOS cell to device failure.

The illustrated structure also enables the use of substantially the same structure in a common semiconductor die to form N-LDMOS and P-LDMOS devices, and enables the use of a low inductance, high current path to couple each LDMOS type to an external circuit. Each LDMOS is formed to have a single large source contact and a single large and shared drain contact (see, for example, FIG. 17), which can simplify the circuit board layout and adhesion problems of an external circuit. Large source and drain contacts are easy to overlay a copper redistribution layer having substantially the same footprint as the large source and drain contacts (see (e.g.) Figure 17B) and finally overlay a lead frame (See (for example) Figure 17D), which further improves conductivity and couples a packaged semiconductor device (see (for example) Figure 18) to an external circuit. The source contact and the common drain contact cover substantially the entire active area of the N-LDMOS and P-LDMOS device, so that the large current contact that does not cover the switching area has less wasted die area.

Regarding the P-LDMOS cell 8001, the source (or source region) is embodied in at least the heavily doped P-type region 8060, and the drain (or drain region) is embodied in the lightly doped P-type region 8070 (for example, a lightly doped drain ("LDD") region) and an adjacent heavily doped P-type region 8080 opposite to the channel region 8003. The gate resides above the channel area 8003 with layers as described in this article. The LDD region provides the P-LDMOS device with a breakdown voltage higher than that of the conventional design. These regions are formed in the order of "heavy doped source region", "gate", "lightly doped drain region" and "heavy doped drain region".

Turning now to FIG. 89, a cross-sectional view of an embodiment of a P-LDMOS device embodied in a semiconductor device or part thereof is illustrated. A P-LDMOS device is formed in a semiconductor die containing a P-doped semiconductor substrate (also referred to as a "substrate") 8005, and an optional epitaxial layer (for example, a light Doped P-type epitaxial layer, not shown). The substrate 8005 is preferably lightly doped with P (for example, boron) between 1.10¹⁴Atoms/cm³And 1.10¹⁶Atoms/cm³between. Especially when the substrate 8005 is a lightly doped P-type substrate, it is not necessary to grow an optional epitaxial layer on the substrate 8005. Although the substrate 8005 is a P-type substrate in the illustrated embodiment, those skilled in the art should understand that the substrate 8005 may be an N-type substrate without departing from the scope of the present invention.

The substrate 8005 is formed with isolation regions (for example, shallow trench isolation regions 8010). The shallow trench isolation region 8010 can also be formed in a substrate or grown in an epitaxial layer on the substrate to provide dielectric isolation between devices implemented on the substrate or on the epitaxial layer. The shallow trench isolation region 8010 is formed by coating, patterning, and etching the substrate 8005 using a photoresist to define the respective regions therein. An exemplary photoresist is an AZ electronic material photoresist. Then etch and use a combination of silicon dioxide, silicon nitride, etc. or any other suitable One of the dielectric materials is dielectric to backfill the shallow trench isolation region 8010. Then, the epitaxial layer of the substrate 8005 and the shallow trench isolation region 8010 are planarized by a thinning process such as a chemical mechanical planarization ("CMP") thinning process to planarize the device while constraining the surface of the die destroy. The steps of masking, etching, dielectric backfilling, and thinning are widely known in the art and will not be described in further detail below.

The P-type substrate 8005 is divided into dielectric separation regions by the shallow trench isolation region 8010 to accommodate a plurality of N-LDMOS and P-LDMOS devices and gate drivers in the illustrated embodiment and embedded on the P-type substrate 8005 Other PMOS and NMOS devices used as low-voltage devices in control circuits. The low-voltage device may be operated in, for example, a controller of a power converter (for example, in a control and signal processing device that may be formed on the surface of a semiconductor device). In addition, the P-type substrate 8005 can accommodate N-LDMOS and P-LDMOS devices used as higher voltage devices in, for example, a power system and a driver of a power converter (ie, power switch and driver switch).

The lightly doped N-type well 8015 is formed by coating and patterning a photoresist mask (not shown) and then etching the photoresist mask to define the area to be occupied by the lightly doped N-type well 8015. An exemplary photoresist is AZ electronic material photoresist. The steps of patterning and etching to define the horizontal dimensions of the lightly doped N-type well 8015 are well known in the art and will not be described in further detail below. (For example, under a control energy of about 100 keV to 300 keV) by an ion implantation process of an appropriate N-type dopant species such as arsenic, the lightly doped N-type well 8015 is formed, and the result is preferably at about 1 .10¹⁴Atoms/cm³To 1.10¹⁶Atoms/cm³A light doping concentration distribution in a range.

The N-type well 8017 is formed in the lightly doped N-type well 8015 by coating and patterning a photoresist mask (not shown) and then etching the mask to define the area to be occupied by the N-type well 8017. (For example, under a control energy of about 100 keV to 300 keV) The N-type well 8017 is formed by an ion implantation process of a suitable N-type dopant species such as phosphorus, and the result is preferably about 1.10¹⁷Atoms/cm³To 2.10¹⁹Atoms/cm³A doping concentration distribution in a range.

A gate oxide layer 8020 (an insulating layer) is formed on the surface of a semiconductor device having a thickness that meets the expected operating voltage of the gate, and a gate electrode is formed on the gate oxide layer 8020 (an insulating layer). The gate oxide layer 8020 is usually silicon dioxide formed by, for example, placing a wafer on which silicon devices are formed in an oven; and using a feature size of about 0.25 microns ("μm") and A device operating at a low gate voltage (for example, 2.5 volts) causes the exposed surface of the wafer to interact with oxygen or other suitable materials having a thickness of about 30 Angstroms ("Å") to 50 Å at 500°C to 900°C The reaction lasts from 10 minutes to 100 minutes (such as to produce a high κ (dielectric constant) stack). Assuming that the gate-source voltage limit of N-LDMOS and P-LDMOS devices is limited to a voltage (for example, about 2.5 volts), a gate dielectric layer thickness as stated above can be used to form a gate oxide layer 8020. Preferably, the gate oxide layer 8020 is constructed to have a uniform thickness to provide the devices with a gate-source rated voltage of approximately 2.5 volts that fully or almost completely saturates the forward conductive properties of the devices. Of course, the aforementioned gate voltage ranges of these devices are provided for illustrative purposes only, and other voltage ranges are expected to fall within the broad scope of the present invention.

The gates include a gate polysilicon layer 8025 deposited on a surface of the gate oxide layer 8020 and used in a subsequent processing step such as having a thickness of about 1.10¹⁹To 5.10²⁰A suitable doping species (such as arsenic) of a doping density in a range performs N-type (or P-type) doping on the gate polysilicon layer 8025 to obtain an appropriate level of conductivity. Anneal the gate polysilicon layer 8025 at a high temperature in an oven (for example, at a temperature ranging from 800°C ("°C") to 1000°C for 2 minutes to 60 minutes) to properly diffuse and activate the dopant . The gate polysilicon layer 8025 may have a thickness ranging from about 100 nanometers to about 500 nanometers, but may have a smaller or larger thickness range depending on an application.

The gate is formed to have an overlying gate oxide layer 8030 (an insulating layer), and the overlying gate oxide layer 8030 is formed on an upper surface of the gate polysilicon layer 8025 by the following operations: an oven Place the wafer on which the silicon device is formed; and make the exposed surface of the gate polysilicon layer 8025 react with oxygen at a high temperature (for example, at 500°C to 900°C One temperature lasts 1 minute to 60 minutes). The overlying gate oxide layer 8030 may be formed to have a thickness of about 50 Å to 500 Å.

The gate oxide layer 8020, the gate polysilicon layer 8025, and the overlying gate oxide layer 8030 are patterned and etched to define and form their horizontal dimensions. A photoresist mask is used with an etching to define the lateral dimensions of the gate polysilicon layer 8025, the gate oxide layer 8020, and the overlying gate oxide layer 8030. In FIG. 89, only reference numerals are used to designate one of the gate polysilicon layer 8025 and the underlying and overlying gate oxide layers 8020, 8030. An exemplary photoresist is AZ electronic material photoresist. The steps of patterning and etching to define and form the horizontal dimensions of the gate polysilicon layer 8025 and the underlying and overlying gate oxide layers 8020, 8030 are well known in the art and will not be described in further detail below. In an alternative embodiment, the gate polysilicon layer 8025 may include or be formed in other ways to have a variety of materials, including various metals, other doped semiconductors, or other conductive materials. It should be noted that the horizontal dimensions of the gate polysilicon layer 8025 and the underlying and overlying gate oxide layers 8020 and 8030 can be masked and etched in the same processing steps, and one of N-LDMOS and P-LDMOS formed on the same silicon Various other structures of both devices. In addition, in a self-aligned process without masking and etching a photoresist, an insulating layer (such as nitride layer) adjacent to the gate polysilicon layer 8025, the underlying oxide layer 8020 and the overlying oxide layer 8030 Silicon) to form sidewall spacers (one of them is designated as 8040). It should be noted that a part of the overlying gate oxide layer 8030 above the gate polysilicon layer 8025 (about a half of the gate width, about 0.2 μm) is removed.

In the N-type well 8017, for example, arsenic is ion-implanted to form a heavily doped N-type region 8090. In one embodiment, the heavily doped N-type region 8090 is doped to about 1.10¹⁹Atoms/cm^-3To 5.10²⁰Atoms/cm^-3One density, and implantation is performed under a control energy of 5keV to 50keV. Surrounding the heavily doped N-type region 8090 is an N-type region 8055 ion-implanted with a suitable atomic species such as phosphorus to make the formed P-LDMOS device reach a usable gate threshold voltage. The N-type area 8055 has about 5.10¹⁷Atoms/cm³To 1.10¹⁹Atoms/cm³One of the range of doping concentration distribution and the control energy is one of about 20keV to 100keV Implant under. Above the N-type region 8055 is a heavily doped P-type region 8060 with P-type ions (for example, boron). The heavily doped P-type region 8060 is implanted (for example, under a control energy of about 5 keV to 50 keV) with a preferably 5.10¹⁸Atoms/cm³To 1.10³⁰Atoms/cm³A doping concentration distribution in a range to enable the formed P-LDMOS device to achieve a low source resistance.

Above the heavily doped N-type region 8090 (and other locations in the lightly doped N-type well 8015) is doped with (for example) boron to about 1.10¹⁹Atoms/cm^-3To 5.10²⁰Atoms/cm^-3A range of density and heavily doped P-type region 8080 implanted under a control energy of 10keV to 100keV. The heavily doped P-type region 8080 above the heavily doped N-type region 8090 is relatively thin (for example, about 10 Å to 100 Å). Also, similar use has about 1.10¹⁹To 5.10²⁰The gate polysilicon layer 8025 is P-doped with boron with a doping density in a range to obtain a suitable level of gate conductivity. Around the heavily doped P-type region 8080 (located in the lightly doped N-type well 8015) is doped with (for example) boron to 1.10¹⁷Atoms/cm³To 1.10¹⁹Atoms/cm³And the lightly doped P-type region 8070 is implanted under a control energy of 10keV to 200keV.

Above the gate and the lightly doped P-type region 8070 is a silicon dioxide region 8105 (an insulating region). Silicide is formed only on exposed silicon. In the area where the silicon is covered by the silicon dioxide area 8105, no silicide layer will be formed. Then, a silicide layer 8115 is formed over the exposed area of silicon, and the polysilicon does not substantially react to wet etching and will not be removed by wet etching. An exemplary wet etching system is aqua regia (a mixture of nitric acid and hydrochloric acid). In one embodiment, the silicide layer 8115 of the overlying gate polysilicon layer 8025 is electrically coupled to the gate metal strip 1131 formed in a first metal layer M1 (see (for example) FIG. 16). The silicide layer 8115 may be formed using, for example, a refractory metal having a thickness preferably in the range of 100 Å to 800 Å, such as tungsten, titanium, and cobalt.

Deposit and pattern an amorphous silicon silicon oxynitride ("Si_xO_yN_z") Layer 8120 (an insulating layer). A first metal (e.g., aluminum) layer M1 (e.g. For example, through a vacuum deposition) the portion between the amorphous silicon silicon oxynitride layer 8120 and down to the silicide layer 8115 in a region of the source and drain contacts. An etch stop refractory layer 8130 is deposited on the first metal layer M1. In one embodiment, the etch stop refractory layer 8130 is made of titanium nitride, cobalt nitride or tungsten nitride. Another silicon oxynitride layer 8140 (an insulating layer) is deposited and patterned on the amorphous silicon silicon oxynitride layer 8120. The silicon oxynitride layers 8120 and 8140 enable the formation of low-resistance metal source and drain contacts of P-LDMOS in a series of processing steps. A second metal (e.g., aluminum) layer M2 (e.g., via a vacuum deposition) is located between the silicon oxynitride layers 8140 and down to an area of the source and drain contacts. Etching above the first metal layer M1 Stop the refractory layer 8130. An etch stop refractory layer 8150 is deposited on the second metal layer M2. In one embodiment, the etch stop refractory layer 8150 is made of titanium nitride, cobalt nitride or tungsten nitride.

Another silicon oxynitride layer 8160 (an insulating layer) is deposited and patterned on the silicon oxynitride layer 8140. The silicon oxynitride layers 8120, 8140, and 8160 enable the formation of low-resistance metal source and drain contacts of P-LDMOS in a series of processing steps. A third metal (e.g., aluminum) layer M3 (e.g., via a vacuum deposition) is located between the silicon oxynitride regions 8160 down to a region of the source and drain contacts. Etching above the second metal layer M2 Stop the refractory layer 8150. A final silicon oxynitride layer 8170 (an insulating layer) is deposited and patterned on the silicon oxynitride layer 8160. The silicon oxynitride layers 8120, 8140, 8160, and 8170 enable the formation of low-resistance metal source and drain contacts of P-LDMOS in a series of processing steps. A polyimide coating 8180 (an insulating layer) is deposited and patterned on the silicon oxynitride layer 8170 and the third metal layer M3. A refractory barrier layer 8190 (for example, titanium nitride, tantalum nitride, or cobalt nitride) is deposited on the semiconductor device.

Next, a thin metal (for example, copper) seed layer is deposited on the refractory barrier layer 8190, and the seed layer is then electroplated to form an electroplated copper layer 8200. Another polyimide coating 8205 (an insulating layer) is deposited and patterned over the copper layer 8200 in the area defined by the polyimide coating 8180. The other polyimide coating in the region of the source of the P-LDMOS device Another thin metal (for example, copper) seed layer 8215 is deposited and patterned over the electroplated copper layer 8200 between 8205. Depositing the copper seed layer 8215 is used to create a new surface for an optional step in the subsequent electrodeposition of metal (eg, copper) pillars.

The metal (for example, copper) pillar 8220 is formed by an electroplating process using an acid solution and is located above the copper seed layer 8215. As illustrated and described above with reference to FIG. 4, the copper pillars 8220 are used as low-resistance source contacts to a conductive patterned lead frame to complete the traces to which the terminals of the semiconductor device can be soldered. Corresponding steps can be used in conjunction with the steps described above for constructing source contacts to form low-resistance drain contacts of P-LDMOS devices. In addition, an encapsulant (for example, an epoxy resin) 8225 can be selectively deposited between the copper pillar 8220 and a patterned lead frame 8230 placed above the copper pillar 8220 to produce the exterior of a packaged semiconductor device. Contact (e.g. (see) Figure 18).

The steps listed in Table 1 below illustrate a series of process steps that can be used to form N-LDMOS and P-LDMOS devices in a common die. It is expected within the broad scope of the present invention that the specific sequence of program steps can be modified to produce N-LDMOS and P-LDMOS devices in a common die.

Number the steps in the leftmost column. In the next column to the right, identify the program steps that apply to both N-LDMOS and P-LDMOS devices. In the third column and the fourth column, respectively, identify the program steps that are only applicable to LDMOS and P-LDMOS devices.

<tables><img he="916" wi="2073" file="twi544591b_d0001.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img he="3106" wi="2115" file="twi544591b_d0002.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img he="3121" wi="2065" file="twi544591b_d0003.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img he="3083" wi="2099" file="twi544591b_d0004.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img he="3113" wi="2061" file="twi544591b_d0005.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img he="2857" wi="2051" file="twi544591b_d0006.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

Those familiar with the art should understand that the previously described embodiments of a semiconductor switch and a power converter and related methods of constructing a semiconductor switch and power converter are for illustration only For sexual purposes. In addition, other switch-mode power converter topologies that can be used to produce other embodiments of a semiconductor switch and a power converter are completely within the broad scope of the present invention. Although the construction of semiconductor switches and power converters has been described in an environment that includes a controller and a power converter for controlling an output characteristic to supply power to a load, the construction of semiconductor switches and power converters can also be applied Other systems, such as a power amplifier, a motor controller, and a system that controls an actuator based on a stepper motor or other electromechanical device.

For a better understanding of integrated circuits, semiconductor devices and their manufacturing methods, see "Semiconductor Device Fundamentals" published by RFPierret and Addison-Wesley (1996) and "Handbook" published by K. Wasa and S. Hayakawa in Noyes Publications (1992) of Sputter Deposition Technology". For better understanding of power converters, please refer to "Modern DC-to-DC Switchmode Power Converter Circuits" published by Rudolph P. Severns and Gordon Bloom (1985) of Van Nostrand Reinhold, New York, USA and JGKassakian, MFSchlecht, GCVerghese, Addison-Wesley (1991) Published "Principles of Power Electronics". The aforementioned references are all incorporated herein by reference.

Moreover, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made in this text without departing from the spirit and scope of the present invention as defined in the scope of the patent application for the embodiments. For example, many of the programs discussed above can be implemented with different methodologies and replaced by other programs or a combination of others.

In addition, the scope of this application is not intended to be limited to the specific embodiments of the procedures, processing, manufacturing, material components, methods, methods, and steps described in the specification. According to the disclosure of the present invention, those skilled in the art will easily understand that the presently existing or subsequently developed procedures, processing, manufacturing, etc. that can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized according to the present invention. Material composition, methods, methods and steps. because Therefore, the scope of patent applications for the embodiments is intended to include these procedures, processing, manufacturing, material components, methods, methods, and steps within the scope of the patent applications.