Method of allocating memory and communication device

Memory allocation method and communication device

METHOD OF ALLOCATING MEMORY AND COMMUNICATION DEVICE

The invention relates to a method for allocating memory and a communication device. More specifically, this memory allocation method and communication device provide an interleaving technique for allocating an unfixed memory capacity between the interleaving operation and the de-interleaving operation.

Interleaving is a technology used in data communication systems to protect codewords or other data words from burst errors during data transmission. When burst errors occur (for example, due to impulse noise), multiple consecutive bits of a data stream are destroyed during transmission. As for the error correction scheme that expects a more even distribution of errors, it may also fail when a burst of errors occurs. Generally speaking, data is often transmitted with multiple error control bits, which enable the receiver to correct a certain number of errors that occur during the transmission. However, if too many errors occur in a codeword, even if an error correction scheme is used, the codeword cannot be decoded correctly. In order to reduce burst errors, the codeword bits are usually interleaved before transmission. In this way, multiple bits from the same codeword will not be transmitted in sequential order. On the contrary, because the codewords are broken up, the bits from different codewords are continuously transmitted. Also, because the codeword bits are more evenly distributed during the data transmission process, the possibility of bursting errors to damage the codeword is smaller. Accordingly, when the interleaving technique is used, the receiver can decode the transmitted codeword more accurately.

The conventional data communication system adopting the interleaving technology provides a fixed memory capacity for allocation between the interleaving operation and the de-interleaving operation. For example, digital subscriber loop (DSL) modems (such as VDSL (Very High Speed DSL) and VDSL2 modems) are usually buffered by a downstream interleaver buffer and an upstream deinterleaver buffer. The upstream de-interleaver buffer provides a total memory size (in the form of delay octet) for allocation. When the codeword is in the downstream direction (that is, from a service provider or operator to a user), interleaving is performed, and when the codeword is in the upstream direction (that is, from the user to the service provider or operator), then Perform de-interlacing processing. Generally speaking, the protection capability of the interleaver depends on the size of the interleaver buffer. In addition, the memory capacity (interleaver depth) of the interleaver buffer is usually proportional to the data rate, the maximum delay, and the required minimum impulse noise protection for downstream and upstream.

This kind of fixed memory is ideally allocated to achieve the desired noise protection capability while maintaining the optimized uplink and downlink data transmission rate, and is not suitable for real environments. In detail, to optimize the uplink and downlink data transmission rate, the actual channel status must be considered, and the memory allocation of the interleaver is usually performed before the modem knows the channel status. These limiting factors are the conventional memory. The distribution technology is not involved. For example, DSL modems are usually based on the data transfer rate, maximum delay, and impulse noise protection configuration parameters provided to the modem as part of the management information base (MIB), and the interleaver buffer and Allocate memory between the deinterleaver buffers. Because these parameters can represent poor channel status, best channel status or expected channel status. Therefore, under some conditions, the memory may not be optimally allocated between the interleaver and the deinterleaver. In other words, the conventional memory allocation technology can no longer solve the existing deficiencies.

According to an embodiment, a first communication device estimates a plurality of uplink channel states of an uplink channel and determines a first buffer for a second communication device and a first buffer of the first communication device according to the uplink channel states. One buffer and one upstream memory requirement. According to a downlink channel state estimated for the downlink channel at the second communication device, a second buffer of the first communication device and a second buffer of the second communication device are received from the second communication device One of the downstream memory requirements. The first communication device determines whether the sum of the upstream memory request and the downstream memory request exceeds the available memory capacity of one of the first buffer and the second buffer at the first communication device; And if the sum of the upstream memory requirements and the downstream memory requirements is different from the available memory capacity, at least one of the memory requirements is modified.

According to another embodiment, a first communication device receives from a second communication device a first buffer of the first communication device and an uplink memory request of a first buffer of the second communication device. The upstream memory requirement is based on the estimated status of a plurality of upstream channels at the second communication device for an upstream channel. The first communication device estimates a plurality of downlink channel states of the downlink channel. The first communication device also determines a downlink memory request for a second buffer of the second communication device and a second buffer of the first communication device according to the downlink channel status, and the downlink memory The request is transmitted to the second communication device.

The independent claims define the invention in different ways. Attached claims define multiple embodiments of the invention.

In a first aspect, the present invention includes a method for allocating a memory to a first communication device, the first communication device being coupled to a second communication device through an uplink channel and a downlink channel, the method Comprising: estimating a plurality of uplink channel states of the uplink channel at the first communication device; according to the uplink channel states, determining at the first communication device an interleaver buffer for the second communication device and the An uplink memory request of a deinterleaver buffer at the first communication device; according to a plurality of downlink channel states estimated for the downlink channel at the second communication device, receiving from the second communication device for the second communication device A downstream memory request of an interleaver buffer at a communication device and a deinterleaver buffer at the second communication device; determining the upstream memory request and the downstream memory request at the first communication device Whether the sum exceeds the available memory capacity of one of the interleaver buffer and the deinterleaver buffer used at the first communication device; and if the sum of the upstream memory requirements and the downstream memory requirements are different Based on the available memory capacity, at least one of the memory requirements is modified at the first communication device. Since memory allocation is based on a better understanding of the downstream channel, at least one effect of the above method is to allocate memory more efficiently.

In an embodiment of the method according to the first aspect of the present invention, the method includes during a channel initialization and training period, the uplink memory determined according to the uplink channel status is required to be on the downlink channel To the second communication device.

In an embodiment of the method according to the first aspect of the present invention, the method includes instructing the second communication device to comply with any memory requirements made at the first communication device during a channel initialization and training period Fix.

In an embodiment of the method according to the first aspect of the present invention, the method includes determining which of the memory requests is to be modified at the first communication device according to a priority bit, wherein the priority The weight bit indicates the priority of the upstream memory request and the downstream memory request.

In an embodiment of the method according to the first aspect of the present invention, the method includes reducing the memory requirement with a lowest priority at the first communication device, so that after the reducing step, the upstream memory requirement The sum of the downstream memory requirements is equal to the available memory capacity.

In an embodiment of the method according to the first aspect of the present invention, the method includes adding a memory request with a highest priority at the first communication device, so that after the adding step, the upstream memory request The sum of the downstream memory requirements is equal to the available memory capacity.

In an embodiment of the method according to the first aspect of the present invention, the method includes correcting the upstream memory requirement and the downstream memory requirement at the first communication device according to a correction factor (CF), After the correction step, the sum of the upstream memory request and the downstream memory request is equal to the available memory capacity.

In an embodiment of the method according to the first aspect of the present invention, the method includes the downlink memory request received from the second communication device according to the uplink memory request determined based on the uplink channel status, the Available memory capacity and one or more interleaver/deinterleaver setting values known at the first communication device, and at least one of the memory requirements is modified at the first communication device.

In a second aspect, the present invention includes a communication device that includes: a processor for establishing a communication link with another communication device through an uplink channel and a downlink channel; and a memory , Used for allocating between an interleaver buffer and a deinterleaver buffer of the communication device; and a memory allocation unit for: estimating a plurality of uplink channel states of the uplink channel; according to the uplink The channel status determines the upstream memory requirements for an interleaver buffer at the other communication device and the deinterleaver buffer of the communication device; according to the multiple estimated at the other communication device for the downstream channel A downlink channel status, processing a downlink memory request received from the other communication device to the interleaver buffer of the communication device and a deinterleaver buffer at the other communication device; judging the uplink memory request and Whether the sum of the downstream memory request exceeds the available memory capacity of one of the interleaver buffer and the deinterleaver buffer used to build the communication device; and if the upstream memory request is more than the downstream memory request If the sum is different from the available memory capacity, modify at least one of the memory requirements. Since memory allocation is based on a better understanding of the downstream channel, at least one function of the above-mentioned device is to allocate memory more efficiently.

In an embodiment of the device according to the second aspect of the present invention, the processor is used to request the uplink memory determined according to the uplink channel status on the downlink channel during a channel initialization and training period. To the other communication device.

In an embodiment of the device according to the second aspect of the present invention, the processor is used to instruct the other communication device to follow any memory request corrections made at the communication device during a channel initialization and training period.

In an embodiment of the device according to the second aspect of the present invention, the memory allocation unit is used to determine which of the memory requests is to be modified according to a priority bit, the priority bit indicating the uplink The priority of the memory request and the downstream memory request.

In an embodiment of the device according to the second aspect of the present invention, the memory allocation unit is used to reduce the memory requirement with a lowest priority, so that after the memory requirement is reduced, the upstream memory requirement and The sum of the downstream memory requirements is equal to the available memory capacity.

In an embodiment of the device according to the second aspect of the present invention, the memory allocation unit is used to increase a memory request with a highest priority, so that after the memory request is increased, the upstream memory request and The sum of the downstream memory requirements is equal to the available memory capacity.

In an embodiment of the device according to the second aspect of the present invention, the memory allocation unit is used to modify the upstream memory request and the downstream memory request according to a correction factor, so that the upstream memory request and the downstream memory request After the memory requirement is corrected, the sum of the upstream memory requirement and the downstream memory requirement is equal to the available memory capacity.

In an embodiment of the device according to the second aspect of the present invention, the memory allocation unit is used for the downlink memory received from the second communication device according to the uplink memory request determined based on the uplink channel status Modify at least one of the memory requirements, the available memory capacity, and one or more interleaver/deinterleaver settings known at the communication device.

In a third aspect, the present invention includes a communication device that includes: a processor for establishing a communication link with another communication device through an uplink channel and a downlink channel; and a memory, Is used to allocate between a first buffer and a second buffer; and a memory allocation unit is used to: estimate the state of a plurality of uplink channels of the uplink channel; determine the first buffer according to the state of the uplink channels An upstream memory request for a buffer; according to a plurality of downstream channel states estimated at the other communication device for the downstream channel, processing a downstream memory received from the other communication device for the second buffer Request; determine whether the sum of the upstream memory request and the downstream memory request exceeds the available memory capacity for building one of the first buffer and the second buffer; and if the upstream memory request and the downstream memory request If the sum of memory requirements is different from the available memory capacity, at least one of the memory requirements is modified. Since memory allocation is based on a better understanding of the downstream channel, at least one function of the above-mentioned device is to allocate memory more efficiently.

In an embodiment of the device according to the third aspect of the present invention, the first buffer is operable to store a piece of data received through the uplink channel at the communication device.

In an embodiment of the device according to the third aspect of the present invention, the second buffer is operable to store a piece of data transmitted from the communication device through the downlink channel.

Those who are familiar with the art will learn other features and advantages of the present invention after reading the following detailed description and viewing the accompanying drawings.

Figure 1 shows an embodiment of a wireless or wired communication device 100 (such as a DSL or cable modem, hub or switch) for transmitting and receiving interleaved data. The communication device 100 includes a processor 102, a digital interface 104, a framer 106 (framer), a de-framer 108 (de-framer), an encoder 110, a decoder 112, an interleaver 114, A deinterleaver 116, a memory 118, and a front end (front end; FE) 120. The processor 102 manages the overall operation of the communication device 100. A transmission data will be transmitted from the communication device 100 to another device (not shown in the figure) via a communication channel in the downstream direction, and a reception data will be received by the communication device 100 via a different channel in the upstream direction. The data transmitted and received by the communication device 100 are interleaved in order to reduce the possibility of data corruption caused by a burst error. The interleaving process is achieved by logically dividing the memory 118 into a lower row interleaver buffer 122 and an upper deinterleaver buffer 124. When the coded data waiting to be transmitted is stored in the interleaver buffer 122, it is interleaved. When the received data is removed from the deinterleaver buffer 124, it is similarly deinterleaved. According to one or more channel states observed by the communication device 100, the memory 118 is between a pre-processing buffer and a post-processing buffer (for example, between the interleaver buffer and the deinterleaver buffer 122, 124). ) To assign. The one or more channel states may be one or more uplink channel states or one or more downlink channel states or a combination of one or more uplink channel states and one or more downlink channel states. In this way, even when the actual channel state (such as impulse noise level, user interference, cross-talk, electrical and radio interference, etc.) is better or worse than expected, it can also be upstream The memory 118 is better allocated between and downstream. Moreover, the memory 118 can be allocated when the communication device 100 initializes a new communication channel. The memory 118 can also be re-allocated for a pre-existing channel, for example, when the status of the uplink and/or downlink channel changes or when the communication device 100 resumes from a low power or sleep mode.

In detail, the digital interface 104 provides a higher-layer network interface (Higher-Layer Network Interface) for the communication device 100. The network interface is compatible with a specific data link layer protocol, such as Ethernet, Asynchronous transfer mode (ATM), Point-to-Point Protocol (PPP), Wireless Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WiMAX), Compatible with IEEE 802.11 specifications and so on. The digital interface 104 provides data received from a network node (not shown in the figure) to the framer 106 for transmission, and receives data from the deframer 108 for higher-level processing. The framer 106 multiplexes the data received from the digital interface 104 into multiple frames. The encoder 110 can perform forward error correction (forward error correction). Then, the interleaver 114 performs interleaving processing on the encoded frame data so that adjacent codeword bits are not transmitted in a continuous sequence. When the encoded frame data is interleaved, it is stored in the interleaver buffer 122. A transmission circuit 126 associated with the device FE 120 transmits the interleaved data downward on a communication link 130 (such as a twisted pair cable or a wireless link). On the receiving end side, the FE 120 includes a receiving circuit 128 for processing the upstream interleaved data transmitted to the communication device 100 via an upstream channel. The FE transmission and reception circuits 126, 128 may include analog circuits, digital circuits, and/or mixed signal circuits that perform signal capture, analog domain filtering, analog-to-digital and digital-to-analog conversion, filtering, and power Functions such as zoom in. The received upstream data is stored in the deinterleaver buffer 124. The deinterleaver 116 performs an inverse operation on the algorithm used for interleaving, so that the encoded frame data can be appropriately extracted from the deinterleaver buffer 124. Then, the decoder 112 decodes the deinterleaved data to recover the frame data. The deframer 108 takes out a piece of frame information and sends the data of interest to the digital interface 104 for further processing.

The size of the memory 118 allocated between a pre-processing buffer and a post-processing buffer (for example, between the interleaver buffer and the deinterleaver buffer 122, 124) is contained in the processor 102 or A memory allocation unit 132 associated with the processor 102 or other logic (not shown in the figure) included in the communication device 100 is determined. The memory allocation unit 132 can be built in hardware, firmware, software, or any combination thereof. Figure 2 shows an embodiment of the program logic executed by the memory allocation unit 132. The program logic is used to allocate memory between the interleaver buffer and the deinterleaver buffer 122, 124 according to a plurality of upstream channel states 118. The memory allocation unit 132 determines the uplink and downlink data transmission rate estimates for the channel based on a plurality of configuration parameters obtained before the communication device 100 initializes a new channel (such as step 200). In one embodiment, the communication device 100 is a VDSL2 modem. According to this embodiment, as is known in the art, the uplink and downlink data transmission rates are estimated based on the uplink and downlink data transmission rates, maximum delay, and impulse noise protection configuration parameters provided as part of the MIB to the device 100. determine. These parameters do not reflect the actual channel state, but represent the poor state, the best state, or the state expected in other ways.

The memory allocation unit 132 initially evaluates how the memory 118 should be allocated between the interleaver buffer and the deinterleaver buffer 122, 124 based on the uplink and downlink data transmission rate estimates (as in step 202). For example, if the estimated downstream rate is higher than the upstream rate, more memory 118 is allocated to the interleaver buffer 122 proportionally, and vice versa. If the rates are the same, the memory 118 is divided equally between the two buffers 122 and 124. The memory allocation unit 132 then modifies the initial estimate of how the memory 118 should be allocated based on the upstream capacity or downstream capacity of the channel observed by the communication device 100 during or after the initialization of the channel (step 204). In one embodiment, the communication device 100 evaluates the upstream channel based on the impulse noise level or other channel status observed by the device 100 in the upstream direction. Then, according to the revised memory allocation estimate, the memory 118 is allocated between the interleaver buffer and the deinterleaver buffer 122, 124 (as in step 206). If the channel status changes or when the communication device 100 recovers from a low power or sleep mode, the memory allocation estimate can be recalculated. In this way, the memory 118 can be reallocated for a pre-existing channel based on the recalculated estimate. Thus, the memory 118 can be allocated more efficiently according to the actual channel state that can substantially deviate from the desired situation.

FIG. 3 shows an embodiment of the program logic executed by the memory allocation unit 132. The program logic is used to modify the initial estimate of how the memory 118 should be allocated according to the upstream capacity of the channel. The memory allocation unit 132 first determines a memory requirement for one of the downstream interleaver buffers 122 (such as step 300). In one embodiment, the communication device 100 is a VDSL2 modem, and as known in the art, the downlink interleaver memory is calculated based on the downlink data transmission rate, maximum delay, and impulse noise protection configuration parameters Require. The memory allocation unit 132 determines the uplink channel status for a new communication channel initialized by the communication device 100 (as in step 302). In one embodiment, the uplink channel status is estimated based on the impulse noise level observed by the communication device 100. Determine a memory requirement of the upstream deinterleaver buffer 124 according to the status of the upstream channels (such as step 304), and perform the interleaver buffer and deinterleaver buffer 122, 124 according to the downstream memory requirement and the upstream memory requirement. The memory 118 is allocated among them (as in step 306). If the channel status changes or when the communication device 100 recovers from a low power or sleep mode, the downstream memory request and the upstream memory request can be modified. In this way, the memory 118 can be re-allocated for a pre-existing channel according to the revised requirements. Therefore, while calculating the upstream memory requirement based on the actual upstream channel state observed by the communication device 100, only the configuration parameters are used to determine the downstream memory requirement.

FIG. 4 shows another embodiment of the programming logic executed by the memory allocation unit 132. The programming logic is used to modify the initial estimate of how the memory 118 should be allocated according to the upstream capacity of the channel. According to this embodiment, both the downstream memory requirement and the upstream memory requirement are calculated based on the status of the upstream channel. The memory allocation unit 132 first determines the upstream channel status of the communication channel initialized by the communication device 100 (such as step 400). Then, the memory allocation unit 132 determines the memory requirement of the upstream deinterleaver buffer 124 according to the status of the upstream channel (as in step 402). In one embodiment, the memory requirements of the uplink deinterleaver are determined according to the above-mentioned Figure 3. The memory allocation unit 132 also determines the memory requirements of the downstream interleaver buffer 122 according to the status of the upstream channel (as in step 404), and determines the memory requirements of the interleaver buffer and deinterleaver buffer 122 according to the downstream memory requirements and the upstream memory requirements. The memory 118 is allocated between 124 and 124 (as in step 406). If the channel status changes or when the communication device 100 recovers from a low power or sleep mode, the downstream memory request and the upstream memory request can be corrected. In this way, the memory 118 can be re-allocated for a pre-existing channel according to the revised requirements.

In one embodiment, the memory allocation unit 132 estimates the downstream capacity of the channel according to the status of the upstream channel, and determines a downstream capacity estimate that satisfies the downstream capacity estimation and one or more predetermined downstream configuration parameters (such as the maximum expected data transmission rate and the minimum Delay) the size of the interleaver buffer. Each parameter has a certain standard (for example, a minimum and/or maximum value). In one embodiment, the buffer size is selected to meet the configuration parameter criteria. Accordingly, according to the status of the upstream channel, the downstream capacity of the channel can be estimated by determining the ratio of a predetermined upstream data transmission rate configuration parameter to the upstream capacity estimation and using the ratio to adjust a predetermined downstream data transmission rate configuration parameter. In one embodiment, the uplink capacity estimate is divided by a maximum uplink data transmission rate configuration parameter. Then, the obtained quotient is multiplied by a maximum downlink data transmission rate configuration parameter to calculate the downlink capacity estimate.

Of course, the downlink capacity estimate can also be adjusted to account for an expected difference between the uplink channel state and the downlink channel state. That is, compared to the upstream direction, more or less degradation can be expected in the downstream direction. The memory allocation unit 132 can adjust the downlink capacity estimate to account for such differences in expectations. Either way, the memory allocation unit 132 allocates the memory 118 between the interleaver buffer and the deinterleaver buffer 122, 124 according to the downstream memory request and the upstream memory request. The memory requirements are calculated based on the actual channel status observed by the communication device 100.

Figure 5 shows another embodiment of the program logic executed by the memory allocation unit 132. The program logic is used to determine the downstream memory request and the upstream memory request, and perform the interleaver buffer and deinterleaving according to the requests. The memory 118 is allocated between the buffers 122 and 124. The communication device 100 receives a plurality of configuration parameters and stores the configuration parameters in the memory 118 or other locations. In one embodiment, the communication device 100 is a VDSL2 modem, and the configuration parameters are obtained from the MIB received by the device 100. The configuration parameters include parameters for the upstream and downstream directions, such as symbol rate (SYMBOL_RATE), total available memory in bytes (TOT_INT_MEM), and minimum uplink pulse noise protection in symbols (MIN_INP_US) , The minimum downlink pulse noise protection in symbols (MIN_INP_DS), the maximum deinterleaving delay in ms (MAX_DELAY_US), the maximum interleaving delay in ms (MAX_DELAY_DS), and the minimum uplink data transmission rate in Kbps (MIN_RATE_US) , The minimum downlink data transmission rate (MIN_RATE_DS), the minimum uplink overhead rate (MIN_MSG_US), the minimum downlink overhead rate (MIN_MSG_DS) and the maximum interleaving depth (DMAX_PROFILE) for a given profile in Kbps. Many of these configuration parameters depend on the selected VDSL profile. For example, DMAX_PROFILE is derived as follows: DMAX_PROFILE=2048 octets for 8 and 12 VDSL profiles; DMAX_PROFILE=3072 octets for 17 VDSL profiles; and DMAX_PROFILE=4096 The octet is used for 30 VDSL profiles. The SYMBOL_RATE and TOT_INT_MEM configuration parameters also depend on the selected profile.

The memory allocation unit 132 retrieves some of the configuration parameters for use in calculating the downstream memory requirements and the upstream memory requirements. Before initializing and training a new communication channel, the memory allocation unit 132 calculates the overhead rate and the downlink overhead rate OH_US and OH_DS according to the following formula (step 500):

OH_US=[1+(2×MIN_INP_US)/(MAX_DELAY_US×SYMBOL_RATE)]

OH_DS=[1+(2×MIN_INP_DS)/(MAX_DELAY_DS×SYMBOL_RATE)] (1)

The uplink overhead rate and the downlink overhead rate take into account the estimated coding required in the uplink direction and the downlink direction, respectively, to meet the minimum uplink and downlink INP requirements. As is known in the art, before channel initialization and training, the memory allocation unit 132 also calculates the minimum interleaver and deinterleaver memory requirement estimates according to the MIN_RATE_US and MIN_RATE_DS configuration parameters (as in step 502).

Then, a communication channel is initialized and trained by the communication device 100. During the channel initialization and training process, the memory allocation unit 132 can determine the status of the uplink channel, for example, according to the pulse noise level observed by the device 100. The upstream capacity of the channel can be estimated according to the status of the upstream channel. In one embodiment, the uplink channel capacity is estimated by calculating the uplink rate (US_LINE_RATE_CALC). The uplink rate is the payload or symbol rate in the uplink direction plus the overhead rate required to account for the observed channel noise. When the noise of the uplink channel is relatively large and the channel capacity used for the actual payload is reduced, additional channel capacity is needed for encoding overhead. When the noise of the uplink channel status is not too big, the opposite is true. The memory allocation unit 132 calculates the size of the uplink deinterleaver buffer 124, which satisfies one or more predetermined uplink data transmission rate configuration parameters and uplink capacity estimation (as in step 504).

In one embodiment, the memory allocation unit 132 calculates the size of the uplink deinterleaver buffer by selecting the minimum uplink rate (MIN_US_LINE_RATE) from a group of self-contained calculated uplink capacity estimates (US_LINE_RATE_CALC) as follows:

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MAX_CONFIG_LINE_RATE_US is a configuration parameter representing the maximum theoretical uplink rate, and PROVISIONED_RATE_US is a configuration parameter representing the maximum data capacity allocated to a user according to the provided uplink bandwidth. The memory allocation unit 132 uses the selected minimum line rate to determine the size of the upstream deinterleaver buffer 124, which satisfies the MIN_INP_US and DMAX_PROFILE configuration parameters.

The memory allocation unit 132 also determines the downlink interleaver by estimating the downlink capacity of one of the channels according to the uplink channel status and determining the size of the downlink interleaver buffer 122 that satisfies one or more predetermined downlink configuration parameters and the downlink capacity estimation. The memory requirements. To this end, the memory allocation unit 132 estimates the downstream line capacity of the channel by calculating one of the estimates of the downstream line rate by the following formula (as in step 506):

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PROVISIONED_RATE_DS is a configuration parameter that represents the maximum data capacity allocated to a user according to the provided lower line bandwidth, and US_LINE_RATE_CALC is the upper line capacity as described above. Therefore, when the channel capacity is greater than the specified upstream line rate, the estimate of the downstream line rate is adjusted upward. On the contrary, when the channel capacity is lower than the specified upstream line rate (that is, the noise of the upstream channel is relatively large), the estimation of the downstream line rate is adjusted downward. Then, the memory allocation unit 132 self-contains one of the initial downlink data transfer rate estimates (DS_LINE_RATE_EST) in the following data transfer rate group to select the minimum downlink line rate (as in step 508):

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Among them, MAX_CONFIG_LINE_RATE_DS is a configuration parameter representing the maximum theoretical downlink line rate. The memory allocation unit 132 uses the selected minimum downlink rate to determine the size of the row deinterleaver buffer 122 that satisfies the MIN_INP_DS and DMAX_PROFILE configuration parameters (as in step 510).

At this time, the size of the interleaver memory buffer and the deinterleaver memory buffer 122, 124 has been determined based on the actual line channel state observed by the communication device 100. In one embodiment, the memory allocation unit 132 then uses a correction factor to adjust the upstream buffer requirements and the downstream buffer requirements as shown in Equations 2 and 4, and allocates the memory 118 according to the adjusted buffer requirements (e.g. Step 512). The correction factor corresponds to the difference between one or more predetermined uplink configuration parameters and downlink configuration parameters. According to an embodiment, the correction factor is given by:

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Then, the memory allocation unit 132 determines whether to perform memory allocation in a fixed mode or an adaptive mode. When operating in a fixed mode, the unit 132 allocates the memory 118 between the interleaver buffer and the deinterleaver buffer 122, 124 according to the initial memory allocation estimate derived before channel initialization and training (step 502). The memory 118 is allocated in a fixed pattern by the following method: It is determined whether the initial uplink deinterleaver memory estimate is less than the total memory (TOT_INT_MEM) allocated to the device adjusted by the correction factor. If so, the size of the deinterleaver buffer 124 is set as the initial uplink deinterleaver memory estimate. Otherwise, the size of the deinterleaver buffer is set to TOT_INT_MEMxCF. The memory allocation unit 132 allocates the remaining memory 118 to the downstream interleaver buffer 122.

On the other hand, when configured in an adaptive memory allocation mode, the memory allocation unit 132 uses the upstream buffer request and the downstream buffer request calculated according to the status of the upstream channel (such as steps 504 and 510). The unit 132 first determines whether there is a total memory 118 sufficient to satisfy both the upstream buffer requirement and the downstream buffer requirement. In one embodiment, the memory allocation unit 132 subtracts the lower line buffer requirement calculated in step 510 from the total memory (TOT_INT_MEM) allocated to the device 100. If the upper line buffer requirement calculated in step 504 is greater than the difference, there is enough memory available for both the buffers 122 and 124 and the memory 118 can be allocated without conflict.

However, when there is not enough memory available to meet the requirements of the two buffers, the memory allocation unit 132 can choose between two embodiments for allocating the memory 118. In the first embodiment, the memory allocation unit 132 determines which of the buffers 122 and 124 has a higher priority. In one embodiment, the buffer priority is determined by evaluating a priority bit extracted from a configuration message received at an input terminal of the communication device 100. If the priority bit indicates that the upstream direction has priority, the memory allocating unit 132 allocates enough memory 118 to the upstream deinterleaver buffer 124 to meet the upstream buffer requirement calculated in step 504, and the remaining The memory 118 is allocated to the downstream interleaver buffer 122. When the priority bit indicates that the downstream direction has priority, the opposite memory allocation is performed. However, if another buffer needs all the memory 118, then any memory 118 may not be allocated to the buffers 122 and 124 with lower priority.

For example, when a conflict occurs, the second embodiment for allocating the memory 118 also includes using the priority bit to determine which of the buffers 122, 124 has a higher priority. According to the second embodiment, depending on the priority and the magnitude of the correction factor (CF) calculated in step 512, the memory 118 can be allocated in three different ways. When the downstream direction has priority and CF&gt;1, the amount of memory 118 allocated to the upstream deinterleaver buffer 124 is given by:

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Where MIN_US_INT_MEM is the upper buffer requirement calculated in step 504. Then, the remaining memory 118 is allocated to the downstream interleaver buffer 122. When the upstream direction has priority and CF&lt;1, the amount of memory 118 allocated to the downstream interleaver buffer 122 is given by:

DS_INT_MEM=max(TOT_INT_MEM×CF,MIN_DS_INT_MEM) (7)

Where MIN_DS_INT_MEM is the lower line buffer requirement calculated in step 510. The remaining memory 118 is allocated to the upstream interleaver buffer 124. When none of the two previous states identified above are satisfied, the third memory allocation option appears. Here, the total available memory 118 is evenly distributed between the interleaver buffer and the deinterleaver buffer 122, 124.

Figure 6 shows an embodiment of a customer premise equipment or customer-provided equipment (CPE) 600 (such as a DSL or cable modem), which is located at a users premises and at a demarcation point (such as establishing It is connected to one or more communication channels of an operator at a point where the user equipment is separated from the operator's network in a building or complex. The operator or a service provider operating on one or more communication channels of the operator also has a device (CO) 620 (such as a DSL or cable modem) for communicating with the CPE 600. CPE 600 and CO 620 include the same or similar components as shown in the communication device 100 in Figure 1 (for example, digital interface, framer/deframer, encoder/decoder, interleaver/deinterleaver , Front end, etc.). Note that both CPE 600 and CO 620 each include a processor 602/622 for managing the overall operation of the corresponding communication device.

Both CPE 600 and CO 620 also each have a memory 604/624, which can be logically divided into a pre-processing buffer and a post-processing buffer, for example, a transmission interleaver buffer 606 /626 and a receiving deinterleaver buffer 608/628. The encoded data to be transmitted at each device 600/620 can be interleaved when it is stored in the corresponding transmission interleaver buffer 606/626 or undergoes other pre-processing buffers before transmission. When the received data is removed from the receiving de-interleaver buffer 608/628 or is buffered by other post-processing after receiving, it can be similarly de-interleaved. To further illustrate, the two memories 604 are allocated between the interleaver buffer and the deinterleaver buffer 606/626, 608/627 according to a plurality of uplink channel states and downlink channel states as observed at the CPE 600 and CO 620. /624. In this way, when the memory is allocated, even when the actual channel status (such as impulse noise level, user interference, crosstalk, electrical and radio interference, etc.) is better or worse than expected, the CO 620 will Both the upstream channel and the downstream channel also have a better understanding. When in CO 620 and CPE When a new communication channel is initialized between 600, each memory 604/624 can be allocated. Each memory 604/624 can also be re-allocated for a pre-existing channel, for example, when the uplink and/or downlink channel status changes or when the CPE 600 or CO 620 resumes from a low power or sleep mode.

Data is transmitted from CO 620 to CPE 600 on a downstream channel (DS) 640. The data is transmitted from CPE 600 to CO 620 on an upstream channel (US) 642. The CPE and CO memory 604/624 are initially allocated according to a predetermined configuration, for example, as described above according to step 202 in FIG. 2, step 300 in FIG. 3, or step 502 in FIG. 5. During the channel initialization and training phase, the CO processor 622 establishes a communication link with the CPE 600 on the downlink channel and the uplink channel 640/642. According to the multiple downlink channel states estimated at the CPE 600, the CPE 600 estimates the interleaver and deinterleaver and/or other pre- and post-processing memory requirements for the downlink direction during the initialization and training period. The CPE 600 passes the downstream memory request to the CO 620 on the upstream channel 642.

Similarly, according to the multiple uplink channel states estimated at the CO 620, the CO 620 estimates the interleaver and deinterleaver and/or other pre- and post-processing memory requirements for the uplink during the initialization and training period. The CO 620 analyzes both the upstream memory requirements and the downstream memory requirements, and determines the final upstream and downstream interleaver and deinterleaver and/or other pre- and post-processing memory allocations based on these memory requirements. If the memory allocation at the CPE 600 changes, according to the analysis performed at the CO 620, the final memory allocation is transferred from the CO 620 to the CPE 600 on the downlink channel 640 during the training and initialization period. Otherwise, instruct CPE 600 to use the initial predetermined memory allocation for subsequent normal data communication.

In detail, the CO 620 includes one of the aforementioned types of memory allocation unit 630. For example, according to the impulse noise level, user interference, crosstalk, electrical and radio interference, etc. observed for the uplink channel 642 at the CO 620, the CO memory allocation unit 630 estimates multiple channel states for the uplink channel 642. According to the upstream channel status, the CO memory allocation unit 630 determines the upstream memory requirement for one of the CO deinterleaver buffer 628 and the CPE interleaver buffer 606. The CO memory allocation unit 630 also processes the lower-line memory requirements for the CPE deinterleaver buffer 608 and the CO interleaver buffer 626 received from the CPE 600. The downstream memory request received from the CPE 600 is based on the multiple downstream channel states estimated at the CPE 600 for the downstream channel 640.

Then, the CO memory allocation unit 630 determines whether the sum of the upstream memory requirement and the downstream memory requirement exceeds the available memory capacity for building the CO interleaver and deinterleaver buffers 626 and 628. If the sum of the upstream memory request and the downstream memory request is different from the total usable amount of the memory 624, the CO memory allocation unit 630 modifies at least one of the memory requirements. As mentioned above, according to the upstream memory requirements determined at CO 620 based on the upstream channel status, the downstream memory requirements received from CPE 600, the available amount of CO/CPE memory 624/604, and CO 620 One or more configuration parameters (such as uplink and downlink data transmission rate, maximum delay, QoS (Quality of Service) requirements, pulse noise protection configuration parameters, etc.) can be used, and the CO memory allocation unit 630 can modify the uplink memory Either or both of requirements and downstream memory requirements. However, compared with the process of estimating the memory requirements of the downstream interleaver based on the status of multiple upstream channels, the CPE 600 provides the memory requirements of the downstream interleaver to the CO 620 based on the actual observed downstream channel status. In this way, according to a better understanding of the downstream channel 640, the CO memory allocation unit 630 can determine a more efficient memory allocation.

According to an embodiment, the CO memory allocation unit 630 determines which of the memory requests to modify according to a priority bit. The priority bit indicates the priority of the upstream memory request and the downstream memory request. If the priority bit indicates that the upstream channel 642 has priority, the CO memory allocation unit 630 allocates enough CO memory 624 to the receiving deinterleaver buffer 628 of the CO 620 to meet the upstream buffer requirement. The remaining CO memory 624 is allocated to the transmission interleaver buffer 626 of the CO 620. When the priority bit indicates that the downstream channel 640 has priority, the opposite memory allocation is performed. In each case, the sum of the upstream memory requirement and the downstream memory requirement is preferably set to be equal to the total amount of CO memory 624 available for interleaving and deinterleaving. The CPE memory 604 can be allocated in the same way according to priority bits.

For example, when a conflict occurs, the second embodiment for memory allocation also includes reusing the priority bit to determine which of the channels 640 and 642 has a higher priority. According to the second embodiment, depending on the priority and the magnitude of a correction factor (CF), the CO memory 624 can be allocated in three different ways. When the downstream channel 640 has priority and CF&gt;1, the amount of the CO memory 624 allocated to the receiving deinterleaver buffer 628 of the CO 620 is given by equation (6). Then, the remaining CO memory 624 is allocated to the transmission interleaver buffer 626 of the CO 620. When the upstream channel 642 has priority and CF&lt;1, the amount of the CO memory 624 allocated to the transmission interleaver buffer 626 of the CO 620 is given by equation (7). The remaining CO memory 624 is allocated to the receiving interleaver buffer 628 of the CO 620. When none of the two previous states identified above are satisfied, the third memory allocation option appears. Here, the total available CO memory 624 is equally divided between the interleaver buffer of the CO 620 and the deinterleaver buffers 626 and 628. In each case, the sum of the upstream memory requirement and the downstream memory requirement is preferably set to be equal to the usable amount of the CO memory 624. The CPE memory 604 can be allocated in the same way according to priority bits and correction factors.

At the CPE 600, during the initialization and training period, the CPE processor 602 assists in establishing a communication link with the CO 620 on the downlink channel and the uplink channel 640, 642. The CPE 600 also includes one of the aforementioned types of memory allocation unit 610. The CPE memory allocation unit 610 processes the upstream memory request received from the CO 620 for one of the CPE deinterleaver buffer 628 and the CO interleaver buffer 606. As described above, the upstream memory requirement is based on the estimated channel status of the upstream channel 642 at the CO 620. Therefore, the CO 620 sets the uplink memory allocation at the CPE 600 based on the multiple uplink channel states estimated at the CO 620.

For example, according to the impulse noise level, user interference, crosstalk, electrical and radio interference, etc. observed at the CPE 600, the CPE memory allocation unit 610 can estimate the status of multiple downlink channels for the downlink channel 640. The CPE 600 can estimate the status of the multiple uplink channels in substantially the same manner as the CO 620 estimates the status of the multiple uplink channels. Then, according to the status of the downlink channel, the CPE memory allocation unit 610 determines the lower memory requirements for the CPE deinterleaver buffer 608 and the CO interleaver buffer 626.

In one embodiment, the CPE memory allocation unit 610 estimates the capacity of the downlink channel 640 according to the downlink channel states, and determines a condition that satisfies the downlink capacity estimation and one or more predetermined downstream configuration parameters (such as the maximum expected Data transfer rate and minimum delay) below the line interleaver/deinterleaver buffer size. Each parameter has a specific standard (such as a minimum and/or maximum). The CPE memory allocation unit 610 can determine the downstream memory requirements to meet the configuration parameter standards. Then, the CPE processor 602 transmits the downlink memory request to the CO 620, and the CO 620 performs the above-mentioned processing to determine whether any memory allocation correction is needed. In one embodiment, after receiving the uplink memory request from the CO 620 during the channel initialization and training period, the CPE processor 602 transmits the downlink memory request to the CO 620 on the uplink channel 642.

According to receiving the upstream memory request from the CO 620 and determining the downstream memory request at the CPE 600, the CPE memory allocation unit 610 allocates the CPE memory between the interleaver buffer of the CPE 600 and the deinterleaver buffers 606 and 608body604. Depending on the total available memory, the CO 620 can determine the modification to the required memory allocation, for example, when there is not enough memory to satisfy both the upstream memory requirements and the downstream memory requirements. When this state occurs, the CO 620 modifies the upstream memory allocation and/or the downstream memory allocation as described above, and transmits the memory allocation correction(s) to the CPE 600. For example, the CO 620 can determine that only the interleaver memory allocation or only the deinterleaver memory allocation needs to be modified. Alternatively, the CO 620 can determine that both the interleaver memory allocation and the deinterleaver memory allocation must be modified. In each case, based on the memory allocation correction(s) received from the CO 620, the CPE memory allocation unit 610 allocates the CPE memory between the interleaver buffer of the CPE 600 and the deinterleaver buffers 606, 608body604. In this way, both the CPE and the CO memory 604/624 are allocated based on the upstream channel status observed at the CO 620 and the downstream channel status observed at the CPE 600.

Figure 7 shows an embodiment of a message protocol that is implemented between the CO 620 and the CPE 600 during the channel initialization and training process. According to this embodiment, both CO 620 and CPE 600 are modems that comply with VDSL2. During the channel initialization and training process, a special operations channel (SOC) is established between the CO 620 and the CPE 600 to enable two-way communication of messages between the two modems to support initialization and quick start (fast startup), and loop diagnostic procedures. When the SOC at the CO 620 is in the active state but is idle (that is, there is no message to be sent), the CO 620 sends an idle message (O-IDLE). When the SOC of the CPE 600 is in the active state but is idle, it can similarly send an idle message (R-IDLE).

Then, the CO 620 sends an O-MSG1 message to the CPE 600, which includes the capabilities of the CO 620 and multiple downlink configuration parameters. As mentioned above, the O-MSG1 message also includes the upstream interleaver memory request/deinterleaver memory request determined at the CO 620 based on the upstream channel status. In one embodiment, two new fields are added to the regular O-MSG1 message. The first new field indicates the upstream interleaver memory requirement/deinterleaver memory requirement determined by CO 620 in the upstream direction for delay path #0. The second new field similarly indicates the upstream interleaver memory requirement/deinterleaver memory requirement determined by CO 620 in the upstream direction for delay path #1. If a single delay path is supported (ie, delay path #0), CO 620 sets the value for delay path #1 to zero in the second column. Each new field can have the size of one or more bytes to indicate the upstream memory requirements.

The CPE 600 responds to the O-MSG1 message received from the CO 620 by sending an R-MSG2 message containing the capabilities of the CPE 600. As mentioned above, the R-MSG2 message also includes the lower row interleaver memory request/deinterleaver memory request determined at the CPE 600 based on the status of the downlink channels. In one embodiment, two new fields are also added to the regular R-MSG2 message. The first new field indicates the row interleaver memory requirement/deinterleaver memory requirement determined by CPE 600 in the downstream direction for delay path #0. The second new field similarly indicates the row interleaver memory requirement/deinterleaver memory requirement determined by CPE 600 in the downstream direction for delay path #1. If a single delay path is supported, the CPE 600 sets the value for delay path #1 to zero in the second field of the R-MSG2 message. Each new field included in the R-MSG2 message can have the size of one or more bytes to indicate downstream memory requirements. Then, CPE 600 sends the R-MSG2 message to CO 620 for processing.

If the sum of the upstream memory requirement determined at the CO 620 and the downstream memory requirement received from the CPE 600 is less than or equal to the maximum memory capacity available for a specific profile at the CO and CPE, it will be the same as the conventional method , CO 620 and CPE 600 continue to exchange information. For example, the CO 620 sends an O-TPS message to the CPE 600 to indicate the configuration of the bearer channel and the required capabilities for both the upstream direction and the downstream direction. The CPE 600 acknowledges the O-TPS message with an R-TPS-ACK message. Then, the CO 620 transmits the uplink frame parameters to the CPE 600 by sending an O-PMS message. The CPE 600 similarly transmits the downlink frame parameters to the CO 620 by sending an R-PMS message. Then, the CO 620 sends an O-PMD message to the CPE 600, which includes the bit, gain, and tone sequence table for the uplink physical media dependent (PMD) function. The CPE 600 responds by sending an R-PMD message to the CO 620, which contains a bit, gain, and tone sequence table for the downstream PMD function. After sending the R-PMD, the CO 620 and the CPE 600 are ready to switch to showtime (ie, normal data communication).

When the sum of the upstream memory requirement and the downstream memory requirement is less than or equal to the maximum memory capacity available at the CO and CPE, as described above, allocate additional available memory to the direction with higher priority. However, if the total memory requirement is greater than the total available memory capacity, the CO 620 modifies one or both of these memory requirements. In one embodiment, the CO 620 will be determined by the CPE 600 and transmitted in the R-MSG2 message to take into account the memory requirements. For example, the CO 620 may also consider one or more additional configuration parameters from the CO MIB, and determine a revised upper memory requirement, a revised lower memory requirement, or both. The CO 620 transmits the memory allocation correction or corrections to the CPE 600 in the downstream direction using O-PMS messages. In this way, without any information about the downlink environment and the corresponding interleaver/deinterleaver settings, the CO 620 will not make arbitrary memory allocation decisions.

When the total memory requested as part of the O-MSG1/R-MSG2 message exchange is more than the total memory designated for a specific profile, the downstream information received from the CPE 600 provides a competitive resolution for the CO 620 Control mechanism. Consider the following only illustrative example, in which the CO 620 and CPE 600 are configured for the VDSL2 profile 12a. The total available memory for the operation of the upstream and downstream interleaver and deinterleaver is 64 KB, and the downstream channel 640 has a higher priority. According to the impulse noise and delay requirements, the CO 620 can determine that the upstream channel 642 requires 48 KB of interleaver/deinterleaver memory, and the CPE 600 can determine that the downstream channel 640 also requires 48 KB of interleaver-deinterleaver memory. Therefore, the total memory system required is 96 KB, which is greater than the total available memory capacity for the 12a VDSL2 profile (64 KB in this example). In response, because the downlink has a higher priority, the CO 620 can allocate 48 KB for the downlink and the remaining available memory (16 KB) for the uplink. This memory allocation can make the data transmission rate of the uplink channel 642 lower. However, considering the status and priority of the uplink and downlink channels, this trade-off is optimized.

CO 620 can also use a correction factor to determine the final memory allocation. The correction factor can be used as a supplement or replacement for priority information. The correction factor determines the percentage of excess or insufficient memory that should be shared between the downstream direction and the upstream direction. In some embodiments, the parameter is in the range of 1% to 100%. In other embodiments, the correction factor may be an integer or non-integer value, rather than a percentage. In another illustrative example only, a correction factor of 50% indicates that if any excess memory is available, it should be shared equally between the upstream and downstream directions. If the available memory is less than the required memory, the reduction of memory should be equally distributed in the upstream direction and the downstream direction. In another illustrative example, a 75% correction factor indicates that if any excess memory is available, then 75% of it should be allocated to the direction with higher priority and the remaining 25% should be allocated To the other direction. If there is not enough memory available, this reduction is achieved by subtracting 75% of the excess requirement from the direction with lower priority and subtracting the remainder from the direction with higher priority. When 64 KB of total memory is available for interleaver and deinterleaver buffering (ie VDSL2 profile 12a) and CPE 600 determines that 48 KB is required for downstream and CO 620 determines that 48 KB for upstream is required, the required memory The volume reduction is 32 KB, so there are 32 KB needs to be adjusted. If the downlink has priority, 25% of the 32 KB reduction (ie 8 KB) is removed from the downlink interleaver/deinterleaver allocation and 24 KB is removed from the uplink interleaver/deinterleaver allocation. Of course, those who are familiar with the technology will easily realize that various other memory allocation correction factors can be used according to the teaching content disclosed in this article.

Based on the above various changes and applications, it should be understood that the present invention is not limited by the above description, and is not limited by the accompanying drawings. In addition, the present invention is only limited by the scope of the following patent applications and their legal equivalents.

<p>100. . . Communication device</p><p>102. . . processor</p><p>104. . . Digital interface</p><p>106. . . Framer</p><p>108. . . Deframer</p><p>110. . . Encoder</p><p>112. . . decoder</p><p>114. . . Interleaver</p><p>116. . . Deinterleaver</p><p>118. . . Memory</p><p>120. . . Front end (FE)</p><p>122. . . Interleaver buffer</p><p>124. . . Deinterleaver buffer</p><p>126. . . Transmission circuit</p><p>128. . . Receiving circuit</p><p>130. . . Communication link</p><p>132. . . Memory allocation unit</p><p>600. . . Customer Provided Equipment (CPE)</p><p>602. . . processor</p><p>604. . . Memory</p><p>606. . . Transmission interleaver buffer</p><p>608. . . Receive deinterleaver buffer</p><p>610. . . Memory allocation unit</p><p>620. . . Communication equipment (CO)</p><p>622. . . processor</p><p>624. . . Memory</p><p>626. . . Transmission interleaver buffer</p><p>628. . . Receive deinterleaver buffer</p><p>630. . . Memory allocation unit</p><p>640. . . Downstream Channel (DS)</p><p>642. . . Uplink channel (US)</p>

Figure 1 is a schematic diagram of an embodiment of a communication device, the communication device including a memory allocated between an interleaver buffer and a deinterleaver buffer;

Figure 2 is a logic flow diagram of an embodiment of the processing logic for allocating a memory between an interleaver buffer and a deinterleaver buffer in a communication device;

Figure 3 is a logic flow diagram of another embodiment of the processing logic for allocating a memory between an interleaver buffer and a deinterleaver buffer in a communication device;

Figure 4 is a logic flow diagram of another embodiment of processing logic for allocating a memory between an interleaver buffer and a deinterleaver buffer in a communication device;

Figure 5 is a logic flow diagram of still another embodiment of the processing logic for allocating a memory between an interleaver buffer and a deinterleaver buffer in a communication device;

Figure 6 is a schematic diagram of an embodiment of a first communication device. The first communication device has a memory allocated between a pre-processing buffer and a post-processing buffer, and the first communication device is coupled On a second communication device, the second communication device also has a memory allocated between a pre-processing buffer and a post-processing buffer; and

FIG. 7 is a message flow diagram of an embodiment for allocating a memory between the pre-processing buffer and the post-processing buffer of the communication devices shown in FIG. 6.