Data transfer between asynchronous clock domains

Data transfer between asynchronous clock domains

Data transfer between asynchronous clock domains

Several embodiments of the present invention generally relate to the field of asynchronous clocks in systems or devices such as processors. More particularly, several embodiments of the present invention are related to system or device configurations that facilitate the testing of systems with asynchronous clock domains.

Integrated circuits traditionally use synchronization protocols for data transmission. Existing testing and verification techniques rely on a cycle-by-cycle deterministic synchronization model.

In massively parallel architecture or platform-level design, the number and diversity of interactive clock domains increase. Because of engineering costs, power consumption, and project-level risks, synchronization of all clock domains can be prohibited. Therefore, more of these architectures and designs utilize multiple asynchronous clock domains. However, it is difficult to use industry standard verification hardware and software to verify or simulate a completely asynchronous architecture.

Large integrated circuits and other systems, including processors and other devices, are increasingly using more asynchronous clock domains. Asynchronous clock domains usually communicate with each other via intermediate buffers that can be accessed from different clock domains.

During development, the device and logic can be monitored to confirm that it operates as desired and produces the expected results. However, the available testing and diagnostic equipment is typically not designed to work with asynchronous clock domains. Rather, such testing and diagnostic equipment typically relies on deterministic relationships between components and subsystems. Up and down Determinism in the text refers to the affirmation of the clock cycle on which processor events occur. It ensures the reproducibility of the event and is the basis for most of the mass manufacturing experiments that include this event. The non-deterministic nature of the asynchronous clock field presents challenges, especially when developers want to record and regenerate conditions and events that cause detected failures or errors.

The example described below provides a method for testing equipment to record and reproduce runtime interactions between asynchronous clock domains. In an embodiment, the first clock domain and the second clock domain transmit data in response to a synchronization signal generated in synchronization with the clock of the first clock domain. Each period of the synchronization signal is called a synchronization period in the text, and the number of clock periods in the second clock domain can be changed. However, the implementation described below generates a report output to indicate the correspondence between the synchronization period and the period of the second clock domain. The report output can be recorded by the test equipment and allows the test equipment to determine the number of clock cycles occurring in the first and second clock domains during each synchronization period in response to actual operating conditions. This allows subsequent simulation of device operations and re-creation of recorded events.

FIG. 1 depicts a device or system 100 having a first clock domain 102 and a second clock domain 104. As an example, the system 100 may be a processor or similar type of device.

The first clock domain 102 has or is associated with a first clock 106 that generates a first clock signal CLOCK1. The second clock domain 104 has or is related to the second clock 108 that generates the second clock signal CLOCK2. The first and second clock signals CLOCK1 and CLOCK2 are asynchronous, and therefore may not have a deterministic frequency or phase relationship.

The first and second clock areas 102 and 104 may each have various components and/or elements (not shown), which operate in response to the respective clock signals CLOCK1 and CLOCK2.

The system 100 may have a synchronization clock 110, which responds to the first clock signal CLOCK1 to generate a synchronization signal or pulse SYNC. In some embodiments, the synchronization clock 110 can be implemented as a frequency divider, so that the synchronization pulse SYNC is generated at a frequency lower than the first clock signal CLOCK1 and has a fixed phase relationship with the first clock signal CLOCK1. For example, the synchronization clock 110 can generate a single synchronization pulse corresponding to every N cycles of the first clock signal CLOCK1, where N is an integer. The period defined by the synchronization signal will be referred to as the synchronization period or cycle in the text.

The system 100 may also have data transfer logic 112 to transfer data between the first and second clock domains 102 and 104. The data transmission logic 112 may include one or more intermediate registers or buffers, and may respond to the synchronization pulse SYNC to initiate and/or implement data transmission or exchange. During the exchange period, data may be transferred from the first clock domain 102 to the second clock domain 104 and/or from the second clock domain 104 to the first clock domain 102. A more specific implementation of the transfer logic 112 will be described below in conjunction with the description of FIG. 4.

The system 100 may include a reporting logic 114 that generates a clock count signal COUNT corresponding to each synchronization period. The clock counting signal COUNT can be generated in response to the synchronization pulse SYNC and the second clock signal CLOCK2. The clock counting signal COUNT can indicate the number of generation periods of the second clock signal CLOCK2 for each SYNC pulse or corresponding synchronization period. Please note This means that because of the asynchronous relationship between the first and second clock domains, the number of CLOCK2 cycles occurring between SYNC pulses can be uncertain and can change over time. The clock count signal COUNT indicates the number of CLOCK2 cycles actually occurring corresponding to the individual synchronization period.

The clock counting signal COUNT can be generated and output in synchronization with the first clock signal CLOCK1, the second clock signal CLOCK2, and/or the synchronization pulse SYNC.

The clock counting signal COUNT provides a mechanism for correlating and reporting the running time operation of the first clock domain 102 and the second clock domain 104, which can be recorded and used by testing and verification equipment to reproduce the status before the error condition and sequence. Because the SYNC pulse is generated from the first clock signal CLOCK1, the number of CLOCK1 cycles per SYNC pulse is known. Because the second clock domain 104 and the first clock domain 102 are asynchronous, the number of CLOCK1 cycles per SYNC pulse may be variable. However, the reporting logic 114 monitors the performance of the actual observations and provides the clock count signal COUNT as an indication of how many CLOCK2 cycles actually occurred for each SYNC pulse. Therefore, the two clock domains can be allowed to run asynchronously, and their operations can be monitored, recorded, and related to each other by verification and test equipment: for each SYNC pulse, the corresponding CLOCK1 and CLOCK2 that actually occur can be determined and recorded The number of cycles.

Figure 2 depicts the signal relationships in the system 100. Please note that in this depiction, the signal under consideration becomes active at its rising edge. Figure 2 shows the relationship between the CLOCK1, SYNC, CLOCK2, and COUNT signals in Figure 1.

The CLOCK1 signal can be a periodic, repetitive, and/or periodic signal, such as the depicted square wave. The synchronization pulse SYNC may be similar to a periodic, repetitive, or periodic signal, such as repetitive or periodically occurring pulses. As explained above, the synchronization pulse SYNC can be synchronized with the CLOCK1 signal, and can have a lower frequency than the CLOCK1 signal. In the depicted example, the synchronization pulse SYNC is repeated every two cycles of the CLOCK1 signal. More generally, the synchronization pulse SYNC can occur once every N cycles of the CLOCK1 signal, where N is an integer. Each synchronization pulse SYNC corresponds to each synchronization period.

The CLOCK2 signal can be a periodic, repetitive, and/or periodic signal, such as the depicted square wave. The CLOCK2 signal may have a different frequency from the CLOCK1 signal, and may have an indeterminate or variable phase relationship with the CLOCK1 signal and the SYNC signal.

In this example, the frequency of the CLOCK2 signal causes it to occur once or twice in each repetition, period, or cycle of the SYNC pulse. At the rising edge of each SYNC pulse, the COUNT signal is updated to indicate the actual number of CLOCK2 cycles (as indicated by x in Figure 2), which occurred during the previous SYNC period, where the synchronization period is defined by the rising edge of the SYNC signal (Indicated by the dashed vertical line in Figure 2). In this example, the low value of the count signal corresponds to one cycle of the CLOCK2 signal, and the high value of the COUNT signal corresponds to two cycles of the CLOCK2 signal. In the case where the normal frequencies of the CLOCK1 and CLOCK2 signals are different from those shown, the COUNT signal can of course be used to indicate different CLOCK2 counts. In addition, the COUNT signal can be in several situations, including multi-bit signals or values.

FIG. 3 depicts an example of a device or system 300 in which an intermediate storage element or buffer 302 is used to transfer data asynchronously between the first clock domain 304 and the asynchronous second clock domain 306. The device or system 300 example uses the techniques described above to transmit buffer indicators between the first and second clock domains 304 and 306.

The intermediate storage buffer 302 may include an elastic buffer such as a first-in first-out (FIFO) buffer. In a specific example, the first clock domain 304 is synchronized with the first clock signal CLOCK1 to write data into the FIFO buffer 302. The second clock area 306 is synchronized with the second clock signal CLOCK2 to read data from the FIFO buffer. The first and second clock signals CLOCK1 and CLOCK2 can be asynchronous.

In order to coordinate the writing and reading between the first and second clock areas 304 and 306, the writing and reading indicators are maintained in the first and second clock areas 304 and 306. More specifically, the first clock area 304 maintains a write indicator 308, which indicates the address of a position below the FIFO buffer 302 to be written. After the first clock area 304 is written to this position of the FIFO buffer 302, the write index 308 is incremented.

The second clock area 306 maintains a read index 310, which indicates the address of a position below the FIFO buffer 302 to be read. After the second clock area 306 is read from this position in the FIFO buffer 302, the read index 310 is incremented.

The first clock area 304 may also have a shaded or duplicate read index 312, which is updated from time to time to reflect the value of the read index 310 of the second clock area 306. In order to prevent the second clock area 306 from overwriting the unread data, the first A clock area 304 does not write to a location beyond the address indicated by the shadow read indicator 312.

Similarly, the second clock area 306 may have a shaded or duplicate write indicator 314, which is updated from time to time to reflect the value of the write indicator 308 of the first clock area 304. In order to avoid reading invalid data, the second clock area 306 does not perform reading from a position exceeding the address indicated by the shadow write indicator 314.

The system 100 may have a synchronization clock 316, which is configured similarly to the synchronization clock 110 of FIG. 1 to generate a synchronization signal or pulse SYNC according to the first clock signal CLOCK1. In this embodiment, the SYNC pulse is used to update the shadow read index 312 and the shadow write index 314. More specifically, the SYNC pulse is used to time or latch the data from the read indicator 310 into the shadow read indicator 312, and to time or latch the data from the write indicator 308 into the shadow write indicator 314.

The shaded read indicator 312 may include a latch or a register, which receives the current value of the read indicator 310 from the second clock domain 306. This value is captured by the latch or register 312 after receiving the SYNC pulse or in response to receiving the SYNC pulse. Similarly, the shadow write indicator 314 may include a latch or register configured to receive the current value of the write indicator 308 from the first clock domain 304. This value is captured by the latch or register 314 in response to receiving the SYNC pulse.

Similar to the embodiment of FIG. 1, the system 300 may have reporting logic 318 to report the number of CLOCK2 cycles that occur during each repetition or period of the SYNC signal. The reporting logic 318 can generate a clock count signal COUNT to indicate the clock period of the first clock domain 304 and the second clock Correlation between clock cycles of domain 306. As explained above, the count signal can be used by the test and verification equipment to record and later simulate the conditions and sequences before the error condition.

The shadow reading index 312 and the shadow writing index 314 can be clocked directly by the SYNC pulse, or can be clocked synchronously with each clock area in response to each SYNC pulse. For example, the reading indicator 312 can be clocked by the CLOCK1 signal in response to each SYNC pulse. Similarly, the write indicator 314 can be clocked by the CLOCK2 signal in response to each SYNC pulse.

Figure 4 depicts an example implementation of the system 400, which demonstrates the concepts described above. The system 400 has a first clock domain 402 and a second clock domain 404. The first clock domain 402 operates in response to the first clock signal CLOCK1. The second clock domain 404 operates in response to the asynchronous second clock signal CLOCK2.

The first and second clock areas 402 and 404 use intermediate elastic buffers or FIFOs (not shown) to transmit data, which can be similar to the FIFO buffer 302 in FIG. 3. As explained with reference to FIG. 3, the buffer is addressed by indicators. Specifically, the first clock area 402 maintains the writing indicator 406 and the shadow reading indicator 408. The second clock area 404 maintains the read index 410 and the shadow write index 412. The shadow write index 412 is periodically updated to reflect the value of the write index 406. The shadow reading index 408 is periodically updated to reflect the value of the reading index 410.

In this example, the synchronous clock can be implemented as being divided by the N divider 414 in the first clock domain 402. The frequency divider 414 generates the SYNC signal as the function of the first clock signal CLOCK1. The SYNC signal can contain fixed Periodic or repetitive pulses, which occur at a lower frequency than the CLOCK1 signal, and are also synchronized with the CLOCK1 signal.

The SYNC signal is transmitted or propagated from the first clock domain 402 to the second clock domain 404, and then returns to the first clock domain 402. More specifically, the SYNC signal is transmitted from the first clock domain 402 to the second clock domain 404 via the first metastable hardening flip-flop 416. The flip-flop 416 generates the write SYNC signal, which can be a delayed version of the SYNC signal. The write SYNC signal is transmitted from the second clock domain 404 via the second metastable hardening flip-flop 418 back to the first clock domain 402. The flip-flop 418 generates the read SYNC signal, which can be a delayed version of the write SYNC signal.

In this embodiment, the DQ latch is used to respond to various versions or examples of synchronization signals, including SYNC signals, write SYNC signals, and read SYNC signals, and transmit the first and second clock domains 402 and 404 Between indicators.

The first latch or transfer register 420 in the first clock area 402 receives the value of the write index 406 in the first clock area 402 at its input. The synchronization cycle is initiated by the SYNC signal, and the latch write index value enters the latch 420, so that it can be received and read by the second clock domain 404.

In response to the write SYNC signal, the second latch or transfer register 422 in the second clock area 404 receives the write index value from the first latch 420 to latch the value.

The third latch or transfer register 424 in the second clock area 404 receives the value of the read index 410 in the second clock area 404 at its input. In response to the write SYNC signal, the value is latched into the third latch 424, so that The value can be received and read by the first clock field 402.

The fourth latch or transfer register 426 in the first clock area 402 receives the read index value from the third latch 424, and responds to the read SYNC signal to latch the read index from the third latch 424 value.

These events can be summarized as the following sequence of actions, which can be collectively referred to as the synchronization cycle in this embodiment: SYNC starts the synchronization cycle and latches the write index into the output latch 420; Writes the SYNC latch from the output latch 420 The write indicator of SYNC enters the input latch 422; Write SYNC also latches the read indicator 410 into the output latch 424; and Read SYNC latch The read indicator from the output latch 424 enters the input latch 426.

The second clock domain 404 may have reporting logic 428, similar to the reporting logic described above. The reporting logic 428 responds to the write SYNC signal and the second clock CLOCK2, and generates a COUNT output for each cycle or pulse of the write SYNC indicating the number of corresponding CLOCK2 cycles that occurred during the previous write SYNC period or the synchronization period.

The value of N can be selected according to the ratio of the first clock signal CLOCK1 and the second clock signal CLOCK2 in a way that has the least possibility of data overwriting and/or data starvation. If the synchronization step defined by the SYNC signal is too fast, the first clock domain can start the synchronization cycle before the second clock domain has a chance to process the previous synchronization cycle. If the synchronization step defined by the SYNC signal is over Slow, the second clock area can sometimes be hungry for data, even if there is unread data in the FIFO buffer.

The components within the dashed box 430 can be regarded as or referred to as the write indicator transfer logic. The components within the dashed box 432 can be regarded as or referred to as read indicator transmission logic. The write and read indicator logics 430 and 432 represent implementation examples of the transfer logic 112 shown in FIG. 1.

FIG. 5 depicts an example of embodiment 500, which is a variation of the embodiment of FIG. 4. In FIG. 5, the write and read index logics 430 and 432 are each copied K times to generate the multi-register write buffer 502 and the multi-register read buffer 504. Each of these buffers can be configured to operate in a FIFO manner, allowing the first and second clock domains 402 and 404 to process synchronization cycles at different rates. For example, this may allow the first clock domain 402 to initiate synchronization cycles at a faster rate than the second clock domain 404 can process synchronization cycles.

The embodiment of FIG. 5 includes a K-phase clock generator 506, which responds to a single-bit SYNC signal to generate a multi-bit SYNCK signal. The SYNCK signal includes K signal bits, which are used to time each instance of the write indicator logic 430 and the read indicator logic 432.

Figure 6 depicts the relationship of individual bits of the SYNCK signal with respect to a single-bit SYNC signal. This example assumes K=4. The SYNCK signal includes K individual bits or signals, called SYNC1, SYNC2, SYNC3, and SYNC4. Each of the individual SYNCK signals is generated by K divided SYNC signals. In addition, the individual SYNCK signals are staggered, so that a single SYNCK signal is generated for each occurrence of the SYNC signal.

Referring again to FIG. 5, each of the write transfer logic conditions 430 can correspond to and respond to a different one of the individual SYNCK signal bits. Similarly, each of the read transfer logic conditions 432 can respond to a different one of the individual SYNCK signal bits. This configuration effectively implements FIFO logic for the transmitted indicator, allowing it to read and write asynchronously through the first and second clock domains 402 and 404.

FIG. 7 depicts an example of a method 700 for transferring data between asynchronous clock domains. Act 702 includes timing the first clock domain with the first periodic clock signal. Act 704 includes timing the second clock domain with the second periodic clock signal. As discussed above, the first and second periodic clock signals may be asynchronous.

Act 706 includes generating a synchronization signal. The synchronization signal can be synchronized with the first clock signal, and can be generated by dividing the frequency of the first clock signal by an integer N. Therefore, the first clock signal may have a frequency that is a fixed integer multiple of the synchronization signal.

Action 708 may include propagating the synchronization signal from the first clock domain to the second clock domain, and then returning from the second clock domain to the first clock domain.

Action 710 may include aligning the index between the first and second clock domains in response to the synchronization signal. In response to propagating the synchronization signal from the first clock domain to the second clock domain, the first buffer indicator can be transmitted from the first clock domain to the second clock domain. In response to propagating the synchronization signal from the second clock domain back to the first clock domain, the second buffer indicator can be transmitted from the second clock domain to the first clock domain.

Action 712 may include indicating and/or reporting the synchronization signal and the second clock Correspondence between the periods of the signal. For example, action 710 may include indicating the corresponding number of cycles of the second clock signal for each occurrence of the synchronization signal.

Figure 8 is a block diagram depicting the architecture of a system 800 that can implement the techniques described above. The system 800 may include one or more processors 802-1, ..., 802-N (where N is a positive integer<img file="TWI506397B_D0001.tif" he="53" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="48" />1), each of which may include one or more processor cores 804-1,...,804-M (where M is a positive integer<img file="TWI506397B_D0002.tif" he="53" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="44" />1). In several implementations, the processor 802 may be a single core processor, while in other implementations, the processor 802 may have many processor cores, each of which may include some or all of the components depicted in FIG. 8.

The processor 802 and the processor core 804 can operate in conjunction with the local interconnect 816 via an integrated memory controller (IMC) 810 to read and write to the memory 812. The processor 802 and the processor core 804 can also execute computer readable instructions stored in the memory 812 or other computer readable media. The memory 812 may include volatile and non-volatile memory and/or removable and non-removable media implemented in any type of technology to store information, such as computer readable instructions, data structures, program modules, or other data . Such memories may include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technologies. In some implementations, if there is a multi-processor core 804, the multi-processor core 804 can share the cache 814, which can be accessed via the local interconnect 816.

The storage 818 may be provided for storing data, codes, programs, registrations, and the like. The storage 818 may include solid-state storage, magnetic disk storage, RAID storage system, storage array, network attached storage, storage area network, cloud storage, CD-ROM, digital audio-visual disc (DVD) or other optical discs. Learning storage, cassette tape, magnetic tape, or any other medium that can be used to store desired information and that can be accessed by a computing device. According to the configuration of the system 800, the memory 812 and/or the storage 818 may be a computer-readable storage medium and may be a non-transitory medium.

In various embodiments, the local interconnect 816 may also communicate with the graphics controller or the graphics processing unit 820 to provide graphics processing. Furthermore, in several embodiments, the local interconnect 816 can communicate with the system agent 822. The system agent 822 can communicate with the hub 824, which is connected to the display engine 826, the peripheral component interconnection device (PCIe) 828, and the desktop management interface (DMI) 830.

The memory 812 can store functional components that can be executed by the processor 802. In some implementations, the functional components include instructions or programs 832, which can be executed by the processor 802. The functional component example depicted in FIG. 8 further includes an operating system (OS) 834 to manage the operations of the system 800.

The system 800 may include one or more communication devices 836, which may include one or more interfaces and hardware components for communicating with various other devices through a communication link, such as one or more networks 838. For example, the communication device 836 can facilitate communication via one or more of the Internet, a cable network, a cellular network, a wireless network (such as Wi-Fi, a cellular component), and a wired network. The components used for communication may depend at least in part on the selected network and/or environment type. The protocols and components used to communicate via these networks are known and will not be discussed in detail in this article.

The system 800 can be further equipped with various input/output (I/O) devices 840. The I/O device 840 may include a display, various user interface controls Control (such as buttons, joysticks, keyboards, touch screens, etc.), audio speakers, ports, etc. An interconnection 824 can be provided, which can include a system bus, a point-to-point interface, a chipset, or other appropriate connections and components to enable the processor 802, memory 812, storage 818, communication device 836, and I/O device 840 Communication between.

Although the subject matter has been described in the special language of structural features and/or methodological actions, the subject matter defined in the scope of the patent application is not limited to the features or actions described above. Rather, the features or actions described above are disclosed in the form of examples implementing the scope of the patent application. This disclosure is intended to cover any or all adaptations or changes of the disclosed implementation, and the scope of the following patent applications should not be interpreted as being limited to the specific implementation disclosed in the specification. On the contrary, the scope of this document is completely defined by the scope of the following patent applications together with all the scopes of equivalent discussions given by the scope of such patent applications.

<p>100, 300, 400, 500, 800 system</p><p>102, 304, 402The first clock domain</p><p>104, 306, 404Second clock area</p><p>106First clock</p><p>108Second Clock</p><p>110, 316Synchronous clock</p><p>112Data transfer logic</p><p>114, 318, 428Report logic</p><p>302Buffer</p><p>308, 406 write indicator</p><p>310, 410Read index</p><p>312,408Shadow reading index</p><p>314, 412Shadow write indicator</p><p>414Crossover</p><p>416The first metastable hardened positive and negative device</p><p>418Second metastable hardened positive and negative device</p><p>420First latch or transfer register</p><p>422Second latch or transfer register</p><p>424Third latch or transfer register</p><p>426Fourth latch or transfer register</p><p>430Write indicator transmission logic</p><p>432Read pointer transmission logic</p><p>502Multi-register write buffer</p><p>504Multi-register read buffer</p><p>506K phase clock generator</p><p>700Method</p><p>702, 704, 706, 708, 710, 712Action</p><p>802, 802-1,..., 802-N processor</p><p>804, 804-1,..., 804-MProcessor core</p><p>810Integrated memory controller</p><p>812Memory</p><p>814Shared cache memory</p><p>816local interconnection</p><p>818Storage</p><p>820Graphics controller or graphics processing unit</p><p>822System Agent</p><p>824 Hub</p><p>824Interconnection</p><p>826Display Engine</p><p>828 Peripheral component interconnection device</p><p>830Desktop management interface</p><p>832Command or program</p><p>834Operating System</p><p>836Communication device</p><p>838Internet</p><p>840Input/Output Device</p><p>CLOCK1First clock signal</p><p>CLOCK2Second clock signal</p><p>COUNTClock counting signal</p><p>SYNCSync pulse</p>

A detailed description is provided with reference to the drawings. In the figure, the leftmost digit of the component symbol identifies the figure where the number first appeared. The same reference symbols are used in different drawings to indicate similar or identical items or features.

Figure 1 is a block diagram depicting an example of transferring data between asynchronous clock domains according to several implementations.

FIG. 2 is a timing diagram depicting the timing relationship in the system depicted in FIG. 1.

Figures 3-5 are block diagrams depicting further examples of transferring data between asynchronous clock domains according to several implementations.

FIG. 6 is a timing diagram depicting the timing relationship between the SYNC and SYNCK signals of FIG. 5.

FIG. 7 is a flowchart depicting an example of a procedure for transferring data between asynchronous clock domains according to several implementations.

Figure 8 is a block diagram depicting the architecture of the system in which the described techniques can be implemented.