Mountable integrated circuit package system with mounting interconnects

Mountable integrated circuit package system with mounting interconnection

MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING INTERCONNECTS

The present invention relates to an integrated circuit package system, and more particularly relates to an integrated circuit package system with a cladding body.

Integrated circuit packaging technology has experienced an increase in the number of integrated circuits mounted on a single circuit board or substrate. The new package design is more concise in terms of form factor, such as the physical size and shape of the integrated circuit, and provides a significant increase in the overall circuit density. However, integrated circuit density continues to be limited by the "real estate" where individual integrated circuits can be mounted on the substrate. Even larger form factor systems, such as personal computers, computer systems, and storage servers, require more integrated circuits in the same or smaller "board surface". In particular, the demand for portable personal electronic devices (such as mobile phones, digital cameras, music players, personal digital assistants, and positioning devices) has further driven the demand for integrated circuit density.

This increasing density of integrated circuits has led to the development of multi-chip packages, package in package (PIP), package on package (POP), or combinations thereof, resulting in more than one Individual integrated circuits can be packaged. Each package provides mechanical support for an individual integrated circuit and one or more layers of interconnection lines, and the interconnection lines can electrically connect the integrated circuit to surrounding circuits. Current multi-chip packages (also commonly referred to as multi-chip modules) typically include a substrate on which a group of individual integrated circuit components are connected. It has been found that such a multi-chip package can increase the density and miniaturization of integrated circuits, increase the signal propagation speed, reduce the size and weight of the entire volume circuit, improve performance, and reduce costs, all of which are the primary goals of the computer industry.

Multi-chip packages or PIPs with stacked configurations can also cause problems. The spacer structure can be used to create space for electrical connections in a stacked structure in which the package structure includes package integrated circuits. The spacer structure and cladding material of a typical package integrated circuit have low adhesion and can become a source of delamination. The conventional spacer and package integrated circuit interfaces perform poor delamination reliability tests at this interface.

Therefore, there is still a continuing need for integrated circuit packaging systems to provide low-cost manufacturing, improved yield, and thinner height for integrated circuits. In view of the increasing demand for cost savings and improved performance, it is found that the answers to these questions are becoming more and more critical.

There have been long-term searches for solutions to these problems, but previous developments have not taught or suggested any solutions. Therefore, solutions to these problems have long troubled those with ordinary knowledge in the technical field.

The present invention provides a mountable integrated circuit packaging method, including: mounting a first integrated circuit device on a carrier; mounting a substrate on the first integrated circuit device, the substrate having mounting interconnections; Connecting a first electrical interconnection with the substrate; and forming a package covering body to cover the carrier, the first integrated circuit device, the first electrical interconnection and the substrate, and the package covering In the cavity of the body, the mounting interconnection is partially exposed from the package covering body and surrounded by the package covering body.

In addition to or in place of the above, or obvious from the above, certain embodiments of the present invention have other aspects. These aspects will become apparent when a person with ordinary knowledge in the relevant technical field reads the following embodiments with the additional drawings.

The following embodiments are described in sufficient detail so that those skilled in the art can make and use the present invention. Other embodiments can be clearly understood based on the disclosure, and the changes in the system, manufacturing process or mechanism do not depart from the present invention. The category.

In the following description, many specific details are given to provide a complete understanding of the present invention. However, the present invention can obviously also be implemented without these specific details. In order to avoid obscuring the present invention, some known circuits, system structures and process steps are not disclosed in detail. Likewise, the drawings showing the embodiments of the system are partially diagrammatic and not to scale, and in particular, some of the dimensions are exaggeratedly shown in the drawings in order to clearly present the invention. Generally, the present invention can operate in any orientation.

In addition, some common features are disclosed and described in multiple embodiments. For clarity and ease of illustration, description, and understanding, similar and identical features will generally be described by the same element symbols. For the convenience of description, these embodiments are numbered as the first embodiment, the second embodiment, etc., and do not have any other meaning or limit the present invention.

For the purpose of illustration, the term "horizontal" used herein is defined as being parallel to the plane or surface of the integrated circuit regardless of its positioning; the term "vertical" refers to the direction of "horizontal" defined by vertical, Terms such as "above", "below", "bottom", "top", "side" (as in "sidewall" ), "higher", "lower", "upper", "over" and "under" are relative to this level Defined as a plane, the term "on" refers to direct contact between components. The term "processing" used here includes material deposition, patterning, exposure, development, etching, cleaning, Molding and/or removal of materials or formation of the above-mentioned structure is required. The term "system" used herein means and refers to the method and device of the present invention in the context in which the term is used.

Referring now to FIG. 1, there is shown a top view of the mountable integrated circuit package system 100 of the first embodiment of the present invention. The top view depicts that the package cover 102 (such as epoxy molding compound) has a cavity 104. The cavity 104 partially exposes the mounting interconnection 108, for example, in the cavity 104 of the package covering body 102, soldering exposed from the package covering body 102 and surrounded by the package covering body 102 Bump. The mounting interconnection 108 may be formed of an electrically conductive material containing tin (Sn), lead (Pb), gold (Au), copper (Cu), or a metal alloy.

For the purpose of illustration, the mountable integrated circuit package system 100 shows that the mounting interconnects 108 are arranged in an unevenly distributed array configuration, but it can be understood that the mountable integrated circuit package system 100 can be in different groups. The installation interconnection 108 under the structure. For example, the mounting interconnection 108 may be in a uniformly distributed array configuration.

Refer now to FIG. 2, which shows a cross-sectional view of the mountable integrated circuit package system 100 along line 2-2 of FIG. 1. The cross-sectional view depicts the mounting integrated circuit package system 100 having the package covering body 102 formed on a carrier 210 (e.g., a substrate), and the carrier 210 has a first integrated circuit device 212 mounted thereon ( For example: integrated circuit chip, flip chip or package integrated circuit device). Preferably, the first integrated circuit device 212 is mounted on the first inactive side 216 of the first integrated circuit device 212 with a first adhesive 214 (for example, die adhesive) and faces the carrier 210 the first carrier side 218. The second external interconnection 220 (for example: solder balls) is connected to the second carrier side 222 of the carrier 210 and is opposite to the first carrier side 218, so as to communicate with a printed circuit board or other integrated circuit package system. Connect to the next system level (not shown).

The second integrated circuit device 224 may optionally be mounted on the first integrated circuit device 212 with a second adhesive 226 (for example, a crystal adhesive). Although this example shows two integrated circuit devices stacked on the carrier 210 and under the substrate 206, it should be understood that any number of integrated circuit devices can be mounted on the first carrier side 218 and on the first carrier side 218. Under the substrate 206.

For illustrative purposes, the first integrated circuit device 212 and the second integrated circuit device 224 are shown as wire bond integrated circuits, but it should be understood that the first integrated circuit device 212 and the second integrated circuit device 212 The integrated circuit device 224 may be a different type of integrated circuit. For example, the first integrated circuit device 212 and the second integrated circuit device 224 may be an integrated circuit die, a package integrated circuit device, a flip chip, or a combination thereof.

The substrate 206 includes a first substrate side 230 with the mounting interconnect 108. The second substrate side 232 of the substrate opposite to the first substrate side 230 is mounted on the second active side 234 of the second integrated circuit device 224 with a third adhesive 236 (such as a film adhesive). In this example, the substrate 206 has an aperture 238 with an electrical interconnection 240. The electrical interconnection 240 (such as a bonding wire or a ribbon bonding wire) connects the second active side 234 and the second active side 234 through the aperture 238. One substrate side 230. The electrical interconnection 240 may also provide an electrical connection between the first carrier side 218 and the first active side 228. Similarly, the electrical interconnect 240 can also connect the first carrier side 218 and the first substrate side 230.

The package covering body 102 covers the first carrier side 218, the first integrated circuit device 212, the second integrated circuit device 224, the electrical interconnection 240 and the first substrate side 230. The package cover 102 includes a cavity 104 on the first substrate side 230, and in the cavity 104, the mounting interconnect 108 is partially exposed from the package cover 102 and is partially exposed by the package. Is surrounded by a covering body 102. The mounting interconnection 108 is coplanar with the first cladding side 242 of the package cladding 102 in the cavity 104. The mounting interconnection 108 such as solder bumps in a spherical, pillar or stub configuration can be planarized using coining, pressing or other planarization processes. The mounting interconnection 108 accommodates and mounts other integrated circuit devices (not shown) on the first cladding side 242. It can also be understood that the mounting and interconnection may optionally include a protrusion 244 protruding above the side 242 of the first cladding body, like a dotted line shown in the cavity 104.

It can be found that in the present invention, the mounting interconnection is partially exposed from the package covering body or protruding from the cavity of the package covering body to reduce the height of the package and improve the reliability of the package. The mountable integrated circuit packaging system 100 provides a reliable electrical connection between the mountable integrated circuit packaging system 100 and the mounting integrated circuit device that can be mounted on the mounting interconnection, and at the same time The overall height of the integrated circuit package system is minimized. The mounting interconnection provides sufficient standoff height above the substrate to minimize the bonding wire offset on the substrate or on the conductive contacts of the substrate when the mounted integrated circuit device is connected. )problem.

It can also be found that the present invention provides sufficient gap height on the substrate to assist in minimizing mold flow interference (mold flash) or mold bleed contamination that may cause mold flash or mold bleed contamination on conductive contacts on the substrate. flow disturbance). The present invention further accommodates the bonding wire between the central interconnection pad of the integrated circuit device under the substrate and the top side of the substrate through a hole in the substrate, without affecting the mold chase during the coating process. ). The present invention also avoids the exposed circuit due to the possible tilt of the substrate after the coating process.

It can also be found that the present invention eliminates the need for mounting integrated devices with large solder ball sizes and pitch sizes in order to clean the pre-mold cap for the inner central bonding wire.

Please refer to FIG. 3, which shows a cross-sectional view of a mountable integrated circuit package system 300 according to a second embodiment of the present invention, which has a top view as illustrated in FIG. 1. The mountable integrated circuit packaging system 300 has a structure similar to that of the mountable integrated circuit packaging system 100 in FIG. 2. The cross-sectional view shows that the mountable integrated circuit package system 300 has a package covering body 302 formed on a carrier 310 such as a substrate, and the carrier 310 has a first integrated circuit device 312 mounted thereon. The first integrated circuit device 312 may be an integrated circuit chip, a flip chip, or a package integrated circuit device. Preferably, the first integrated circuit device 312 is mounted on the first inactive side 316 of the first integrated circuit device 312 with a first adhesive 314 (such as die adhesive) facing the carrier 310 The first carrier side 318. For example, the second external interconnection 320 of solder balls is connected to the second carrier side 322 of the carrier 310 and opposite to the first carrier side 318 to connect to the next system level (not shown), such as a printed circuit board Or other integrated circuit package system.

Although the first integrated circuit device 312 is shown as a wire-bonded integrated circuit, it should be understood that the first integrated circuit device 312 can be various types of integrated circuits. For example, the first integrated circuit device 312 can be an integrated circuit chip, a packaged integrated circuit device, or a flip chip.

The second packaged integrated circuit device 346 is mounted on the first active side 328 of the first integrated circuit device 312 with a second adhesive 326 (for example, a wire-in-film adhesive). The second packaged integrated circuit device 346 includes a substrate 306 having a first substrate side 330 with mounting interconnects 308 and a side facing the first integrated circuit device 312 relative to the first substrate side 330 332 on the second substrate side.

An electrical interconnection 340 such as a bonding wire or a ribbon bonding wire is connected between the first carrier side 318 and the first substrate side 330. The electrical interconnection 340 may also provide an electrical connection between the first carrier side 318 and the first active side 328.

The package covering body 302 covers the first carrier side 318, the first integrated circuit device 312, the second packaged integrated circuit device 346, the first substrate side 330 and the electrical connection 340. The package covering body 302 includes a cavity 304 on the first substrate side 330, and the mounting interconnection 308 is partially exposed from the package covering body 302 in the cavity 304 and is partially exposed by the package. The covering body 302 is surrounded. The mounting interconnect 308 is coplanar with the first cladding side 342 of the package cladding 302 in the cavity 304. The mounting interconnection 308, such as solder bumps in a ball, pillar, or stub configuration, can preferably be planarized using embossing, pressing, or other planarization processes. The mounting interconnection 308 accommodates and mounts other integrated circuit devices (not shown) on the first cladding side 342. It can also be understood that the mounting interconnection 308 may optionally include a protrusion 344 protruding above the first cladding body side 342, like a dotted line shown in the cavity 304.

Referring now to FIG. 4, which is a top view of a mountable integrated circuit package system 400 of the third embodiment of the present invention. The top view depicts the package cover 402 (such as epoxy molding compound) with partially exposed mounting interconnects 408, as if partially exposed from the package cover 402 and surrounded by the package cover 402 Solder bumps. The mounting interconnection 408 may be formed of an electrically conductive material containing tin (Sn), lead (Pb), gold (Au), copper (Cu), or a metal alloy.

Referring now to FIG. 5, which is a cross-sectional view of the mountable integrated circuit package system 400 shown in FIG. 4 along line 5-5. The cross-sectional view depicts the mountable integrated circuit package system 400 having the package covering body 402 formed on a carrier 510 (such as a substrate), and the carrier 510 has a first integrated circuit device 512 mounted thereon Above, the first integrated circuit device 512 may be an integrated circuit chip, flip chip or package integrated circuit device. Preferably, the first integrated circuit device 512 is mounted on the first inactive side 516 of the first integrated circuit device 512 with a first adhesive 514 (such as die adhesive) and faces the carrier 510 The first carrier side 518. The second external interconnection 520 such as solder balls is connected to the second carrier side 522 of the carrier 510 and opposite to the first carrier side 518 to connect to the next system level (not shown), such as printing Circuit board or other integrated circuit package system.

Although the first integrated circuit device 512 is shown as a wire-bonded integrated circuit, it should be understood that the first integrated circuit device 512 can be various types of integrated circuits. For example, the first integrated circuit device 512 may be an integrated circuit chip, a packaged integrated circuit device, a flip chip, or a combination thereof. An electrical interconnection 540 such as a bonding wire or a ribbon bonding wire is connected between the first carrier side 518 and the first active side 528 of the first integrated circuit device 512.

The substrate 506 has a first substrate side 530 with the mounting interconnection 408, and the second substrate side 532 of the substrate 506 relative to the first substrate side 530 is provided with a second adhesive 526 (such as a wire bonding in a thin film) Agent) is installed on the first active side 528. Preferably, the electrical interconnection 540 can also connect the first carrier side 518 and the first substrate side 530.

The package covering body 402 covers the first carrier side 518, the electrical Interconnect 540, the first integrated circuit device 512, and the first substrate side 530. The mounting interconnection 408 is partially exposed from the package covering body 402 and surrounded by the package covering body 402. The mounting interconnect 408 is coplanar with the first cladding side 542 of the package cladding 402. The mounting interconnection 408, such as solder bumps of, for example, a ball, pillar, or stub configuration can be planarized using embossing, pressing, or other planarization processes. The mounting interconnection 408 accommodates and mounts other integrated circuit devices (not shown) on the first cladding side 542. It can also be understood that the mounting interconnection 408 may optionally include a protrusion 544 protruding above the side 542 of the first cladding body, as shown by a dotted line.

Referring now to FIG. 6, there is shown a mountable integrated circuit package system 600 with the top view illustrated in FIG. 4 according to the fourth embodiment of the present invention. The mountable integrated circuit packaging system 600 has a structure similar to that of the mountable integrated circuit packaging system 400 in FIG. 5. The cross-sectional view depicts that the mountable integrated circuit package system 600 has a package cover 602 formed on a carrier 610 like a substrate, and the carrier 610 has a first integrated circuit device 612 mounted thereon, The first integrated circuit device 612 may be an integrated circuit chip, flip chip or package integrated circuit device. Preferably, the first integrated circuit device 612 is mounted on the first inactive side 616 of the first integrated circuit device 612 with a first adhesive 614 (such as die adhesive) facing the carrier 610 The first carrier side 618. For example, the second external interconnection 620 of the solder ball is connected to the second carrier side 622 of the carrier 610 and opposite to the first carrier side 618 to connect to the next system level (not shown), such as a printed circuit Board or other integrated circuit package system.

Although the first integrated circuit device 612 is shown as a wire-bonded integrated circuit, it should be understood that the first integrated circuit device 612 can be various types of integrated circuits. For example, the first integrated circuit device 612 may be an integrated circuit chip, a package integrated circuit device or a flip chip.

The second packaged integrated circuit device 646 is mounted on the first active side 628 of the first integrated circuit device 612 with a second adhesive 626 (for example, an in-film wire adhesive). The second packaged integrated circuit device 646 includes a substrate 606 having a first substrate side 630 with mounting interconnects 608. An electrical interconnection 640 such as a bonding wire or a ribbon bonding wire is connected between the first carrier side 618 and the first substrate side 630. The electrical interconnection 640 may also provide an electrical connection between the first carrier side 618 and the first active side 628.

The package covering body 602 covers the first carrier side 618, the first integrated circuit device 612, the second packaged integrated circuit device 646 (including the first substrate side 630 ), and the electrical connection 640. The mounting interconnection 608 is partially exposed from the package covering body 602 and surrounded by the package covering body 602. The mounting interconnect 608 is coplanar with the first cladding side 642 of the package cladding 602. The mounting interconnection 608, such as solder bumps of, for example, a ball, pillar, or stub configuration can preferably be planarized using embossing, pressing, or other planarization processes. The mounting interconnection 608 accommodates and mounts other integrated circuit devices (not shown) on the first cladding side 642. It can also be understood that the mounting interconnection 608 may optionally include a protrusion 644 protruding above the first cladding body side 642, as shown by the dotted line.

Referring now to FIG. 7, there is shown an integrated circuit package-on-package system (integrated circuit package-on-package system) using the mountable integrated circuit package system 100 of FIG. 2 in the fifth embodiment of the present invention 700 above view. The integrated circuit package on package system 700 can be formed by other embodiments of the present invention, such as the mountable integrated circuit package system 300 in FIG. 3. The mounting integrated circuit device 702 for packaging integrated circuits is mounted on the mountable integrated circuit packaging system 100 in the cavity 104 of the mountable integrated circuit packaging system 100 in FIG. 2.

Referring now to FIG. 8, there is shown a cross-sectional view of the integrated circuit stack package system 700 along line 8-8 of FIG. 7. The mounting integrated circuit device 702 is mounted on the mountable integrated circuit packaging system 100, and one of the mounting interconnects 108 exposed in the cavity 104 of the mountable integrated circuit packaging system 100 superior. Preferably, mounting contacts 802 (such as electrical conductive pads or conductive balls of the mounting integrated circuit device 702) are mounted on the mounting interconnect 108 and connected to the mounting interconnect 108 to provide electrical power therebetween. connect. For the purpose of illustration, the integrated circuit package on package system 700 is shown as having the mounted integrated circuit device 702 as a packaged integrated circuit, but it should be understood that the integrated circuit package on package system 700 can be used as the Various types of integrated circuits on which the integrated circuit device 702 is mounted are formed together. For example: the mounted integrated circuit device 702 may include multiple integrated circuits, ball grid array (BGA) devices, land grid array (LGA), quad flat nonleaded (QFN) devices, Quad flat package (QFP) devices, bump chip carrier (BCC) devices, flip chips, passive components, or combinations thereof.

Referring now to FIG. 9, there is shown a top view of an integrated circuit stack package system 900 using the mountable integrated circuit package system 400 of FIG. 5 in the sixth embodiment of the present invention. The integrated circuit package on package system 900 can be formed by other embodiments of the present invention, such as the mountable integrated circuit package system 600 in FIG. 6. The mounting integrated circuit device 902 for packaging integrated circuits is mounted on the mountable integrated circuit packaging system 400 shown in FIG. 5.

Reference is now made to FIG. 10, which shows a cross-sectional view of the integrated circuit stack package system 900 along line 10-10 of FIG. 9. The mounting integrated circuit device 902 is mounted on the mountable integrated circuit package system 400 and on the mounting interconnection 408 of the mountable integrated circuit package system 400. Preferably, the mounting contact 1002 (such as the electrical conductive pad or conductive ball of the mounting integrated circuit device 902) is mounted on the mounting interconnect 408 and connected to the mounting interconnect 408 to provide electrical conductivity therebetween. connect. For illustrative purposes, the integrated circuit package on package system 900 is shown as having the mounted integrated circuit device 902 as a packaged integrated circuit, but it should be understood that the integrated circuit package on package system 900 can be used as The various types of integrated circuits of the mounting integrated circuit device 902 are formed together. For example: the mounted integrated circuit device 902 may include multiple integrated circuits, ball grid array (BGA) devices, planar grid arrays (LGA), quad flat no-pin (QFN) devices, quad flat package (QFP) devices , Bump Chip Carrier (BCC) device, flip chip, passive component or a combination thereof.

Referring now to FIG. 11, it shows a flowchart of a mountable integrated circuit packaging method 1100 for manufacturing the mountable integrated circuit packaging system 100 in an embodiment of the present invention. The method 1100 includes: in block 1102, mounting a first integrated circuit device on a carrier; in block 1104, mounting a substrate on the first integrated circuit device, the substrate having mounting interconnections; in block 1106 In, connect a first electrical interconnection between the carrier and the substrate; and in block 1108, form a package covering to cover the carrier, the first integrated circuit device, the first electrical interconnection, and The substrate is partially exposed from the packaging body and surrounded by the packaging body so that the mounting interconnection is partially exposed from the packaging body in the cavity of the packaging body.

Other important aspects of the embodiment include valuable support and help to reduce costs, simplify the system, and increase the historical trend of performance.

These and other valuable aspects of the present invention inevitably advance the state of technology to at least the next level.

Therefore, it can be found that the mountable integrated circuit package system of the present invention provides solutions, capabilities, and functional aspects that are important for improving reliability in the system and have hitherto been unknown and unused. The resulting manufacturing process and structure are clear, cost-saving, not complicated, highly versatile and effective, and can be implemented by using known techniques, and therefore can be easily applied to efficiently and economically manufacture integrated circuit packages Pieces of equipment.

Although the present invention has been described in a specific best mode, it should be understood that in view of the foregoing description, many alternatives, modifications and changes will be obvious to those familiar with the art. Therefore, it is intended to cover all such substitutions, modifications and changes that fall within the scope of the included patent application. All matters presented here or shown in the drawings should be regarded as illustrative explanations rather than limiting.

<p>100, 300, 400, 600Installable integrated circuit package system</p><p>102, 302, 402, 602Packaging package body</p><p>104, 304 chamber</p><p>108, 308, 408, 608Installation and interconnection</p><p>206, 306, 506, 606Substrate</p><p>210, 310, 510, 610Carrier</p><p>212, 312, 512, 612First integrated circuit device</p><p>214, 314, 514, 614The first adhesive</p><p>216, 316, 516, 616The first non-active side</p><p>218, 318, 518, 618First carrier side</p><p>220, 320, 520, 620Second external interconnection</p><p>222, 322, 522, 622Second carrier side</p><p>224Second Integrated Circuit Device</p><p>226, 326, 526, 626Second Adhesive</p><p>228, 328, 528, 628First active side</p><p>230, 330, 530, 630First substrate side</p><p>232, 332, 532Second substrate side</p><p>234Second active side</p><p>236Third Adhesive</p><p>238Porosity</p><p>240, 340, 540, 640Electrical interconnection</p><p>242, 342, 542, 642. . . First coating side</p><p>244, 344, 544, 644. . . Convex</p><p>700, 900. . . Integrated circuit stack package system</p><p>702, 902. . . Install integrated circuit device</p><p>802, 1002. . . Installation contact</p><p>1100. . . Mountable integrated circuit packaging method</p><p>1102, 1104, 1106, 1108. . . Flow block</p>

Figure 1 is a top view of the mountable integrated circuit packaging system of the first embodiment of the present invention;

Figure 2 is a cross-sectional view of the mountable integrated circuit package system along line 2-2 in Figure 1;

Figure 3 is a cross-sectional view of the mountable integrated circuit package system of the second embodiment of the present invention, which has a top view as illustrated in Figure 1;

Figure 4 is a top view of a mountable integrated circuit package system according to a third embodiment of the present invention;

Figure 5 is a cross-sectional view of the mountable integrated circuit package system along line 5-5 in Figure 4;

Figure 6 is a cross-sectional view of the mountable integrated circuit package system of the fourth embodiment of the present invention, which has a top view as illustrated in Figure 4;

Figure 7 is a top view of an integrated circuit stack package system using the mountable integrated circuit package system of Figure 2 in the fifth embodiment of the present invention;

Figure 8 is a cross-sectional view of the integrated circuit stack package system along line 8-8 in Figure 7;

Fig. 9 is a top view of an integrated circuit stack package system using the mountable integrated circuit package system of Fig. 5 in the sixth embodiment of the present invention; A cross-sectional view of the integrated circuit stack package system along line 10-10; and Figure 11 is a mountable integrated circuit package used to manufacture a mountable integrated circuit package system according to an embodiment of the present invention Flow chart of the method.