System for high-speed backplane applications using pre-coding

Transmitter and receiver

SYSTEMS FOR HIGH-SPEED BACKPLANE APPLICATIONS USING PRE-CODING

The present invention relates to high-speed communication, and it relates to a high-speed communication system through a backplane.

The communication system is designed to transfer information between two devices through a medium, and the medium usually has annoying interference. Inter-Symbol Interference (ISI) is a common annoying interference in which the transmitted signal is lengthened and interferes with adjacently transmitted signals. This propagation or "tailing" of the signal is usually caused by the dispersion characteristics of general-purpose communication media. Because of the same effect of ISI and noise, communication becomes unreliable.

One of the most basic solutions to mitigating the effects of ISI is to reduce the rate at which signals are sent through the medium. More specifically, the transmission rate can be reduced so that the signal can only be transmitted after the previous transmission signal pulse is allowed to dissipate. The time required for the signal pulse to dissipate is called "propagation delay", and the original time of the signal pulse (including any time before the next signal pulse is sent) is called the signal time. If the propagation delay is less than or equal to the signal time, ISI will not occur.

Although reducing the signal rate can eliminate the impact of ISI, it is almost an unacceptable solution for many current communications applications. In fact, many communication applications currently require a rate range of several gigabits per second. At such a high rate, ISI can completely cover signals sent through a few inches of printed circuit board wiring, a few feet of copper trace cable, or tens of meters of multimode optical fiber.

Backplane Ethernet is a type of communication application that suffers from ISI. Backplane Ethernet has been standardized by the IEEE802.3ap standard at least to some extent and is commonly used in some devices , Such as routers, switches, and blade servers. The IEEE802.3ap standard specifically specifies the operating characteristics of the configuration of a 10Gbps backplane Ethernet that transmits data differentially through two pairs of copper traces on the printed circuit board. Using one bit, pulse amplitude modulation (PAM) method and 10.3125GHZ serial transmission rate data, data is sent in one direction through each pair of copper traces.

Although the traditional 10Gbps rate limit has faced huge signal loss challenges from ISI and other noise sources, vendors of backplane Ethernet applications are still pushing designers to achieve speeds that are up to twice the traditional 10Gbps limit. However, at these rates, due to ISI and other noise sources, traditional, cost-effective transceiver designs for backplane Ethernet applications cannot reliably send and receive information through the copper traces on the printed circuit board.

Therefore, there is a need for a cost-effective system that can support backplane applications with speeds up to and exceeding twice the traditional 10Gbps limit.

According to one aspect of the present invention, there is provided a transmitter configured to control an input data flow to be appropriately formatted into an output data flow so as to transmit through a channel located on a backplane at a serial transmission rate of at least 10.3125 GHz. The transmitter includes: a scrambler configured to remove a sequence of digit 0 or digit 1 value from the input data flow to provide a scrambled data flow; a forward error correction encoder configured to generate and add redundant symbols To the scrambled data flow to provide a forward error correction coded data flow, wherein the redundant symbols enable the receiver to detect and correct the forward error correction coded data flow during the transmission process The linear code encoder is configured to use a pulse amplitude modulation method with an order M greater than 2 to modulate the forward error correction coded data flow to provide a modulated data flow; a precoder is configured to The modulated data flow performs channel pre-equalization and power limiting to provide a precoded data flow; and a linear filter at the transmitting end configured to adjust the precoded data flow to compensate for the high frequency attenuation of the channel to provide The output data flow.

Preferably, the precoder includes an infinite impulse response filter for performing channel pre-equalization and an M-mode device for performing transmission power limitation.

Preferably, the infinite impulse response filter is configured to have a transfer function that is substantially the same as the inverse transfer function of the channel.

Preferably, the M-mode device is configured to limit the signal of the precoded data flow so that its amplitude is within the interval [0, 1,..., M-1].

Preferably, the forward error correction encoder is configured to generate the redundant symbols according to a Reed Solomon coding technique.

Preferably, the transmitter further includes a training sequence generator configured to generate a training bit sequence known by the receiving entity.

Preferably, the transmitter further includes a second linear code encoder configured to modulate the training bit sequence.

Preferably, the transmitter further includes a multiplexer configured to provide the modulated training bit sequence or the modulated data flow as an output according to the selection signal.

Preferably, the transmitter is configured to perform an auto-negotiation process with the receiving entity according to at least one of the signal-to-noise ratio supported by the channel and the expected delay to determine the forward error correction used by the forward error correction encoder method.

Preferably, the sender is configured to perform an auto-negotiation process with the receiving entity according to a common clock to establish a master-slave relationship so that the sender and the receiving entity can send data to each other.

According to one aspect of the present invention, there is provided a receiver configured to control a modulated data flow received through a channel on a backplane at a serial transmission rate of at least 10.3125 GHz to be properly restored to an output data flow, which is characterized by The receiver includes: a discrete time sampler configured to sample the modulated data flow in time domain to provide a sampled modulated data flow; a DFE with an inverse precoder configured to detect The symbols in the sampled modulation data flow perform an M-mode operation on the detected symbols to provide an inversely precoded symbol stream; a linear code decoder is configured to demodulate the inversely precoded symbol stream to Provide sutra The demodulated data flow, wherein the inversely precoded symbol stream is modulated according to a pulse amplitude modulation method with an order greater than 2; the forward error correction decoder is configured to detect in the demodulated bit stream And correcting errors to provide an error-corrected data flow; and a descrambler configured to perform an inverse scrambling function on the error-corrected data flow to provide the output data flow.

Preferably, the receiver further includes a feedforward equalizer configured to reduce pre-cursors on the sampled modulation data flow before the DFE with the inverse precoder processes the sampled modulation data flow (pr-cursor) Inter-symbol interference.

Preferably, the receiver further includes a cancellation summer configured to eliminate the sampled modulation data flow before the DFE with the inverse precoder processes the sampled modulation data flow Near-end crosstalk noise.

According to one aspect of the present invention, there is provided a receiver configured to control a modulated data flow received through a channel on a backplane at a serial transmission rate of at least 10.3125 GHz to be properly restored to an output data flow, which is characterized by The receiver includes: a discrete-time sampler configured to sample the modulated data flow in the time domain to provide a sampled modulated data flow; an inverse precoder with an extended slicer (slicer) configured to Detecting symbols in the sampled modulation data flow and performing an M-mode operation on the detected symbols to provide an inversely precoded symbol stream; a linear code decoder configured to demodulate the inversely precoded symbol stream In order to provide a demodulated data flow, the inversely precoded symbol stream is modulated according to a pulse amplitude modulation method with an order greater than 2; the forward error correction decoder is configured to be used in the demodulated bit stream. Detecting and correcting errors in the stream to provide an error-corrected data flow; and a descrambler configured to perform an inverse scramble function on the error-corrected data flow to provide the output data flow.

Preferably, the receiver further includes a feedforward equalizer configured to reduce the sampled modulation data before the inverse precoder with extended slicer processes the sampled modulation data flow Pre-cursor (pr-cursor) inter-symbol interference on the process.

Preferably, the receiver further includes a cancellation summer, configured to obtain data from the sampled modulation data before the inverse precoder with an extended slicer processes the sampled modulation data flow. Eliminate near-end crosstalk noise in the modulation data process.

According to one aspect of the present invention, there is provided a receiver configured to control a modulated data flow received through a channel on a backplane at a serial transmission rate of at least 10.3125 GHz to be properly restored to an output data flow, which is characterized The receiver includes: a discrete-time sampler configured to sample the modulated data flow in the time domain to provide a sampled modulated data flow; a partial DFE (partial DFE) with an inverse precoder is configured to Detecting symbols in the sampled modulation data flow and performing an M-mode operation on the detected symbols to provide an inversely precoded symbol stream; a linear code decoder configured to demodulate the inversely precoded symbol stream In order to provide a demodulated data flow, the inversely precoded symbol stream is modulated according to a pulse amplitude modulation method with an order greater than 2; the forward error correction decoder is configured to be used in the demodulated bit stream. Detecting and correcting errors in the stream to provide an error-corrected data flow; and a descrambler configured to perform an inverse scramble function on the error-corrected data flow to provide the output data flow.

Preferably, the receiver further includes a feed-forward equalizer configured to reduce the pre-sampled modulation data flow before the local DFE with the inverse precoder processes the sampled modulation data flow. Cursor (pr-cursor) inter-symbol interference.

Preferably, the receiver further includes a cancellation summer, configured to remove the sampled modulation data from the sampled modulation data flow before the local DFE with the inverse precoder processes the sampled modulation data flow. Eliminate near-end crosstalk noise.

According to another aspect of the present invention, there is provided a transmitter configured to control an input data flow to be appropriately formatted into an output data flow so as to transmit through a channel located on a backplane at a serial transmission rate of at least 10.3125 GHz, so The transmitter includes: a scrambler, configured to clear a sequence of digit 0 or digit 1 value from the input data flow to provide a scrambled data flow; a forward error correction encoder, equipped with Set to generate and add redundant symbols to the scrambled data flow to provide a forward error correction coded data flow; the serial-to-parallel module is configured to perform the forward error correction coded data flow De-serialize, and disperse the forward error correction encoded data flow into at least two parallel forward error correction encoded data flows, wherein at least one redundant data flow generated by the forward error correction encoder The remaining symbols are generated based on the data sent through at least two parallel forward error correction coding data processes; the linear code encoder is configured to modulate the parallel forward error correction coding using a pulse amplitude modulation method of order M A data flow to provide a modulated data flow; and a transmitting-end linear filter configured to adjust the modulated data flow to compensate for the high frequency attenuation of the channel to provide the output data flow.

Preferably, the forward error correction encoder is configured to generate the redundant symbols according to a Reed Solomon coding technique.

Preferably, the transmitter further includes a precoder configured to perform channel pre-equalization and power limiting on the modulated data flow before the linear filter at the transmitting end processes the modulated data flow to provide Pre-encoded data flow.

Preferably, the precoder includes an infinite impulse response filter configured to perform channel pre-equalization and an M-mode device configured to perform transmission power limitation.

Preferably, the infinite impulse response filter is configured to have a transfer function that is substantially the same as the inverse transfer function of the channel.

Preferably, the M-mode device is configured to limit the signs of the precoded data flow so that the amplitude is within the interval [0, 1,..., M-1].

Preferably, the transmitter further includes a training sequence generator configured to generate a training bit sequence known by the receiving entity.

Preferably, the transmitter further includes a second linear code encoder configured to modulate the training bit sequence.

Preferably, the transmitter further includes a multiplexer configured to provide the modulated training bit sequence or the modulated data flow as an output according to the selection signal.

Preferably, the transmitter is configured according to the signal-to-noise ratio supported by the channel and the At least one of the expected delays performs an auto-negotiation process with the receiving entity to determine the forward error correction method used by the forward error correction encoder.

Preferably, the sender is configured to perform an auto-negotiation process with the receiving entity according to a common clock to establish a master-slave relationship so that the sender and the receiving entity can send data to each other.

According to one aspect of the present invention, there is provided a receiver configured to control a modulated data flow received through a channel on a backplane at a serial transmission rate of at least 10.3125 GHz to be properly restored to an output data flow, which is characterized by The receiver includes: a discrete-time sampler configured to sample the modulated data flow in the time domain to provide a sampled modulated data flow; a data detector configured to detect the sampled modulated data flow The symbol in the symbol stream is configured to provide a symbol stream; a linear code decoder is configured to demodulate the symbol stream to provide a demodulated data flow, wherein the inversely precoded symbol stream is based on a pulse amplitude modulation method having an order Modulated; parallel-to-serial module, configured to mix the demodulated data flow with one or more other demodulated data flows to provide a serial data flow; forward error correction decoder, configured to Use redundant symbols to detect and correct errors in a serial data flow to provide an error-corrected data flow, wherein the redundant symbols are based on at least two demodulated data flows including the serial data flow And a descrambler configured to perform an inverse scramble function on the error-corrected data flow to provide the output data flow.

Preferably, the data detector includes an inverse precoder with an extended slicer, configured to detect symbols in the sampled modulation data flow and perform an M-mode operation on the detected symbols.

Preferably, the data detector includes a local DFE with an inverse precoder, configured to detect symbols in the sampled modulation data flow and perform an M-mode operation on the detected symbols.

Preferably, the data detector includes a DFE with an inverse precoder, and is configured to detect symbols in the sampled modulation data flow and perform execution on the detected symbols. Line M mode operation.

Preferably, the receiver further includes a feedforward equalizer configured to reduce a pre-cursor (pr-cursor) on the sampled modulation data flow before the data detector processes the sampled modulation data flow. ) Inter-symbol interference.

Preferably, the receiver further includes a cancellation summer configured to substantially eliminate near-end crosstalk from the sampled modulation data flow before the data detector processes the sampled modulation data flow Noise.

<p>100Backplane Ethernet System</p><p>110Back plate</p><p>120Line Card</p><p>130Line Card</p><p>140Connector</p><p>150Connector</p><p>160Transceiver</p><p>170Transceiver</p><p>180Trace</p><p>200Transmitter</p><p>210Scrambler</p><p>220Forward Error Correction (FEC) Encoder</p><p>230Serial to Parallel Module</p><p>240Linear Code Encoder</p><p>250Precoder</p><p>260Linear Filter at Transmitter</p><p>270Input terminal</p><p>280output</p><p>300Receiver</p><p>305Programmable Gain Amplifier (PGA)</p><p>310Continuous Time Filter (CTF)</p><p>315Discrete Time Sampler</p><p>320Noise Eliminator</p><p>325Feed Forward Equalizer (FFE)</p><p>330Data Detector</p><p>335Inverse precoder</p><p>340Linear Code Decoder</p><p>345Parallel to Serial Module</p><p>350FEC Decoder</p><p>355Descrambler</p><p>360Input terminal</p><p>365Output</p><p>620Extended Splitter</p><p>630M module</p><p>800DFE with inverse precoder</p><p>810Precoder</p><p>820Network Channel C(z)</p><p>830DFE</p><p>840FIR filter B(z)</p><p>850M module</p><p>900Inverse precoder with extended divider</p><p>910Precoder</p><p>920Channel B(z)</p><p>930Extended Splitter</p><p>940M module</p><p>1000Local DFE with inverse precoder</p><p>1010Precoder</p><p>1020Channel B(z)</p><p>1030Channel F(z)</p><p>1040DFE</p><p>1050Extended divider</p><p>1060Filter [f(z)-1]</p><p>1070M module</p><p>1100Receiver</p><p>1110Training Sequence Generator</p><p>1120Linear Code Encoder</p><p>1130Multiplexer</p>

The drawings described here that constitute a part of this specification illustrate the present invention, and together with specific embodiments explain the principle of the present invention, and enable those skilled in the art to implement and use the present invention.

FIG. 1 is a schematic diagram of an exemplary backplane operating environment according to an embodiment of the present invention; FIG. 2 is a schematic diagram of an exemplary transmitter according to an embodiment of the present invention; FIG. 3 is a schematic diagram of an exemplary receiver according to an embodiment of the present invention; Fig. 4 is a schematic diagram of a precoder according to an embodiment of the present invention; Fig. 5 is a linear schematic diagram of the precoder shown in Fig. 4 according to an embodiment of the present invention; Fig. 7 is a schematic diagram of an exemplary pre-emphasis or transmitting-end linear filter according to an embodiment of the present invention; Fig. 8 is a schematic diagram of a combination of an exemplary DFE and an inverse precoder according to an embodiment of the present invention; 9 is a schematic diagram of an exemplary inverse precoder with an extended splitter according to an embodiment of the present invention; FIG. 10 is a schematic diagram of an exemplary combination of a partial DFE and an inverse precoder according to an embodiment of the present invention; The configuration of an embodiment of the invention is a schematic diagram of an exemplary transmitter that generates and transmits a training sequence to a receiver during a selected time period.

In the following description, various specific details are given to provide an in-depth understanding of the present invention. However, it is obvious to those skilled in the art that the present invention, including the structure, system and method, can be implemented without these specific details. The description and characterization here are the means used by those skilled in the art in order to convey their work most effectively to others in the field. For other situations, this article does not specifically describe known methods, steps, components, and circuits in order to avoid unnecessarily obscuring the features of the present invention.

The marks "one embodiment", "an embodiment", "an exemplary embodiment", etc. in the specification indicate that the described embodiment includes a specific feature, structure, or property, but not every embodiment must include the specific feature , Structure or nature. In addition, these words do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or property is described with reference to one embodiment, it is believed that those skilled in the art can apply the feature, structure, or property to other embodiments whether or not specifically described herein.

FIG. 1 is a schematic diagram of an exemplary backplane Ethernet system 100 according to an embodiment of the present invention. As shown in FIG. 1, an exemplary backplane Ethernet system 100 includes a backplane 110 and two line cards (or daughter cards) 120 and 130. The line cards 120 and 130 are respectively connected to the backplane 110 through connectors 140 and 150 (for example, HMZd connectors) arranged on the surface of the backplane 110, and each line card includes transceivers 160 and 170, respectively.

During operation, the transceivers 160 and 170 are configured to send and receive data to and from each other. The communication data between the two transceivers is sent through the two pairs of traces 180 (such as copper traces) exposed on the surface of the backplane 110: the first pair of traces is used to transmit differently from the transceiver 160 to the transceiver 170 Data, the second pair of traces is used to transmit data from the transceiver 170 to the transceiver 160 differently. In one embodiment, pulse amplitude modulation (PAM) is used to modulate the data sent between the two transceivers.

In the existing backplane Ethernet system, the data is specifically transmitted in one direction through each pair of traces using one bit, the PAM method and a serial transmission rate of 10.3125GHz, providing an effective bit rate of 10.3125Gbps . Backplane Ethernet System The data transmission rate that can make the data reliably received in the system is usually limited by the ISI caused by the dispersion characteristics of the copper trace, the surface effect of the copper trace and the frequency-dependent transmission loss caused by the beginning of the dielectric loss, and the crosstalk from adjacent communication lines. . The present invention relates to a system for eliminating the above-mentioned and other signal losses, so as to obtain a rate that is up to and exceeding twice the traditional 10Gbps limit value in the backplane Ethernet system and more than that.

However, it should be noted that the exemplary backplane Ethernet system 100 only provides an exemplary system capable of implementing the features of the present invention. For example, the features of the present invention can be implemented in a communication system for sending and receiving data, and the format of the data can be based on other signaling standards than Ethernet. In addition, the features of the present invention may be implemented in a communication system for sending and receiving data through a medium, which may be a medium other than copper traces arranged on a printed circuit board. For example, other possible transmission media include coaxial cable, optical fiber (single-mode and multi-mode), twisted pair, wireless, and satellite. In addition, other digital modulation methods other than PAM can also be used, including, for example, Quadrature Amplitude Modulation (QAM) and Quadrature Phase Shift Keying (QPSK). Although there are the above-mentioned and other systems that implement the features of the present invention, the various features of the present invention will be specifically described with respect to the backplane Ethernet system 100 below.

FIG. 2 is a schematic diagram of an exemplary transmitter 200 according to an embodiment of the present invention. As shown in FIG. 2, the transmitter 200 includes a scrambler 210, a forward error correction (FEC) encoder 220, a serial to parallel module 230, a linear code encoder 240, a precoder 250, and a linear filter at the transmitting end ( Also called pre-emphasis filter) 260.

In one embodiment, the transmitter 200 is located in a line card transceiver and is configured to send data through one or more traces on a printed circuit board in a backplane Ethernet system (such as a backplane Ethernet system 100). More specifically, the transmitter 200 is configured to pass through one or more traces on the printed circuit board in the backplane Ethernet system to exceed the data rate of 10.3125Gbps specified by the IEEE802.3ap standard for traditional backplane Ethernet. , Use the PAM method, which has an order greater than the order often used in the PAM-2 method, to send data. For example, PAM-4 is a two-bit modulation method. For each transmitted signal, this method maps the two-bit data to one of the four possible signal levels per transmitted symbol. Piece. Therefore, using PAM-4 at the traditional 10.3125GHz serial transmission rate can provide a data rate close to 20.625Gbps.

However, using high-level modulation methods such as PAM-4 to send data is not without cost. Generally, due to high-order modulation, the receiver will require a higher signal-to-noise ratio (SNR) to reliably decode the data. In other words, although increasing the number of bits per symbol leads to a correspondingly higher data rate, the signals that make up the modulation method constellation must be more tightly packed and therefore more sensitive to noise (assuming the constellation of the constellation) The average energy remains constant).

For example, in PAM-4, the constellation includes 4 points that are usually evenly distributed on the solid line. However, PAM-2, on the other hand, only includes 2 points that are usually evenly distributed on the solid line. Therefore, the point-to-point distance of the PAM-2 constellation is greater than the point-to-point distance of the PAM-4 constellation (again assuming that the average energy of the constellation remains constant) and therefore has a greater noise amplitude.

Due to the reduced point-to-point distance in PAM-4 and other high-level PAM methods, the ISI caused by the dispersion characteristics of the copper trace, the surface effect of the copper trace and the frequency-dependent transmission loss caused by the beginning of the dielectric loss, and the frequency-dependent transmission loss from adjacent communication lines Crosstalk, the transmitted signal will be more fragile. Therefore, the transmitter 200 includes a novel structure that can overcome these signal losses, allowing data to pass through the channel, using PAM-4 and other higher-order modulation methods, at a rate higher than the existing 10.3125GHz serial transmission rate of the backplane Ethernet Send it.

In the working process, the transmitter 200 receives the input data flow at the input terminal 270, and controls the input data flow to be appropriately formatted into an output data flow so as to be sent through the channel at the output terminal 280. The data input process can include voice, video, or any other application or program-specific data. The input data flow is first received and processed by the scrambler 210. The scrambler 210 is configured to clear the long sequence of digits '0' or '1' values in the input data flow. The long sequence of clearing the value of digits '0' or '1' can facilitate the timing recovery in the receiver and the work of the adaptive circuit. In one embodiment, the scrambler 210 includes a linear feedback shift register (LFSR) and provides a scrambled output data flow. The output data flow is the input data flow and stored in its shift register. Linear function of the previous state in the device. In another embodiment, the scrambler 210 is implemented based on the 64/66 encoder described in the IEEE802.3ap standard.

After the scrambler 210 scrambles the input data flow, the scrambled data flow is received and processed by the FEC encoder 220. In one embodiment, the FEC encoder 220 is used to provide coding gain that at least partially compensates for the higher SNR requirements caused by data transmission using higher-order modulation methods. The coding gain is defined as the effective difference in the SNR level between the uncoded system and the coded system. FEC provides coding gain by introducing redundancy in the data to be transmitted, so as to allow the detection and recovery of transmission errors.

Some dedicated FEC methods can be used to encode the scrambled data flow, including, for example, Trellis Code Modulation (TCM), Low Density Check (LDPC) codes, Turbo codes, BCH and Reed Solomon (RS) codes.

In one embodiment, RS coding is used to add FEC to the scrambled data flow. RS coding technology adds 2t redundant signals to each k m-ary digital token block to create a coded message block (where t represents the symbol error correction capacity designed by the code). These 2t symbols or terms are selected from the Galois field as the roots of the implemented code generator polynomial. There are n=k+2t symbols in the RS-coded message block. The RS decoder implemented in the receiver can use 2t redundant symbols to correct up to t errors generated during the transmission of a block containing k data symbols. In another example, 2t+1 redundant symbols can be created and appended to each block containing k m-element data symbols, ensuring that the RS decoder implemented in the receiver can correct up to t of all modes. In general, t+1 errors of all modes will not be corrected by mistake.

In one embodiment, the traditional 10.3125GHz serial transmission rate used in the backplane Ethernet can be increased to compensate for the extra 2t redundant symbols sent in each coded message block. For example, the traditional 10.3125GHz serial transmission rate can be increased by 5% to compensate for the 5% extra data sent due to 2t redundant symbols. In another embodiment, the traditional 10.3125GHz serial transmission rate generated by the 156.25MHz clock can be increased by a multiple of 156.25MHz to provide redundancy for excess 2t Symbol compensation. In yet another embodiment, one bit in each 65-bit Ethernet frame that is commonly used as error correction codes by the Ethernet standard can be deprived of, also known as Fair codes, to compensate for each encoded message block Extra 2t redundant symbols sent. In particular, depriving this bit of each 65-bit Ethernet frame can provide about 1.5% of additional transmission space for excess 2t redundant symbols. In other embodiments, the traditional 10.3125GHz serial transmission rate can be increased by a multiple of 62.5MHz, 78.125MHz, or 125MHz to provide compensation for excess 2t redundant symbols.

The scrambled data flow and the redundant symbols added by the FEC encoder 220 will then enter the serial-to-parallel module 230. Generally, when the transmitter 200 sends data to the receiving entity through at least two traces (that is, when the transmitter 200 sends the input data flow received from the input terminal 270 to the receiving entity through at least two parallel streams), the serial-to-parallel conversion is performed. The group 230 is optionally included in the transmitter 200. The serial-to-parallel module 230 is configured to serialize and process the FEC-encoded data stream through the parallel channel, and place the data in at least two parallel data flows for further processing. It should be noted that, for clarity, the serial-to-parallel module 230 shown in FIG. 2 only shows one processing block set of a parallel data flow.

In one embodiment, in the transmitter chain shown in FIG. 2, the FEC encoder 220 is located in front of the serial-to-parallel module 230, so that the FEC encoder 220 generates at least one according to the data to be sent through at least two parallel data processes. Redundant symbol. Generally speaking, FEC encoding will perform better when redundant symbols are generated from larger data blocks. However, once the size of the data block increases, the system delay will also increase, because the receiver must wait for the entire data and redundant symbol block to be received before any error correction/detection occurs. Therefore, generating redundant symbols based on data to be sent through at least two parallel data flows will reduce the system delay compared to symbols generated by sending the same amount of data through one parallel data flow.

In another embodiment, the FEC encoder 220 is located after the serial-to-parallel module 230 in the transmitter chain. In this example, each parallel data flow output by the serial-to-parallel module 230 uses a separate FEC encoder 220.

Continuing to describe the transmitter chain shown in FIG. 2, after being serialized and processed by the serial-to-parallel module 230, each parallel data flow needs to receive other processing before being sent to the receiving entity through the physical channel. FIG. 2 specifically shows the reserved processing block of a single parallel data flow output by the serial-to-parallel module 230. The parallel data flow is first received and processed by the linear code encoder 240. The linear code encoder 240 is configured to put the parallel data flow into a format suitable for transmission through the physical channel. This process is usually called modulation. In one embodiment, the linear code encoder 240 is configured to modulate the bits of the parallel data flow according to the above-mentioned PAM method with an order higher than 2. For example, in one embodiment, the linear code encoder 240 is configured to modulate the bits of the received parallel data stream using PAM-4. However, any reasonable PAM modulation method can also be used, including, for example, PAM-2, PAM-6, and PAM-8. In another embodiment, the linear code encoder 240 is configured to modulate the bits of the received parallel data flow using a complex modulation method, such as QAM or QPSK of any reasonable order.

After being modulated, the data flow is passed from the linear code encoder 240 to the precoder 250. Generally speaking, the precoder 250 uses modular arithmetic to achieve pre-equalization and limit the transmission power. Fig. 4 shows a basic embodiment of a precoder 250 according to an embodiment of the present invention. The original symbol sequence {a[k]} selected from the constellation of the PAM-M modulation method used is precoded to generate a precoded data sequence {x[k]}. In the working process, the precoder 250 performs inverse channel filtering using a feedback filter defined by [B(z)-1] and a modulo operation with a modulo M. The modulo operation is performed in the following manner: the output of the precoder 250 is limited to the interval [0, M-1]. Define PAM-M as an integer [0,1,...,M-1] without generating loss. For favorable situations, the output of the precoder 250 is still'PAM-M', where the coefficient B(z) is an integer. Generally speaking, if the sum of the PAM-M symbol and the feedback value is greater than or equal to M, an integer multiple of M can be subtracted to make the result less than M. In addition, if the sum is less than 0, an integer multiple of M can be added to make the result greater than or equal to 0.

Because the feedforward path of the precoder 250 uses a nonlinear modulo M device to limit the dynamic range of the output of the precoder 250 (it can also be unrestricted), the precoder 250 produces The generated output data sequence can be better analyzed using the linear model shown in Figure 5. It can be seen from Fig. 5 that the output data sequence of the precoder 250 is given by the following formula in the z-domain:<maths><img file="TWI474658B_D0001.tif" he="276" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="886" /></maths>

Where B[z] represents the discrete time channel through which the data sequence is sent, and V[z] is the z transform of the integer sequence.

In one embodiment, the receiving entity estimates B[z] during initialization. The above process can be achieved by adaptively adjusting the DFE, such as using a known training sequence, and then passing the feedback part of the DFE to the transmitter, and the feedback part of the DFE gives the impulse response required by the channel. In another embodiment, if the transmitter does not fully understand the channel, any remaining ISI or mismatch due to estimation errors can then be cleared by the receiver's adaptive equalization. Generally speaking, the precoder 250 in use can help avoid the adverse effects associated with the Resolution Feedback Equalizer (DFE), including error growth.

The effect of the precoder 250 can be seen from FIG. 6, which shows an exemplary flow chart 600 of the precoded symbol sequence {x[k]} through the channel B(z) 610, in which ISI and others are introduced. For noise, the changed symbol sequence {y[k]} is obtained at the receiver. At the receiver, the inverse precoder estimates the original data sequence to generate recovered data symbols<img file="TWI474658B_D0002.tif" he="108" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="229" />, In theory<img file="TWI474658B_D0003.tif" he="97" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="220" />Same as the original symbol sequence {a[k]}. In FIG. 6, the inverse precoder in the receiver is specifically implemented as the extended splitter 620 and the modulo M module 630. The extended divider 620 is configured to quantize the samples of the received symbol sequence {y[k]} to generate a quantized data symbol sequence<img file="TWI474658B_D0004.tif" he="114" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="218" />. The extended form shows that the extended splitter 620 can not only operate on the original PAM-M constellation set, but also on all copies of the original constellation generated after the channel B_z is introduced into the ISI.

It should be noted that in at least one embodiment of the precoder 250, the discrete channel B(z) is usually the first equation and the smallest phase, and only includes integer coefficients.

Returning to FIG. 2, after the precoding is completed, the TX filter 260 finally processes the precoding data flow. Generally speaking, high-speed symbols sent through traces on the PCB tend to suffer high-frequency attenuation, making it more difficult to reliably detect the transmitted data at the receiver. The overall effect is similar to a low-pass filter that reduces the gain of high-frequency symbols. Generally, dielectric loss, surface effects and crosstalk are the main influencing factors.

In one embodiment, the TX filter 260 is configured to boost the high frequency components of the data symbol without affecting the low frequency components. In another embodiment, the TX filter 260 is configured to suppress low frequency components without affecting high frequency components.

FIG. 7 is a schematic diagram of an embodiment of an exemplary TX filter 260 according to an embodiment of the present invention. As shown in FIG. 7, the TX filter 260 is implemented as an infinite impulse response (FIR) filter and may include one or more delay terms "D" and weights. In one embodiment, the weights b0, b1, ..., bm can be dynamically adjusted during the working process to provide different pre-weighting levels according to channel conditions.

After the TX filter 260 completes the filtering, the modulated data flow can then be placed in the physical channel of the output terminal 280 and sent to the receiving entity. However, before placing it on the physical channel, the TX filter 260 can level shift the modulated data flow so that the average DC sent is zero. An exemplary receiving entity will be described below with reference to FIG. 3. Before describing the receiving entity, it should be noted that those skilled in the art should understand that at least one processing block in the transmitter 200 may be omitted and/or replaced by reasonable variants without departing from the spirit and scope of the present invention.

Fig. 3 is a schematic diagram of an exemplary receiver 300 according to an embodiment of the present invention. As shown in FIG. 3, the receiver 300 includes a programmable gain amplifier (PGA) 305, a continuous-time filter (CTF) 310, a discrete-time sampler 315, a noise canceller 320, a feedforward equalizer (FFE) 325, and data The detector 330, the inverse precoder 335, the linear code decoder 340, the parallel-to-serial module 345, the FEC decoder 350 and the descrambler 355.

In one embodiment, the receiver 300 is implemented in a line card transceiver and is configured to receive data through one or more traces on a printed circuit board in a backplane Ethernet system, such as a backplane Ethernet system 100 . More specifically, the receiver 300 is configured to Receive data, the data is modulated according to the PAM method, the order of the PAM method is higher than the order of the PAM-2 method commonly used in traditional backplane Ethernet systems. For example, in one embodiment, the receiver 300 is configured to receive data modulated according to PAM-4 and received at a serial transmission rate equal to or higher than the conventional rate of 10.3125 GHz. However, it is worth noting that the receiver 300 can be configured to receive data modulated according to any reasonable modulation order and method.

In the working process, the receiver 300 receives the modulated data flow from the physical channel at the input terminal 360. The receiver 300 is configured to control the modulated data flow to be properly restored to the output data flow and provide the output data flow at the output terminal 365. The output data flow can include voice, video, or any other application or program-specific data.

In order to restore the output data flow, the modulated data flow received at the input terminal 360 is first processed by the PGA305. The PGA 305 is configured to amplify the modulated data flow while adding minimal noise to the modulated data flow. Since the attenuation provided to the modulated data flow by the sending channel of the receiving data flow can be greatly changed during the sending process, the PGA 305 is programmable, so that the receiver 300 can be adjusted to different channel conditions such as length.

After being amplified by the PGA 305, the modulated data flow is received and processed by the CTF 310. In one embodiment, the CTF 310 is configured to suppress unwanted thermal noise and other high frequency noise sources (such as any electromagnetic radiation) in the modulated data flow. In another embodiment, the CTF 310 is further configured to boost the intermediate frequency components in the modulated data flow to high frequency components.

The modulated data flow is filtered by the CTF 310 and then received and processed by the discrete-time sampler 315. Generally speaking, a discrete-time sampler is configured to sample the modulated data flow in the time domain and provide discrete samples at its output. In one embodiment, the discrete-time sampler 315 is an analog-to-digital converter (ADC), which can not only sample in the time domain, but can also perform amplitude quantization on the modulated data flow.

After being sampled, the samples of the modulated data flow are then received and processed by the denoiser 320. In one embodiment, the denoiser 320 is configured to retrieve the modulated data from Eliminate one or more noise sources or distortions that can be imitated in the sampling of the material flow. For example, the noise canceler 320 may be configured to add cancellation symbols that mimic the near-end crosstalk (NEXT) noise and/or distortion generated by the PGA 305, CTF 310, and/or sampler 315. In one embodiment, the noise canceller 320 is configured to only mimic and eliminate the third harmonic component of the noise source or distortion, which is usually the most dominant component. In other embodiments, the noise canceler 320 is configured to mimic and eliminate noise sources or distortion other harmonic components other than the third harmonic component.

FFE 325 is followed by noise canceller 320. In one embodiment, FFE 325 is implemented as a parallel FFE and is configured to reduce the negative impact of the advance ISI on the data symbols received through the physical channel. In particular, FFE 325 is configured to delay the data symbol by one or more symbol periods in order to compensate for the advanced ISI using a suitable weighted combination of future symbols that interfere with the current symbol. In another embodiment, the FFE 325 is configured to reduce the advance and/or postcusor ISI on the data symbols received through the physical channel. In yet another embodiment, FFE 325 is configured to place ISI and noise in the optimal relationship of the data detector and/or the resolution feedback equalizer (DFE).

Generally speaking, in a non-parallel FFE embodiment, a series of delay terms and weights are used to compensate for the advance contribution of one or more future symbols on the current symbol. The future symbol is stored in or flows out of the delayed item series. Then, the outflow value is multiplied by the corresponding weight value related to the excess advance ISI contributed by future symbols. The resulting product is then subtracted from the current symbol that has been substantially eliminated from the advanced ISI. In one embodiment, the weight value is determined by an adaptive engine (not shown), and can be continuously used by the adaptive engine to change with the channel condition of the received data.

It should be noted that the FFE 325 is optionally included in the receiver 300. For example, in other embodiments, the FFE 325 may be omitted and its function may be performed by a combination of other linear filters (for example, the transmitting-end linear filter 260 and the CTF 310).

The next two processing blocks after FFE 325 are the data detector 330 and the inverse precoder 335. The implementation of one module often affects the implementation of the other module. Therefore, the two modules will be described together in several different embodiments below.

FIG. 8 specifically shows the first embodiment of this combination, which is also referred to as "DFE with inverse precoder" 800. For illustrative purposes, an exemplary precoder 810 and network channel C(z) 820 are also shown in "DFE with Inverse Precoder" 800. However, it should be noted that the precoder 810 and channel C(z) 820 are not actually included in the "DFE with inverse precoder" 800. On the contrary, the precoder 810 is implemented in the sending entity, and the channel C(z) 820 represents the physical channel network through which the data is sent to the receiver 300, and the transmitter 200 and the receiver 300 may also include other linear filters Device.

In the first embodiment of the combination of the data detector 330 and the inverse precoder 335, the data detector 330 is implemented as the DFE 830, and the inverse precoder 335 is implemented as the infinite impulse response (FIR) filter B(z) 840 and the modulus Combined implementation of M module 850. In this embodiment, the DFE 830 has no knowledge of the precoder 810 on the transmitter side. Therefore, the polynomial B(z) used to implement filtering in the feedback loop of the precoder 810 does not have to exactly match the polynomial C(z) describing the discrete-time channel C(z) 820. DFE 830 simply estimates the precoded symbols {x[k]}.

FIG. 9 shows a second embodiment of the combination of the material detector 330 and the inverse precoder 335, which is also referred to as the "inverse precoder with extended splitter" 900. For illustrative purposes, an exemplary precoder 910 and channel B(z) 920 are also shown in "Inverse Precoder with Extended Splitter" 900. However, it should be noted that the precoder 910 and the channel B(z) 920 are not actually included in the "inverse precoder with extended splitter" 900. On the contrary, the precoder 910 is implemented in the sending entity, and the channel network B(z) 920 represents the physical channel through which the data is sent to the receiver 300, and the transmitter 200 and the receiver 300 may also include other linear filters Device.

In the second embodiment of the combination of the data detector 330 and the inverse precoder 335, the data detector 330 is implemented as an extended divider 930, and the inverse precoder 335 is implemented as a modulo M module 940. In this embodiment, the DFE is completely cleared and replaced by the extended splitter 930. In one embodiment, since there is no feedback in the extended splitter 930, the devices can be processed in parallel in a fairly simple manner, so that the High-speed implementation under conditions that require additional hardware. In addition, since DFE is not used in this second embodiment, the known defect of error growth associated with DFE will also be eliminated.

FIG. 10 shows a third embodiment of the combination of the data detector 330 and the inverse precoder 335, which is also referred to as "local DFE with inverse precoder" 1000. For illustrative purposes, an exemplary precoder 1010 and a channel representing the combination of channel B(z) 1020 and F(z) 1030 are also shown in "Local DFE with Inverse Precoder" 1000. However, it should be noted that the precoder 1010 and the channel representing the combination of the channels B(z) 1020 and F(z) 1030 are not actually included in the "inverse precoder with extended splitter" 1000. In contrast, the precoder 1010 is implemented in the sending entity, and the serial combination of B(z) 1020 and F(z) 1030 represents a physical channel through which data is sent to the receiver 300 as shown in FIG. 3.

In the third embodiment of the combination of the data detector 330 and the inverse precoder 335, the data detector 330 is implemented as a DFE 1030, and the inverse precoder 335 is implemented as a modulo M module 1070. As shown in FIG. 10, the DFE 1040 includes an expanded divider 1050 and a filter [f(z)-1] 1060 implemented in its feedback loop. The DFE 1040 is configured to perform equalization processing on the F(z) part of the channel, which is not processed by the precoder 1010. However, the amount of the expansion divider 1040 still needs to be expanded to the same amount as the precoder 1010 expands the precoded and filtered data symbols {y[k]}. For example, when the fundamental mode L1 of F(z) is small, the third embodiment can be preferably used, because the error increase of DFE will be small at this time.

Returning to FIG. 3, after being processed by the data detector 330 and the inverse precoder 335, the inversely precoded data symbols will be received and processed by the linear code decoder 340. Generally speaking, the linear code decoder 340 is configured to demodulate the symbols of the inversely precoded data symbols. For example, assuming that the symbol represents PAM-4 data, the linear code decoder 340 is configured to demodulate each symbol to its corresponding two-bit value.

The demodulated bit stream is then passed to the parallel-to-serial module 345, and the parallel-to-serial module 345 is configured to perform parallel-to-serial processing on at least two demodulated bit streams and convert them into a serial data process. Generally speaking, when the receiver 300 passes at least two When the trace receives data, the parallel-to-serial module 345 is optionally included in the receiver 300. For clarity, only one serial processing block set connected to the input end of the parallel-to-serial module 345 is shown. However, it needs to be noted that based on the number of parallel data flows that are configured to receive, other sets of serial processing blocks can be used in the receiver 300.

The parallel-to-serial data flow generated by the parallel-to-serial module 345 will then be received and processed by the FEC decoder 350. Generally speaking, the FEC decoder 350 is configured to detect and recover transmission errors in the parallel-to-serial data flow, and can be configured to operate according to any different FEC methods, including, for example, trellis code modulation (TCM), low Density check (LDPC) codes as well as BCH codes such as Reed Solomon (RS). In one embodiment, the FEC decoder 350 is configured to use one or more redundant symbols conveying error detection and correction messages to correct and/or detect blocks of data received by the receiver 300 through at least two parallel data flows Error in.

In another embodiment, the FEC decoder 350 is located before the parallel-to-serial module 345 in the receiver chain. At this time, each parallel data flow received by the parallel-to-serial module 345 uses a separate FEC decoder 350.

Finally, after being processed by the FEC decoder 350, the error-corrected serial data flow is received and processed by the descrambler 355. The descrambler 355 performs the inverse function of any scrambling function performed by the sending entity to eliminate digital bits. Long sequence of '0' or '1' values. The descrambled data is provided at the output terminal 365 as a restored output data flow.

FIG. 11 is a schematic diagram of an exemplary receiver 1100 including a training sequence path according to an embodiment of the present invention. More specifically, the receiver 1100 basically includes the same structure as the transmitter 200 shown in FIG. 2. However, an additional training sequence generator 1110, a linear code encoder 1120, and a multiplexer 1130 are added. Generally speaking, the training sequence generator 1110 is configured to generate a bit sequence known by the receiving entity, such as the receiver 300 shown in FIG. 3, in order to adjust other processing blocks in the receiver and the transmitter.

For example, in one embodiment, the impulse response of the physical channel between the transmitter and the receiver can be estimated using the training sequence of the receiver. The channel estimation can be used to set the FFE and DFE of the receiver or the precoder of the transmitter, as shown in Figure 2. The precoder 250. In one embodiment, a known training sequence is used to adaptively adjust the DFE implemented at the receiver, and then the feedback part of the DFE is passed to the transmitter, and the precoder can be adjusted. The feedback part gives the impulse response required by the channel.

In another embodiment, the gain setting of the PGA, such as the PGA 305 in the receiver 300, can be determined by using a known training sequence. In yet another embodiment, the duration filter (CTF), such as the CTF 310 in the receiver 300, can be adjusted according to a known training sequence. In yet another embodiment, the training sequence may be used in a receiver, such as the receiver 300, to estimate the distortion produced by a module in the receiver that processes the received symbols. For example, the distortion generated by the PGA 305 and the sampler 315 in the receiver 300 can be estimated using a known training sequence, so that the noise canceller 320 removes the distortion from the received symbols.

The above embodiments only provide examples of a few processing blocks that can be adjusted in the receiver and transmitter in communication. Those skilled in the art should understand that adjustment of other processing blocks, such as the processing blocks in the transmitter 200 shown in FIG. 2 and the receiver 300 shown in FIG. 3, can also be implemented.

Returning to FIG. 11, a linear code encoder 1120 may be optionally included to modulate the bits of the training sequence generated by the training sequence generator 1110 according to a modulation method different from the modulation method implemented by the linear code encoder 240. For example, in one embodiment, the linear code encoder 240 may be configured to modulate the data bits received by itself according to PAM-4, and the linear code encoder 1120 may be configured to modulate the bits of the training sequence according to PAM-2. In one embodiment, the use of lower-order modulation methods may better allow the processing blocks of the transmitter and receiver to be adjusted according to the training sequence.

The multiplexer 1130 is used to select between the modulated training sequence and the modulated actual data sequence. In one embodiment, when the communication channel between the transmitter and the receiver is initialized, the modulated training sequence is selected. In another embodiment, the training sequence is temporarily selected after the communication line between the transmitter and the receiver is established, so as to adjust the processing block according to the changing channel conditions.

In one embodiment, the auto-negotiation process can also be used to make the two backplane Ethernet The network transceivers automatically transmit their respective capacities and make full use of their maximum universal capacity. For example, two backplane Ethernet transceivers can automatically negotiate the specific FEC method used during mutual communication. In one embodiment, the at least one backplane Ethernet transceiver may include a transmitter configured according to the transmitter 200 shown in FIG. 2 and a receiver configured according to the receiver 300 shown in FIG. 3.

In one embodiment, the selection from one FEC method to the other in the auto-negotiation process is determined according to the SNR and/or general noise conditions supported by the physical link connecting the two backplane Ethernet transceivers. If the physical link supports low SNR, due to, for example, noisy PCB lines or noisy backplanes, more energy FEC can be selected. On the other hand, if the physical link supports high SNR, a lower energy FEC method can be selected to increase the delay. Generally speaking, the power of the FEC method increases with the number of redundant bits or the transmitted symbols containing a given number of data bits or symbols.

In another embodiment, the selection from one FEC method to another in the auto-negotiation process can be determined according to the required delay. In order to provide a smaller delay, a lower energy FEC method can be selected during auto-negotiation. Generally speaking, the delay increases with the power of the FEC method.

Another area where auto-negotiation can be used and the SNR of the backplane Ethernet communication system can be increased to achieve higher data rates is in the crosstalk area between the transmitter and receiver of the transceiver. Generally speaking, the power of the transmitted signal of the backplane Ethernet transceiver is higher than the weak signal it usually receives. Since the transmitting lines connected to the transmitter and receiver of the backplane Ethernet transceiver are closed on the printed circuit board, they are more sensitive to crosstalk. In particular, the receiver of the backplane Ethernet transceiver can be filled with near-end crosstalk noise from its own transmitter.

One way to reduce near-end crosstalk (NEXT) noise and increase SNR is to remove these signals. The cancellation of these signals can be performed in the receiver 300, for example, by the noise canceller 320 described above. However, if the transmitter and receiver respectively use a common clock to send and receive data, the elimination of these signals will be performed more effectively. In the traditional backplane Ethernet system, the two transceivers in the communication transmit according to their respective drive clocks. material. In one embodiment, when the communication between the two backplane Ethernet transceivers is initialized, a master-slave relationship can be established through an auto-negotiation process. In particular, two backplane Ethernet transceivers in communication can negotiate and then determine their respective master-slave status. The backplane Ethernet transceiver established as the main body can provide a clock, and the respective transmitters of the two backplane Ethernet transceivers can send data according to the clock. In other words, the slave Ethernet transceiver locks the transmission clock of the main backplane Ethernet transceiver and sends data according to the clock. As mentioned above, using a universal clock for data transmission can increase the efficiency of eliminating crosstalk noise generated between the transmitter and the receiver.

In one embodiment, each parallel stream sent by the backplane Ethernet is sent according to the same master clock, and each physical layer related to the message stream is designed as an all-master or all-slave. In another embodiment, each parallel stream in the first-class designed parallel stream group (for example, 4 25Gbps streams into 100Gbps stream) can be synthesized by the backplane Ethernet according to the same master clock. One physical layer related to the message flow is designed as an all-master or all-slave.

It is worth noting that what is used to interpret the claims is the specific embodiment part rather than the abstract part. The abstract section may give one or more but not all exemplary embodiments of the present invention contemplated by the inventor, and therefore, the abstract section does not limit the present invention and the claims in any way.

The above embodiments use functional modules to describe the execution process of specific functions and their relationships. For ease of description, the boundaries of these functional modules are specifically defined in the text. However, as long as the specific functions and their relationships can be appropriately performed, other boundaries can be defined.

The above specific embodiments can reveal the general features of the present invention, so that those skilled in the art can easily modify and/or apply these specific embodiments without undue experimentation without departing from the scope of the present invention. Therefore, according to the teaching of the present invention, these applications and modifications are included in the spirit and scope of equivalent substitutions of the disclosed embodiments. It can be understood that the terms or terms herein are for description rather than limitation, and these terms or terms in this specification can be explained with reference to those skilled in the art.

The scope of the present invention is not limited by any of the foregoing embodiments, but is defined by the claims of the present invention and equivalents thereof.