Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

Microelectronic device with penetrating substrate interconnection and related manufacturing method

MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING

The technical overview of the present invention relates to microelectronic devices with through-substrate interconnection and related manufacturing methods.

A semiconductor die usually includes a plurality of integrated circuits, bonding pads coupled to the integrated circuits, and a metal routing layer for routing electrical signals between the bonding pads and external contacts. Fabricating and packaging the semiconductor dies includes forming interconnects to electrically couple bonding pads and/or metal routing layers to external devices (eg, lead frames, printed circuit boards, etc.).

In some applications, the interconnection extends completely through the semiconductor die or through most of the semiconductor die (commonly referred to as "through-substrate interconnection"). A conventional process for forming through-substrate interconnects may include forming deep vias aligned with corresponding bonding pads on the front and/or back sides of the die. Then, the via holes are filled with conductive material (for example, copper). Solder balls and/or other external electrical contacts are then attached to the through-substrate interconnect.

The through-substrate interconnection can be (1) formed before the integration process (usually called the "drilling first" process), or (2) formed after the integration process has been substantially completed (usually called the "post-drilling" process) . However, both the first-drilling and post-drilling processes have certain disadvantages, as discussed in more detail below. Therefore, some improvements in the penetration substrate forming process can be expected.

Hereinafter, some embodiments of the technology of the present invention will be described with reference to a process for forming a through via and a conductive routing layer in a semiconductor substrate. Many details of certain embodiments are described below with reference to semiconductor dies. The term "semiconductor substrate" is used throughout to include various products, for example, including individual integrated circuit dies, imager dies, sensor dies, and/or dies with other semiconductor characteristics.

Some of the processes described below can be used to form through vias and conductive routing layers in individual dies or in multiple dies on a wafer or part of a wafer. The wafer or wafer portion (for example, in wafer form) may include an unsingulated wafer or wafer portion, or a reassembled carrier wafer. The reassembled carrier wafer may include an adhesive material (for example, a flexible adhesive) surrounded by a substantially rigid frame with a peripheral shape equivalent to that of the unsingulated wafer, and may include an adhesive material surrounded by the adhesive. Individualized components (for example, die).

Many specific details of certain embodiments are set forth in FIGS. 1-4F and the following text is used to provide a thorough understanding of these embodiments. Some other embodiments may have different configurations, components, and/or processes from those described below. Therefore, those skilled in the relevant art should understand that additional embodiments can be implemented without some details of the embodiments shown in FIGS. 1-4F.

FIG. 1 is a schematic cross-sectional view of a part of a microelectronic package 100 according to an embodiment of the present technology. As shown in FIG. 1, the microelectronic package 100 may include a plurality of conductive couplers 104 (for example, solder balls) stacked in series with a plurality of semiconductor dies 102. For illustration purposes, four semiconductor dies 102 (identified individually as first, second, third, and fourth semiconductor dies 102a-102d, respectively) are shown in FIG. 1. In other embodiments, the microelectronic package 100 may include any other desired number of semiconductor dies 102 that are coupled to each other via wire bonds, solder balls, conductive tape, and/or other suitable electrical connectors.

The semiconductor die 102 may individually include a semiconductor substrate 106, which carries a signal routing structure 108 on the first side 106a close to the semiconductor substrate 106; a plurality of bonding pads 112 (identified individually as the first To the fifth bonding pad 112a-112e); and a plurality of through-substrate interconnects 110 extending between the first side 106a and the second side 106b of the semiconductor substrate 106 (respectively identified as the first to fourth interconnects 110a-110d). The semiconductor die 102 may also include an input/output ("I/O") buffer 114 connected to the first through-substrate interconnect 110a and connected to the second, third, and fourth through-substrate interconnects 110b-110d The chip selection ("C/S") buffer 116 is used.

The through-substrate interconnect 110 can be selectively connected to certain metallization layers (not shown in FIG. 1) in the signal routing structure 108 to be between the first side 106a and the second side 106b of the semiconductor die 102 Carrying electrical signals. The details of some embodiments of the process for forming the signal routing structure 108 and the through-substrate interconnect 110 are discussed in more detail below with reference to FIGS. 2A-4F.

The conductive coupler 104 may be interfaced with the corresponding bond pad 112 based on the desired signal routing scheme. As shown in FIG. 1, not all bonding pads 112 are electrically coupled to one of the conductive couplers 104. For example, the first through-substrate interconnect 110a of the first semiconductor die 102a is electrically coupled via the conductive coupler 104 and the first bonding pad 112a of the first semiconductor die 102a. In contrast, the second bonding pad 112b of the semiconductor die 102, the third bonding pad 112c of the third semiconductor die 102c, and the third and fourth bonding pads 112c and 112d of the fourth semiconductor die 102d are not electrically coupled to the conductive Any of the couplers 104. Instead, the signal routing structure 108 interconnects the chip selection signal (and/or other suitable signals) received at the second bonding pad 112b of the first semiconductor die 102a via the second through-substrate interconnect 110b of the first semiconductor die 102a The third through-substrate interconnect 110c of the second semiconductor die 102b and the fourth through-substrate interconnect 110d of the third semiconductor die 102c are routed to the C/S buffer 116 of the fourth semiconductor die 102d.

During operation, the first through-substrate interconnect 110 a of the electrically coupled semiconductor die 102 forms an electrical path for carrying input/output signals to all the semiconductor die 102. The signal routing structure 108 of the individual semiconductor die 102 routes the input/output signals from the electrical path to the individual I/O buffer 114 of the semiconductor die 102. The signal routing structure 108 can also route the chip selection signal (and/or other suitable signals) to the selected semiconductor die 102 so that the selected semiconductor die 102 can process the input/output signals received at the I/O buffer 114 . For example, the signal routing structure 108 routes the chip selection signal received at the fifth bonding pad 112e to the C/S buffer 116 of the first semiconductor die 102a so that the first semiconductor die 102a can process and receive input/output signals . In another example, the signal routing structure 108 can also route the chip selection signal received at the fourth bonding pad 112d to the second semiconductor die 102b via the fourth through-substrate interconnect 110d of the first semiconductor die 102a.

According to conventional techniques, the through-substrate interconnect 110 may be formed based on a first drilling process or a second drilling process. However, the inventors have realized that both the first-drilling and post-drilling processes have certain disadvantages. For example, the post-drilling process may not fully adapt to the routing of the chip selection signal, because the improvement can significantly increase the cost and/or complexity of the manufacturing process. For example, techniques that can be used to route signals in the final metallization layer may include (1) controlling adjacent semiconductor die 102 to form (or avoid forming) conductive bumps; (2) routing signals back to the lower metallization layer; 3) Add a control gate (eg, MOSFET) to the signal routing structure 108; (4) Pattern each of the semiconductor die 102 in different ways; and (5) Add a redistribution layer on the semiconductor die 102 (Not shown).

The inventors have also realized that the first drilling process can adversely affect the electrical reliability of the semiconductor die 102 because the signal routing structure 108 and the integrated circuit (not shown) in the semiconductor die 102 during the formation of the signal routing structure 108 The electrical contacts between the display) may be damaged. Hereinafter, some embodiments of the process for solving at least some of the above-mentioned shortcomings of the first-drilling and post-drilling processes are discussed with reference to FIGS. 2A-2N.

2A-2N are schematic cross-sectional views of a portion of a semiconductor substrate 106 undergoing a process for forming some embodiments of the semiconductor die 102 shown in FIG. 1 according to an embodiment of the present technology. In the following description, similar processing operations can use roughly similar processing techniques. Therefore, for the sake of simplicity, suitable techniques for performing processing operations (for example, patterning the deposited material, removing part of the dielectric material, depositing conductive material, etc.) are described only once.

As shown in FIG. 2A, the process may include forming an integrated circuit 118 in and/or on the first side 106a of the semiconductor substrate 106. In the illustrated embodiment, for illustration purposes, the integrated circuit 118 is schematically shown as a field effect transistor having a source 120a, a drain 120b, and a gate 122. In other embodiments, the integrated circuit 118 may also include vertical transistors, three-dimensional transistors, capacitors, and/or other suitable electrical components forming a dynamic random access memory (DRAM) and/or other suitable electronic devices.

The process may include forming an insulator 124 on the semiconductor substrate 106. In the illustrated embodiment, the insulator 124 includes four layers of silicon oxide, silicon nitride, and/or other suitable dielectrics (identified individually as first to fourth insulating materials 124a-124d, respectively). In other embodiments, the insulator 124 may also include another desired amount of dielectric and/or other suitable insulating materials. The techniques used to form the insulator 124 may include thermal oxidation, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), spin-on glass, and/or other suitable techniques.

The process may also include forming a conductive link 126 in the insulator 124, which is electrically connected to the integrated circuit 118. In one embodiment, forming the conductive link 126 includes patterning the insulator 124 using photolithography and/or other suitable techniques, and removing a portion of the pattern through wet etching, dry etching, reactive ion etching, and/or other suitable techniques The insulator 124 is converted to form a hole 127. The conductive material 129 (eg, copper, aluminum, gold, and/or other suitable conductive materials) may then be used to fill the hole 127 via physical vapor deposition (PVD), CVD, ALD, electroplating, and/or other suitable techniques. In other embodiments, in addition to or instead of the above operations, forming the conductive link 126 may include other processing operations.

The process may include forming a first metallization layer 128a, which is implemented by forming a first dielectric 130 on the insulator 124, patterning the first dielectric 130 according to a desired metal routing profile, and removing a portion of the first dielectric 130 to Trenches, channels, and/or other openings 135 are formed in the first dielectric 130, and a conductive material 137 (for example, copper, aluminum, gold, and/or other suitable conductive materials) is deposited in the opening 135. The process may then include forming a first barrier rib 132 (e.g., BLOK provided by Applied Materials, Santa Clara, California) on the first metallization layer 128a and depositing a second dielectric 134 on the first barrier rib 132 (e.g., oxide Silicon). The second dielectric 134 includes a first surface 134a close to the first barrier rib 132 and a second surface 134b opposite to the first surface 134a.

After the formation of the first metallization layer 128a, FIGS. 2B-2H illustrate the through-substrate interconnection forming process module (hereinafter referred to as "TSV") for forming the through-substrate interconnection 110 (FIG. 1) in the semiconductor substrate 106 Module"). As shown in FIG. 2B, the TSV module may include depositing a first photoresist 136 on the second dielectric 134 via spin coating and/or other suitable techniques. Then, the first photoresist 136 may be patterned to form the first opening 138. The term "photoresist" as used herein generally refers to materials that can be chemically modified when exposed to electromagnetic radiation. The term encompasses positive photoresists that are structured to be soluble when activated by electromagnetic radiation and negative photoresists that are structured to be soluble when activated by light.

As shown in FIG. 2C, the TSV module may include interconnecting holes 140 formed in the semiconductor substrate 106. The interconnection hole 140 may be formed by removing material from the first dielectric 130, the first barrier rib 132, the second dielectric 134, the insulator 124, and at least a portion of the semiconductor substrate 106 through the opening 138 in a continuous operation. In other embodiments, forming the interconnection hole 140 may include a first material removal operation (for example, using wet etching) to remove a portion of the first dielectric 130, the first barrier rib 132, the second dielectric 134, and the insulator 124; and the second material A removal operation (for example, using reactive ion etching) is to remove a part of the semiconductor substrate 106.

As shown in FIG. 2D, the TSV module may further include removing the first photoresist 136 and sequentially forming a hole insulator 142, a hole barrier 144, and a seed material 146 in the interconnect hole 140. The hole insulator 142 may include silicon oxide, silicon nitride, and/or other suitable insulating materials formed by thermal oxidation, CVD, ALD, and/or other suitable techniques. The hole barrier 144 may include tantalum (Ta), tungsten (W), and titanium nitride formed by pulsed chemical vapor deposition ("pCVD"), ion physical vapor deposition ("iPVD"), ALD, and/or other suitable techniques. (TiN), and/or other suitable barrier materials. The seed material 144 may include copper, tungsten, and/or other suitable conductive materials deposited by pCVD, iPVD, ALD, and/or other suitable techniques.

As shown in FIG. 2E, the TSV module may also include depositing a second photoresist 148 on the seed material 146. Then, the second photoresist 148 may be patterned to form the second opening 150. As shown in FIG. 2F, the TSV module may include filling the interconnection hole 140 with the first conductive material 152 through the second opening 150 to form the through-substrate interconnect 110. The first conductive material 152 includes a first portion 152 a located in the interconnect hole 140 and a second portion 152 b extending beyond the second dielectric 134. The first conductive material 152 may include copper, aluminum, tungsten, gold, and/or alloys with the foregoing components. In a specific embodiment, the first conductive material 152 includes electrolytic copper introduced into the interconnection hole 140. Electrolytic copper has enhanced purity compared with electroless deposited materials and compared with solder. For example, the first conductive material 152 may be at least 90% copper and in some cases 99% copper. The second photoresist 148 can then be removed.

As shown in FIG. 2G, the second portion 152b of the first conductive material 152 (FIG. 2F) can then be removed so that the first portion 152a of the first conductive material 152 and the second surface 134b of the second dielectric 134 are substantially flat. The technique for removing the second portion 152b of the first conductive material 152 may include chemical-mechanical polishing ("CMP"), electrochemical-mechanical polishing ("ECMP"), and/or other suitable techniques. As shown in FIG. 2H, the TSV module may optionally include depositing a second barrier 154 on the second surface 134b of the second dielectric 134 and the first portion 152a of the first conductive material 152 (for example, by Applied Materials, Santa Clara, BLOK provided by California). In other embodiments, the deposition of the second barrier rib 154 may be omitted.

Although the TSV module discussed above includes the deposition and patterning of the second photoresist 148, in some embodiments, the second photoresist 148 may be omitted. Instead, the TSV module may include depositing the first conductive material 152, where the first portion 152a is in the interconnection hole 140 and the second portion 152b substantially covers the second surface 134b of the second dielectric 134. Subsequently, at least a portion of the second portion 152b can be removed to produce the through-substrate interconnect 110 as shown in FIG. 2G.

After the TSV module, the process may include forming a second metallization layer. As shown in FIG. 2I, the process may include forming a third dielectric 156 on the optional second barrier 154. The third dielectric 156 includes a first surface 156a close to the optional second barrier 154 and a second surface 156b opposite to the first surface 156a. Then, a plurality of first vias 159 that penetrate the third dielectric 156, the optional second barrier 154, and the second dielectric 134 to the first metallization layer 128a may be formed.

The process may then include depositing a third photoresist 158 on the third dielectric 156 and patterning the third photoresist 158 to form a third corresponding to the desired routing profile of the second metallization layer 128b (not shown). Opening 160. As shown in FIG. 2J, the process may include removing a portion of the third dielectric 156 and optionally a portion of the second barrier 154 to form the opening 162. The opening 162 exposes at least a portion of the second surface 134b of the second dielectric 134 and the upper surface of the first portion 152a of the first conductive material 152.

As shown in FIG. 2K, the process may include filling the opening 162 and the first via 159 with the second conductive material 164, and then removing the excessive second conductive material 164 outside the opening 162 to make the second conductive material 164 and the third dielectric The second surface 156b of 156 is substantially flat. In the illustrated embodiment, the second conductive material 164 includes a first portion 164a, a second portion 164b extending laterally away from the first portion 164a, and a third portion 164c located in the first via 159. The first portion 164a of the second conductive material 164 is in direct physical contact with the first portion 152a of the first conductive material 152 of the penetrating substrate interconnect 110. The third portion 164c of the second conductive material 164 is electrically connected to the second portion 164b and the first metallization layer 128a.

In one embodiment, the second conductive material 164 includes the same composition as the first conductive material 152 (for example, copper). Therefore, the first conductive material 152 and the second conductive material 164 may be substantially the same (the dotted line is used in FIG. 2K to show the artificial dividing line between the first conductive material 152 and the second conductive material 164). In other embodiments, the second conductive material 164 may include a composition that is at least partially different from the first conductive material 152. Therefore, the first metallization layer 128a is electrically connected to the through-substrate interconnect 110 via the second conductive material 164.

After forming the second metallization layer 128b, the process may include forming an additional metallization layer on the semiconductor substrate 106. For example, FIGS. 2L and 2M illustrate the operation of forming the third metallization layer 128c. As shown in FIG. 2L, the process may include depositing a fourth dielectric 166 on the second surface 156b of the third dielectric 156 and the second metallization layer 128b. The deposited fourth dielectric 166 has a first surface 166a close to the third dielectric 156 and a second surface 166b opposite to the first surface 166a. The process may then include patterning and removing a portion of the fourth dielectric 166 to form a plurality of second vias 168 extending from the second surface 166b of the fourth dielectric 166 to the second metallization layer 128b.

The third metallization layer 128c can then be formed according to operations generally similar to those described with reference to FIGS. 2I and 2J. As shown in FIG. 2M, the third metallization layer 128c includes a third conductive material 170, which is electrically connected to the second metallization layer 128b via a second via 168. In the illustrated embodiment, the third conductive material 170 has the same composition as the first conductive material 152 and the second conductive material 164 (eg, copper). In other embodiments, the third dielectric material 170 may have a different composition from the first dielectric material 152 and/or the second dielectric material 164.

In some embodiments, the process may also include processing the semiconductor substrate 106 to form additional features in and/or on the semiconductor substrate 106. For example, as shown in FIG. 2N, a mechanical or chemical-mechanical technique may be used to remove a portion of the semiconductor substrate 106 from the second side 106b to expose the through-substrate interconnect 110. The conductive components 172 (for example, conductive posts, solder balls, solder bumps, redistribution layers, through-silicon via studs, and/or other suitable interconnection devices) can then be attached to the through-substrate interconnect 110. To interconnect with external components (not shown).

Although only the first metallization layer 128a, the second metallization layer 128b, and the third metallization layer 128c are illustrated in FIGS. 2A-2M, in some embodiments, the process may include repeating at least the above-referenced figure Some of the operations discussed in 2L and 2M are used to form four, five, or any desired number of metallization layers. In these embodiments, the through-substrate interconnect 110 may be electrically connected to the second metallization layer 128b, the third metallization layer 128c, or the N-1 metallization layer (not shown).

Some embodiments of the above process can reduce the risk of damaging the electrical connection between the first metallization layer 128a and the conductive link 126. The inventors have observed that forming the through-substrate interconnect 110 before forming the first metallization layer 128a creates a defective electrical connection between the first metallization layer 128a and the conductive link 126. Without wishing to be limited by theory, it is believed that some operations (eg, depositing conductive material, removing excess conductive material, etc.) during the formation of the first metallization layer 128a can substantially weaken and/or damage the first metallization layer 128a and the conductive material. Electrical connection between links 126. Therefore, by forming the through-substrate interconnect 110 after forming the first metallization layer 128a, the risk of defective electrical connections can be reduced.

Some embodiments of the above process are also more cost-effective and more flexible than conventional technologies. For example, the selection of the electrical connection between the through-substrate interconnect 110 and the metallization layer can be postponed to a processing stage later than the first drilling process. Therefore, the number of general intermediate products (ie, semiconductor dies that partially form a metallization layer) can be increased so that the production manager can continuously produce semiconductor dies 102 before making a decision on the final connection configuration of the semiconductor dies 102.

Although the specific operation of forming the second metallization layer 128b and connecting it to the through-substrate interconnect 110 is discussed above with reference to FIGS. 2A-2N, in other embodiments, additional and/or different process operations may be used to form the second metallization layer 128b. The layer 128b is metalized and connected to the through-substrate interconnect 110. For example, FIGS. 3A-3F are schematic cross-sectional views of a portion of a semiconductor substrate undergoing a process for forming some embodiments of the semiconductor die 102 shown in FIG. 1 according to additional embodiments of the present technology. As shown in FIG. 3A, the process may include forming an integrated circuit 118 in and/or on the semiconductor substrate 106, forming a conductive link 126, a first metallization layer 128a, and forming on the first metallization layer 128a The first barrier 132 is as described above with reference to FIG. 2A.

Unlike the embodiment shown in FIG. 2A, the process shown in FIG. 3B may include using a TSV module before depositing the second dielectric 134 on the first barrier rib 132, as discussed above with reference to FIGS. 2B-2H. Subsequently, a second dielectric 134 may be formed on the first barrier rib 132 and the through-substrate interconnect 110. Therefore, the penetration substrate interconnection 110 and the first barrier rib 132 can be substantially in a plane and can directly contact the first surface 134 a of the second dielectric 134.

As shown in FIG. 3C, the process may include depositing a third dielectric 156 on the second dielectric 134. Therefore, the first surface 156a of the third dielectric 156 can directly contact the second surface 134b of the second dielectric 134. The process may include forming a plurality of access vias 180 penetrating the third dielectric 156, the second dielectric 134, and the barrier 132 in the second dielectric 134 and the third dielectric 156. The access vias 180 include (1) a first group 180a roughly corresponding to the access vias 180 penetrating the substrate interconnect 110; and (2) a first group 180a roughly corresponding to the access vias 180 of the first metallization layer 128a The second group 180b.

The process may then include depositing a photoresist 182 on the third dielectric 156 and patterning the photoresist 182 to form an opening 184 corresponding to the desired routing profile of the second metallization layer 128b. As shown in FIG. 3E, the process may include removing a portion of the third dielectric 156 to form an opening 186. The opening 186 exposes at least a part of the second surface 134 b of the second dielectric 134 and communicates with at least some of the access vias 180.

As shown in FIG. 3F, the process may include filling the opening 186 with the second conductive material 164 and accessing the via 180. Then, the excess second conductive material 164 outside the opening 186 can be removed, so that the second surface 156b of the second conductive material 164 and the third dielectric 156 are substantially flat. The second conductive material 164 includes a first portion 164a, a second portion 164b extending laterally away from the first portion 164a, a third portion 164c in the first group 180a of the access vias 180, and a second portion 164c in the access vias 180 The fourth part 164d in group 180b. The third portion 164c of the second conductive material 164 electrically connects the first portion 164a of the second conductive material 164 to the through-substrate interconnect 110. The fourth portion 164d of the second conductive material 164 electrically connects the second portion 164b of the second conductive material 164 to the first metallization layer 128a. As discussed with reference to FIGS. 2L-2N, the process may then include forming an additional metallization layer and performing subsequent processing.

4A-4F are schematic cross-sectional views of a portion of a semiconductor substrate 100 undergoing a process for forming some embodiments of the semiconductor die 102 shown in FIG. 1 according to other embodiments of the present technology. As shown in FIG. 4A, the process may include forming an integrated circuit 118 in and/or on the semiconductor substrate 106, forming a conductive link 126, a first metallization layer 128a, and forming on the first metallization layer 128a The first barrier 132 is as discussed above with reference to FIG. 2A. The process may also include forming the second metallization layer 128b, as discussed above with reference to FIGS. 2H-2K. The process then optionally includes depositing a second barrier 154 on the second metallization layer 128b.

As shown in FIG. 4B, the process may include forming a fourth dielectric 166 on the second barrier rib 154 and depositing a photoresist 190 on the fourth dielectric 166. The photoresist 190 can then be patterned to form an opening 192 corresponding to a portion of the second metallization layer 128b and penetrating the substrate interconnect 110 (not shown). Therefore, a part of the fourth dielectric 166 and the underlying second barrier rib 154 are exposed in the opening 192 (hereinafter referred to as the exposed portion 194).

As shown in FIG. 4C, the process may include forming interconnection holes 140 in the semiconductor substrate 106 and removing exposed portions 194 (FIG. 4B). In one embodiment, the interconnection hole 140 may be formed and the exposed portion 194 may be removed using a phase shift mask, a leaky-chrome mask, and/or other suitable techniques in one continuous operation. In another embodiment, a first mask (not shown) roughly corresponding to the interconnection hole 140 may be used for etching to form the interconnection hole 140. The exposed portion 194 may be removed using a second mask (not shown) substantially corresponding to the exposed portion 194. In other embodiments, the exposed portion 194 may be removed via other suitable techniques.

As shown in FIG. 4D, the process may include forming a hole insulator 142 in the interconnection hole 140. In the illustrated embodiment, the hole insulator 142 includes a first portion 142 a located in the interconnect hole 140 and a second portion 142 b located outside the interconnect hole 140. The second portion 142b at least partially overlaps and directly contacts the second metallization layer 128b. In other embodiments, by using, for example, a photomask roughly corresponding to the interconnection hole 140 used when forming the hole insulator 142, the hole insulator 142 may only include the first portion 142a.

As shown in FIG. 4E, the process may include at least partially removing the second portion 142b of the via insulator 142 and exposing the second metallization layer 128b. In one embodiment, the second portion 142b may be partially removed via spacer etching. Therefore, a portion 142c of the second portion 142b is still located on the second metallization layer 128b. In other embodiments, the second portion 142b may be partially removed by laser ablation and/or other suitable techniques. In other embodiments, the second portion 142b may be completely removed.

The process may then include depositing hole barriers 144 and seed material 146 in interconnect holes 140, as discussed above with reference to FIG. 2C. Then, the process may include filling the interconnection hole 140 with the first conductive material 152 and removing the excess first conductive material 152 from the fourth dielectric 166.

As shown in FIG. 4F, the through-substrate interconnect 110 includes a vertical section 110 a located in the interconnect hole 140 and a horizontal section 110 b located outside the interconnect hole 140. The horizontal section 110b extends laterally toward the second metallization layer 128b so that at least a part of the horizontal section 110b directly contacts the upper surface of the second metallization layer 128b. The process may optionally include forming a third barrier 196 on the fourth dielectric 166 and the through-substrate interconnect 110. The process may then include forming an additional metallization layer as discussed with reference to FIGS. 2L-2N and performing subsequent processing to produce the semiconductor die 102 shown in FIG. 4E.

Based on the foregoing, it should be understood that specific embodiments of the technology have been described herein for the purpose of illustration, but various modifications can be made without departing from the technology. In addition to or instead of the elements of other embodiments, many elements of one embodiment can be combined with other embodiments. Therefore, this technology is only limited by the scope of the attached application patent.

<p>100. . . Microelectronic packaging</p><p>102. . . Semiconductor die</p><p>102a. . . First semiconductor die</p><p>102b. . . Second semiconductor die</p><p>102c. . . Third semiconductor die</p><p>102d. . . Fourth semiconductor die</p><p>104. . . Conductive coupler</p><p>106. . . Semiconductor substrate</p><p>106a. . . The first side of the semiconductor substrate</p><p>106b. . . The second side of the semiconductor substrate</p><p>108. . . Signal routing structure</p><p>110. . . Through-substrate interconnect</p><p>110a. . . First through-substrate interconnect</p><p>110b. . . Second through-substrate interconnection</p><p>110c. . . Third through-substrate interconnection</p><p>110d. . . Fourth through-substrate interconnection</p><p>112. . . Bonding pad</p><p>112a. . . First bonding pad</p><p>112b. . . Second bonding pad</p><p>112c. . . Third bonding pad</p><p>112d. . . Fourth bonding pad</p><p>112e. . . Fifth bonding pad</p><p>114. . . Input/output buffer</p><p>116. . . Chip selection buffer</p><p>118. . . Integrated circuit</p><p>120a. . . Source</p><p>120b. . . Dip pole</p><p>122. . . Gate</p><p>124. . . Insulator</p><p>124a. . . First insulating material</p><p>124b. . . Second insulating material</p><p>124c. . . Third insulating material</p><p>124d. . . Fourth insulating material</p><p>126. . . Conductive link</p><p>127. . . hole</p><p>128a. . . First metallization layer</p><p>128b. . . Second metallization layer</p><p>128c. . . The third metallization layer</p><p>129. . . Conductive material</p><p>130. . . First dielectric</p><p>132. . . First barrier</p><p>134. . . Second dielectric</p><p>134a. . . The first surface of the second dielectric</p><p>134b. . . The second surface of the second dielectric</p><p>135. . . Opening</p><p>136. . . First photoresist</p><p>137. . . Conductive material</p><p>138. . . First opening</p><p>140. . . Interconnect hole</p><p>142. . . Hole insulator</p><p>142a. . . The first part of the hole insulator</p><p>142b. . . The second part of the hole insulator</p><p>142c. . . Part of the second part of the hole insulator</p><p>144. . . Hole barrier</p><p>146. . . Seed material</p><p>148. . . Second photoresist</p><p>150. . . Second opening</p><p>152. . . First conductive material</p><p>152a. . . The first part of the first conductive material</p><p>152b. . . The second part of the first conductive material</p><p>154. . . Second barrier</p><p>156 Third Dielectric</p><p>156a. . . The first surface of the third dielectric</p><p>156b. . . The second surface of the third dielectric</p><p>158. . . Third photoresist</p><p>159. . . First via</p><p>160. . . Third opening</p><p>162. . . Opening</p><p>164. . . Second conductive material</p><p>164a. . . The first part of the second conductive material</p><p>164b. . . The second part of the second conductive material</p><p>164c. . . The third part of the second conductive material</p><p>164d. . . The fourth part of the second conductive material</p><p>166. . . Fourth dielectric</p><p>166a. . . The first surface of the fourth dielectric</p><p>166b. . . The second surface of the fourth dielectric</p><p>168. . . Second via</p><p>170. . . Third dielectric material</p><p>172. . . Conductive components</p><p>180. . . Access via</p><p>180a. . . The first group of access vias</p><p>180b. . . The second set of access vias</p><p>182. . . Photoresist</p><p>184. . . Opening</p><p>186. . . Opening</p><p>190. . . Photoresist</p><p>192. . . Opening</p><p>194. . . Exposed part</p><p>196. . . The third barrier</p>

FIG. 1 is a schematic cross-sectional view of a microelectronic package with stacked dies according to an embodiment of the present technology.

FIGS. 2A-2N are schematic cross-sectional views of a portion of a semiconductor substrate that can be used to form some embodiments of the semiconductor die shown in FIG. 1 through the experience of the present technology.

3A-3F are schematic cross-sectional views of a portion of a semiconductor substrate that can be used in the process of forming some embodiments of the semiconductor die shown in FIG. 1 through the experience of additional embodiments of the present technology.

4A-4F are schematic cross-sectional views of a portion of a semiconductor substrate that can be used in the process of forming some embodiments of the semiconductor die shown in FIG. 1 through other embodiments of the technology.