Integrated capacitor with alternating layered segments

Integrated capacitor with alternate laminated parts

INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS

[Related Application Cases]

This patent application is co-owned by Patrick J. Quinn with the U.S. patent application titled "Integrated Capacitor Shading", and the patent application jointly owned by Patrick J. Quinn titled "Integration with a tartan cross-section" The U.S. patent application for "Capacitors", the U.S. patent application titled "Integrated Capacitors with Interconnecting Flanks" co-owned by Patrick J. Quinn, and the U.S. patent application titled "With Cable Flat Panels" co-owned by Patrick J. Quinn The U.S. patent application for "Integrated Capacitors" and the U.S. patent application titled "Integrated Capacitors with Cross Element Array" co-owned by Patrick J. Quinn were filed at the same time. The disclosures of these U.S. patent applications actually differ It is incorporated in this article in its entirety by reference.

The present invention relates to a capacitor formed in an integrated circuit (IC; integrated circuit), which is generally referred to as an "integrated capacitor".

The method of manufacturing IC typically includes: a front-end processing sequence, in which various electrical components such as transistors are formed on a semiconductor substrate; and, a back-end processing sequence, generally including the formation of dielectric materials with conductive vias and Alternating layers of patterned conductive material (typically metal) or other techniques are used to interconnect metal layers to form a three-dimensional wiring structure that connects electrical components to other electrical components and IC terminals.

Capacitors are used in IC systems for various purposes. In many instances, it is desirable to incorporate (integrate) a capacitor into the IC chip. A simple way is to form two conductive plates with an intervening dielectric; however, this consumes a considerable amount of area for the obtained capacitance. One technique for increasing the capacitance of a given area uses multiple conductive plates, each conductive plate being separated from adjacent plates by a dielectric. Another technique uses conductive strips, also known as conductive lines, conductive fingers or conductive traces, which are alternately connected to the first and second capacitor terminals (nodes). The sidewalls coupled between the conductive slats provide capacitance. Conductive strip layers arranged or arranged in a vertical consistency can be added to further increase the capacitance of an integrated capacitor structure.

A capacitor has a number of conductive strips connected to a first node in a continuous layer and alternates with an equal number of conductive strips connected to a second node of the integrated capacitor. The conductive slats are offset by half of the unit on the continuous layer, so that one of the conductive slats connected to the first node has a conductive slat connected to the second node on both sides thereof. The provision of an equal number of conductive slats for each node on a layer is balanced with the coupling of each node to the substrate. This is expected in some applications, but not in others, such as: switching applications, where, It is expected to have less coupling at one node.

Another way to provide an integrated capacitor is to have conductive strips in one layer connected to alternating nodes of the capacitor and overlapping conductive strips connected to the same node. The essence is to form a conductive strip and interconnection path connected to a curtain of the first node of the capacitor and a conductive strip and interconnection path connected to an adjacent curtain of the second node. The overlapping conductive slats connected to the same node avoid the lost surface area associated with the bus slats; however, the capacitance between layers is reduced because the upper slats are connected to the same node as the lower slats. This effect is slightly ruled out, because as the critical dimension shrinks, the capacitance between the slats becomes stronger than the capacitance between the layers. In other words, the dielectric separation between the continuous metal layers becomes more and more larger than the dielectric separation between the conductive strips as the critical size decreases.

Long, parallel conductive fingers often cause design constraints, such as the minimum width for a given length of a given metal layer. In some designs, a long conductive finger causes an unexpected inductance-resistance curve, and the inductance increases as the length of the finger increases.

Therefore, an integrated capacitor that overcomes the shortcomings of the prior art is desired. More generally, it is expected that the integrated capacitor has high capacitance per unit area, low loss (resistance) and low self-inductance, which improves the application of high frequency by improving the self-resonance frequency and the quality of the capacitor circuit.

A capacitor in an integrated circuit (IC) has: a first node plate link formed on a first metal layer of the IC, which is electrically connected and forms part of a first node of the capacitor, And extend along a first axis; and, a second node plate link formed on a second metal layer of the IC, which extends along the axis and is connected to the first node plate link through a path . A third node plate link formed in the first metal layer is electrically connected and forms a part of a second node of the capacitor, and extends along a second axis of the node plate array and is transverse to the first node plate link, It is adjacent to one end of the plate link of the first node and overlaps a part of the plate link of the second node.

Composite ICs such as programmable logic devices often have several patterned metal layers separated by dielectric material layers formed on a semiconductor substrate, which are used for wiring connections and other functions, and are commonly referred to as the "back end" of the IC . Some embodiments of the present invention can be adapted to existing CMOS processing procedures, by using a mask that forms a desired pattern on an appropriate metal layer and passes through an inter-metal dielectric (IMD; inter- Metal dielectric layer or inter-layer dielectric (ILD; inter-layer dielectric) via. The vias are formed using any of several conventional techniques, such as contact plug, damascene or dual damascene technology. In the same way, the conductive slats are formed by any of several conventional techniques, such as thin film metal etching (etch), thin film metal lift-off, metal damascene and bimetal damascene technologies. In some embodiments, one of the conductive layers is a polysilicon or silicide layer. In yet another embodiment, a conductive well in the semiconductor substrate forms a part of a capacitor plate or a shield.

Field programmable gate array (FPGA; field programmable gate array) uses integrated capacitors in various circuit applications, such as filter capacitors, switching capacitors, and RF coupling capacitors. The embodiment of the integrated capacitor can be expanded to provide a wide range of total capacitance values for various circuit applications. High specific capacitance (capacitance per unit area of silicon) is achievable and maintains low resistance and inductance impedance, and high total capacitance is obtained in a small area, keeping the IC chip size small. Capacitors are generally used in a wide variety of integrated circuits and in a wide variety of applications. For example, one or more capacitors can be used in a switched capacitor network, such as in an analog-to-digital converter, or as a decoupling or filter capacitor for AC signaling (e.g., in MGT). In summary, the capacitor structure described herein can be used in any application that requires capacitance.

FIG. 1A is a plan view of a part of an integrated capacitor 100 according to an embodiment of the present invention. The plan view shows the portion of the two patterned conductive layers of an IC with the dielectric material removed between them. The lower metal layer is shown by diagonal lines to more clearly distinguish the features of the lower metal layer and those on the upper metal layer. In addition, the metal features of the lower layer extending below the metal features of the upper layer are shown by dotted lines for the improved illustration of the two-layer structure.

The integrated capacitor has a first node A and a second node B. In some embodiments, the A and B nodes are the top and bottom nodes of a switching capacitor of an IC. In some switched capacitor applications, shielding the top node from electrical noise or stray coupling is particularly desirable. In other embodiments, nodes A and B are balanced nodes of an RF coupling capacitor. In some RF coupling applications, it is particularly expected that one node has substantially the same impedance as another node and the capacitor has a high self-resonant frequency. In still other embodiments, the nodes A and B are nodes of a filter capacitor. High specific capacitance and high total capacitance are usually expected from filter capacitors. Note: A capacitor is generally regarded as a two-terminal device, and the "top" and "bottom" nodes described herein generally correspond to the two terminals of the capacitor. Therefore, the following structure can be regarded as (e.g., electrically) connected to one node or another node or forming part of a node. A node does not separate the capacitor structure to which it is connected, but their structure can form part of a node.

The integrated capacitor 100 is composed of several node plate links 102, 104, 106, 108, and 110. The node plate links are essentially the same, but alternative embodiments are applied to different links in different layers or different links within one layer. Additional embodiments use additional conductive elements connected to the node plate links of the node plate array (see, for example, the central "H element" shown in Figure 2A). The nodal plate links are rectangular and have a length-to-width aspect ratio from about 1.5:1 to about 5:1. Node links with lower aspect ratios (see, for example, reference symbol 104 in FIG. 1A) typically have more than one junction between the layers. A node link with a single contact (see, for example, reference symbol 237 in FIG. 2C) may have a higher aspect ratio. In a specific embodiment, a node plate link (see, for example, reference symbol 237 in FIG. 2C) has: a width, which is for the node plate link to be a metal trace formed on the patterned metal layer. The minimum design width; and, a length that is approximately equal to three times the width (for example: the path is formed in its two square end portions and the node plate link is a central square of the horizontal node plate link underneath the overlap Part) plus two minimum metal wire spacing (for example: the spacing between the horizontal node plate link under link 237 and the link end around link 237 (basically perpendicular to link 237) The length between the dashed pair)). In a specific embodiment, the minimum metal line spacing is approximately equal to the minimum metal line width, resulting in an aspect ratio of approximately 5:1. In an alternative embodiment, a node plate link is approximately 3f wide and 6f long, where f is the critical minimum dimension for node technology formed on the metal layer of the node plate link.

Compared with the metal wires used in many conventional integrated capacitors (which often have an aspect ratio greater than 100:1), the aspect ratio of the nodal plate link is quite low. The low aspect ratio of the node plate link provides a high specific capacitance, by connecting to the first node one node plate link to the corresponding node plate link connected to the second node at the two ends and two sides In-layer (edge-to-edge) capacitance (see: Figure 1C and associated instructions). For ease of discussion, the length of a nodal plate link is the longer dimension of a plan view of a nodal plate link, which typically extends between the contacts of a first axis of a nodal plate array, and the width is relatively short The dimension, which typically extends along a second axis of the nodal plate array, and the second axis is typically orthogonal to the first axis.

Some node plate links 108, 110 are on the lower metal layer, and other node plate links 102, 104, 106, 122 are on the upper metal layer. The node plate link on the first layer (for example: the node plate link 102 on the upper layer) is electrically connected by the conductive path ("path") 112 to the node plate link on the other layer (for example: the node plate link 108), And the nodal plate links are sufficiently wide to accommodate at least one (and or two or more) through holes. The node plate link is a "basket-weave" pattern in columns B1, B2, B3 and rows A1, A2, A3, A4, and A5, alternating from one layer to the next. That is, a node plate link 102 extending in the upper layer along row A5 connected to the first node passes over a node plate link 114 extending in the lower layer along B1 connected to the second node. The node plate link 102 is connected in series to a second node plate link 108 extending in the lower layer along row A5, and the second node plate link 108 is connected to the second node and extends along column B2 to a node plate in the upper layer. Below link 106. This sequence is repeated along the columns and rows of the integrated capacitor 100.

On the upper patterned metal layer, the node plate link 102 connected to the first node extends along a first axis above the node plate link 114 of the lower patterned metal layer, and the node plate link 114 is connected to the first node. Two nodes and extend along a second axis orthogonal to the first axis. Row A5 includes node plate links attached to the first node of the integrated capacitor alternately between the first (upper) and second (lower) metal layers, and column B1 includes the second node attached to the integrated capacitor and Node plate links alternate between the first and second metal layers. On the upper metal layer, extending along a first axis of the node plate link array ("node plate array"), one of the first nodes connected to the integrated capacitor is the first node plate link along the first axis ( That is: the long dimension of the node plate link is oriented along the first axis, and then connected to one of the second nodes of the integrated capacitor. The second node plate link is oriented along the second axis, and then connected to the first axis. One of the third node plate links of the nodes is oriented along the first axis.

Each node plate link in each row is connected to the node A of the type of capacitor, and each node plate link in each column is connected to the node B of the type of capacitor. This is further discussed with respect to FIG. 1B.

Compared to conventional integrated capacitors that use long and thin conductive wires, the basket-woven pattern provides high specific capacitance and low inductance and resistance. The node plate link 102 in the upper layer is capacitively coupled to the node plate link 114 in the lower layer. The links are bridged (partially overlapped), and are called "interlayer capacitance". The end of the node plate link 102 is capacitive The edge of the plate link 106 that is coupled to the adjacent node is called "in-layer capacitance", and the end of the plate link 104 of the adjacent node is capacitively coupled to the edge of the plate link 102 of the node. Therefore, this kind of basket-woven pattern provides interlayer and intralayer capacitance. The ratio of the inter-layer effect to the intra-layer effect of the total capacitance is selectable by adjusting the aspect ratio and scale of the plate links of the nodes and the pattern layout. In some embodiments, the nodal plate elements are laid out using minimum spacing rules. In some embodiments, the nodal plate element is patterned using the smallest metal line width rule and the smallest pitch. In an alternative embodiment (see, for example, FIG. 1A), the layout of the node plate element is larger than the minimum metal line width.

In yet another embodiment, the additional metal layer above or below the two illustrated layers is patterned. For example, a third metal layer (see: FIG. 2E) is patterned to be substantially similar to the first metal layer and overlaps the upper metal layer shown in FIG. 1A. Another patterned metal is the layer shown below in a similar manner. The stacked vias extend from the lowermost metal layer and pass through the middle metal layer to the uppermost (third) metal layer. Embodiments may have an even number of patterned metal layers or an odd number of patterned metal layers (larger than one). The additional patterned metal layer increases the specific capacitance of the integrated capacitor.

FIG. 1B is a plan view of a one-node plate array 150 of integrated capacitors according to an embodiment. The node plate array 150 is a block of node plate links that are duplicated and repeated to form part of the integrated capacitor, similar to how a memory cell array is segmented and repeated. The number of node plate links in the node plate array is reduced for illustration. The node plate array 150 has a coverage area generalized as a square, and provides highly symmetrical impedance characteristics for the two nodes of the capacitor. An alternative embodiment of the nodal plate array is non-square. In a particular embodiment, the number of columns and rows in an array (and therefore the number of series links along the corresponding row or column) is selected to adjust the ratio of capacitance to series resistance.

The serial nodal plate link is implemented in columns and rows. A typical nodal plate link array has 10 to 100 nodal plate links connected in series in a row or row. The number of links between bus bars ("metal wires") or other common node connectors in series is determined by several factors, such as the desired capacitance and impedance characteristics of the integrated capacitor. For example, the via can have a relatively high series resistance. One embodiment may use a narrow node plate link with a single path, while another embodiment uses a wider node plate link with two or more paths in each tier. The use of a wider node plate link enhances the interlayer capacitance and provides low series resistance through multiple (parallel) paths, but by reducing the total length of the edge-to-edge coupling for a known area of the node plate array To reduce the intra-layer capacitance, the ratio of the intra-layer capacitance to the inter-layer capacitance can be adjusted (selected) according to the aspect ratio of the node plate link.

The rows of nodal plate links extend between a first bus bar 152 and a second bus bar 154 generally parallel to the first bus bar. The bus bars 152, 154 are along a first axis of the nodal plate array ( X axis), the rows of nodal plate links extend between a third bus bar 156 and a fourth bus bar 158, and the bus bars 156, 158 extend along a second axis (Y axis) of the nodal plate array . The third and fourth bus bars 156, 158 are shown in dashed lines to indicate that they are patterned on the underlying metal layer and in a simplified manner for clarity of description. The vias 160 and 162 are electrically connected to the node plate link 164 on the upper layer to the bus bar 156 on the lower layer. Similarly, the vias 166 and 168 connect the first bus bar 152 to a node plate link (not shown) of the lower metal layer (see, for example, FIG. 1A). Other configurations of the bus bar are alternative applications. For example, vertical and horizontal bus bars are essentially patterned on a single metal layer, using any one of several bridging techniques, where the bus bars cross or otherwise intersect.

The bus bar is summarized as a low-resistance, low-impedance element, which connects one or more node plate link arrays to the circuit nodes of the integrated capacitor. Providing a bus bar along the opposite edges of the node plate link array 150 presents a symmetrical electrical environment and reduces the series resistance or inductance that will appear in the single-ended column or row. In other words, a plate link at a node in the center of the array has a similar resistance to each of the bus bars, basically providing two resistors in parallel and reducing significant series resistance.

In a typical integrated capacitor, a multi-node plate link array is connected to the bus bar. For example, additional node plate link arrays (not shown) are connected to the left and right sides of the bus bars 156 and 158 or above or below the bus bars 152 and 154. Using a standard nodal plate link array makes it easy to manufacture integrated capacitors of different values and different physical sizes. Some embodiments of integrated capacitors use a single node plate array.

The integrated capacitor using a basket-woven pattern technology provides good manufacturing consistency and high specific capacitance. Manufacturing consistency (ie: low variation and low batch-to-batch variation across a wafer or across an IC) is particularly expected for actually large ICs, such as FPGAs, where the integrated capacitors may actually be separated from the IC chip Quite a distance. Embodiments that use node plate components manufactured with greater than the minimum metal line width (see, for example, the node plate link of Figure 1A, which is wide enough to accommodate two vias) is a good way to provide a wafer across multiple ICs. Consistency and good wafer-to-wafer and lot-to-lot consistency. Compared with conventional wire-line capacitors manufactured with the smallest metal line width, integrated capacitors manufactured with a minimum metal line width provide higher specific capacitance and higher manufacturing yield.

FIG. 1C is a plan view of a portion 120 of the upper metal layer of FIG. 1A. A node plate link 122 connected to one node (ie: node A) (for example: the node plate link intersecting row A2 in column B2 of FIG. 1A) has adjacent connections to other nodes (ie: node B) The ends 124, 126 of the node plate links 128, 130. The side edges 132 and 134 of the node plate link 122 are also adjacent to the node plate links 136 and 138 connected to other nodes. The ends 124, 126 of the node plate link 122 are coupled to the sides of the opposite node plate links 128, 130 to provide in-layer capacitance. In the same way, the sides 132 and 134 of the node plate link 122 are coupled to the ends of the opposite node plate links 136 and 138 to provide additional in-layer capacitance. A rectangular node plate link configured by a basket-weaving technique provides in-layer capacitance at the ends and sides of the conductive elements, thereby providing a high specific capacitance.

FIG. 2A is a plan view of a part of the first patterned metal layer 201 (ie, the upper metal layer in FIG. 2C) of a node plate array. The node plate links 210, 214, 211, and 218 are arranged along rows A1, A2, A3 and columns B1, B2, B3. An H element 202 has side elements 205, 207 and a junction element 209 extending between the side elements. The H element 202 is connected to the A node, such as node plate links 210 and 214. The junction element 209 extends along the direction of the row, such as the node plate link connected to node A, and the side elements 205, 207 extend along the direction of the column, as the node plate link connected to node B. extend. This allows the side elements to be coupled to the Node B link plates along the longer edge columns compared to the end edges of a simple rectangular link (compare: reference signs 124, 126 in FIG. 1C), thus providing Improved in-layer capacitance. For example, the intra-layer coupling 213, 215 between the H element 202 and the node plate link 218 is increased to the end-to-side coupling 217, which will happen if the H element is replaced by a rectangular link. In addition, the side element 205 is coupled to the nodal plate link 221, as indicated by the double-ended arrow 219. Those familiar with integrated capacitors will understand that the side elements of the H element provide additional in-layer capacitance for other node plate links (such as links 211 and 223).

2B is a plan view of a part of the second patterned metal layer 203 (ie, the lower metal layer in FIG. 2C) of a node plate array. The portion of the second patterned metal layer 203 is substantially similar to the portion of the first patterned metal layer in FIG. 2A after being rotated ninety degrees. Therefore, the detailed description of this part of the second patterned metal layer is omitted. The second H element increases the in-layer capacitance, as described above with respect to FIG. 2A, and also increases the interlayer capacitance, as described below with respect to FIG. 2C.

2C is a plan view of a part of a one-node plate array 200 of integrated capacitors according to another embodiment. The upper metal layer of FIG. 2A is shown without oblique lines and is overlapped with the lower metal layer of FIG. 2B, which shows oblique lines. The H element 202 is defined in the upper conductive (metal or polysilicon/silicide) layer, and the second H element 204 is defined in the lower conductive layer. The second H element 204 is rotated ninety degrees from the first H element 202. The vias 206, 208 together electrically connect the conductive node elements. The first H element 202 is connected to a first node (node A) through the node plate link and path of row A2 and the second H element 204 is connected to the integrated capacitor through the node plate link and path of column B2 A second node (Node B). The electrical connection to the first node is made along rows A1, A2, A3, and the electrical connection to the second node is made along columns B1, B2, B3. The label as a column or as the axis of a row is arbitrary, and the terms are used only for ease of discussion. The node plate links 210, 212, 214 connected to the first node and the orthogonal plate portions 216, 238, 220 connected to the second node are alternated in the conductive layer in a "basket weave" pattern, as in Figure 1A As described in 1B above.

In some embodiments, the pattern of FIG. 2C is repeated along columns and rows to form a nodal plate array (see, for example, FIG. 3A). The H element increases the interlayer capacitance as described above with respect to FIG. 2A, and also increases the interlayer capacitance in the regions P1, P2, P3, and P4. In these regions, the side elements of the first and second H elements overlap , And will be described below with respect to FIG. 2D. The ratio of the interlayer capacitance to the intralayer capacitance is variable according to the width and length of the plate portion and the line spacing in the layer.

FIG. 2D is a cross section 220 of the node plate array 200 of FIG. 2C, which is taken along the section line LL. The section line extends through the nodal plate link 218, the H elements 202 and 204, and the passage 208 in FIG. 2C. The cross-sections of node plate links 2/2, 218 and H elements 202, 204 are capacitively coupled to conductive elements. The inter-layer couplings 222, 224, and 226 and the intra-layer couplings 228, 230, 232, and 234 are represented by double-ended arrows. The spacing between conductive elements is exaggerated for illustration. The node plate element is formed on a first (lower) conductive layer M_NAnd on a second (upper) conductive layer M_N+1. In a specific embodiment, M_NWith M_N+1All are metal layers. Alternatively, one or both is a polysilicon or silicide layer.

FIG. 2E is a cross-section of a part of a four-layer integrated capacitor 250 according to another embodiment. On a third conductive layer M_N+2The pattern is essentially the same as the first conductive layer M_NThe pattern. In the same way, in a fourth conductive layer M_N+3The pattern is essentially the same as the second conductive layer M_N+1The pattern. An embodiment may include an odd number of layers or an even number of layers. The additional patterned conductive layer increases the specific capacitance of the integrated capacitor.

FIG. 3A is a plan view of a portion of a node plate array 300 using a pattern according to FIG. 2C. The nodal plate H elements are linked along columns and rows, and generally alternate with nodal plate links (compare Figure 1A). This pattern is repeated to form a nodal plate array (see, for example, reference symbol 312 in FIG. 3B). In a specific embodiment, the pattern is repeated along the columns and rows to form a substantially square-shaped node plate array, which provides substantially interchangeable first and second nodes.

FIG. 3B is a plan view of a part of an integrated capacitor 301 in an IC according to an embodiment. The bus bars 302, 304, 306, and 308 are the IC circuit nodes that connect the node plate arrays 312, 314 to the integrated capacitors. As described above with respect to the node plate array, the horizontal bus bars 306 and 308 are electrically connected to the row elements of the node plate array, and the vertical bus bars 302 and 304 are electrically connected to the column elements of the node plate array. The bus bars 302, 304, 306, and 308 are all formed on the same metal layer, and the bridges of the vias 310 are used. Alternatively, the bus bar connected to the first node is defined in a first metal layer, and the bus bar connected to the second node is defined in a second metal layer (compare: FIG. 1B). In a specific embodiment, each node plate array is surrounded by bus bars (see, for example, FIG. 1B). Alternatively, the plate array of nodes on the periphery of the integrated capacitor is not surrounded. In a specific embodiment, each node plate array has about twenty unit cells according to FIG. 2A.

4 is a plan view of a part of a one-node plate array 400 of integrated capacitors according to another embodiment. Compared with the H element 202 of FIG. 2A, the H element 402 of FIG. 4 includes side extensions 403, 404, 406, and 408, which link the side elements 405, 407 of the H element 402 to the node plate links 410, 411, 414, 415. The side extensions provide additional in-layer capacitance, such as shown by the double-ended arrow 416, and reduce the resistance of the node plate links by interconnecting the H element and the node plate links on the metal layer. As described with respect to FIG. 2A, the side elements extending along the X direction have the same node polarity as the links 410, 411, 414, 415 extending along the Y direction. An integrated capacitor according to FIG. 4 has a second or third metal layer that is rotated ninety degrees above or below the layer shown in FIG. 4. Alternatively, an integrated capacitor according to FIG. 4 has a different patterned metal layer above or below the layer of FIG. 4, such as the pattern shown in FIG. 2B.

Note: The type and number of layers described are only examples, and in some embodiments, other suitable layers are available, and any number of layers can be used. For example, the layers used may depend on the type and number of layers available in the process, and other configurations will be obvious to those skilled in the art. In summary, according to embodiments of the present invention, any suitable layer and any number of layers are applicable.

Figure 5 is a plan view of an FPGA 500 incorporating one or more integrated capacitors according to embodiments. The FPGA 500 includes a CMOS part in several functional blocks, such as RAM and logic, and is manufactured using a CMOS process. According to one or more embodiments of the present invention, one or more integrated capacitors 544 are included in any one of several functional blocks of the FPGA, such as an I/O section, transceiver, or power supply distribution network.

FPGA architecture includes a number of different programmable tiles, including: multi-gigabit transceiver (MGT; multi-gigabit transceiver) 501, configurable logic block (CLB; configurable logic block) 502, random memory Take memory block (BRAM; random access memory block) 503, input/output block (IOB; input/output block) 504, configuration and clock logic (CONFIG/CLOCK) 505, digital signal processing (DSP; digital signal processing) ) Block 506, dedicated input/output (I/O) block 507 (for example: configuration port and clock port) and other programmable logic 508, such as: digital clock manager, analog-to-digital converter, system monitoring logic and many more. Some FPGAs also include a dedicated processor (PROC) block 510.

In some FPGAs, each programmable tile includes a programmable interconnection element (INT; interconnect) 511, which has a standardized connection to and from each adjacent tile for a corresponding interconnection element. Therefore, the programmable interconnect components that work together implement the programmable interconnect structure for the FPGA shown in the figure. Programmable interconnection element (INT) 511 also includes connections to and from programmable logic elements within the same tile, as shown by the example included at the top of FIG. 5.

For example, a CLB 502 may include a configurable logic element (CLE; configurable logic element) 512 that can be programmed to implement user logic plus a single programmable interconnect element (INT) 511. In addition to one or more programmable interconnect components, a BRAM 503 may include a BRAM logic element (BRL; BRAM logic element) 513. Typically, the number of interconnecting elements incorporated in a tile depends on the height of the tile. In the depicted embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. In addition to an appropriate number of programmable interconnect elements, a DSP tile 506 may include a DSP logic element (DSPL; DSP logic element) 514. In addition to one instance of Programmable Interconnect Element (INT) 511, an IOB 504 may include, for example, two instances of input/output logic element (IOL; input/output logic element). element)515. As will be understood by those skilled in the art, for example, the actual I/O pads connected to the I/O logic element 515 are made of laminated metal on top of various illustrated logic blocks, and are typically unrestricted. In the area of the input/output logic element 515. In the depicted embodiment, the columnar area near the center of the chip (shown as shaded in FIG. 5) is used for configuration, clock, and other control logic.

Some FPGAs used in the architecture shown in FIG. 5 include additional logic blocks that disintegrate the regular columnar structure that constitutes most of the FPGA. The additional logic block can be a programmable block and/or exclusive logic. For example, the processor (PROC) block 510 shown in FIG. 5 spans several rows of CLB and BRAM.

Note: Figure 5 is only intended to illustrate an example FPGA architecture. The number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the type of logic blocks included in the rows, the relative size of the logic blocks, and the interconnection/logic included at the top of Figure 5 The implementation is purely exemplary. For example, an actual FPGA typically includes more than one adjacent row of CLBs regardless of where the CLBs appear, so as to facilitate the efficient implementation of user logic.

Although the foregoing describes exemplary embodiments according to one or more viewpoints of the present invention, other and further embodiments according to one or more viewpoints of the present invention can be designed without departing from its scope. The scope of the present invention is determined by the scope of subsequent patent applications Determined by its equivalent. The scope of the patent application for listing the steps does not imply any order of the steps.

<p>100. . . Integrated capacitor</p><p>102, 104, 106, 108, 110, 114. . . Node plate link</p><p>112. . . path</p><p>120. . . The part of the upper metal layer</p><p>122, 128, 130, 136, 138, 164. . . Node plate link</p><p>124, 126. . . End</p><p>132, 134. . . Side</p><p>150. . . Node Plate Array</p><p>152, 154, 156, 158. . . Bus bar</p><p>160, 162, 166, 168. . . path</p><p>200. . . Node Plate Array</p><p>201, 203. . . Patterned metal layer</p><p>202, 204. . . H element</p><p>205, 207. . . Side element</p><p>206, 208. . . path</p><p>209. . . Handover components</p><p>210, 211, 212, 214. . . Node plate link</p><p>213, 215. . . In-Layer Coupling</p><p>216, 220. . . Flat part</p><p>217. . . Link/end-to-side coupling</p><p>218. . . Node plate link/plate part</p><p>219. . . Double-ended arrow</p><p>221, 223. . . link</p><p>222, 224, 226. . . Layer coupling</p><p>228, 230, 232, 234. . . In-layer coupling</p><p>237. . . Node plate link</p><p>238. . . Flat part</p><p>250. . . Four-layer integrated capacitor</p><p>300. . . Node Plate Array</p><p>301. . . Integrated capacitor</p><p>302, 304, 306, 308. . . Bus bar</p><p>310. . . path</p><p>312, 314, 400. . . Node Plate Array</p><p>402. . . H element</p><p>403, 404, 406, 408. . . Side extension</p><p>405, 407. . . Side element</p><p>410, 411, 414, 415. . . Node plate link</p><p>416. . . Double-ended arrow</p><p>500. . . FPGA</p><p>501. . . Multi-gigabit transceiver</p><p>502. . . Configurable logic block</p><p>503. . . Random access memory block</p><p>504. . . Input/output block</p><p>505. . . Configuration and clock logic</p><p>506. . . Digital signal processing block</p><p>507. . . Dedicated input/output block</p><p>508. . . Other programmable logic</p><p>510. . . Dedicated processor block</p><p>511. . . Programmable Interconnect Components</p><p>512. . . Configurable logic element</p><p>513. . . BRAM logic element</p><p>514. . . DSP logic element</p><p>515. . . Input/output logic element</p><p>544. . . Integrated capacitor</p><p>A1, A2, A3, A4, A5. . . Row</p><p>B1, B2, B3. . . List</p><p>M_N, M_N+1, M_N+2, M_N+3. . . Conductive layer</p><p>P1, P2, P3, P4. . . area</p>

The accompanying drawings show exemplary embodiments according to one or more viewpoints of the present invention; however, the accompanying drawings should not be regarded as limiting the illustrated embodiment of the present invention, but only for explanation and understanding.

Fig. 1A is a plan view of a part of an integrated capacitor according to an embodiment of the present invention.

Figure 1B is a plan view of a one-node plate array of integrated capacitors according to one embodiment.

FIG. 1C is a plan view of a part of the upper metal layer of FIG. 1A.

Fig. 2A is a plan view of a part of a first patterned metal layer of a node plate array.

Fig. 2B is a plan view of a part of a second patterned metal layer of a node plate array.

Fig. 2C is a plan view of a part of a one-node plate array of integrated capacitors according to another embodiment.

Fig. 2D is a cross section of the nodal plate array of Fig. 2C, taken along the section line LL.

FIG. 2E is a cross-section of a part of a four-layer integrated capacitor 250 according to another embodiment.

Fig. 3A is a plan view of a part of a nodal plate array using a pattern according to Fig. 2C.

FIG. 3B is a plan view of a part of an integrated capacitor in an IC according to an embodiment.

4 is a plan view of a part of a one-node plate array 400 of integrated capacitors according to another embodiment.

Fig. 5 is a plan view of an FPGA incorporating an integrated capacitor according to an embodiment.