Memory device with bi-directional tracking of timing constraints

Memory device capable of bidirectionally tracking time sequence parameters

MEMORY DEVICE WITH BI-DIRECTIONAL TRACKING OF TIMING CONSTRAINTS

The present invention relates to a memory device capable of tracking timing parameters, in particular to a memory device capable of bidirectionally tracking dynamic random access memory timing parameters.

Random access memory (RAM) is a data storage device, which can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). ) Two types. In dynamic random access memory, each memory cell (cell) is composed of a pair of transistor-capacitors. The capacitors can be charged or uncharged. The transistor functions as a switch, enabling the peripheral control circuit to be able to Read or change the state of the capacitor. The energy stored in the capacitor can only be maintained for a few milliseconds, so it is necessary to periodically perform a refresh action to maintain the correct data.

When a specific command is received, the dynamic random access memory needs an execution time to complete the corresponding action, and then a waiting time is required to correctly receive the next command. The above-mentioned execution time and waiting time are called timing constraints, and the dynamic random access memory must comply with all the timing parameters defined in the relevant specifications during operation. However, in relation to the dynamic Many timing parameters are defined in the random access memory specification. Each timing parameter has a different limit time. In order to improve the performance of the controller, the prior art will set a different one-way tracking circuit for each timing parameter. , But a large number of one-way tracking circuits will increase design complexity and manufacturing costs. Another prior art applies the most relaxed timing parameters to all commands, so that a simple controller can be used, but the overall operating performance will be reduced.

The present invention provides a memory device capable of detecting timing parameters, which includes a dynamic random access memory, a first two-way tracking circuit and a second two-way tracking circuit. The dynamic random access memory includes a memory cell; a word line used to turn on or off the memory cell; a bit line used to write a first charge into the memory cell or receive the memory cell One of the second charge. The first two-way tracking circuit is used to track a first timing parameter, where the first timing parameter is related to the action of opening or closing the word line. The second bidirectional tracking circuit is used to track a second timing parameter, wherein the second timing parameter is related to turning on the bit line, turning off the bit line, and writing the first charge to the memory cell through the bit line Or read the second charge from the memory cell through the bit line.

FIG. 1 is a functional block diagram of a memory device 100 in the present invention. The memory device 100 includes a dynamic random access memory 10 and a character decoder (word line decoder) 20, a bit line decoder (bit line decoder) 30, a sense amplifier (sense amplifier) 40, a controller 50, a first bi-directional tracking circuit (bi-directional tracking circuit) TR1, and a The second bidirectional tracking circuit TR2.

The dynamic random access memory 10 includes a plurality of parallel word lines WL, a plurality of parallel bit lines BL, and a plurality of memory cells CL. The word line WL and the bit line BL are vertically interlaced with each other, and a plurality of memory cells are arranged at the intersection of the corresponding word line WL and the bit line BL to form a memory array. In the embodiment of the present invention, each memory cell includes a capacitor and a transistor. The first end of the transistor is coupled to a corresponding bit line, the second end of the transistor is coupled to a corresponding word line, and the capacitor is coupled to the third end of the transistor and a bias voltage between.

The controller 50 can provide control signals necessary for the operation of the dynamic random access memory 10, such as a row address strobe signal RAS, a row address strobe signal CAS, a write-in address A write enable (WE) signal, an output enable (OE) signal, and a data signal DATA, etc. The character decoder 20 can select the corresponding character line according to the column address selection communication number RAS, and then turn on each column of memory cells in sequence. The bit decoder 30 can select the corresponding bit line by selecting the communication number CAS according to the incoming row address, so that the sense amplifier 40 can write the data signal DATA into the corresponding according to the write enable signal WE and output enable OE The memory unit or read the data signal DATA of the corresponding memory unit memory.

As is well known by those with ordinary knowledge in the relevant field, the control commands of the dynamic random access memory 10 include active, precharge, refresh, mode register set (MRS), Self-refresh entry (SRE), power down entry (power down entry), ZQ calibration long/ZQ calibration short (ZQCL/ZQCS), etc., when issuing control commands, the relevant timing parameters must be met .

The main timing parameters of the dynamic random access memory 10 include the column address precharge time (RAS precharge time) T_RP, Column address to row address delay time (RAS to CAS delay time) T_RCD, Row cycle time (row cycle time) T_RC, Write recovery time (write recovery time) T_WR, Column address access time (RAS access time) T_RAS, And overdrive time (overdrive time) T_ODWait. After a precharge command is issued in a bank, at least the column address precharge time T is required_RPOnly allow a start command to be issued in the same memory bank. After selecting the communication number RAS based on the column address to find a specific address, at least the interval from the column address to the row address delay time T is required_RCD,It is allowed to select the communication number CAS based on the row address to find another specific address. After issuing an activation command to a memory bank, at least the interval of the row address access time (RAS access time) T is required_RAS, It is allowed to issue a precharge command to the same memory bank. After issuing a write command to a memory bank, at least the interval write recovery time T is required_WR, It is allowed to issue a precharge command to the same memory bank. Overdrive time (overdrive time) T_ODRepresents the length of time that the memory cell is overcharged at a higher potential than the data signal DATA.

The first two-way tracking circuit TR1 of the present invention can track the timing parameters related to the opening of the word line (such as the row address delay time T_RCD) Or turn off the timing parameters of the word line (e.g. column address precharge time T_RP). The second two-way tracking circuit TR2 of the present invention can track the timing parameters related to the precharge bit line (for example, the write recovery time T_WR), timing parameters related to sensing bit lines (e.g. overcharge time T_OD), timing parameters related to writing memory cells from bit lines (e.g. column address access time T_RASAnd write reply time T_WR), and the timing parameters related to reading the memory cell to the bit line (for example, the column address to the row address delay time T_RCD )。

Figure 2 is a schematic diagram of the first two-way tracking circuit TR1 in an embodiment of the present invention. The first bidirectional tracking circuit TR1 includes a tracking word line WL', switches SW1 and SW2, input terminals IN1 and IN2, and output terminals OUT1 and OUT2. The first terminal of the switch SW1 is coupled to a bias voltage VPP1, the second terminal is coupled to the output terminal OUT1, and the control terminal is coupled to the input terminal IN1. The first terminal of the switch SW2 is coupled to a bias voltage VSS, the second terminal is coupled to the output terminal OUT2, and the control terminal is coupled to the input terminal IN2. The switch SW1 and the switch SW2 can be complementary transistors, for example, the switch SW1 can be a P-type gold P-type metal-oxide-semiconductor field-effect transistor (PMOS), and switch SW2 can be an N-type metal-oxide-semiconductor field-effect transistor (PMOS). NMOS). The potential of the bias voltage VPP1 is higher than the potential of the bias voltage VSS.

When the input terminal IN1 receives the input signal T_{RCD_IN}When the switch SW1 will be turned on, the tracking word line WL' will be turned on by the bias voltage VPP1. At this time, the first bidirectional tracking circuit TR1 can provide the column address to row address delay time T at the output terminal OUT2._RCDThe output signal T_{RCD_OUT}. When the input terminal IN2 receives the input signal T_{RP_IN}At this time, the switch SW2 will be turned on, and the tracking word line WL' will be turned off by the bias voltage VSS. At this time, the first bidirectional tracking circuit TR1 can provide the column address precharge time T at the output terminal OUT1._RPThe output signal T_{RP_OUT}. Therefore, the controller 50 can be based on the output signal T_{RCD_OUT}To track the column address to row address delay time T_RCDOr according to the output signal T_{RP_OUT}To track the column address precharge time T_RP 。

FIG. 3 is a schematic diagram of the second bidirectional tracking circuit TR2 in an embodiment of the present invention. The second bidirectional tracking circuit TR2 includes a tracking bit line BL', a tracking memory cell CL', an isolation circuit ISO, switches SW3 and SW4, input terminals IN3 and IN4, and output terminals OUT3~OUT5. The first terminal of the switch SW3 is coupled to a bias voltage VPP2, the second terminal is coupled to the output terminal OUT3, and the control terminal is coupled to the input terminal IN3. The first terminal of the switch SW4 is coupled to the bias voltage VSS, the second terminal is coupled to the output terminal OUT5, and the control terminal is coupled to the input terminal IN4. The tracking bit line BL' and the isolation circuit ISO are coupled in series between the output terminal OUT3 and the output terminal OUT4, and the tracking memory cell CL' is coupled between the output terminal OUT4 and the output terminal OUT5. The switch SW3 and the switch SW4 can be complementary transistors. For example, the switch SW3 can be a P-type MOSFET, and the switch SW4 can be an N-type MOSFET. The potential of the bias voltage VPP2 is higher than the potential of the bias voltage VSS.

When the input terminal IN3 receives the input signal T_{RAS_IN}Or input signal T_{WR_IN}When the switch SW3 is turned on, the charge of the bias voltage VPP2 can be transferred from the tracking bit line BL' to the tracking memory cell CL'. At this time, the second bidirectional tracking circuit TR2 can provide the column address access time at the output terminal OUT5. T_RASThe output signal T_{RAS_OUT}Or related to write reply time T_WRThe output signal T_{WR_OUT}. Therefore, the controller 50 can be based on the output signal T_{RAS_OUT}To track the row address access time T_RAS, Or according to the output signal T_{WR_OUT}To track the write reply time T_WR 。

When the input terminal IN3 receives the input signal T_{RP_IN}When the switch SW3 is turned on, the charge of the bias voltage VPP2 can precharge the tracking bit line BL'. At this time, the second bidirectional tracking circuit TR2 can provide the column address precharge time T at the output terminal OUT4._RPThe output signal T_{RP_OUT}. Therefore, the controller 50 can be based on the output signal T_{RP_OUT}To track the column address precharge time T_RP 。

When the input terminal IN3 receives the input signal T_{OD_IN}When the switch SW3 will When turned on, the charge of the bias voltage VPP2 can overcharge the tracking bit line BL'. At this time, the second bidirectional tracking circuit TR2 can provide an overcharge time T at the output terminal OUT4._ODThe output signal T_{OD_OUT}. Therefore, the controller 50 can be based on the output signal T_ODTo track the overcharge time T_OD 。

When the input terminal IN4 receives the input signal T_{RCD_IN}When the switch SW4 is turned on, the charge of the bias voltage VSS can be transferred from the tracking memory cell CL' to the tracking bit line BL. At this time, the second bidirectional tracking circuit TR2 can provide the column address to the row address at the output terminal OUT3. Delay time T_RCDThe output signal T_{RCD_OUT}. Therefore, the controller 50 can be based on the output signal T_RCDTo track the column address to row address delay time T_RCD 。

In the embodiment of the present invention, the element line width of the first bidirectional tracking circuit TR1 and the second bidirectional tracking circuit TR may be greater than the element line width of the dynamic random access memory 10. For example, the line width of the tracking word line WL' can be greater than the line width of the word line WL, the line width of the tracking bit line BL' can be greater than the line width of the bit line BL, and the line width of the tracking memory cell CL' It can be larger than the line width of the memory cell CL.

In the memory device 100 of the present invention, the first two-way tracking circuit TR1 can track the timing parameters related to the opening or closing of the word line, and the second two-way tracking circuit TR2 can track the timing parameters related to the precharge bit Line timing parameters, timing parameters related to sensing bit lines, timing parameters related to writing memory cells from bit lines, and related to reading memory cells to bit lines The timing parameters. Therefore, the present invention only needs to set up two two-way tracking circuits, which can track all timing parameters to improve the overall operating efficiency.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

<p>10Dynamic random access memory</p><p>20Character Decoder</p><p>30Bit Decoder</p><p>40Induction amplifier</p><p>50controller</p><p>100Memory device</p><p>TR1The first two-way tracking circuit</p><p>TR2The second two-way tracking circuit</p><p>WLCharacter line</p><p>WL'Tracing character lines</p><p>BLBit Line</p><p>BL'Tracking bit line</p><p>CLMemory Unit</p><p>CL'Tracking memory unit</p><p>ISOIsolated circuit</p><p>VSS, VPP1, VPP2Bias</p>

Figure 1 is a functional block diagram of a memory device in the present invention.

Figures 2 and 3 are schematic diagrams of the two-way tracking circuit in the embodiment of the present invention.