Semiconductor device

Semiconductor device

The present invention relates to a semiconductor device, and particularly to a logic configuration method that can realize high-efficiency access between three-dimensional stacked wafers.

When you want to improve the performance of the information processing device or the processor or memory set in the information processing device, the integration of the semiconductor device used in the information processing device, the processor, or the memory can be improved while data transmission can be carried out with good efficiency. The logical way is important. Regarding the improvement of the accumulation degree of semiconductor devices, in recent years, the so-called three-dimensional accumulation technology has been used to increase the accumulation degree in the vertical direction by laminating a plurality of semiconductor chips and connecting each semiconductor chip through the through hole of the interface electrode. It is proposed. According to this rule, there is no need to greatly increase the size of semiconductor chip units, and while ensuring high yields, it is possible to achieve a further increase in accumulation.

Regarding such a three-dimensional build-up technology, there is a semiconductor memory device disclosed in Patent Document 1, for example. In the semiconductor memory device disclosed in Patent Document 1, a plurality of memory chips are mounted on an interface chip stack, and a latch circuit is respectively provided on the via path of each memory chip, by using the latch circuit The pipeline (pipiline) action to carry out the data transmission.

Patent Document 1: Japanese Patent Application Publication No. 2006-330974

<p>FIG. 2 is a schematic diagram showing an example of a logic structure method using a three-dimensional build-up layer in a semiconductor device under examination as the premise of the present invention. The semiconductor device in FIG. 2 reflects the technology of Patent Document 1. A plurality of memory chips 100, 200, 300, and 400 are laminated in three dimensions on the I/O chip 10 used to control the input and output of memory data. It constitutes an example of a large-capacity memory device. As shown in this example, when a plurality of memory chips are stacked to form a large-capacity memory device, a method of distributing and distributing data equally to each memory chip, such as using an interleave method, is usually adopted. For example, in FIG. 2, a method of distributing and distributing data in 8-byte units to 4 memory chips every 2 bytes can be considered.</p><p>The I/O chip 10 is laminated on the bottom of the large-capacity memory device, and is composed of: a read buffer 21 that temporarily stores read data from the memory; and temporarily stores write data to the memory. Into the buffer 22; and the transfer control logic 30, used to send a transfer control signal 35 to control the data transfer of each memory chip.</p><p>In addition, the memory chips 100, 200, 300, and 400 are sequentially applied to the three-dimensional build-up layer on the upper portion of the I/O chip 10. Taking the memory chip 100 as an example, the memory chip is composed of the following: the memory core 101 for storing memory data and the memory core control logic 102 for the control and the fetching and retention of data transmission; FT selection The device 121 selects the read data from the memory core 101 or the upper layer chip according to the FT (fetch) selection signal 131; the FT buffer 111 is used to temporarily store the output of the FT selector 121; ST (storage) The buffer 112 is used to temporarily store the write data from the lower-level chip; the ST selector 122, according to the ST selection signal 132, selects the transfer target of the write data to the memory core 101 or the upper-level chip for the output ; And the I/O control logic 130, which controls the FT selection signal 131 and the ST selection signal 132 according to the transmission control signal 35. In addition, other memory chips 200, 300, and 400 also have the same structure.</p><p>FIG. 3 shows the sequence of the read data transfer process in the memory of the semiconductor device shown in FIG. 2. FIG. At time t0, the I/O chip 10 sends a memory core read request to the memory chips 100, 200, 300, 400 (hereinafter referred to as the memory chip group). The memory core parts 101, 201, 301, and 401 that have received this output the read data DT1, DT2, DT3, and DT4, respectively, at time t1.</p><p>In addition, the transfer control logic 30 in the I/O chip 10 sends a transfer control signal 35 to the memory chip group at timing t1 so that the read data DT1 to DT4 are transferred to the FT buffers 111, 211, 311, 411 (hereinafter referred to as the FT buffer group) method to control the I/O control logic 130, 230, 330, 430 (hereinafter referred to as the I/O control logic group). The I/O control logic group that accepts this uses the FT selection signals 131, 231, 331, 431 to control the FT selectors 121, 221, 321, 421 (hereinafter referred to as the FT selector group), and the data will be read out at timing t2 DT1 ~ DT4 are sent to the FT buffer group.</p><p>After that, the transfer control logic 30, in order to sequentially transfer the data of the FT buffer group to the read buffer 21, at timing t2, the transfer control signal 35 controls the I/O control logic group in the memory chip group to Make the FT selector group select the transmission data from the upper layer. In this way, at time t3, the read data from the FT buffer 411 is sent to the FT buffer 311 through a pipeline, and the read data from the FT buffer 311 is sent to the FT buffer 211, and the FT buffer is The read data of the device 211 is sent to the FT buffer 111, and the read data of the FT buffer 111 is sent to the part for storing DT1 in the read buffer 21.</p><p>In the same way below, the pipeline transfer is repeated. At timing t3~t5, the transfer control logic 30 controls the FT selector group so that the transfer data (DT2~DT4) are sent to the storage and readout respectively. DT2-DT4 in the buffer 21. In this way, the last read data DT1 to DT4 will all be transferred to the read buffer 21 at timing t6.</p><p>Among them, when the read data DT1 to DT4 want to transfer the next read data to the read buffer 21 at the fastest timing, the transfer control logic 30 sends a transfer control signal 35 to the memory chip group at timing t4 to enable the read The output data DT11~DT14 are sent to the FT buffer group to control the I/O control logic group. The I/O control logic group accepts this and controls the FT selector in the same way as the above description, and transmits the read data DT11 to DT14 to the FT buffer group at time t6. The reason why the above sequence is the fastest is that in the previous transmission of the read data DT1 to DT4, the FT buffer 111 is used until the timing t5, and the read data DT11 to DT14 can be transmitted to the FT buffer 111. After timing t6.</p><p>Then, the transfer control logic 30 in the I/O chip 10 can sequentially transfer the data of the FT buffer group to the readout buffer 21, and at timing t6, the transfer control signal 35 is used to transfer the data in the memory chip group. The I/O control logic group is controlled by the way that the FT selector group selects the transmission data from the upper layer. In this way, the read data from the FT buffer 411 is sent to the FT buffer 311 in a pipeline, the read data from the FT buffer 311 is sent to the FT buffer 211, and the read data from the FT buffer 211 is sent to The FT buffer 111 transmits the read data of the FT buffer 111 to the part of the read buffer 21 for storing DT11.</p><p>The pipeline transmission is repeated in the following, and at timing t7~t9, the transmission data (DT12~DT14) are respectively transmitted to the storage and read buffer 21 by controlling the FT selector group of the transmission control logic 30 Part of DT12~DT14. In this way, the read data DT11 to DT14 will eventually be all transferred to the read buffer 21 at timing t10.</p><p>FIG. 4 is a sequence diagram showing the flow of write data transfer of the memory in the semiconductor device of FIG. 2. FIG. In order to transfer the write data DT1 to DT4 prepared by the write buffer 22 to the memory chip group, the transfer control logic 30 sends a transfer control signal 35 to the memory chip group at time t1 so that the write data DT4 is sent to The ST buffer 112 is used to control the I/O control logic group. The I/O control logic group accepts it and uses ST selection signals 132, 232, 332, 432 to control ST selectors 122, 222, 322, 422 (hereinafter referred to as ST selector group), and write data DT4 at time t2 Transfer to the ST buffer 112.</p><p>After that, the transfer control logic 30 transfers the write data DT4 in the ST buffer 112 to the ST buffer 212 in the upper memory chip 200, and transfers the write data DT3 in the write buffer 22 to the ST The buffer 112 controls the I/O control logic group at time t2. The I/O control logic group is accepted to control the ST selector group, and the write data DT4 is sent to the ST buffer 212 and the write data DT3 is sent to the ST buffer 112 at timing t3, respectively.</p><p>The same control is repeated below, and the write data DT1 to DT4 are respectively sent to the memory chip group at time t5. Finally, at time t5, the I/O chip 10 sends a memory core write request to the memory chip group. The memory cores 101, 201, 301, and 401 that receive it write the write data DT1, DT2, DT3, and DT4 at time t6, respectively.</p><p>Here, for the written data DT1 to DT4, when the next written data DT1 to DT4 are to be transmitted to the ST buffers 112, 212, 312, 412 (hereinafter referred to as ST buffer group) at the fastest timing, the transmission control logic 30 At time t5, the transfer control signal 35 is sent to the memory chip group, so that the write data DT14 is transferred to the ST buffer 112 to control the input/output control logic group. The I/O control logic group is accepted to control the ST selector group, and the write data DT14 is sent to the ST buffer 112 at timing t6, respectively. The reason why the above timing is the fastest is that in the previous transmission of the write data DT1 to DT4, the ST buffer 112 is used until timing t5, and the write data DT11 to DT14 can be transmitted to the ST buffer 112. After timing t6.</p><p>After that, the transfer control logic 30 transfers the write data DT14 in the ST buffer 112 to the ST buffer 212 in the upper memory chip 200, and transfers the write data DT13 in the write buffer 22 to the ST The buffer 112 controls the I/O control logic group at time t6. The I/O control logic group is accepted to control the ST selector group, and the write data DT14 is sent to the ST buffer 212 and the write data DT13 is sent to the ST buffer 112 at timing t7, respectively.</p><p>The same control is repeated below, and the write data DT11 to DT14 are respectively sent to the memory chip group at time t9. Finally, at time t9, the I/O chip 10 sends a memory core write request to the memory chip group. The memory cores 101, 201, 301, and 401 that receive it write the write data DT11, DT12, DT13, and DT14 at time t10, respectively.</p><p>However, as shown in the description using FIG. 3, when the semiconductor device of FIG. 2 intends to continuously transfer the read data to the read buffer, the data will be read the next time relative to the transfer completion timing t6 of the read data DT1 to DT4. After the transmission of DT11 to DT14 is completed, it is time t10 even in the fastest case. Therefore, the read data can only be obtained at each of the 4 timings (4 cycles). In addition, similarly, as shown in the description using FIG. 4, when the write data is to be continuously written into the memory core portion, the data DT11 to DT11 to DT11 to DT11 to DT11 to DT11 are written in the next time relative to the write completion timing t6 of the write data DT1 to DT4. After the writing of DT14 is completed, it becomes the timing t10 even in the fastest case. Therefore, the writing of the written data can only be performed at each of the 4 timings (4 cycles).</p><p>As explained above, in the conventional logic structure method of transferring data through pipelines, when you want to continuously process the read data, or when you want to continuously process the written data, the processing can only be performed in each of the 4 cycles. The entire memory device There is a problem that the transmission efficiency (through-put) cannot be improved. In this example, the number of stacked wafers is 4, so the processing efficiency is limited to each of the four cycles. However, when the number of stacked wafers increases again, the processing efficiency will be lowered corresponding to the number of wafers.</p><p>One of the objects of the present invention is to provide a semiconductor device capable of realizing high transmission efficiency in data transmission between the above-mentioned three-dimensional laminated wafers. The above and other objectives and novel features of the present invention can be understood from the description of this specification and the attached drawings.</p>

<p>The outline of a representative embodiment of the present invention is briefly described as follows.</p><p>The semiconductor device of this embodiment replaces the FT buffer configured as a pipeline in the prior art, and is replaced with a selector provided in each chip. The selector is used to select: transfer data from the FT buffer or Either the upper or lower layer transmits data, so that the output of the selector becomes the input of the selector in the upper or lower layer chip, so that the selector in each chip becomes a subsidiary connector. Or, instead of the ST buffer configured as a pipeline, a branch selector is set in each chip. The branch selector is used to select: the transfer path of the ST buffer, or the transfer path of the upper or lower layer. One of them is such that the transmission path of the branch selector to the upper or lower layer becomes the input of the branch selector in the upper or lower layer chip, so that the branch selector in each chip becomes a subsidiary connector.</p><p>In this way, the FT buffers in each chip can independently transmit the read buffers in the I/O chip. In addition, the write buffers in the I/O chip can also be independently transmitted to the read buffers in each chip. The ST buffer is transferred. Therefore, the transmission path formed by the selectors or branch selectors that are attached to each other can be compared to the circuit parts (such as memory circuits, arithmetic circuits, or input and output buffers) that perform specific actions in each chip. The operation clock of the ST buffer, FT buffer, etc.) of the device operates synchronously with an independent and higher-speed clock, which can achieve high transmission efficiency.</p>

The following describes the embodiments of the present invention based on the drawings. In addition, the same components in all the drawings in the description of the embodiment are given the same reference numerals in principle, and repeated descriptions are omitted.

FIG. 1 shows a schematic diagram of an example of the structure of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a plurality of memory chips 100, 200, 300, and 400 are an example in which an I/O chip 10 that controls the input and output of memory data is applied to a three-dimensional layer to form a large-capacity memory device. As shown in this example, when multiple memory chips are stacked to form a large-capacity memory device, an interleaving method is usually used to distribute data evenly and arrange them on each memory chip. For example, in this embodiment, a method of distributing 8-byte data in 2-byte units and distributing them on 4 memory chips can be considered.

The I/O chip 10 is composed of: a read buffer 21 that is laminated on the bottom of the large-capacity memory device to temporarily store read data from the memory; temporarily stores write data to the memory The buffer 22; and the transfer control logic 30 are used to send a transfer control signal 35 to control the data transfer of each memory chip.

In addition, the memory chips 100, 200, 300, and 400 are sequentially applied to the three-dimensional build-up layer on the upper portion of the I/O chip 10. Taking the memory chip 100 as an example, the memory chip 100 is composed of the following: a memory core 101 for storing memory data and its control and the memory core control logic 102 for fetching and holding data transmission; FT The selector 121 selects the read data from the FT buffer 111 or the upper layer chip according to the FT (capture) selection signal 131, and transmits its output to the lower layer chip; the ST selector 122, according to the ST selection signal 132, For the transfer target of the data from the lower layer chip, one of the ST buffer 112 or the upper layer chip is selected; and the I/O control logic 130 controls the FT selection signal 131 and the ST selection signal 132 according to the transmission control signal 35. In addition, other memory chips 200, 300, and 400 also have the same structure.

FIG. 5 shows a schematic diagram of a configuration example including through vias in the semiconductor device of FIG. 1 taking a part of the wafer as an example. Taking the read path of the memory chip 100 as an example, the read data from the upper layer chip through the through via 141r is connected to one of the inputs of the FT selector 121. The read data output by the FT selector 121 is transmitted to the lower layer wafer through the through via 141t. In addition, taking the writing path of the memory chip 100 as an example, the writing data from the lower layer chip through the through via 142r is transmitted to the ST selector 122, and one of the outputs of the ST selector 122 is through The through via 142t is connected to the upper layer wafer. In addition, taking the transfer control path of the memory chip 100 as an example, the transfer control signal 35 that is transferred from the lower layer chip through the through via 152r is distributed to the I/O control logic 130 and The transmission path to the upper layer, that is, the through hole 152t.

These through-holes 141r, 141t, or 142r, 142t, 152r, and 152t are independent of each other and form a logical structure between the two through-holes. In addition, the memory chip 200 is also provided with through vias 241r, 241t, 242r, 242t, 252r, 252t in the same way as the through vias 141r, 141t, 142r, 142t, 152r, and 152t in the memory chip 100.

On the other hand, the through vias 41r, 42t, and 52t of the I/O chip 10 are respectively connected to the input of the read buffer 21, the output of the write buffer 22, and the output of the control logic 30. When the memory chips 100, 200 and the I/O chip 10 are stacked, the through vias 141t and 41r, 142r and 42t, 152r and 52t, 141r and 241t, 142t and 242r, 152t and 252r are connected, respectively. In this way, a large-capacity memory device is constructed.

FIG. 6 shows a sequence diagram of the flow of read data transfer of the memory in the semiconductor device of FIG. 1. FIG. The clock supplied to the I/O chip 10 (I/O chip clock) is 4 times faster than the clock supplied to the memory chip group. The timings are respectively t0, t1, t2, Express. In addition, although the clocks (memory chip clocks) supplied to the memory chips 100, 200, 300, and 400 are of the same frequency, they have independent and different phases. Their timings are T10, T11, and T11, respectively. , T20, T21, , T30, T31, T40, T41, said. The timing relationship between each clock t0, t1, t2, and T10, T11, , T20, T21, , T30, T31, T40, T41, is as As shown in FIG. 6, the phases are adjusted by making t0 and T10, t1 and T20, t2 and T30, and t3 and T40 into the same timing, respectively.

Here, when the logic in each memory chip is the memory chip 100 as an example, the memory core 101, the memory core control logic 102, the FT buffer 111 and the ST buffer 112 are the same as the memory chip clock T10, T11, Synchronous action, the rest of the logic, namely FT selector 121, ST selector 122, FT selection signal 131, ST selection signal 132, and I/O control logic 130, and I/O chip clock t0, t1 ,Synchronous action. This is because the FT selector 121, ST selector 122, FT selection signal 131, ST selection signal 132 and I/O control logic 130 do not have internal flip-flops that require a clock, even if they are not synchronized with the clock of the memory chip You can also move.

In FIG. 6, first, at time t7, the I/O chip 10 sends a memory core read request to the memory chip group. In order to set all memory chip groups to be trusted, the memory core read request is continuously sent out during the period from time t7 to time t10. Receiving the request, the memory cores 101, 201, 301, and 401 are respectively the memory chip clocks that operate on the memory core after the memory core read request is sent, with the shortest timing (for example, In the case of the memory core unit 101, it is time sequence T12, and in the case of the memory core unit 201, it is time sequence T22, ) respectively output the read data DT1, DT2, DT3, DT4. The read data DT1, DT2, DT3, DT4 are respectively at the next time sequence, such as time T13 in the case of DT1, and time T23, in the case of DT2, and are transferred to the FT buffer 111, of each memory chip 211, 311, 411.

After that, the transfer control logic 30, at timing t12, controls the FT selection signal 131 for the I/O control logic 130 in the memory chip 100 via the transfer control signal 35 so that the FT selector 121 selects from the FT buffer 111 Send data. In this way, the read data of the FT buffer 111 will be transferred to the part of the read buffer 21 where DT1 is stored. After that, the transfer control logic 30 controls the FT selection signal 131 via the transfer control signal 35 at timing t13, so that the FT selector 121 selects the transfer data from the upper layer chip. In addition, for the memory chip 200 The I/O control logic 230 controls the FT selection signal 231 so that the FT selector 221 selects the transmission data from the FT buffer 211. In this way, the read data of the FT buffer 211 will be transferred to the part of the read buffer 21 where DT2 is stored.

In the following, by the same control as above, DT3 at timing t14 and DT4 at timing t15 are respectively transmitted to the parts storing DT3 and DT4 in the readout buffer 21.

When the read data DT1 to DT4 want to transfer the next read data to the read buffer 21 at the fastest timing, the I/O chip 10 sends a memory core read request to the memory chip group at timing t11. When it is desired to set all the memory chip groups to be trusted, the memory core read request will continue to be sent out during the period from time t11 to time t14. Receiving the request, the memory cores 101, 201, 301, and 401 are respectively the memory chip clocks that operate on the memory core after the memory core read request is sent, with the shortest timing (for example, In the case of the memory core unit 101, it is time sequence T13, and in the case of the memory core unit 201, it is time sequence T23, ) respectively output the read data DT11, DT12, DT13, and DT14. The read data DT11, DT12, DT13, and DT14 are respectively at the next timing, such as timing T14 in the case of DT11, and timing T24, in the case of DT12, and are transferred to the FT buffer 111, of each memory chip 211, 311, 411.

The reason why the above sequence is the fastest is that in the previous transfer of the read data DT1, the FT buffer 111 is used until the timing T13, and the read data DT11 can be transferred to the FT buffer 111 after the timing T14. The other read data DT12, DT13, and DT14 are the same, and can be sent to the FT buffers 211, 311, and 411 after timing T24, T34, and T44.

After that, the transfer control logic 30, at timing t16, controls the FT selection signal 131 for the I/O control logic 130 in the memory chip 100 via the transfer control signal 35 so that the FT selector 121 selects from the FT buffer 111 Send data. In this case, the read data of the FT buffer 111 will be transferred to the part of the read buffer 21 where DT11 is stored. After that, the transfer control logic 30 controls the FT selection signal 131 via the transfer control signal 35 at timing t17, so that the FT selector 121 selects the transfer data from the upper layer chip. In addition, for the memory chip 200 The I/O control logic 230 controls the FT selection signal 231 so that the FT selector 221 selects the transmission data from the FT buffer 211. In this way, the read data of the FT buffer 211 will be transferred to the part of the read buffer 21 where DT12 is stored.

Hereinafter, by the same control as above, DT13 at timing t18 and DT14 at timing t19 are respectively transmitted to the parts storing DT13 and DT14 in the readout buffer 21.

According to the examples in Figures 1 and 6 described above, in the read buffer, the read data sequence of the memory chip group is ready, the first read data DT1 ~ DT4 are time t15, and the next read data DT11 ~ DT14 It is timing t19. Considering that t0, t1, t2, of the I/O chip clock are 4 times the high-speed operation of each memory chip clock, when viewed from each memory chip clock, it means that the read data is The interval of 1 sequence (1 cycle) is prepared. Therefore, when the configuration example of FIG. 1 and the configuration example of FIG. 2 are set to the same speed of the memory chip clock, compared with the configuration example of FIG. 2, the configuration example of FIG. 1 can achieve 4 times the efficiency.

FIG. 7 shows a sequence diagram of the flow of the write data transfer of the memory in the semiconductor device of FIG. 1. FIG. The clock supplied to the I/O chip 10 (I/O chip clock) is 4 times the speed of the clock supplied to the memory chip group, and its timing is t0, t1, t2, Express. In addition, although the clocks (memory chip clocks) supplied to the memory chips 100, 200, 300, and 400 are of the same frequency, they have independent and different phases. Their timings are T10, T11, and T11, respectively. , T20, T21, , T30, T31, T40, T41, said. The timing relationship between each clock t0, t1, t2, and T10, T11, , T20, T21, , T30, T31, T40, T41, is as follows As shown in FIG. 7, the phases are adjusted by making t0 and T10, t1 and T20, t2 and T30, and t3 and T40 into the same timing, respectively.

Here, when the logic in each memory chip is the memory chip 100 as an example, the memory core 101, the memory core control logic 102, the FT buffer 111 and the ST buffer 112 are the same as the memory chip clock T10, T11, Synchronous action, the rest of the logic, namely FT selector 121, ST selector 122, FT selection signal 131, ST selection signal 132, and I/O control logic 130, and I/O chip clock t0, t1 ,Synchronous action. This is because the FT selector 121, ST selector 122, FT selection signal 131, ST selection signal 132 and I/O control logic 130 do not have internal flip-flops that require a clock, even if they are not synchronized with the clock of the memory chip You can also move.

In FIG. 7, firstly, to transfer the write data prepared by the write buffer 22 to the ST buffer group, the transfer control logic 30 is set at the timing t7, and the transfer control signal 35 is directed to the input/output in the memory chip 100 The control logic 130 controls the ST selection signal 132 so that the ST selector 122 sends the transmission data to the ST buffer 112. In this case, the write data DT1 in the read buffer 21 will be transferred to the ST buffer 112. After that, the transfer control logic 30 controls the ST selection signal 132 via the transfer control signal 35 at timing t8, so that the ST selector 122 sends the transfer data to the upper layer chip, and in addition, for the output in the memory chip 200 The input control logic 230 controls the ST selection signal 232 so that the ST selector 222 sends the transmission data to the ST buffer 212. In this case, the DT2 written in the buffer 22 will be transferred to the ST buffer 212. Hereinafter, by the same control as above, DT3 is transmitted to the ST buffers 312 and 412 at timing t9 and DT4 at timing t10, respectively.

Finally, at time t11, the I/O chip 10 sends a memory core write request to the memory chip group. In order to set all the memory chip groups to be trusted, the memory core write request is continuously sent out during the period from time t11 to time t14. Receiving the request, the memory cores 101, 201, 301, and 401 are respectively the memory chip clocks that operate on the memory core after the memory core write request is sent, with the shortest timing (for example, In the case of the memory core 101, it is timing T13, and in the case of the memory core 201, it is timing T23, ) The write data DT1, DT2, and 412 sent to the ST buffers 112, 212, 312, and 412, respectively DT3 and DT4 are written into the memory cores 101, 201, 301, and 401.

For the write data DT1 to DT4, when the next write data DT1 to DT14 are to be transferred to the memory chip group at the fastest timing, the transfer control logic 30 is set at the timing t11, and the transfer control signal 35 is directed to the memory chip 100 The I/O control logic 130 controls the ST selection signal 132 so that the ST selector 122 sends transmission data to the ST buffer 112. In this case, the write data DT11 in the write buffer 22 will be transferred to the ST buffer 112. The reason why the above sequence is the fastest is that in the previous transfer of write data DT1 to DT4, the write buffer 22 is used until timing t10, and the next write data DT11 to DT14 can be transferred to write The buffer 22 is after the timing t11.

After that, the transfer control logic 30 controls the ST selection signal 132 via the transfer control signal 35 at timing t12, so that the ST selector 122 sends the transfer data to the upper layer chip, and in addition, for the output in the memory chip 200 The input control logic 230 controls the ST selection signal 232 so that the ST selector 222 sends the transmission data to the ST buffer 212. In this case, the DT12 written in the buffer 22 will be transferred to the ST buffer 212.

Hereinafter, by the same control as above, DT13 is transmitted to the ST buffers 312 and 412 at timing t13 and DT14 at timing t14, respectively.

Finally, at time t15, the I/O chip 10 sends a memory core write request to the memory chip group. In order to set all memory chip groups to be trusted, the memory core write request is continuously sent out during the period from time t15 to time t18. Receiving the request, the memory cores 101, 201, 301, and 401 are respectively the memory chip clocks that operate on the memory core after the memory core write request is sent, with the shortest timing (for example, In the case of the memory core part 101, it is time sequence T14, and in the case of the memory core part 201, it is time sequence T24, ) will send the write data DT11, DT12, and DT12 to the ST buffer 112, 212, 312, and 412, respectively DT13 and DT14 are written into the memory cores 101, 201, 301, and 401.

According to the examples of FIGS. 1 and 7 described above, in the ST buffer group, the timing of writing data is ready, the first writing data DT1 to DT4 are timing t10, and the next writing data DT11 to DT14 are timing t14. Considering that t0, t1, t2, of the I/O chip clock are 4 times the high-speed operation of each memory chip clock, when viewed from each memory chip clock, it means that the written data is The interval of 1 sequence (1 cycle) is prepared. Therefore, when the configuration example of FIG. 1 and the configuration example of FIG. 2 are set to the same speed of the memory chip clock, compared with the configuration example of FIG. 2, the configuration example of FIG. 1 can achieve 4 times the efficiency.

In addition, here, the memory chip clocks of the memory chips 100, 200, 300, and 400 are made to have a phase difference. If each memory chip is a ROM (read-only memory), there is no need to have a phase difference. That is, in synchronization with the same clock signal, each memory chip outputs the read data at the same time, and the FT selectors 121, 221, 321, and 421 are sequentially controlled during one cycle of the clock signal. However, in this case, the address operation becomes difficult. Therefore, in this embodiment, the address operation can be realized by having a phase difference.

FIG. 8 shows a schematic diagram of a configuration example around the transmission control logic and the I/O control logic in the semiconductor device of FIG. 1. As shown in FIG. 8, the I/O control logic 130, 230, 330, 430 in each memory chip is equipped with liter 1 adders 130a, 230a, 330a, 430a; and judges 130b, 230b, 330b, 430b. In addition, the transfer control logic 30 in the I/O chip 10 includes an ID generating unit 30a and a command generating unit 30b.

The output of the ID generating unit 30a is attached to the liter 1 adders 130a, 230a, 330a, and 430a via the through-holes of each memory chip. The output of the command generating unit 30b is inputted by one of the determiners 130b, 230b, 330b, and 430b through the through holes of the memory chips. The other input to the determiner 130b is connected to the input of the litre 1 adder 130a. Similarly, the input to the other side of the determiner 230b, 330b, 430b is connected to the litre 1 adder 230a, 330a, 430a input.

In this configuration, for example, when the ID generating unit 30a outputs a signal of "00", the input from the other side of the determiners 130b, 230b, 330b, and 430b is transmitted as "00", "01", "10", and " 11", it can be set as the identification number of each memory chip. Therefore, for example, when the FT selector 221 of the memory chip 200 is to be controlled, the command generation unit 30b only needs to send the information of the identification number "01" and the command indicating that the object is the FT selector (here, Read "01" "), the determiner 230b can recognize it and control the FT selector 221. In addition, the control methods of the ST selector and the FT selector are not limited to this, and can be implemented by various conventionally known control methods.

The representative effects obtained by the semiconductor device of the embodiment of the present invention are summarized as follows. In the conventional method of Patent Document 1, the transmission data is moved in a pipeline between the FT buffers or the ST buffers. Therefore, before the transmission data is ready, it is necessary to wait for all the transmission data to be between the FT buffers or the ST buffers. The time is transmitted sequentially, and the transmission efficiency is reduced. In contrast, in the method of this embodiment, the FT buffers in each chip can independently transfer the read buffers, and the write buffer can also independently transfer the ST buffers in each chip. Therefore, the transfer from the FT buffer in each chip to the read buffer or the transfer from the write buffer to the ST buffer in each chip can be combined with the logic in each chip (such as FT buffer or ST buffer). The operation clock of the core part of the memory is synchronized with an independent higher-speed clock, which can achieve higher transmission efficiency than the conventional method.

The present invention has been specifically described based on the embodiments, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be implemented without departing from the gist.

For example, in the above-mentioned embodiment, an example in which four memory chips are stacked is described, but the same logic configuration can also be applied when the number of stacked chips is different. In this case, for example, when the number of chips is 8 chips, the clock of the I/O chip can be used, for example, which is 8 times faster than the clock of the memory chip.

In addition, the I/O chip clock relative to the memory chip clock does not necessarily have to be a high-speed clock within the range of the number of memory chips, and any value can be used. In this case, for example, when the number of memory chips is 4 chips, using the I/O chip clock that is twice or 8 times the high-speed clock of the memory chip can improve the transmission efficiency. When using the 2x high-speed clock, the read or write operation is completed in 2 cycles of the memory chip clock, and when the 8x high-speed clock is used, the read or write operation is completed in the half cycle of the memory chip clock.

In addition, the present embodiment is not only applicable to the case of a stacked memory chip, but also applicable to cases other than a memory chip such as a stacked processor chip. In addition, it can also be applied to a situation where different chip types such as memory chips and processor chips are mixed.

In addition, in this embodiment, it is desired to make it possible to perform read and write operations in parallel, and to separately provide separate paths for the write path and the read path, but it may also be a common path. In this case, for example, in FIG. 5, the output from the FT selector 121 and the input to the ST selector 122 are connected to a common through hole to form a structure. Similarly, the input to the FT selector 121 is connected to the input from the ST selector 121. The output of the selector 122 is connected to a common through via. For example, a bidirectional tri-state buffer or the like may be provided on the common through via.

(Industrial availability)

The semiconductor device of this embodiment is particularly suitable for a large-capacity memory device formed by stacking a plurality of memory chips, but it is not limited to this. It can be widely applied to include a suitable combination of memory chips or logic. Various layered devices composed of chips, etc., or the single chip used in it.

(Inventive effect)

The effects that can be obtained by the representative embodiment of the present invention are briefly described as follows. High transfer efficiency can be achieved between 3D laminated semiconductor wafers.

<p>10. . . I/O chip</p><p>100, 200, 300, 400. . . Memory chip</p><p>101, 201, 301, 401. . . Memory core</p><p>102, 202, 302, 402. . . Memory core control logic</p><p>111, 211, 311, 411. . . FT buffer</p><p>112, 212, 312, 412. . . ST buffer</p><p>121, 221, 321, 421. . . FT selector</p><p>122, 222, 322, 422. . . ST selector</p><p>130, 230, 330, 430. . . I/O control logic</p><p>130a, 230a, 330a, 430a. . . Liter 1 adder</p><p>130b, 230b, 330b, 430b. . . Judge</p><p>131, 231, 331, 431. . . FT selection signal</p><p>132, 232, 332, 432. . . ST selection signal</p><p>twenty one. . . Read buffer</p><p>twenty two. . . Write buffer</p><p>30. . . Transmission control logic</p><p>30a. . . ID generation department</p><p>30b. . . Command generation department</p><p>35. . . Transmission control signal</p><p>41r, 141r, 142r, 152r, 241r, 242r, 252r. . . Through guide hole (input)</p><p>42t, 52t, 141t, 142t, 152t, 241t, 242t, 252t. . . Through hole (output)</p>

FIG. 1 shows a schematic diagram of an example of the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a logic structure method using a three-dimensional build-up layer among the semiconductor devices examined as the premise of the present invention.

FIG. 3 shows a sequence diagram of the flow of read data transfer of the memory in the semiconductor device of FIG. 2. FIG.

FIG. 4 shows a sequence diagram of the flow of writing data transfer of the memory in the semiconductor device of FIG. 2. FIG.

FIG. 5 shows a schematic diagram of a configuration example including through vias in the semiconductor device of FIG. 1 taking a part of the wafer as an example.

FIG. 6 shows a sequence diagram of the flow of read data transfer of the memory in the semiconductor device of FIG. 1. FIG.

FIG. 7 shows a sequence diagram of the flow of the write data transfer of the memory in the semiconductor device of FIG. 1. FIG.

FIG. 8 shows a schematic diagram of a configuration example around the transmission control logic and the I/O control logic in the semiconductor device of FIG. 1.