Control register mapping in heterogeneous instruction set architecture processor

Control register corresponds to heterogeneous instruction set architecture processor

Control register Mapping in heterogeneous instruction set architecture processor

[References in related applications]

This application is part of the continuous case of the US patent application in the application. These cases are all included in the case:<tables><img alt="" file="twi474191b_d0001.tif" he="628" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1865" /></tables>

This application claims priority from the following US Provisional Patent Applications, each of which is incorporated herein by reference.<tables><img alt="" file="twi474191b_d0002.tif" he="1100" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1879" /></tables>

US official patent application<tables><img alt="" file="twi474191b_d0003.tif" he="149" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1869" /></tables>

It refers to the following priority of the US temporary application:<tables><img alt="" file="twi474191b_d0004.tif" he="156" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1875" /></tables><tables><img alt="" file="twi474191b_d0005.tif" he="301" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1879" /></tables>

The following three official US applications<tables><img alt="" file="twi474191b_d0006.tif" he="395" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1882" /></tables>

These are the continuations of the following US official application:<tables><img alt="" file="twi474191b_d0007.tif" he="155" id="" img-content="drawing" img-format="tif" inline="no" orientation="portrait" wi="1873" /></tables>

And cite the following US temporary application priority:<tables><img id="" he="515" wi="1863" file="twi474191b_d0008.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

This application is related to the following US official patent applications:<tables><img id="" he="875" wi="1863" file="twi474191b_d0009.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

The present invention relates to the technical field of microprocessors, and more particularly to the support of microprocessor multi-instruction set architectures.

The x86 processor architecture developed by Intel Corporation of Santa Clara, California and the advanced reduced risc machines (ARM) architecture developed by ARM Ltd. of Cambridge, UK are two well-known processes in the computer field. Architecture. Many computer systems using ARM or x86 processors have emerged, and the demand for this computer system is growing rapidly. Today, the ARM architecture processing core dominates the low-power, low-cost computer market, such as mobile phones, handheld electronics, tablets, network routers and hubs, and set-top boxes. For example, the main processing power of Apple's iPhone and iPad is provided by the processing core of the ARM architecture. On the other hand, x86 architecture processors dominate high-priced markets that require high performance, such as laptops, desktops, and servers. However, as the performance of ARM cores has improved and the power and cost of some x86 processors have improved, the boundaries between the aforementioned low-priced and high-priced markets have become blurred. In the mobile computing market, such as smart phones, these two architectures have begun to compete fiercely. In the laptop, desktop and server markets, it is expected that these two architectures will compete more frequently.

The aforementioned competitive situation has caused computer device manufacturers and consumers to be in a dilemma because it is impossible to determine which architecture will dominate the market. More precisely, it is impossible to determine which architecture software developers will develop more software. For example, some monthly or annual purchases of large amounts of computer systems are regularly purchased. Individuals, based on cost-efficiency considerations, such as price concessions for large purchases and simplification of system maintenance, tend to purchase computer systems with the same system configuration settings. However, the user groups in these large consumer individuals often have various computing needs for these computer systems with the same system configuration settings. Specifically, some users' needs are to be able to execute programs on ARM architecture processors. Other users need to be able to execute programs on x86 architecture processors, and some users hope to be able to simultaneously The program is executed on the architecture. In addition, new, unexpected computing needs may arise and require another architecture. Under these circumstances, some of the funds invested by these large individuals become waste. In another example, the user has an important application that can only be executed on the x86 architecture, so he purchased a computer system with an x86 architecture (and vice versa). However, subsequent versions of this application were developed for ARM architecture and are superior to the original x86 version. The user would like to convert the architecture to execute the new version of the application, but unfortunately he has invested considerable cost in the architecture that is not intended to be used. Similarly, users originally invested in applications that can only be executed on the ARM architecture, but later hope to use applications developed for the x86 architecture that are not found in the ARM architecture or applications that are better than the ARM architecture. Will encounter such problems, and vice versa. It is worth noting that although the small entity or individual invested in a larger amount of entities is small, the investment loss ratio may be higher. Other examples of similar investment losses may occur in a variety of different computing markets, such as when converting from an x86 architecture to an ARM architecture or from an ARM architecture to an x86 architecture. Finally, computing device manufacturers that invest large amounts of resources to develop new products, such as OEMs, will also fall into this rack. The dilemma of choice. If the manufacturer develops and manufactures a large number of products based on the x86 or ARM architecture, and the user's demand suddenly changes, it will lead to the waste of many valuable research and development resources.

It is helpful for manufacturers and consumers of computing devices to be able to protect their investments from the winners of the two architectures. It is therefore necessary to propose a solution for system manufacturers to develop x86 for users simultaneously. Arithmetic device for architecture and ARM architecture.

The need to enable systems to execute multiple instruction set programs has been around for a long time. These requirements are mainly due to the fact that consumers are consuming software programs that are executed on old hardware at considerable cost, and their instruction sets are often incompatible with new hardware. For example, the IBM 360 System Model 30 has the pain of being compatible with the features of the IBM 1401 system to mitigate the 360 system in which users switch from a 1401 system to a higher performance and improved feature. The Model 30 has a 360 system and a Read Only Storage (ROS) of the 1401 system, enabling it to be used in the 1401 system with the auxiliary storage space pre-stored with the required information. In addition, in the case of software programs developed in high-level languages, new hardware developers have little control over the software programs compiled for old hardware, and software developers lack the motivation to recompile for new hardware (re-compile). The source code, especially in the case where the software developer and the hardware developer are different individuals. An article by Siberman and Ebcioglu in Computer, June 1993, No. 6 "An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures reveals a system that uses the Reduced Instruction Set (RISC), superscalar and super long instruction word (VLIW) architectures (hereafter native architecture) to improve the existing Complex Instruction Set (CISC) architecture ( For example, IBM S/390) performance efficiency techniques The system disclosed includes a native engine that executes the native code and a migrant engine that executes the destination code, and can translate the object bode into a native code according to the translation software. The translation effect is converted between the two encodings as needed. Referring to U.S. Patent No. 7,047,394, issued May 16, 2006, Van Dyke et al. discloses a processor having an execution pipeline for executing program instructions of a native reduced instruction set (Tapestry) and utilizing hardware The combination of translation and software translation translates x86 program instructions into instructions for the native reduced instruction set. Nakada et al. proposed a heterogeneous multi-threaded processor (heterogeneous SMT) with a front-end pipeline of the ARM architecture and a front-end pipeline of the Fujitsu FR-V (ultra-long instruction word) architecture. Processor), the ARM architecture front-end pipeline is used for irregular software programs (such as operating systems), and the Fujitsu FR-V (ultra-long instruction word) architecture front-end pipeline is used for multimedia applications, which will be added The very long instruction word queue is provided to the FR-V very long instruction word after the end pipeline to maintain instructions from the front end pipeline. Please refer to Buchty and Weib, eds, Universitatsverlag Karlsruhe in November 2008 at First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC' 08), Lake Como, Italy, (with MICRO-41) Proceedings of the collection (ISBN 978-3-86644-298-6) "OROCHI: A Multiple Instruction Set SMT The method proposed in the paper is to reduce the space occupied by the entire system in a heterogeneous system single-chip (SOC) device (such as the Texas Instruments OMAP application processor). The heterogeneous system single-chip device has an ARM processor core plus One or more co-processors (eg TMS320, multiple digital signal processors, or It is a variety of graphics processing units (GPUs). These coprocessors do not share instruction execution resources, but are integrated into different processing cores on the same die.

Software translators, or software emulators, dynamic binary translators, etc., are also used to support the ability to execute software programs on processors that differ from the software architecture. . Among the popular commercial examples are the Motorola 68K-to-PowerPC emulator with an Apple Macintosh computer, which can execute a 68K program on a Macintosh computer with a PowerPC processor, and a subsequent PowerPC- A to-x86 emulator that executes a 68K program on a Macintosh computer with an x86 processor. Transmeta, Inc., located in Santa Clara, Calif., combines the core hardware of the Very Long Instruction Word (VLIW) with the "Software Direct Translator (Code Morphing Software)) To dynamically compile or emulate x86 code sequences to execute x86 code, please refer to the 2011 Wikipedia instructions for Transmeta.<u style="single">http://en.wikipedia.org/wiki/Transmeta&gt;</u>. In addition, reference is made to U.S. Patent No. 5,832,205, issued to Kelly et al. IBM's DAISY (Dynamic Architecture Instruction Set from Yorktown) system features a very long instruction word (VLIW) machine and dynamic binary software translation that provides 100% legacy architecture software compatible simulation. DAISY has a Virtual Machine Monitor in read-only memory to parallelize and store VLIW primitives to some of the main memory systems that are not found in the legacy system architecture. It is possible to avoid the code segments of these legacy architectures being te-translationed in subsequent programs. DAISY has high speed editing Fast compiler optimization algorithms to improve performance. QEMU is a machine simulator with a software dynamic translator (machine Emulator). QEMU can emulate a variety of central processing units such as x86, PowerPC, ARM and SPARC in a variety of host systems such as x86, PowerPC, ARM, SPARC, Alpha and MIPS. Please refer to QEMU, a Fast and Portable Dynamic Translator, Fabrice Bellard, USENIX Association, FREENIX Track: 2005 USENIX Annual Technical Conference, as its developer calls "the dynamic translation of the target processor instruction execution (runtime conversion), Convert it to the main system instruction set, the resulting binary code is stored in a translation cache for repeated access....QEMU [compared to other dynamic translators] is much simpler, because it only connects to GNC C compiler A machine code fragment generated when off line." Also refer to the dissertation "Lee Wang Hao" of the University of Adelaide on June 19, 2009 "ARM Instruction Set Simulation on Multi-core x86 Hardware. Although the software translation-based solution provides processing power that meets multiple computing needs, it is less than adequate for multiple users.

Static binary translation is another technology with high performance potential. However, there are technical problems with the use of binary translation techniques (such as self-modifying code, in-direct branches only at run-time), and business and law. Obstacles (for example, this technology may require hardware developers to work with the pipeline needed to develop new programs; potential licenses for original programmers or the risk of copyright infringement).

An embodiment of the present invention provides a microprocessor that can execute an x86 instruction set architecture (ISA) machine language program and an advanced RISC Machines (ARM) ISA machine language program. . The microprocessor includes an instruction mode instructing the microprocessor to retrieve an x86 ISA or an ARMISA machine language program instruction. The microprocessor also includes a plurality of specific model registers (MSRs) for controlling the manner in which the microprocessor operates. When the instruction mode instructs the microprocessor to retrieve x86 ISA machine language program instructions, each particular model register is accessible via an x86 ISA RDMSR/WRMSR53 instruction, and the x86 ISA MRRC/MCRR instruction is specified The address of this particular model register. When the instruction mode instructs the microprocessor to retrieve an ARM ISA machine language program instruction, each particular model register can be accessed via an ARM ISA MRRC/MCRR instruction, and the ARM ISA MRRC/MCRR instruction specifies the The address of a particular model register.

Another embodiment of the present invention provides a method of accessing a plurality of specific model registers (MSRs) that control a microprocessor operation mode and execute an x86 instruction set architecture (ISA) machine The language program and the Advanced Reduced Instruction Set Machine (ARM) ISA machine language program, the microprocessor having an instruction mode instructing the microprocessor to retrieve an x86 ISA or an ARM ISA machine language program instruction. The method includes accessing one of the specific model registers via an x86 ISA RDMSR/WRMSR instruction when the instruction mode instructs the microprocessor to retrieve the x86 ISA machine language program, and the x86 ISA RDMSR /WRMSR instruction is used to specify one bit of the specific model register site. The method further includes accessing one of the specific model registers via an ARM ISA MRRC/MCRR instruction when the instruction mode instructs the microprocessor to retrieve the ARM ISA machine language program instructions, and the ARM The ISA MRRC/MCRR command is used to specify one of the addresses of the particular model register.

A further embodiment of the present invention provides a computer program product encoded in at least one computer readable storage medium for use in an computing device, the computer program product comprising a computer readable program code for use in the computer The storage medium can be read to specify a microprocessor executable x86 Instruction Set Architecture (ISA) machine language program and an Advanced Reduced Instruction Set Machine (ARM) ISA machine language program. The computer readable code includes a first code for specifying an instruction mode instructing the microprocessor to retrieve an x86 ISA or an ARMISA machine language program instruction. The computer readable code further includes a second code for specifying a plurality of specific model registers (MSRs), and the specific model registers control the manner of operation of the microprocessor. When the instruction mode instructs the microprocessor to retrieve x86 ISA machine language program instructions, each particular model register can be accessed via an x86 ISA RDMSR/WRMSR53 instruction, and the x86 ISA MRRC/MCRR instruction specifies The address of a particular model register. When the instruction mode instructs the microprocessor to retrieve an ARM ISA machine language program instruction, each particular model register can be accessed via an ARM ISA MRRC/MCRR instruction, and the ARM ISA MRRC/MCRR instruction specifies the The address of a particular model register.

Yet another embodiment of the present invention provides a microprocessor that executes an x86 Instruction Set Architecture (ISA) machine language program and an advanced reduced instruction set machine (ARM) ISA machine language program. The microprocessor includes an instruction mode and a plurality of hardware registers, the instruction mode instructing the microprocessor to retrieve an x86 ISA or an ARM ISA machine language program instruction. When the instruction mode instructs the microprocessor to retrieve x86 ISA machine language program instructions, the hardware registers store the x86 ISA architecture state. When the instruction mode instructs the microprocessor to retrieve the ARM ISA machine language program instructions, the hardware registers store the ARM ISA architectural state.

Another embodiment of the present invention provides a method of operating a microprocessor executable x86 instruction set architecture (ISA) machine language program and an advanced reduced instruction set machine (ARM) ISA machine language program. The method includes setting an instruction mode to instruct the microprocessor to retrieve an x86 ISA or ARM ISA machine language program instruction. The method further includes storing the x86 ISA architectural state in a plurality of hardware registers of the microprocessor when the instruction mode instructs the microprocessor to retrieve the x86 ISA machine language program instructions. The method further includes storing the ARM ISA architectural state in a plurality of hardware registers of the microprocessor when the instruction mode instructs the microprocessor to retrieve the ARM ISA machine language program instructions.

Another embodiment of the present invention provides a computer program product encoded in at least one computer readable storage medium for use in an computing device. The computer program product includes a computer readable program code for the computer readable storage medium to specify a microprocessor executable x86 instruction set architecture (ISA) machine language program and an advanced reduced instruction set machine (ARM) ) ISA machine language program. The computer readable code includes a first code for specifying an instruction mode instructing the microprocessor to retrieve an x86 ISA or an ARMISA machine language program instruction. The computer The readable code further includes a second code for specifying a plurality of hardware registers. When the instruction mode instructs the microprocessor to retrieve x86 ISA machine language program instructions, the hardware registers store the x86 ISA architecture state. When the instruction mode instructs the microprocessor to retrieve the ARM ISA machine language program instructions, the hardware registers store the x86 ISA architecture state.

The requirements of embodiments of the invention disclosed herein require a multi-core processor design that can execute an x86 instruction set architecture (ISA) machine language program and an advanced reduced instruction set (RISC) machine (ARM). ISA machine language program.

Another embodiment of the present invention provides a microprocessor. The microprocessor includes a plurality of processing cores. Each of the processing cores includes a hardware instruction translator that translates an x86 instruction set architecture (ISA) machine language program and an advanced reduced instruction set machine (ARM) ISA machine language program into a plurality of microinstructions. And the microinstructions are defined by one of the microinstructions of the microprocessor. The microinstructions are encoded in a unique encoding that is encoded by instructions defined by the instruction set of the x86 ISA and ARM ISA. Each processing core of the processing cores further includes an execution pipeline coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to produce the results defined by the x86 ISA and the ARM ISA instructions.

Another embodiment of the present invention is directed to a microprocessor method comprising a plurality of processing cores, each core of the processing core having an instruction to indicate an x86 instruction set architecture (ISA) machine language Program or an advanced Reduced Instruction Set Machine (ARM) ISA machine. For each core of the processing cores, the method includes determining that the instruction is indicative of the X8 6 ISA or the ARM ISA, and when the instruction indicates the x86 ISA, the machine language instructions are translated into a plurality of microinstructions according to the x86 ISA, and when the instruction indicates the ARM ISA, the machine is based on the ARM ISA Language instructions are translated into a plurality of microinstructions. The microinstructions are defined by a microinstruction set of the microprocessor, and the microinstructions are encoded in a unique encoding manner, and the unique encoding mode is defined by the instruction set of the x86 ISA and ARM ISA. The code is encoded by the instruction. The translation is performed by a hardware instruction translator of the microprocessor. The method further includes executing the microinstructions to generate the microinstructions defined by the x86 ISA when the instruction indicates the x86 ISA, and executing the microinstructions to generate the ARM ISA when the instructions indicate the ARM ISA Microinstructions. The execution is processed by one of the microprocessor execution pipelines, and the execution pipeline is coupled to the hardware instruction translator.

Another embodiment of the present invention provides a computer program product encoded in at least one computer readable storage medium for use in an computing device. The computer program product includes a computer readable program code for use in the computer readable storage medium to designate a microprocessor. The computer readable code contains a code for specifying a plurality of processing cores. Each core of the processing cores includes a hardware instruction translator that translates x86 instruction set architecture (ISA) machine language program instructions and advanced reduced instruction set machine (ARM) ISA machine language program instructions into a plurality of microinstructions . The microinstructions are encoded in a unique encoding that is encoded by instructions defined by the instruction set of the x86 ISA and ARM ISA. Each core of the processing cores further includes an execution pipeline coupled to the hardware instruction translator. The execution pipeline executes the microinstructions Generates the results defined by the x86 ISA and the ARM ISA directive.

Another embodiment of the present invention provides a microprocessor that operates as an x86 Instruction Set Architecture (ISA) microprocessor and an Advanced Reduced Instruction Set Machine (ARM) ISA microprocessor. The microprocessor includes a first storage, a second storage, and a third storage, the first storage stores an x86 ISA specific state of the microprocessor, and the second storage stores the microprocessor The ARM ISA specific state, the third storage stores the non-ISA specific state of the microprocessor. Corresponding to resetting, the microprocessor initializes the first storage to a preset value specified by the x86 ISA, and initializes the second storage to a preset value specified by the ARM ISA, and then The third storage is initialized to a preset value and then begins to retrieve a first ISA command. The first ISA command is the x86 ISA or the ARM ISA, and a second ISA is the other ISA. The microprocessor updates at least a portion of the third storage corresponding to one or more of the first ISA commands. Corresponding to a subsequent instruction in the first ISA instruction, instructing the microprocessor to reset the second ISA, corresponding to a subsequent instruction in the first ISA instruction, instructing the microprocessor to reset the second ISA to avoid Correcting the non-ISA specific state stored in the third storage, and then starting to retrieve the second ISA command.

Another embodiment of the present invention provides a method of operating a microprocessor as an x86 instruction set architecture (ISA) microprocessor and an advanced reduced instruction set machine (ARM) ISA microprocessor, the method comprising When one of the microprocessors is reset, a first memory is initialized to a preset value specified by the x86 ISA, and then a second memory is initialized to a preset value specified by the ARM ISA, and then a third storage initialized to The preset value is followed by a first ISA command. The first storage stores the x86 ISA specific state of the microprocessor. The second storage stores the ARM ISA specific state of the microprocessor. The third storage stores a non-ISA specific state of the microprocessor. The first ISA command is the x86 ISA or the ARM ISA, and a second ISA is the other ISA. The method further includes instructing the microprocessor to reset the second ISA corresponding to a subsequent instruction in the first ISA instruction, and then avoiding correcting the non-ISA specific state stored in the third storage, and extracting the Second ISA directive.

Another embodiment of the present invention provides a computer program product encoded in at least one computer readable storage medium for use in an computing device. The computer program product includes a computer readable program code for the computer readable storage medium to designate a microprocessor to operate as an x86 instruction set architecture (ISA) microprocessor and an advanced reduced instruction set Machine (ARM) ISA microprocessor. The computer readable code includes a first code for specifying a first memory to store the x86 ISA specific state of the microprocessor. The computer readable code further includes a second code for specifying a second storage to store the ARM ISA specific state of the microprocessor. The computer readable code further includes a third code for specifying a third storage to store the non-ISA specific state of the microprocessor. Corresponding to a reset, the microprocessor initializes the first storage to a preset value specified by the x86 ISA, and then initializes the second storage to a preset value specified by the ARM ISA, and then The third storage is initialized to a preset value and begins to retrieve a first ISA command. The first ISA command is the x86 ISA or the ARM ISA, and a second ISA is the other ISA. The microprocessor corresponds to one or more of the first ISA commands, and New at least a portion of the third storage. Corresponding to the subsequent instruction in the first ISA instruction, instructing the microprocessor to reset the second ISA, and the microprocessor avoids correcting the non-ISA specific state stored in the third storage, and starting to capture The second ISA instruction.

<u style="single">Noun definition</u>

The instruction set defines the correspondence between the set of binary code values (ie, machine language instructions) and the operations performed by the microprocessor. Machine language programs are basically encoded in binary systems, but other systems can be used, such as some of the early IBM computer language programs, although they are ultimately represented by physical signals that exhibit binary values at high or low voltages. It is encoded by the decimal system. The machine language instruction instructs the microprocessor to perform operations such as: adding the operands in the scratchpad 1 to the operands in the scratchpad 2 and writing the result to the scratchpad 3, and the operand of the memory address 0x12345678 The immediate operation element specified by the instruction is subtracted and the result is written into the scratchpad 5. The value in the temporary register 6 is moved according to the number of bits specified by the temporary register 7, and if the zero flag is set, the branch is commanded. The latter 36 bytes are loaded into the scratchpad 8 with the value of the memory address 0xABCD0000. Thus, the instruction set defines the binary encoded values of the various machine language instructions that cause the microprocessor to perform the operations to be performed. It should be understood that the instruction set defines the correspondence between the binary value and the operation of the microprocessor, and does not mean that a single binary value corresponds to a single microprocessor operation. Specifically, in some instruction sets, multiple binary values may correspond to the same microprocessor operation.

Instruction Set Architecture (ISA), from the context of the microprocessor family, contains (1) Instruction set; (2) a set of resources accessible by the instruction set instruction (eg, a scratchpad and a mode required for memory addressing); and (3) an exception generated by the execution of the instruction in the microprocessor in response to the instruction set Event set (for example: division by zero, page fault, memory protection violation, etc.). Because programmers, such as compilers and compiler writers, want to make machine language programs executed in a microprocessor family, they need the ISA definition of this microprocessor family, so the makers of microprocessor families usually The ISA is defined in the operator's manual. For example, the Intel 64 and IA-32 Architectures Software Developer's Manual, published in March 2009, defines the ISA for Intel 64 and IA-32 processor architectures. This software developer's manual contains five chapters. The first chapter is the basic architecture; the second chapter is the instruction set reference A to M; the second chapter is the instruction set reference N to Z; the third chapter is the system programming guide. The third chapter is the second part of the system programming guide. This manual series is the reference document for this case. This type of processor architecture is often referred to as the x86 architecture. In this article, it is x86, x86 ISA, x86. ISA family, x86 family or similar terms to illustrate. In another example, the ARM architecture reference manual published in 2010, ARM v7-A and ARM v7-R version Errata markup, defines the ISA of the ARM processor architecture. This reference manual series is a reference file. The ISA of this ARM processor architecture is also referred to herein as ARM, ARM ISA, ARM ISA family, ARM family or similar terms. Other well-known ISA families include IBM System/360/370/390 and z/Architecture, DEC VAX, Motorola 68k, MIPS, SPARC, PowerPC and DEC Alpha. The definition of ISA will cover the processor family, because in the development of the processor family, manufacturers will add new instructions in the instruction set, and/or A new scratchpad is added to the bank to improve the ISA of the original processor. For example, with the development of the x86 programming architecture, the Intel Pentium III processor family imported a set of 128-bit multimedia extended instruction set (MMX) registers as a single instruction multiple data stream extension (SSE) instruction set. Part of the x86 ISA machine language program has been developed to take advantage of the XMM scratchpad to improve performance, although the existing x86 The ISA machine language program does not use the single instruction multiple data stream extension instruction set XMM register. In addition, other manufacturers have designed and manufactured microprocessors that can execute x86 ISA machine language programs. For example, AMD and VIA Technologies are adding new technology features to the x86 ISA, such as 3DNOW for AMD! Single-instruction multiple data stream (SIMD) vector processing instructions, and VIA Technologies' Padlock security engine random number generator and advanced cryptography engine technology, all of which are machines using x86 ISA Language programs, but not implemented by existing Intel microprocessors. As another example, the ARM ISA originally defined an ARM instruction set state with a 4-bit instruction. However, as the ARM ISA evolves, other instruction set states are added, such as the Thumb instruction set state with 2-bit instruction to increase the encoding density and the Jazelle instruction set state to accelerate the Java bytecode program, while the ARM ISA Machine language programs have been developed to use some or all of the other ARM ISA instruction set states, even if the existing ARM ISA machine language program does not use these other ARM ISA instruction set states.

An instruction set architecture (ISA) machine language program that contains a sequence of ISA instructions, that is, an ISA instruction set corresponding to the sequence of operations performed by the program writer A sequence of binary encoded values. Therefore, the x86 ISA machine language program contains the x86 ISA instruction sequence, and the ARM ISA machine language program contains the ARM ISA instruction sequence. Machine language program instructions are stored in memory and retrieved and executed by the microprocessor.

A hardware instruction translator comprising a plurality of transistor configurations for receiving ISA machine language instructions (eg, x86 ISA or ARM ISA machine language instructions) as input and correspondingly outputting one or more microinstructions to the microprocessor The execution pipeline. The execution result of the execution pipeline execution microinstruction is defined by the ISA instruction. Thus, the execution pipeline "implements" the ISA instructions through collective execution of these microinstructions. That is, the execution pipeline implements the operations specified by the input ISA instructions through the collective execution of the microinstructions that are output to the hardware instruction translator to produce the results defined by the ISA instructions. Thus, a hardware instruction translator can be considered to "translate" an ISA instruction into one or more execution microinstructions. The microprocessor described in this embodiment has a hardware instruction translator to translate x86 ISA instructions and ARM ISA instructions into microinstructions. However, it should be understood that the hardware instruction translator does not necessarily translate the entire instruction set defined by the x86 user manual or the ARM user manual, but often only translates a subset of these instructions, as Most x86 ISA and ARM ISA processors only support a subset of instructions defined in their corresponding user manual. Specifically, the x86 user operation manual defines a subset of instructions translated by the hardware instruction translator, which does not necessarily correspond to all existing x86 The ISA processor, the ARM user operating manual defines a subset of instructions that are translated by the hardware instruction translator, and does not necessarily correspond to all existing ARM ISA processors.

The execution pipeline is a sequence of stages. Each level of the multi-level sequence has hardware logic and a hardware register. The hardware register maintains the output signal of the hardware logic and provides the output signal to a level below the multi-level sequence according to the clock signal of the microprocessor. The execution pipeline can have multiple multi-level sequences, such as multiple execution pipelines. The execution pipeline receives the microinstruction as an input signal and accordingly performs an operation specified by the microinstruction to output an execution result. The operations specified by the microinstructions and performed by the hardware logic of the execution pipeline include, but are not limited to, arithmetic, logic, memory load/store, compare, test, and branch parsing, and the data formats for operations include, but are not limited to, integers. , floating-point numbers, characters, binary encoding decimals (BCD), and packed formats. The execution pipeline executes microinstructions to implement ISA instructions (such as x86 and ARM) to generate the results defined by the ISA instructions. The execution pipeline is different from the hardware instruction translator. Specifically, the hardware instruction translator generates the execution micro-instructions, and the execution pipeline executes the instructions, but does not generate these execution micro-instructions.

The instruction cache is a random access memory device in the microprocessor. The microprocessor places instructions of the ISA machine language program (such as x86 ISA and ARM ISA machine language instructions), and the instructions are retrieved from the system memory. The microprocessor is executed by the microprocessor according to the execution flow of the ISA machine language program. Specifically, the ISA defines an instruction address register to hold the memory address of the next pending ISA instruction (for example, the x86 ISA is defined as an instruction indicator (IP) and is defined as a program in the ARM ISA system). Counter (PC)), and when the microprocessor executes a machine language program to control the program flow, the microprocessor updates the contents of the instruction address register. The ISA instructions are cached for subsequent retrieval. When the next machine included in the register The ISA instruction address of the language program is located in the current instruction cache, and the ISA instruction can be quickly fetched from the system memory by the instruction cache according to the contents of the instruction register. In particular, the program obtains data from the instruction cache based on the memory address of the instruction address register (such as instruction index (IP) or program counter (PC), instead of specifically using a load or store instruction. The specified memory address is used for data retrieval. Therefore, the instruction set architecture instruction is treated as a dedicated data cache of data (eg, data presented by the hardware portion of the software translation system), specifically using a load/store address rather than an instruction address. The value of the register is accessed, not the instruction cache referred to here. In addition, a hybrid cache of instructions and data is available, based on the value of the instruction address register and based on the load/store address, rather than just the load/store address, and is also covered in this description. Within the definition of the instruction cache. In the present description, a load instruction is an instruction to read data from a memory to a microprocessor, and a storage instruction is an instruction to write data to a memory by a microprocessor.

A microinstruction set is a collection of instructions (microinstructions) that a microprocessor's execution pipeline can execute.

<u style="single">Description of the embodiments</u>

The microprocessor disclosed in the embodiment of the present invention can translate the corresponding x86 ISA and ARM ISA instructions into micro instructions directly executed by the microprocessor execution pipeline to implement the executable x86 ISA and ARM ISA machine language programs. purpose. This microinstruction is defined by a microinstruction set different from the microarchitecture of the x86 ISA and ARM ISA. Since the microprocessor described in this article needs to execute x86 and ARM machine language programs, the microprocessor's hardware instruction translator will use x86 and ARM instructions. The translations are microinstructions and are provided to the execution pipeline of the microprocessor, which is executed by the microprocessor to implement the aforementioned x86 and ARM instructions. Since these implementation micro-instructions are directly provided by the hardware instruction translator to the execution pipeline, unlike systems using software translators, the host instructions are pre-stored to the memory before executing the pipeline execution instructions. Therefore, the aforementioned microprocessor has the potential to execute x86 and ARM machine language programs at a faster execution speed.

1 is a block diagram showing an embodiment of a microprocessor 100 of the present invention that executes x86 ISA and ARM ISA machine language programs. The microprocessor 100 has an instruction cache 102; a hardware instruction translator 104 for receiving x86 ISA instructions and ARM ISA instructions 124 by the instruction cache 102 and translating them into microinstructions 126; an execution pipeline 112, Executing the microinstruction 126 received by the hardware instruction translator 104 to generate the microinstruction result 128, the result is returned to the execution pipeline 112 in the form of an operand; a temporary register file 106 and a memory subsystem 108, respectively An operand is provided to execution pipeline 112 and receives microinstruction result 128 by execution pipeline 112; an instruction fetch unit and branch predictor 114 provides a fetch address 134 to instruction fetch 102; an ARM ISA defined program counter is temporarily The memory 116 and an x86 ISA defined instruction indicator register 118 are updated in accordance with the microinstruction result 128 and provide its contents to the instruction fetch unit and the branch predictor 114; and a plurality of configuration registers 122, An instruction mode indicator 132 and an environmental mode indicator 136 are provided to the hardware instruction translator 104 and the instruction fetch unit and the branch predictor 114, and are updated based on the microinstruction result 128.

Since the microprocessor 100 can execute x86 ISA and ARM ISA machine language instructions, the microprocessor 100 is based on the program flow from the system memory (not The illustration captures instructions to the microprocessor 100. The microprocessor 100 accesses the recently retrieved x86 ISA and ARM ISA machine language instructions to the instruction cache 102. The instruction fetch unit 114 will generate a fetch address 134 based on the x86 or ARM instruction byte segments retrieved by the system memory. If the hit instruction cache 102, the instruction cache 102 provides the x86 or ARM instruction byte segment located in the capture address 134 to the hardware instruction translator 104, otherwise the instructions in the system memory are retrieved from the instruction set architecture. 124. The instruction fetch unit 114 generates the fetch address 134 based on the values of the ARM program counter 116 and the x86 command indicator 118. Specifically, the instruction fetch unit 114 maintains a fetch address in a fetch address register. At any time, the instruction fetching unit 114 retrieves the new ISA instruction byte segment, and it updates the retrieval address according to the size of the segment, and sequentially performs according to the existing method until a control flow event occurs. . The control flow event contains the generation of the exception event, and the prediction of the branch predictor 114 shows that there is a branch that will occur within the capture segment (taken The ARM program counter 116 and the x86 instruction indicator 118 are updated by the execution pipeline 112 in response to an execution result of the branch instruction that is not predicted by the branch predictor 114. The instruction fetch unit 114 updates the capture address to the exception handler address, the prediction target address, or the execution target address in response to a control flow event. In one embodiment, the instruction cache 102 is a hybrid cache to access the ISA instructions 124 and data. It should be noted that in this hybrid cache embodiment, although the hybrid cache can write data to the cache or read data from the cache based on a load/store address, the microprocessor 100 is mixed. In the case of cache fetching instructions 124 of the instruction set architecture, the hybrid cache is accessed based on the values of the ARM program counter 116 and the x86 command indicator 118. Rather than based on loading/storing addresses. The instruction cache 102 can be a random access memory device.

The command mode indicator 132 is a state indicating whether the microprocessor 100 is currently capturing, formatting/decoding, and translating the x86 ISA or ARM ISA instructions 124 into the microinstructions 126. In addition, execution pipeline 112 and memory subsystem 108 receive this instruction mode indicator 132, which affects the manner in which microinstruction 126 is executed, although only a small set within the microinstruction set is affected. The x86 instruction index register 118 holds the memory address of the next x86 ISA instruction 124 to be executed, and the ARM program counter register 116 holds the memory address of the next ARM ISA instruction 124 to be executed. In order to control the program flow, the microprocessor 100 updates the x86 instruction index register 118 and the ARM program counter register 116 to the next instruction, the target address of the branch instruction, or the target code of the branch instruction, respectively, when executing the x86 and ARM machine language programs. Is the exception handler address. Executing x86 and ARM at microprocessor 100 When the ISA machine language program is instructed, the microprocessor 100 retrieves the instructions of the instruction set architecture of the machine language program from the system memory and places it into the instruction cache 102 to replace the recent less than being retrieved and executed. instruction. The instruction fetch unit 114 is based on the value of the x86 instruction index register 118 or the ARM program counter register 116, and instructs the ISA instruction 124 that the microprocessor 100 is capturing according to the instruction mode indicator 132 to be x86 or ARM mode. To generate the capture address 134. In one embodiment, the x86 instruction index register 118 and the ARM program counter register 116 can be implemented as a shared hardware instruction address register for providing its contents to the instruction fetch unit and the branch predictor. 114 and the mode indicated by execution pipeline 112 in accordance with command mode indicator 132 is x86 Or ARM and x86 or ARM semantics to update.

The environmental mode indicator 136 is a state indicating that the microprocessor 100 is using x86 or ARM ISA to describe various execution environments operated by the microprocessor 100, such as virtual memory, exception events, cache control, and global execution time protection. . Thus, the command mode indicator 132 and the environmental mode indicator 136 together produce a plurality of execution modes. In the first mode, both the command mode indicator 132 and the environmental mode indicator 136 point to the x86 ISA, which acts as a general x86 ISA processor. In the second mode, both the command mode indicator 132 and the environment mode indicator 136 point to the ARM ISA, and the microprocessor 100 acts as a general ARM ISA processor. In the third mode, the command mode indicator 132 points to the x86 ISA, but the environment mode indicator 136 points to the ARM ISA, which facilitates the execution of the user mode x86 machine language program under the control of the ARM operating system or the hypervisor. Conversely, in the fourth mode, the command mode indicator 132 points to the ARM ISA, but the environmental mode indicator 136 points to the x86. ISA, this mode facilitates the execution of user mode ARM machine language programs under the control of an x86 operating system or hypervisor. The values of the command mode indicator 132 and the environmental mode indicator 136 are determined at the beginning of the reset. In one embodiment, this initial value is encoded as a microcode constant, but may be modified by blowing the configuration fuse and/or using microcode patching. In another embodiment, this initial value is provided to microprocessor 100 by an external input. In one embodiment, the ambient mode indicator 136 will only change after a reset by reset to the ARM (reset-to-ARM) instruction 124 or a reset to x86 (reset-to-x86) instruction 124. (Refer to Figure 6A and Figure 6B below); that is, the microprocessor 100 is operating normally. The environmental mode indicator 136 does not change without a normal reset, reset to x86, or reset to ARM instruction 124 to perform a reset.

The hardware instruction translator 104 receives the x86 and ARM ISA machine language instructions 124 as inputs, and accordingly provides one or more microinstructions 126 as output signals to implement the x86 or ARM ISA instructions 124. Execution pipeline 112 executes one or more microinstructions 126, the result of which is collectively implemented to implement x86 or ARM ISA instructions 124. That is, the collective execution of these microinstructions 126 may perform the operations specified by the x86 or ARM ISA instructions 124 in accordance with the x86 or ARM ISA instructions 124 specified at the input to produce the x86 or ARM ISA instructions 124 defined by the instructions. result. Thus, hardware instruction translator 104 translates x86 or ARM ISA instructions 124 into one or more microinstructions 126. The hardware instruction translator 104 includes a set of transistors configured in a predetermined manner to convert the x86 ISA to the ARM. The ISA machine language instructions 124 are translated to implement microinstructions 126. The hardware instruction translator 104 also has a Boolean logic gate to generate a microinstruction 126 (such as the simple instruction translator 204 shown in FIG. 2). In one embodiment, the hardware instruction translator 104 has a microcode read-only memory (such as element 234 of the complex instruction translator 206 in FIG. 2), and the hardware instruction translator 104 utilizes the microcode read-only memory. The implementation of the microinstruction 126 is based on the complex ISA instruction 124, which will be further described in the description of FIG. In a preferred embodiment, the hardware instruction translator 104 does not necessarily have to translate the entire set of ISA instructions defined in the x86 user manual or the ARM user manual, as long as one of these instructions can be translated. The collection is fine. In particular, a subset of the ISA instructions 124 defined by the x86 user operation manual and translated by the hardware instruction translator 104 does not have to However, corresponding to any Intel-developed x86 ISA processor, the subset of ISA instructions 124 defined by the ARM user operating manual and translated by the hardware instruction translator 104 does not necessarily correspond to any development developed by ARM Ltd. Existing ISA processor. One or more of the previous ones to achieve x86 or ARM The execution microinstructions 126 of the ISA instructions 124 may be provided by the hardware instruction translator 104 all at once to the execution pipeline 112 or sequentially. An advantage of this embodiment is that the hardware instruction translator 104 can provide the execution microinstructions 126 directly to the execution pipeline 112 without having to store the microinstructions 126 in memory between the settings. In the embodiment of the microprocessor 100 of FIG. 1, when the microprocessor 100 executes an x86 or ARM machine language program, the microprocessor 100 executes the x86 or ARM instructions 124 each time the hardware instruction translator 104 The x86 or ARM machine language instructions 124 are translated into one or more microinstructions 126. However, the embodiment of Figure 8 utilizes a microinstruction cache to avoid the problem of repeated translations encountered by the microprocessor 100 each time the x86 or ARM ISA instructions 124 are executed. An embodiment of the hardware instruction translator 104 will be described in more detail in FIG.

Execution pipeline 112 executes the execution microinstructions 126 provided by hardware instruction translator 104. Basically, execution pipeline 112 is a general purpose high speed microinstruction processor. Although the functions described herein are performed by an execution pipeline 112 having x86/ARM specific features, most of the x86/ARM specific functions are actually performed by other portions of the microprocessor 100, such as the hardware instruction translator 104. . In one embodiment, execution pipeline 112 executes register renaming, super-scaling, and non-sequential execution of microinstruction 126 received by hardware instruction translator 104. Execution line 112 will be described in more detail in Figure 4.

The micro-architecture of the microprocessor 100 includes: (1) a microinstruction set; (2) a set of resources that can be accessed by the microinstruction 126 of the microinstruction set, which is a superset of the resources of the x86 and the ARM ISA. And (3) the micro-exception set defined by the microprocessor 100 corresponding to the execution of the microinstruction 126, which is a superset of the exception events of the x86 ISA and the ARM ISA. This microarchitecture is different from x86 ISA and ARM ISA. Specifically, this microinstruction set is oriented in many instruction sets that differ from x86 ISA and ARM ISA. First, the microinstructions of the microinstruction set indicate that the operations performed by the execution pipeline 112 and the instructions of the x86 ISA and ARM ISA instruction sets indicate that the operations performed by the microprocessor are not one-to-one correspondence. Although many of these operations are the same, there are still some operations specified by the microinstruction set that are not specified by the x86 ISA and/or ARM ISA instruction set. Conversely, some of the operations specified by the x86 ISA and/or ARM ISA instruction set are not specified by the microinstruction set. Second, the microinstructions of the microinstruction set are encoded in an encoding that is different from the instructions of the x86 ISA and ARM ISA instruction sets. That is, although there are many identical operations (eg: add, offset, load, return) in the microinstruction set as well as x86 and ARM There is a ISA instruction set that specifies that there is no one-to-one correspondence between the microinstruction set and the binary opcode value correspondence table of the x86 or ARM ISA instruction set. It is often coincidental that the microinstruction set is identical to the binary opcode value correspondence table of the x86 or ARM ISA instruction set, and there is still no one-to-one correspondence between them. Third, the microinstruction bit field of the microinstruction set does not have a one-to-one correspondence with the instruction bit field of the x86 or ARM ISA instruction set.

In general, the microprocessor 100 can execute x86 ISA and ARM ISA machine language program instructions. However, the execution pipeline 112 itself cannot execute x86 Or an ARM ISA machine language instruction; rather, an implementation microinstruction 126 that executes a microinstruction set of the microprocessor 100 microarchitecture translated by the x86 ISA and ARM ISA instructions. However, although this micro-architecture is different from the x86 ISA and the ARM ISA, the present invention also proposes other embodiments to open the microinstruction set and other micro-architecture-specific resources to the user. In these embodiments, the microarchitecture can effectively function as a third ISA with a machine language program executable by the microprocessor outside of the x86 ISA and ARM ISA.

The following table (Table 1) describes some of the bit fields of the microinstructions 126 of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

<tables><img id="" he="1813" wi="1845" file="twi474191b_d0010.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img id="" he="574" wi="1872" file="twi474191b_d0011.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

The following table (Table 2) describes some of the microinstructions of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

<tables><img id="" he="2043" wi="1826" file="twi474191b_d0012.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img id="" he="2901" wi="1854" file="twi474191b_d0013.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables><tables><img id="" he="951" wi="1876" file="twi474191b_d0014.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

The microprocessor 100 also contains some micro-architecture-specific resources, such as micro-architecture-specific general-purpose registers, media registers, and sector registers (such as scratchpads for renaming or used by microcode). The scratchpad) and the control scratchpad not found on x86 or ARM ISA, and a private random access memory (PRAM). In addition, this micro-architecture can generate exception events, which are the aforementioned micro-exception events. These exceptions are not seen or specified by the x86 or ARM ISA, and are typically replays of the microinstructions 126 and associated microinstructions 126. For example, these situations include: loading a load miss, which is an execution pipeline 112 assuming a load action and re-executing the load microinstruction 126 upon miss; missing the translation lookaside buffer (TLB), at After the page table walk and the translation lookaside buffer are filled, the microinstruction 126 is re-executed; the floating-point microinstruction 126 receives an abnormal operand (the denormal operand) but the operand is evaluated as normal and needs to be executed in the pipeline. After the operation unit is normalized, the micro-instruction 126 is re-executed; after the execution of the micro-instruction 126, an earlier storage micro-instruction 126 is detected and its address-colliding conflicts, and the loading micro-requirement needs to be re-executed. Instruction 126. It should be understood that the bit column listed in Table 1 of this document, the micro listed in Table 2 The instructions, as well as the micro-architecture-specific resources and micro-architecture-specific exceptions, are merely illustrative of the microarchitecture of the present invention and are not exhaustive of all possible embodiments of the present invention.

The scratchpad file 106 contains hardware registers used by the microinstructions 126 to hold resources and/or destination operands. Execution pipeline 112 writes its result 128 to scratchpad file 106 and receives the operand by micro-instruction 126 from scratchpad file 106. The hardware scratchpad is an instantiated x86 ISA definition shared with the ARM ISA shared scratchpad family of some of the scratchpad files 106. For example, in one embodiment, the scratchpad file 106 references fifteen 32-bit scratchpads, from the ARM ISA scratchpad R0 to R14 and the x86 ISA estenator (EAX register) to R14D. Shared by the scratchpad. Therefore, if a first microinstruction 126 writes a value to the ARM R2 register, then a subsequent second microinstruction 126 reads the x86 accumulator to receive the same write as the first microinstruction 126. Value and vice versa. This technical feature facilitates the rapid communication of x86 ISA and ARM ISA machine language programs through the scratchpad. For example, assume that the ARM machine language program executed in the ARM machine language operating system can change the command mode 132 to x86 ISA and convert control to an x86 machine language program to perform specific functions because the x86 ISA can support some instructions. , it performs operations faster than ARM ISA, in this case will benefit the speed of execution. The ARM program can provide the required information to the x86 executive through the shared register of the scratchpad file 106. Conversely, the x86 executive can provide execution results to the shared scratchpad of the scratchpad file 106 so that the ARM program can see the execution result after the x86 executable program replies. Similarly, in the x86 machine language operating system The x86 machine language program can change the command mode 132 to the ARM ISA and transfer control to the ARM machine language program; the x86 program can provide the required information to the ARM executive program through the shared register of the scratchpad file 106. The ARM executable can provide execution results through the shared scratchpad of the scratchpad file 106, so that the x86 program can see the execution result after the ARM executable reply. Because the ARM R15 scratchpad is an independently referenced ARM program counter register 116, the sixteenth 32-bit scratchpad that references the x86 R15D register is not shared with the ARM R15 scratchpad. In addition, in one embodiment, sixteen 128-bit XMM0 to XMM15 registers of x86 and sixteen 128-bit advanced single instruction multiple data extensions (Advanced SIMD ("Neon")) register 32 The bit segment is shared with thirty-two 32-bit ARM VFPv3 floating point register. The scratchpad file 106 also references the flag register (ie, the x86 EFLAGS register and the ARM condition flag register), and the various control and status registers defined by the x86 ISA and ARM ISA. The state register includes a model specific registers (MSRs) of the x86 architecture and a coprocessor (8-15) register reserved for the ARM architecture. The scratchpad file 106 also references non-architected scratchpads, such as non-architected general-purpose registers for register renaming or used by microcode 234, and non-architected x86-specific model registers and implementation definitions. Or an ARM coprocessor register specified by the manufacturer. The scratchpad file 106 will be further described in Figure 5.

The memory subsystem 108 includes a cache memory hierarchy consisting of cache memory (in one embodiment, a level-1 instruction cache 102 and a level-1 data) are included. Take a mix with Layer 2 cache). This memory The volume system 108 includes a plurality of memory request queues, such as load, store, fill, snoop, and merge write merge buffers. The memory subsystem also includes a memory management unit (MMU). The memory management unit has translation look-aside buffers (TLBs), especially independent instruction and data translation back buffers. The memory subsystem also includes a table walk engine to obtain translations between virtual and physical addresses in response to missed translation buffer buffers. Although instruction cache 102 and memory subsystem 108 are shown as separate in FIG. 1, logically, instruction cache 102 is also part of memory subsystem 108. The memory subsystem 108 is configured to share a common memory space between the x86 and the ARM machine language program so that the x86 and ARM machine language programs can easily communicate with each other through the memory.

The memory subsystem 108 learns the command mode 132 and the environment mode 136 to enable it to perform various operations in the appropriate ISA content. For example, the memory subsystem 108 performs an inspection of a particular memory access violation (eg, a limit violation check) as indicated by the instruction mode indicator 132 as x86 or ARM ISA. In another embodiment, in response to a change in the environmental mode indicator 136, the memory subsystem 108 will flush the translation lookaside buffer; however, when the command mode indicator 132 changes, the memory subsystem 108 does not update the translation accordingly. The backup buffer provides better performance in the third and fourth modes of x86 and ARM in the aforementioned command mode indicator 132 and environmental mode indicator 136. In another embodiment, in response to a translation lookaside buffer miss (TKB miss), the lookup engine indicates x86 or ARM ISA based on the ambient mode indicator 136, thereby deciding to perform a page lookup using the x86 page table or the ARM page table. Action to retrieve the translation lookaside buffer. In another embodiment, if it is an environmental status indicator 136 Indicated as x86 ISA, memory subsystem 108 checks the architectural state of the x86 ISA control registers (such as CR0 CD and NW bits) that affect the cache strategy; if the environment mode indicator 136 indicates ARM ISA, then check the relevant ARM The architectural mode of the ISA control register (such as SCTLR I and C bits). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control register (eg, CR0 PG bit) that affects memory management; if the environmental mode indicator 136 Indicated as ARM ISA, check the architectural mode of the associated ARM ISA control register (such as SCTLR M bits). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control register (eg, CR0 AM bit) that would affect alignment detection, if the environmental mode indicator 136 Indicated as ARM ISA, check the architectural mode of the associated ARM ISA control register (such as SCTLR A bit). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 102 (and the hardware instruction translator 104 for privileged instructions) checks the x86 ISA control staging of the currently assigned privilege level (CPL). The architectural state of the device; if the environmental mode indicator 136 indicates an ARM ISA, then the architectural mode of the associated ARM ISA control register indicating the user or privileged mode is checked. However, in one embodiment, x86 ISA and ARM The ISA system shares control bits/scratches with similar functions in the microprocessor 100. The microprocessor 100 does not reference independent control bits/storage registers for each instruction set architecture.

Although the configuration register 122 and the register file 106 are separate in the illustration, the configuration register 122 can be understood as part of the register file 106. The configuration register 122 has a global configuration register for Controls the microprocessor 100's various operations in the x86 ISA and ARM ISA, such as the ability to validate or disable multiple features. The global configuration register can disable the ability of the microprocessor 100 to execute the ARM ISA machine language program, that is, the microprocessor 100 becomes a microprocessor 100 capable of executing only x86 instructions, and can make other related and exclusive ARM The ability to initiate x86 (launch-x86) and reset to x86 instructions 124 and the implementation-defined coprocessor register referred to herein is invalid. The global configuration register can also cause the microprocessor 100 to execute x86 The ability of the ISA machine language program to fail, that is, to make the microprocessor 100 a microprocessor 100 capable of executing only ARM instructions, and to enable other related capabilities (such as starting ARM and resetting to ARM instructions 124 and this article) Called the new non-architectural-specific model register) failed. In one embodiment, the microprocessor 100 has a predetermined configuration setting at the time of manufacture, such as a hard coded value in the microcode 234. The microcode 234 uses the hard coded value to set the microprocessor 100 at startup. The configuration is written, for example, to the code register 122. However, the partial code register 122 is set in hardware rather than in microcode 234. Additionally, the microprocessor 100 has a plurality of fuses that can be read by the microcode 234. These fuses can be blown to modify the preset configuration values. In one embodiment, the microcode 234 reads the fuse value, performs a mutual exclusion or operation on the preset value and the fuse value, and writes the result of the operation to the configuration register 122. In addition, the effect of the fuse value modification can be recovered with a microcode 234 patch. In the case where the microprocessor 100 is capable of executing x86 and ARM programs, the global configuration register can be used to confirm that the microprocessor 100 (or a particular core 100 of one of the multi-core portions of the processor as shown in FIG. 7) is heavy Or as shown in Figures 6A and 6B, in response to the x86 form of the INIT instruction, it will be x86 microprocessor The form is still booted in the form of an ARM microprocessor. The global configuration register has some bits to provide the initial preset values to specific architecture control registers, such as the ARM ISA SCTLT and CPACR registers. The multi-core embodiment shown in FIG. 7 has only one global configuration register, even if the configuration of each core can be set separately, such as when the command mode indicator 132 and the environmental mode indicator 136 are both set to x86 or ARM. Choose to boot from x86 core or ARM core. In addition, the enable ARM instruction 126 and the start x86 instruction 126 can be used to dynamically switch between the x86 and ARM instruction modes 132. In one embodiment, the global configuration register can read a new non-architectural specific model register through an x86 RDMSR instruction, and some of the control bits can be uncovered by the x86 WRMSR instruction. A write to a non-architectural-specific model register for a write operation. The global configuration register can also be read by an ARM MCR/MCRR instruction to an ARM coprocessor register that corresponds to the previously unreleased non-architecture specific model register, and some of the control bits are transparent. The ARM MRC/MRRC instruction corresponds to the write to the ARM coprocessor register of this new non-architectural specific model register for write operations.

The register 122 is configured and includes a plurality of different control registers for controlling the operation of the microprocessor 100 from different sides. These non-x86 (non-x86)/ARM control registers include the global control register, non-instruction set architecture control register, non-x86/ARM control register, general control register, And other similar scratchpads. In one embodiment, these control registers can utilize x86 RDMSR/WRMSR instructions to access non-architectural specific model registers (MSRs) and utilize ARM MCR/MRC (or MCRR/MRRC) instructions to new implementations. Defined coprocessor register Row access. For example, the microprocessor 100 includes a non-x86/ARM control register to confirm the fine-grained cache control, which is smaller than the x86 ISA and ARM ISA control registers. By.

In one embodiment, the microprocessor 100 provides an ARM ISA machine language program to define an ARM ISA co-processor register to access an x86 ISA-specific model register by implementing the ARM ISA co-processor register. It corresponds directly to the corresponding x86 specific model register. The address of this particular model register is specified in the ARM ISA R1 scratchpad. This data is read or written by the ARM ISA register specified by the MRC/MRRC/MCR/MCRR instructions. In one embodiment, a subset of a particular model register is password protected, i.e., the instruction must use a password when attempting to access a particular model register. In this embodiment, the cipher is assigned to the ARM R7:R6 register. If this access action results in an x86 general protection fault, the microprocessor 100 then generates an ARM ISA undefined instruction abort mode (UND) exception event. In one embodiment, the ARM coprocessor 4 (address: 0, 7, 15, 0) accesses the corresponding x86 specific model register.

Microprocessor 100 also includes an interrupt controller (not shown) coupled to execution pipeline 112. In one embodiment, the interrupt controller is an x86 type of Advanced Programmable Interrupt Controller (APIC). The interrupt controller maps the x86 ISA interrupt event to the ARM ISA interrupt event. In one embodiment, x86 INTR corresponds to an ARM IRQ interrupt event; x86 NMI corresponds to an ARM IRQ interrupt event; x86 INIT triggers an INIT-reset sequence when microprocessor 100 starts, regardless of which The instruction set architecture (x86 or ARM) was originally booted by a hardware reset; the x86 SMI corresponds to the ARM FIQ interrupt event; and the x86 STPCLK, A20, Thermal, PREQ, and Rebranch do not correspond to ARM interrupt events. The ARM machine language accesses the advanced programmable interrupt controller through the new implementation-defined ARM coprocessor register. In an embodiment, the APIC register address is specified in ARM R0 register, the address of this APIC register is the same as the address of x86. In an embodiment, the ARM coprocessor 6 is typically used for the privileged mode function of the operating system. The address of the ARM coprocessor 6 is: 0, 7, nn, 0; wherein nn is 15 An advanced programmable interrupt controller; nn is 12-14 to access the bus interface unit to perform 8-bit, 16-bit, and 32-bit input/output cycles on the processor bus. The microprocessor 100 also includes a bus interface unit (not shown) coupled to the memory subsystem 108 and the execution pipeline 112 as an interface between the microprocessor 100 and the processor bus. In one embodiment, the processor bus is compliant with the specifications of a microprocessor bus of the Intel Pentium microprocessor family. The ARM machine language program can access the function of the bus interface unit through the new implementation-defined ARM coprocessor register to generate an input/output loop on the processor bus, that is, from the input/output bus to the input. A specific address of the output space is used to communicate with the system chipset. For example, the ARM machine language program can generate an SMI-approved specific loop or an input-output loop for C-state transitions. In an embodiment, the input and output address is specified in ARM R0 register. In one embodiment, the microprocessor 100 has power management capabilities, such as the well-known P-state and C-state management. The ARM machine language program can perform power management through a new implementation of the ARM coprocessor register. In one embodiment, the microprocessor 100 includes an encryption unit (not shown) that is located in the execution pipeline. Within 112. In one embodiment, the encryption unit is substantially similar to the encryption unit of the VIA microprocessor with Padlock security technology functionality. The ARM machine language program can obtain the functionality of an encryption unit, such as an encrypted instruction, through a new implementation-defined ARM coprocessor register. In one embodiment, the ARM coprocessor is used for user mode functions typically performed by user mode applications, such as those produced using the technical features of the cryptographic unit.

When the microprocessor 100 executes the x86 ISA and ARM ISA machine language programs, each time the microprocessor 100 executes the x86 or ARM ISA instructions 124, the hardware instruction translator 104 performs a hardware translation. Conversely, a software-translated system can reuse the same translation across multiple events instead of repeatedly translating previously translated machine language instructions, thus helping to improve performance. In addition, the embodiment of Figure 8 uses microinstruction cache to avoid repeated translations that may occur each time the microprocessor executes the x86 or ARM ISA instructions 124. The manners described in the various embodiments of the present invention are in accordance with different program features and their execution environments, and thus indeed contribute to improved performance.

The branch predictor 114 accesses the history data of the x86 and ARM branch instructions that were previously executed. The branch predictor 114 analyzes whether the cache line obtained by the instruction cache 102 has x86 and ARM branch instructions and its target address based on the previous cache history data. In an embodiment, the cache history data includes a memory address of the branch instruction 124, a branch target address, a direction indicator, a type of branch instruction, a start byte of the branch instruction in the cache line, and a display whether An indicator that spans multiple cache lines. In one embodiment, such as the United States, 61/473, 067, filed on April 7, 2011 No. Provisional Application "APPARATUS AND METHOD FOR USING BRANCH PREDICTION TO EFFICIENTLY EXECUTE CONDITIONAL NON-BRANCH INSTRUCTIONS', which provides a method of improving the performance of the branch predictor 114 to enable it to predict the direction of the ARM ISA conditional non-branch instruction. In an embodiment The hardware instruction translator 104 includes a static branch predictor, and can predict the direction and branch of the x86 and ARM branch instructions according to the execution code, the type of the condition code, the backward or the forward, and the like. Target address.

The present invention also contemplates a variety of different embodiments to achieve a combination of different features of the x86 ISA and ARM ISA definitions. For example, in one embodiment, the microprocessor 100 implements the ARM, Thumb, ThumbEE, and Jazelle instruction set states, but provides a trivial implementation for the Jazelle extended instruction set; the microprocessor 100 implements The following extended instruction set includes: Thumb-2, VFPv3-D32, Advanced SIMD (Neon), multiple processing, and VMSA; but does not implement the following extended instruction set, including: security extension Fast content switching expansion, ARM debugging (ARM program can achieve x86 debugging function through ARM MCR/MRC instruction to new implementation definition coprocessor register), performance detection counter (ARM program can pass new real Define the coprocessor register to get the x86 performance counter). For example, in one embodiment, the microprocessor 100 treats the ARM SETEND instruction as a no-op (NOP) and only supports the Little-endian data format. In another embodiment, the microprocessor 100 does not implement the functionality of x86 SSE 4.2.

The present invention contemplates improvements to the microprocessor 100 of various embodiments, such as commercial microprocessor processing produced by VIA Technologies, Inc., Taipei, Taiwan. VIA Nano^TMMake improvements. This Nano microprocessor is capable of executing x86 ISA machine language programs, but cannot execute ARM ISA machine language programs. The Nano microprocessor includes high-performance register renaming, super-scaling instruction technology, a non-sequential execution pipeline, and a hardware translator to translate x86 ISA instructions into microinstructions for execution pipeline execution. The present invention improves the Nano hardware instruction translator to translate ARM ISA machine language instructions into microinstructions for execution pipeline execution in addition to interpreting x86 machine language instructions. Improvements to the hardware instruction translator include improvements to simple instruction translators and improvements to complex instruction translators (including microcode). In addition, the microinstruction set can add new microinstructions to support translation between ARM ISA machine language instructions and microinstructions, and improve the execution pipeline to enable execution of new microinstructions. In addition, the Nano scratchpad file and memory subsystem can be improved to support the ARM ISA, as well as the sharing of specific scratchpads. The branch prediction unit can be improved to make it predictable in the x86 branch, and can also be applied to ARM branch instruction prediction. The advantage of this embodiment is that, because it is largely independent of ISA-agnostic, it is only necessary to make minor modifications to the execution pipeline of the Nano microprocessor. ISA instructions. Improvements to the execution pipeline include the generation and use of condition code flags, the semantics of updating and reporting instruction metric registers, access privilege protection methods, and various memory management related functions, such as access violation detection, The use of paging and translation lookaside buffers (TLBs), and cache policies. The foregoing is merely illustrative and not limiting of the invention, and some of the features are further described in the following. Finally, as mentioned above, some of the features defined by the x86 ISA and ARM ISA may not be supported by the previously unmodified embodiment of the Nano microprocessor, such as x86 SSE 4.2. With ARM security extensions, fast content switching extensions, debugging and performance counters, some of these features will be further explained in the following sections. In addition, the implementation of the ARM ISA machine language program through the improvement of the Nano processor is an embodiment that integrates design, test and manufacturing resources to implement a single integrated circuit product capable of executing x86 and ARM machine language programs. This single integrated circuit product product covers most of the existing machine language programs in the market, and is in line with the current market trend. Embodiments of the microprocessor 100 described herein can be substantially configured as an x86 microprocessor, an ARM microprocessor, or can simultaneously execute x86 ISA and ARM ISA machine language program microprocessor. The microprocessor can dynamically perform x86 ISA and ARM ISA machine language programs by dynamically switching between x86 and ARM command mode 132 on a single microprocessor 100 (or core 100 of FIG. 7). One or more cores may be configured as an ARM core by configuring one or more cores of the multi-core micro-processing 100 (corresponding to FIG. 7) to be an x86 core, that is, through each core of the multi-core 100. Dynamic switching between x86 and ARM instructions for the ability to execute both x86 ISA and ARM ISA machine language programs. In addition, the ARM ISA core is traditionally designed as the core of intellectual property and is being incorporated into its applications by third-party third-party vendors, such as system-on-a-chip and/or embedded applications. Therefore, the ARM ISA does not have a specific standard processor bus as the interface between the ARM core and other parts of the system, such as chipset or other peripherals. Advantageously, the Nano processor has a high speed x86 type processor bus as an interface to the memory and peripherals, and a memory coherency structure that cooperates with the microprocessor 100 to support the ARM ISA in an x86 computer system environment. Execution of machine language programs.

Referring to FIG. 2, the hardware command translator 104 of FIG. 1 is shown in detail in a block diagram. This hardware instruction translator 104 contains hardware, and more specifically, a collection of transistors. The hardware instruction translator 104 includes an instruction formatter 202 that receives the instruction mode indicator 132 and the blocks of the x86 ISA and ARM ISA instruction bytes 124 from the instruction cache 102 of FIG. 1 and outputs the formatted x86 ISA. With ARM ISA instruction 242; a simple instruction translator (SIT) 204 receives the instruction mode indicator 132 and the environment mode indicator 136, and outputs the execution microinstruction 244 and a microcode address 252; a complex instruction translator (CIT) 206 (also known as a microcode unit), receiving the microcode address 252 and the environment mode indicator 136, and providing the implementation microinstruction 246; and a multiplexer 212, one of which receives the microinstruction 244 by the simple instruction translator 204, and the other The input is received by the complex instruction translator 206 for the microinstruction 246 and provides an execution pipeline 112 that executes the microinstructions 126 through FIG. Instruction formatter 202 will be described in more detail in Figure 3. The simple instruction translator 204 includes an x86 simple instruction translator 222 and an ARM simple instruction translator 224. The complex instruction translator 206 includes a micro-PC 232 that receives the microcode address 252, and a microcode counter 232 receives the microcode read-only memory 234 of the read-only memory address 254. Micro-serializer 236, an instruction indirect register (instruction indirection) A register, IIR 235, and a microtranslator 237 for generating a microinstruction 246 output by the complex instruction translator. Both the execution microinstruction 244 generated by the simple instruction translator 204 and the execution microinstruction 246 generated by the complex instruction translator 206 belong to the microinstruction 126 of the microinstruction of the microarchitecture of the microprocessor 100, and can be directly Execution pipeline 112 executes.

The multiplexer 212 is controlled by a select input 248. In general, multiplexer 212 will select microinstructions from simple instruction translator 204; however, when simple instruction translator 204 encounters a complex x86 or ARM ISA instruction 242, it transfers control or encounters traps. To transition to the complex instruction translator 206, the simple instruction translator 204 controls the selection input 248 to cause the multiplexer 212 to select the microinstructions 246 from the complex instruction translator. When the scratchpad configuration table (RAT) 402 (see FIG. 4) encounters a microinstruction 126 having a particular bit indicating that it is the last microinstruction 126 that implements the sequence of complex ISA instructions 242, the scratchpad configuration table 402 then selects control input 248 to cause multiplexer 212 to revert to selecting microinstruction 244 from simple instruction translator 204. In addition, when the rearrangement buffer 422 (see FIG. 4) is ready to cause the microinstruction 126 to retired and the state of the instruction indicates that a microinstruction from the complex instructor needs to be selected, the rearrangement buffer 422 controls the selection input 248 to The worker 212 selects the microinstructions 246 from the complex instruction translator 206. In the case where the microinstruction 126 needs to be retired, the microinstruction 126 has caused an exceptional condition to be generated.

The simple instruction translator 204 receives the ISA instructions 242 and treats these instructions as x86 ISA instructions for decoding when the instruction mode indicator 132 indicates x86, and treats these instructions as ARM ISA when the instruction mode indicator 132 indicates ARM. The instruction is decoded. The simple instruction translator 204 confirms that the ISA instruction 242 is a simple or complex ISA instruction. The simple instruction translator 204 can output the microinstruction 126 for implementing the ISA instruction 242 for the simple ISA instruction 242; that is, the complex instruction translator 206 does not provide any execution microinstructions 126 to the simple ISA instruction 124. Conversely, complex ISA instructions 124 require complex instruction transfers. Translator 206 provides at least some, if not all, of the execution microinstructions 126. In one embodiment, for a subset of the instructions of the ARM and x86 ISA instruction sets 124, the simple instruction translator 204 outputs a portion of the microinstructions 244 that implement the x86/ARM ISA instructions 126, and then transfers control to complex instruction translations. The 206 is connected by the complex instruction translator 206 to output the remaining microinstructions 246 to implement x86/ARM. ISA Directive 126. The multiplexer 212 is controlled to first provide the execution microinstructions 244 from the simple instruction translator 204 as microinstructions 126 provided to the execution pipeline 112, and then provide the execution microinstructions 246 from the complex instruction translator 206 as provided to the execution pipeline. 112 microinstructions 126. The simple instruction translator 204 is known to be executed by the hardware instruction translator 104 to generate an address of the starting microcode read memory 234 of the plurality of microcode programs that implement the microinstruction 126 for a plurality of different complex ISA instructions 124, And when the simple instruction translator 204 decodes a complex ISA instruction 242, the simple instruction translator 204 provides the corresponding microcode program address 252 to the microprogram counter 232 of the complex instruction translator 206. The simple instruction translator 204 outputs the microinstructions 244 required to implement a substantial proportion of the instructions 124 in the ARM and x86 ISA instruction sets, particularly for the ISA instructions 124 that are required to be executed more frequently by the x86 ISA and ARM ISA machine language programs. Only a relatively small number of instructions 124 need to be provided by the complex instruction translator 206 to implement the microinstructions 246. According to an embodiment, x86 instructions, such as RDMSR/WRMSR, CPUID, and complex arithmetic instructions (such as FSQRT and transcendental instructions) are implemented primarily by complex instruction translator 206. Instruction)), and IRET instructions; ARM instructions such as MCR, MRC, MSR, MRS, SRS, and RFE instructions implemented primarily by complex instruction translator 206. Previously listed instructions The invention is not limited, and only the types of ISA instructions that can be implemented by the complex instruction translator 206 of the present invention are exemplified.

When instruction mode indicator 132 indicates x86, x86 simple instruction translator 222 decodes x86 ISA instruction 242 and translates it into execution microinstruction 244; when instruction mode indicator 132 indicates ARM, ARM simple instruction translator 224 for ARM The ISA instruction 242 decodes and translates it into a practice microinstruction 244. In one embodiment, the simple instruction translator 204 is a Boolean logic gate block that can be synthesized by conventional synthesis tools. In one embodiment, the x86 simple instruction translator 222 and the ARM simple instruction translator 224 are separate Boolean logic gate blocks; however, in another embodiment, the x86 simple instruction translator 222 and the ARM simple instruction translator 224 The system is located in the same Boolean logic gate block. In one embodiment, the simple instruction translator 204 translates up to three ISA instructions 242 and provides up to six execution microinstructions 244 to the execution pipeline 112 in a single clock cycle. In one embodiment, the simple instruction translator 204 includes three sub-translators (not shown), each sub-translator translating a single formatted ISA instruction 242, wherein the first inter-translator can translate no more than Three formatted ISA instructions 242 that implement microinstructions 126; the second translator can translate no more than two formatted ISA instructions 242 that implement microinstructions 126; the third translator can require no more than one translation The formatted ISA instruction 242 of the microinstruction 126 is implemented. In one embodiment, the simple instruction translator 204 includes a hardware state machine that is capable of outputting a plurality of microinstructions 244 over a plurality of clock cycles to implement an ISA instruction 242.

In one embodiment, the simple instruction translator 204 performs a number of different exceptions depending on the command mode indicator 132 and/or the environmental mode indicator 136. Piece detection. For example, if the command mode indicator 132 indicates x86 and the x86 simple instruction translator 222 decodes an ISA instruction 124 that is invalid for the x86 ISA, the simple instruction translator 204 then generates an x86 invalid opcode exception event; Similarly, if the command mode indicator 132 indicates ARM and the ARM simple instruction translator 224 decodes an ISA instruction 124 that is invalid for the ARM ISA, the simple instruction translator 204 then generates an ARM undefined instruction exception event. In another embodiment, if the environmental mode indicator 136 indicates an x86 ISA, the simple instruction translator 204 then detects if each x86 ISA instruction 242 it encounters requires a particular privilege level, and if so, detects the current Whether the privilege level (CPL) satisfies the special privilege level required by this x86 ISA instruction 242 and generates an exception event when not satisfied; similarly, if the environment mode indicator 136 indicates an ARM ISA, the simple instruction translator 204 then detects if Each formatted ARM The ISA instruction 242 requires a privileged mode instruction, and if so, whether the current mode is privileged mode and an exception condition is generated when the current mode is the user mode. Complex instruction translator 206 also performs similar functions for specific complex ISA instructions 242.

Complex instruction translator 206 outputs a series of execution microinstructions 246 to multiplexer 212. The microcode read only memory 234 stores the read only memory command 247 of the microcode program. The microcode read only memory 234 outputs a read only memory command 247 in response to the address of the next read only memory instruction 247 retrieved by the microcode read only memory 234 and held by the microprogram counter 232. In general, microprogram counter 232 receives its start value 252 by simple instruction translator 204 in response to simple instruction translator 204 for a complex ISA instruction 242. Decoding action. In other cases, such as responding to a reset or exception event, the microprogram counter 232 receives the reset microcode program address or the appropriate microcode exception event processing address, respectively. Microprogrammer 236 typically updates microprogram counter 232 to a sequence of microcode programs and selectively updates to execution pipeline 112 in response to control microinstructions 126 (eg, branch instructions) in accordance with the size of read only memory instructions 247. The target address is validated for a branch that points to a non-program address within the microcode read-only memory 234. The microcode read only memory 234 is fabricated in a semiconductor wafer of the microprocessor 100.

In addition to the microinstructions 244 used to implement the simple ISA instructions 124 or portions of the complex ISA instructions 124, the simple instruction translator 204 also generates ISA instruction information 255 for writing to the instruction indirect registers 235. The ISA instruction information 255 stored in the instruction indirect register 235 contains information about the translated ISA instruction 124, for example, information identifying the source and destination registers specified by the ISA instruction, and the format of the ISA instruction 124, such as ISA. The instructions 124 are executed on one of the memory elements or in one of the architecture registers 106 of the microprocessor 100. This allows the microcode program to become versatile, i.e., does not require the use of different microcode programs for the various source and/or destination architecture registers 106. In particular, the simple instruction translator 204 knows the contents of the scratchpad file 106, including which registers are the shared registers 504, and can pass the scratchpad information provided in the x86 ISA and ARM ISA instructions 124 through the ISA instructions. The use of information 255 is translated to the appropriate register in the scratchpad file 106. The ISA command information 255 includes a shift bar, an immediate bar, a constant bar, renaming information of each source operand and the microinstruction 126 itself, and a first series of microinstructions 126 for implementing the ISA command 124. Information and storage of the last microinstruction 126 The other bits of the useful information collected by the hardware instruction translator 104 when the ISA instruction 124 was translated.

The micro translator 237 receives the read only memory instruction 247 from the contents of the microcode read only memory 234 and the indirect instruction register 235, and generates the execution microinstruction 246 accordingly. The micro-translator 237, based on the information received by the indirect instruction register 235, such as in accordance with the format of the ISA instruction 124 and its source and/or destination architecture register 106, specifies a particular read-only memory instruction 247. Translated into different microinstructions 246 series. In some embodiments, a number of ISA instruction messages 255 are combined with read-only memory instructions 247 to generate execution micro-instructions 246. In one embodiment, each of the read only memory instructions 247 is approximately 40 bits wide, and each microinstruction 246 is approximately 200 bits wide. In one embodiment, the micro-translator 237 can generate up to three micro-instructions 246 from one micro-read memory instruction 247. Micro-translator 237 includes a plurality of Boolean logic gates to generate execution microinstructions 246.

The advantage of using the micro-translator 237 is that since the simple instruction translator 204 itself generates the ISA instruction information 255, the microcode-reading memory 234 does not need to store the ISA instruction information 255 provided by the indirect instruction register 235, thereby reducing Reduce its size. In addition, because the microcode read-only memory 234 does not need to provide a separate program for each different ISA instruction format, and a combination of various source and/or destination architecture registers 106, the microcode read-only memory 234 program can Contains fewer conditional branch instructions. For example, if the complex ISA instruction 124 is a memory format, the simple instruction translator 204 generates a logic programming of the microinstruction 244, which includes the microinstruction 244 that loads the source operand from the memory into a temporary register 106. And the micro-translator 237 generates microinstructions 246 for temporarily storing the results. The processor 106 stores to the memory; however, if the complex ISA instruction 124 is in the scratchpad format, the logic programming moves the source operand from the source register specified by the ISA instruction 124 to the temporary register, and the micro-translator 237 generates microinstruction 246 for moving the result from the temporary register to the architectural destination register 106 designated by the indirect instruction register 235. In one embodiment, the many aspects of the micro-translator 237 are similar to the application of U.S. Patent No. 12/766,244, filed on Apr. 23, 2010, which is incorporated herein by reference. However, the micro-translator 237 of this case has been modified to translate the ARM ISA instructions 124 in addition to the x86 ISA instructions 124.

It should be noted that the micro-program counter 232 is different from the ARM program counter 116 and the x86 command indicator 118, that is, the micro-program counter 232 does not hold the address of the ISA command 124, and the address held by the micro-program counter 232 is not Fall in the system memory address space. Moreover, more notably, the microinstructions 246 are generated by the hardware instruction translator 104 and are provided directly to the execution pipeline 112 for execution, rather than as an execution result 128 of the execution pipeline 112.

Please refer to FIG. 3, which illustrates the instruction formatter 202 of FIG. 2 in a block diagram. The instruction formatter 202 receives the x86 ISA and ARM ISA instruction byte 124 blocks from the instruction cache 102 of FIG. With the variable length of the x86 ISA instructions, the x86 instructions 124 can begin with any byte of the instruction byte 128 block. Since the x86 ISA allows the length of the first code byte to be affected by the current address length and the default length of the operand, the task of confirming the length and position of the x86 ISA instruction in the cache block is more complicated. In addition, according to the current ARM instruction set state 322 and the ARM ISA instruction 124 opcode, the length of the ARM ISA instruction is not A 2-byte is a 4-byte, so a 2-bit alignment is a 4-byte alignment. Thus, the instruction formatter 202 fetches different x86 ISA and ARM ISA instructions from the instruction byte 124 stream, which is formed by the block received by the instruction cache 102. That is, the instruction formatter 202 formats the x86 ISA and ARM ISA instruction byte strings, thereby greatly simplifying the difficult task of decoding and translating the ISA instructions 124 by the simple instruction translator of FIG.

The instruction formatter 202 includes a predecoder 302 that, when the instruction mode indicator 132 indicates x86, pre-decodes the instruction byte 124 as an x86 instruction byte to generate pre-decoded information, in the instruction When mode indicator 132 is indicated as ARM, predecoder 302 pre-decodes instruction byte 124 as an ARM instruction byte to generate pre-decoded information. Instruction byte array (IBQ) 304 receives the ISA instruction byte 124 block and associated pre-decode information generated by pre-decoder 302.

An array of length decoders and chopping logic gates 306 receives the contents of the bottom entry of the instruction byte array 304, i.e., the ISA instruction byte 124 block and associated pre-decode information. The length decoder and chopping logic gate 306 also receives the command mode indicator 132 and the ARM ISA instruction set state 322. In one embodiment, the ARM ISA instruction set state 322 includes the J and T bits of the ARM ISA CPSR scratchpad. In response to its input information, the length decoder and chop logic gate 306 generate decoded information including the length of the x86 and ARM instructions within the block of the ISA instruction byte 124, the x86 first code information, and the respective ISAs. An indicator of the instruction byte 124 indicating whether the byte is a start byte, a termination byte, and/or a valid bit of the ISA instruction 124 group. A multiplexer array 308 receives the ISA instruction byte 126 block, the associated pre-decode information generated by the predecoder 302, and the associated decoded information generated by the length decoder and the chop logic gate 306.

Control logic (not shown) examines the contents of the bottom item of the multiplexer queue (MQ) 308 and controls the multiplexer 312 to retrieve different, or formatted, ISA instructions and associated pre-decode and decode information. The information obtained is provided to a formatted command queue (FIQ) 314. The formatter command queue 314 acts as a buffer between the formatted ISA command 242 and the associated information provided to the simple instruction translator 204 of FIG. In one embodiment, multiplexer 312 retrieves up to three formatted ISA instructions and associated information in each clock cycle.

In one embodiment, the instruction formatting program 202 is similar in many respects to U.S. Patent Nos. 12/571,997, 12/572,002, 12/572,045, 12/572,024, issued October 1, 2009. The XIBQ, the instruction formatter, and the FIQ are disclosed in the application Serial No. 12/572,052, the disclosure of which is incorporated herein by reference. However, the XIBQ, the instruction formatter, and the FIQ are modified by the aforementioned patent application to enable formatting of the ARM ISA instructions 124 in addition to formatting the x86 ISA instructions 124. Length decoder 306 is modified to enable decoding of ARM ISA instructions 124 to produce length and start, end and validity byte metrics. In particular, if the command mode indicator 132 is indicated as an ARM ISA, the length decoder 306 detects the current ARM instruction set state 322 and the ARM ISA instruction 124 opcode to verify that the ARM instruction 124 is a 2-bit length or a 4-bit long. Degree of instruction. In one embodiment, the length decoder 306 includes a plurality of independent length decoders for generating the length data of the x86 ISA instructions 124 and the ARM ISA, respectively. The length information of the instructions 124, the outputs of these independent length decoders are coupled together in a wire-ORed manner to provide an output to the chopper logic gate 306. In one embodiment, the formatted command queue 314 includes separate queues to hold a plurality of separate portions of the formatted instructions 242. In one embodiment, the instruction formatter 202 provides a simple instruction translator 204 to at most three formatted ISA instructions 242 in a single clock cycle.

Referring to FIG. 4, the execution pipeline 112 of FIG. 1 is shown in detail in a block diagram. The execution pipeline 112 is coupled to the hardware instruction translator 104 to directly receive the hardware instruction translator 104 from FIG. Implement microinstructions. The execution pipeline 112 includes a microinstruction queue 401 for receiving the microinstruction 126; a register configuration table 402 for receiving the microinstruction by the microinstruction queue 401; an instruction scheduler 404 coupled to the register configuration table 402 A plurality of reservation stations 406 are coupled to the instruction scheduler 404; an instruction transmission unit 408 is coupled to the reservation station 406; a reorder buffer 422 is coupled to the register configuration table 402, the instruction scheduler 404, and Retention station 406; and execution unit 424 is coupled to reservation station 406, instruction transmission unit 408, and reorder buffer 422. The scratchpad configuration table 402 and the execution unit 424 receive the command mode indicator 132.

In the case where the hardware instruction translator 104 generates a rate at which the microinstruction 126 is executed differently than the execution pipeline 112 executes the microinstruction 126, the microinstruction queue 401 acts as a buffer. In one embodiment, the microinstruction queue 401 includes an M to N compressible microinstruction queue. The compressible microinstruction queue enables execution pipeline 112 to receive at most M (in one embodiment, M is six) microinstructions 126 from hardware instruction translator 104 for a given clock cycle, and subsequently The received microinstructions 126 are stored to a queue structure having a width N (in one embodiment, N is three) to provide for each clock cycle Up to N microinstructions 126 are provided to the scratchpad configuration table 402, which is capable of processing up to N microinstructions 126 per clock cycle. The microinstruction queue 401 is compressible because it will sequentially fill the empty items of the queue by the microinstruction 126 transmitted by the hardware instruction translator 104 regardless of the particular clock cycle in which the microinstruction 126 is received. Therefore, it will not leave a void in the queue project. An advantage of this method is that the execution unit 424 can be fully utilized (see Figure 4) because it provides higher instruction storage performance than an instruction array of incompressible width M or width M. In particular, a queue of incompressible widths N would require a hardware instruction translator 104, particularly a simple instruction translator 204, to repeatedly translate one or more already preceding clock cycles during subsequent clock cycles. The ISA instruction 124 that has been translated. The reason for this is that the queue of incompressible width N cannot receive more than N microinstructions 126 in the same clock cycle, and repeated translations will result in power loss. However, the incompressible width M column does not require a simple instruction translator 204 to repeatedly translate, but it creates a void in the queue item and wastes, thus requiring more columns and a larger and more energy-consuming flaw. Columns provide considerable buffering power.

The scratchpad configuration table 402 receives the microinstructions 126 from the microinstruction queue 401 and generates the associated information with the microinstructions 126 in progress in the microprocessor 100, the scratchpad configuration table 402 and performs a register rename operation to increase The ability of microinstructions to be processed in parallel to facilitate execution of the ultra-scalable, non-sequential execution capability of pipeline 112. If the ISA instruction 124 indicates x86, the register configuration table 402 will correspond to the x86 ISA register 106 of the microprocessor 100, generate the affiliate information and perform the corresponding register rename operation; otherwise, if the ISA command 124 indicates For ARM, the scratchpad configuration table 402 will be The affiliate information is generated by the ARM ISA register 106 of the microprocessor 100 and the corresponding scratchpad rename operation is performed; however, as previously described, the partial register 106 may be shared by the x86 ISA and the ARM ISA. The scratchpad configuration table 402 also configures an entry in the reorder buffer 422 in accordance with the program order for each microinstruction 126, so the reorder buffer 422 can cause the microinstruction 126 and its associated x86 ISA and ARM ISA instructions 124 to be programmed. Retiring sequentially, even if the execution of microinstruction 126 corresponds to the x86 ISA and ARM that it is intended to implement The ISA instruction 124 is performed in a non-sequential manner. The rearrangement buffer 422 includes a circular array of items for storing information about the in-progress microinstruction 126. The information includes, among other things, the microinstruction 126 execution status, a confirmation microinstruction. 126 is a tag translated by x86 or ARM ISA instructions 124 and a storage space for storing the results of microinstructions 126.

The instruction dispatcher 404 receives the scratchpad rename microinstruction 126 and the affiliate information from the scratchpad configuration table 402, and assigns the microinstruction 126 and its ancillary information to the appropriate one depending on the type of the instruction and the availability of the execution unit 424. Retention station 406 of execution unit 424. This execution unit 424 will execute the microinstruction 126.

For each microinstruction 126 that is waiting in the reservation station 406, the instruction issue unit 408 detects that the correlation execution unit 424 can be used and its ancillary information is satisfied (eg, the source operand can be used), ie, issues the microinstructions 126. Execution unit 424 is available for execution. As described above, the microinstructions 126 issued by the instruction issuing unit 408 can be executed in a non-sequential manner and in a super-scaling manner.

In an embodiment, execution unit 424 includes integer/branch unit 412, media unit 414, load/store unit 416, and floating point unit 418. Execution unit 424 executes microinstructions 126 to produce results 128 and provides them to reorder buffer 422. Although execution unit 424 is not greatly affected by the translation of microinstructions 126 that it executes by x86 or ARM ISA instructions 124, execution unit 424 will still use instruction mode indicator 132 and environment mode indicator 136 to perform relatively small. A subset of microinstructions 126. For example, execution pipeline 112 manages the generation of flags, the management of which is slightly different depending on the command mode indicator 132 indicating x86 ISA or ARM ISA, and the execution pipeline 112 is indicated by the command mode indicator 132 as x86 ISA or ARM ISA, for x86 The EFLAGS register or the ARM condition code flag in the Program Status Register (PSR) is updated. In another example, execution pipeline 112 samples instruction mode indicator 132 to determine whether to update x86 instruction index (IP) 118 or ARM program counter (PC) 116 or to update a common instruction address register. In addition, the execution pipeline 122 also uses this to determine the use of x86 or ARM semantics to perform the aforementioned actions. Once the microinstruction 126 becomes the oldest completed microinstruction 126 in the microprocessor 100 (i.e., in the top of the rearrangement buffer 422 queue and presents the completed state) and other to implement the associated ISA instruction 124 All microinstructions 126 have been completed and the reorder buffer 422 retires the ISA instruction 124 and releases the items associated with the microinstruction 126. In one embodiment, microprocessor 100 can retid up to three ISA instructions 124 in a clock cycle. An advantage of this processing method is that the execution pipeline 112 is a high performance, general purpose execution engine that can execute the microinstructions 126 of the microprocessor 100 microarchitecture supporting the x86 ISA and ARM ISA instructions 124.

Please refer to FIG. 5, which illustrates the register file 106 of FIG. 1 in a block diagram. In a preferred embodiment, the scratchpad file 106 is independent. The scratchpad block entity. In one embodiment, the general purpose register is implemented by a register file entity having a plurality of read and write ports; other registers can be physically separate from the general register file and other Adjacent function blocks that access these registers but have fewer read writes. In an embodiment, some non-general-purpose scratchpads, especially those that do not directly control the hardware of the microprocessor 100 and only store the values that the microcode 234 will use (such as partial x86 MSR or ARM collaboration) The processor register is implemented in a private random access memory (PRAM) accessible by the microcode 234. However, x86 ISA and ARM ISA programmers cannot see this private random access memory, which means that this memory is not in the ISA system memory address space.

In summary, as shown in FIG. 5, the scratchpad file 106 is logically divided into three types, namely, an ARM-specific register 502, an x86-specific register 504, and a shared register 506. In one embodiment, the shared scratchpad 506 includes fifteen 32-bit scratchpads shared by the ARM ISA scratchpads R0 through R14 and the x86 ISA EAX through R14D registers, with an additional sixteen 128 bits. The meta-register is shared by the x86 ISA XMM0 to XMM15 registers and the ARM ISA Advanced Single Instruction Multiple Data Extension (Neon) register, which is partially overlapped by thirty-two 32-bit ARM VFPv3 Floating point register. As described in Figure 1 above, the sharing of the general purpose register means that the value written by the x86 ISA instruction 124 to a shared register is seen by the ARM ISA instruction 124 when the shared register is subsequently read. vice versa. The advantage of this approach is that it enables the x86 ISA and ARM ISA programs to communicate with each other through the scratchpad. In addition, as mentioned above, the specific bits of the x86 ISA and ARM ISA architecture control registers can also be referenced as The shared register 506. As described above, in an embodiment, the x86 specific model register can be accessed by the ARM ISA instruction 124 through the implementation of the coprocessor register, thus by the x86 ISA and ARM. Shared by ISA. This shared scratchpad 506 can include non-architected scratchpads, such as non-architected equivalents of conditional flags, which are also renamed by the scratchpad configuration table 402. The hardware instruction translator 104 knows which register is shared by the x86 ISA and the ARM ISA, and thus executes the microinstruction 126 to access the correct register.

The ARM specific scratchpad 502 contains other scratchpads defined by the ARM ISA but not included in the shared scratchpad 506, while the x86 specific scratchpad 502 contains x86 ISA defined but not included in the shared scratchpad 506 other scratchpads. For example, the ARM-specific register 502 includes an ARM program counter 116, a CPSR, an SCTRL, an FPSCR, a CPACR, a coprocessor register, an alternate general-purpose register of various exception event modes, and a program state save register ( Saved program status registers, SPSRs) and more. The ARM-specific registers 502 listed above are not intended to limit the invention, but are merely illustrative to illustrate the invention. In addition, for example, the x86-specific register 504 includes x86 instruction indicators (EIP or IP) 118, EFLAGS, R15D, 64-bit R0 to R32 registers above the 32-bit (ie, not falling under the share) Part of the register 506), sector register (SS, CS, DS, ES, FS, GS), x87 FPU register, MMX register, control register (such as CR0-CR3, CR8) Wait. The x86 specific registers 504 listed above are not intended to limit the invention, but are merely illustrative to illustrate the invention.

In one embodiment, the microprocessor 100 includes a new implementation-defined ARM coprocessor register, indicated in the command mode indicator 132 as an ARM ISA. This implementation defines that the coprocessor register can be accessed to perform x86 ISA related operations. These operations include, but are not limited to, the ability to reset microprocessor 100 to an x86 ISA processor (reset to x86 instructions); initialize microprocessor 100 to an x86-specific state, switch command mode indicator 132 to x86 And begin to capture the ability of the x86 instruction 124 (boot to x86 instruction) on a particular x86 target address; the ability to access the aforementioned global configuration register; access to x86 specific registers (eg EFLAGS), This x86 register is specified in the ARM R0 register, accessing power management (such as P state and C state conversion), accessing processor bus functions (such as input/output cycles), and interrupt controller storage. Access and access to the encryption acceleration function. Moreover, in an embodiment, the microprocessor 100 includes a new x86 non-architectural specific model register that can be accessed to execute ARM when the instruction mode indicator 132 is indicated as an x86 ISA. ISA related operations. These operations include, but are not limited to, resetting the microprocessor 100 to an ARM The ability of the ISA processor (reset to ARM instructions); initializes the microprocessor 100 to an ARM-specific state, switches the instruction mode indicator 132 to ARM, and begins to fetch the ARM instruction 124 at a particular ARM target address (start The ability to access the ARM instruction); the ability to access the aforementioned global configuration register; the ability to access an ARM-specific register (such as the CPSR) specified in the EAX register.

Referring to Figures 6A and 6B, there is shown a flow chart illustrating the operation of the microprocessor 100 of Figure 1. This process begins in step 602.

As shown in step 602, the microprocessor 100 is reset. A reset signal can be sent to the reset input of microprocessor 100 to perform this reset action. Moreover, in an embodiment, the microprocessor bus is arranged in an x86 type The processor bus, this reset action can be performed by the x86 type of INIT command. In response to this reset action, the reset procedure of the microcode 234 is invoked to execute. The action of resetting the microcode includes: (1) initializing the x86 specific state 504 to a preset value specified by the x86 ISA; (2) initializing the ARM specific state 502 to a preset value specified by the ARM ISA; 3) Initializing the non-ISA-specific state of the microprocessor 100 to a preset value specified by the microprocessor 100 manufacturer; (4) initializing the shared ISA state 506, such as GPRs, to a preset value specified by the x86 ISA And (5) setting the command mode indicator 132 and the environmental mode indicator 136 to indicate the x86 ISA. In another embodiment, unlike the pre-launch actions (4) and (5), the reset microcode initializes the shared ISA state 506 to an ARM ISA-specific preset value and directs the command mode indicator 132 to the environmental mode indicator. 136 is set to indicate the ARM ISA. In this embodiment, the actions of steps 638 and 642 need not be performed, and prior to step 614, the reset microcode initializes the shared ISA state 506 to x86. The preset value specified by the ISA sets the command mode indicator 132 and the environmental mode indicator 136 to indicate the x86 ISA. Next, proceed to step 604.

At step 604, the reset microcode confirms that the microprocessor 100 is configured as an x86 processor or an ARM processor to boot. In one embodiment, as previously described, the preset ISA boot mode is hard coded in the microcode, but may be modified by blowing the fuse configuration or by using a microcode patch. In one embodiment, the preset ISA boot mode is provided as an external input to the microprocessor 100, such as an external input pin. Next, proceed to step 606. In step 606, if the preset ISA boot mode is x86, then step 614 is entered; otherwise, if the preset boot mode is ARM, then Will proceed to step 638.

In step 614, resetting the microcode causes microprocessor 100 to begin the x86 instruction 124 by the reset vector address specified by the x86 ISA. Next, proceed to step 616.

In step 616, the x86 system software (e.g., BIOS) configures the microprocessor 100 to use, for example, the x86 ISA RDMSR and WRMSR instructions 124. Next, proceed to step 618.

In step 618, the x86 system software executes an instruction 124 to reset to the ARM. This reset to ARM instruction causes the microprocessor 100 to reset and exit the reset procedure in the state of an ARM processor. However, because the x86 specific state 504 and the non-ISA specific configuration state are not changed by the instruction 126 reset to the ARM, this approach facilitates the x86 system firmware to perform the preliminary setup of the microprocessor 100 and the microprocessor 100 It is then rebooted in the state of the ARM processor, while still allowing the non-ARM configuration of the microprocessor 100 executed by the x86 system software to remain intact. In this way, the method can use the "small" micro boot code to execute the boot process of the ARM operating system without using the micro boot code to solve the complicated problem of how to configure the microprocessor 100. In one embodiment, this reset to the ARM instruction is an x86WRMSR instruction to a new non-architectural specific model register. Next, proceed to step 622.

At step 622, the simple instruction translator 204 enters the trap to reset the microcode in response to a complex reset to ARM (complex reset-to-ARM) instruction 124. This reset microcode initializes the ARM specific state 502 to a preset value specified by the ARM ISA. However, resetting the microcode does not modify the non-ISA specific state of the microprocessor 100, thereby facilitating the saving of step 616. Required configuration settings. In addition, resetting the microcode causes the shared ISA state 506 to be initialized to a preset value specified by the ARM ISA. Finally, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the ARM ISA. Next, proceed to step 624.

In step 624, resetting the microcode causes microprocessor 100 to begin fetching ARM instruction 124 at the address specified by the x86 ISA EDX:EAX register. The process ends at step 624.

In step 638, the reset microcode will share the ISA state 506, such as GPRs, to the preset value specified by the ARM ISA. Next, proceed to step 642.

In step 642, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the ARM ISA. Next, proceed to step 644.

In step 644, resetting the microcode causes the microprocessor 100 to begin fetching the ARM instruction 124 at the reset vector address specified by the ARM ISA. This ARM ISA defines two reset vector addresses and can be selected by an input. In one embodiment, microprocessor 100 includes an external input to select between two ARM ISA defined reset vector addresses. In another embodiment, the microcode 234 includes a preset selection between two ARM ISA defined reset vector addresses, which may be modified by a blow fuse and/or a microcode patch. Next, proceed to step 646.

In step 646, the ARM system software sets up the microprocessor 100 to use specific instructions, such as the ARM ISA MCR and MRC instructions 124. Next, proceed to step 648.

In step 648, the ARM system software executes a reset 124 to x86 instruction to reset the microprocessor 100 to an x86 processor state. Leave the reset program. However, because the ARM-specific state 502 and the non-ISA-specific configuration state are not changed by the instruction 126 reset to x86, this approach facilitates the ARM system firmware to perform the preliminary setup of the microprocessor 100 and the microprocessor 100 It is then rebooted in the state of the x86 processor while still maintaining the non-x86 configuration of the microprocessor 100 executed by the ARM system software intact. In this way, the method can use the "small" micro boot code to execute the boot process of the x86 operating system without using the micro boot code to solve the complicated problem of how to configure the microprocessor 100. In one embodiment, this reset to the x86 instruction is an ARM MRC/MRCC instruction to a new implementation-defined coprocessor register. Next, proceed to step 652.

In step 652, the simple instruction translator 204 enters the trap to reset the microcode in response to the complex reset to x86 instruction 124. Resetting the microcode initializes the x86 specific state 504 to the preset value specified by the x86 ISA. However, resetting the microcode does not modify the non-ISA specific state of the microprocessor 100, which facilitates saving the configuration settings performed at step 646. In addition, resetting the microcode causes the shared ISA state 506 to be initialized to a preset value specified by the x86 ISA. Finally, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the x86 ISA. Next, proceed to step 654.

In step 654, resetting the microcode causes microprocessor 100 to begin fetching ARM instruction 124 at the address specified by the ARM ISA R1:R0 register. This process ends at step 654.

Referring to Figure 7, a dual core microprocessor 700 of the present invention is illustrated in a block diagram. The dual core microprocessor 700 includes two processing cores 100, each of which includes components of the microprocessor 100 of FIG. 1, whereby each core can execute x86 ISA and ARM ISA machines. Language program. These cores 100 can be configured such that both cores 100 execute x86 ISA programs, both cores 100 execute ARM ISA programs, or one core 100 executes x86 ISA programs and the other core 100 executes ARM ISA programs. During the operation of the microprocessor 700, the aforementioned three settings may be mixed and dynamically changed. As described in the description of FIG. 6A and FIG. 6B, each core 100 has a preset value for its command mode indicator 132 and the environment mode indicator 136, and the preset value can be modified by using fuse or microcode patching. Thereby, each core 100 can be independently changed to an x86 or ARM processor through a reset. Although the embodiment of Figure 7 has only two cores 100, in other embodiments, the microprocessor 700 can have more than two cores 100, and each core can execute x86 ISA and ARM ISA machine language programs.

Referring to FIG. 8, a block diagram of a microprocessor 100 emulating an x86 ISA and ARM ISA machine language program according to another embodiment of the present invention is illustrated. The microprocessor 100 of Fig. 8 is similar to the microprocessor 100 of Fig. 1, in which the component numbers are similar. However, the microprocessor 100 of FIG. 8 also includes a microinstruction cache 892 that accesses the microinstructions 126 generated by the hardware instruction translator 104 and provided directly to the execution pipeline 112. The microinstruction cache 892 is indexed by the retrieved address generated by the instruction fetch unit 114. If the capture address 134 hits the microinstruction cache 892, the multiplexer (not shown) in the execution pipeline 112 selects the microinstruction 126 from the microinstruction cache 892 instead of the microinstruction translator 104. Instruction 126; conversely, the multiplexer selects microinstructions 126 that are provided directly by hardware instruction translator 104. Micro-instruction cache operations, also commonly referred to as trace caches, are techniques known in the art of microprocessor design. Surgery. The advantage of microinstruction cache 892 is that the time required to retrieve microinstruction 126 by microinstruction cache 892 is typically less than the instruction fetch 124 by instruction fetch 102 and is translated using a hardware instruction interpreter. The time for the microinstruction 126. In the embodiment of Figure 8, the microprocessor 100 is executing x86 or ARM. In the ISA machine language program, the hardware instruction translator 104 does not need to perform a hardware translation every time the x86 or ARM ISA instruction 124 is executed, that is, when the micro instruction 126 is already present in the micro instruction cache 892, it is not required. Perform hardware translations.

An advantage of an embodiment of the microprocessor described herein is that it can execute x86 ISA and ARM ISA through a built-in hardware instruction translator to translate x86 ISA and ARM ISA instructions into microinstructions of the microinstruction set. A machine language program that differs from the x86 ISA and ARM ISA instruction sets, and the microinstructions can be executed using a shared execution pipeline of the microprocessor to provide execution microinstructions. An advantage of the embodiment of the microprocessor described herein is that the microprocessor is designed and manufactured by cooperatively utilizing a large number of ISA-independent execution pipelines to execute micro-instructions that are hard-translated by x86 ISA and ARM ISA instructions. The resources required are less than two independently designed microprocessors (that is, one capable of executing an x86 ISA machine language program, one capable of executing an ARM ISA machine language program). Moreover, embodiments of these microprocessors, particularly those using ultra-pure non-sequential execution pipelines, have the potential to provide higher performance than existing ARM ISA processors. In addition, embodiments of these microprocessors offer greater potential for higher performance in x86 and ARM implementations than systems employing software interpreters. Finally, since the microprocessor can execute x86 ISA and ARM ISA machine language programs, this microprocessor is conducive to constructing a A system that efficiently executes x86 and ARM machine language programs simultaneously. Control corresponds to the status register

As described above, the configuration register 122 of FIG. 1 controls the operation of the microprocessor 100 in a different manner. The configuration register 122 described herein is also a control and status register 122. Typically, but not exclusively, the control and status register 122 is read and written by the system firmware (e.g., BIOS) and system software (e.g., an operating system) to configure the desired microprocessor 100.

The x86 ISA provides a generic mechanism for accessing control and status registers. In the x86 ISA, many control and status registers are called specific model registers, which can be read via a specific model register (Read MSR; RDMSR) and write to a specific model register (Write MSR; WRMSR) instructions to read and write. Specifically, the RDMSR instruction reads the contents of the 64-bit specific model register to the EDX:EAX register, and the address of the 64-bit specific model register is specified in the ECX register; The WRMSR instruction writes the contents of the EDX:EAX register to the 64-bit specific model register, and the address of the 64-bit specific model register is specified in the ECX register. The specific model register address is defined by the microprocessor manufacturer.

Advantageously, embodiments of the present invention provide a mechanism for an ARM ISA program to access the x86 specific model register 122 of the microprocessor 100 of FIG. In particular, microprocessor 100 uses an ARM ISA coprocessor register mechanism to access x86 specific model registers 122.

Moving from the coprocessor to the ARM register from the Coprocessor (MRC) and moving from the coprocessor to the two ARM registers (Move to two ARM Registers from In the Coprocessor; MRRC) instruction, the contents of the coprocessor (CP) are respectively moved to one or two 32-bit general-purpose registers. From the ARM to Coprocessor from ARM Register (MCR) instruction, and from the Move to Coprocessor from two ARM Registers (MCRR) instructions, Move the contents of one or two 32-bit general purpose registers to a coprocessor (CP). The coprocessor is identified by a coprocessor number. Advantageously, when an MCR/MCRR/MRC/MRRC instruction 124 specifies a preset implementation-defined ARM When the ISA co-operates with the coprocessor register of the processor scratchpad space, the microprocessor 100 knows that the instruction 124 instructs it to access (e.g., read and write) the particular model register 122. In one embodiment, the specific model register 122 address is specified in a preset ARM ISA general purpose register. The specific model register 122 of the microprocessor 100 as described above and disclosed herein is a method shared by the x86 ISA and ARM ISA, as will be described in more detail later.

Embodiments including controlling the operation mode of the microprocessor 100 by the specific model register 122 include, but are not limited to, memory sort buffer control and status, page fault code, clear page directory cache memory, and backup buffer entry Controlling different cache memories in the memory layer of the microprocessor 100, such as invalidating some or all of the caches, removing power from some or all of the caches, and invalidating the cache tags; microcode patching Mechanism control; debug control, processor bus control; hardware data and instruction prefetch control; power management control, such as sleep and wake-up control, P-state and C-state transition, and clock or power supply for various function blocks Invalidation Control and status, error correction code memory error status; bus line check error status; thermal management control and status; service processor control and status; inter-core communication; inter-chip communication; Function; voltage regulator (VID) control of voltage regulator module; phase-locked loop control; cache snoop control, combined write buffer control and state; overclocking function control; interrupt controller control and state; temperature sensing Control and state; enable multiple functions to be enabled or disabled, such as encryption/decryption, specific model register protection passwords, parallel requirements for L2 cache and processor bus (making parallel Requests); individual branch prediction functions, instruction merging, microinstruction timeouts, execution counters, store forwarding, and speculative tablewalks; loading queue size; cache memory size; Access to undefined specific model registers that have been processed; and multi-core configuration. These methods are common to the operation of the microprocessor 100, for example they are not specific to the x86 ISA and ARM ISA. That is, despite the special ISA indicated by the instruction mode indicator 132, the operation of the general purpose microprocessor still affects the processing of the instructions. For example, controlling the bits in the scratchpad will determine the configuration of the cache memory, such as deselecting the corrupted rows of bit cells in the cache memory, and using the redundant rows of the bit cells. To replace it. For all ISAs, such a cache configuration can affect the operation of the microprocessor 100, and thus the operation of the microprocessor is universal. Other implementations, such as the general purpose microprocessor 100, operate in a phase-locked loop duty cycle and/or clock ratio of the microprocessor 100, and are set voltage identification symbol pins, while the set voltage identification symbol pins are for micro processing. The device 100 controls the voltage source. In general, the ARM ISA instruction 124 accesses the generic The particular model register 122 is by way of a specific model register 122 that is not designated by x86.

As described above, in one embodiment, the microprocessor 100 is an enhanced version of a commercial microprocessor that can execute x86 ISA programs and, more particularly, can execute x86 ISA RDMSR/WRMSR instructions. A particular model register 122 is accessed. Commercial microprocessors are enhanced in accordance with the access of the particular model register 122 provided by the embodiments herein to the ARM ISA program. In one embodiment, the complex instruction translator 206 of FIG. 2 uses the read only memory instruction 247 output via the microcode read only memory 234 to generate the microinstruction 126 to execute the RDMSR/WRMSR instruction. An advantage of such an embodiment is that when the ARM ISA MRC/MRRC/MCR/MCRR instructions are added to access the functions of a particular model register general control and status register, only the existing x86 ISA RDMSR/WRMSR instruction access is required. The microcode 234 of the above-described specific model register general control and status register function may add a relatively small number of microcodes 234.

Please refer to FIG. 9, which is a block diagram for describing in detail the microprocessor 100 accessing the specific model register of the microprocessor 100 of FIG. 1 by starting the x86 ISA and ARM ISA programs. A plurality of 64-bit specific model registers 122 have been disclosed in the figure, each particular model register 122 having a different specific model register address (eg, 0x1110, 0x1234, 0x2220, 0x3330, 0x4440). As noted above, the particular model register 122 can be considered a portion of the first map register file 106.

Figure 9 shows the x86 ISA program, specifically the RDMSR/WRMSR instruction 124, when the command mode indicator 132 indicates x86 In ISA, the x86 ISA program accesses a register in a particular model register 122. In the embodiment of Figure 9, the particular model register 122 as an access has the address 0x1234. Thus, as specified by the x86 ISA, the particular model register 122 address value has been stored in the x86 ECX register 106 by the x86 program prior to the RDMSR/WRMSR instruction 124. Furthermore, in the case of the RDMSR instruction 124, as specified by the x86 ISA, the microprocessor 100 reads the 64-bit data value from the specific model register 122 of address 0x1234 and then copies it to the x86 EDX: EAX register. 106. In the case of the WRMSR instruction 124, as specified by the x86 ISA, the microprocessor 100 copies the 64-bit data value in the x86 EDX:EAX register 106 to the particular model register 122 at address 0x1234. .

Figure 9 also shows the ARM ISA program, specifically the MRRC/MCRR instruction 124. When the command mode indicator 132 indicates the ARM ISA, the x86 ISA program accesses the scratchpad with the address 0x1234 in the particular model register 122. The specific model register 122 address value 0x1234 has been stored in the ARM R1 register 106 by the ARM program prior to the MRRC/MCRR instruction 124. Moreover, in the case of the MRRC instruction 124, the microprocessor 100 reads the 64-bit data value from the particular model register 122 of address 0x1234 and then copies it to the ARM R2:R0 register 106; and at the MCRR instruction 124 In the case of the microprocessor 100, the 64-bit data value in the ARM R2:R0 register 106 is copied to the particular model register 122 at address 0x1234. The MRRC/MCRR instruction 124 specifies a predetermined ARM coprocessor number. In an embodiment, the preset ARM coprocessor number is 4. The MRRC/MCRR instruction 124 also specifies a predetermined ARM scratchpad number. In an embodiment, the preset The ARM scratchpad number is (0, 7, 15, 0), which represents the values of the CRn, opc1, CRm, and opc2 fields, respectively. In the case of the MRC/MCR command 124 and the case of the MRRC/MCRR command 124, the opc1 column is 7 and the CRm column is 15. In one embodiment, if the ARM ISA instruction 124 is an MRC or MCR instruction, then only the lower 32 bits (lower 32 bits) than the specified 64-bit specific model register are read and written.

In one embodiment, as described above, the general purpose register defined by the x86 ISA and the ARM ISA is an example of a physical register of the scratchpad file 106. In an embodiment, the correspondence is as shown in the following table.

<tables><img id="" he="887" wi="477" file="twi474191b_d0015.tif" alt="" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

The correspondence shown in the above table can be observed that the ARM R1 register corresponds to the x86 ECX register, and the ARM R2:R0 register corresponds to the x86 EDX:EAX register. The advantage is that the microcode 234 can be simple. Chemical.

Although it can be understood from the above disclosed embodiments that the R1 register is a preset ARM register and is used to specify a specific model register 122 address, other methods are used to specify a specific model temporary storage. 122 bits Embodiments of the address are also contemplated in the present invention, such as, but not limited to, another general purpose register being a preset scratchpad or specifying a scratchpad at the MRRC/MCRR instruction 124 itself. Similarly, although the above embodiment discloses that the R2: R0 register is a preset ARM register and is used to process data, in other conceivable embodiments, the register for processing data is borrowed. Embodiments specified by other means are also contemplated by the present invention, such as, but not limited to, other general purpose registers being preset registers or specifying registers in the MRRC/MCRR instruction 124 itself. In addition, although the above embodiment discloses that the scratchpad (0, 7, 15, 0) of the coprocessor 4 is a preset ARM coprocessor register and is used to access the specific model register 122, but other In the conceivable embodiment, another predetermined ARM coprocessor register is also considered by the present invention. Finally, although the above embodiments disclose the universal register shared entity register files of the x86 ISA or ARM ISA, they are not shared with each other, or other embodiments that are different from the foregoing are also considered by the present invention.

Referring to FIG. 10, FIG. 10 is a flow diagram depicting instructions 124 of microprocessor 100 of FIG. 1 for accessing a particular model register 122.

In step 1002, the microprocessor 100 retrieves an ISA command 124 and provides it to the hardware command translator 104 of FIG. 1, and then proceeds to step 1004.

In step 1004, if the command mode indicator 132 indicates the x86 ISA, then step 1012 is performed, and if the command mode indicator 132 indicates the ARM ISA, then step 1022 is performed.

In step 1012, the x86 simple instruction translator 222 of FIG. 2 encounters the x86 ISA RDMSR/WRMSR instruction 124 and enters the trap. The complex instruction translator 206 of Figure 2 is shown. In particular, the simple instruction translator 204 provides the microcode address 252 to the microprogram counter 232, which enters the routine for processing the RDMSR/WRMSR instruction 124 in the microcode read only memory 234. The entry point. Then step 1014 is performed.

In step 1014, complex instruction translator 206 utilizes microcode read-only memory instructions 247 that process routines of RDMSR/WRMSR instruction 124 to generate microinstructions 126 to execute RDMSR/WRMSR instructions 124. Figure 11 shows the virtual code of the microcode 234 routine for processing the RDMSR/WRMSR instruction 124. As shown in Figure 11, TEMP1 and TEMP2 refer to temporary (eg, non-architectural) 64-bit scratchpads that are used to store temporary values. Then step 1016 is performed.

In step 1016, execution pipeline 112 executes microinstructions 126 generated at step 1014 to execute RDMSR/WRMSR instructions 124. That is, in the case of the RDMSR instruction 124, the microinstruction 126 copies the value in the particular model register 122 to the EDX:EAX register, and the address of the particular model register 122 is from the ECX register. Specified; conversely, in the case of the WRMSR instruction 124, the microinstruction 126 copies the value in the EDX:EAX register to the particular model register 122, and the address of the particular model register 122 is temporarily Specified by the register. It ends after step 1016 is performed.

In step 1022, the ARM Simple Instruction Translator 224 of Figure 2 encounters the ARM ISA MRRC/MCRR instruction 124 and enters the trap to the Complex Instruction Translator 206. In particular, the simple instruction translator 204 provides the microcode address 252 to the microprogram counter 232, which is tied to An entry point in the microcode read-only memory 234 for processing the routine of the MRRC/MCRR instruction 124. Then step 1024 is performed.

In step 1024, complex instruction translator 206 utilizes microcode read-only memory instructions 247 that process routines of RDMSR/WRMSR instruction 124 to generate microinstructions 126 to execute MRRC/MCRR instructions 124. Figure 11 also shows the virtual code of the microcode 234 routine for processing the RDMSR/WRMSR instruction 124. As shown in FIG. 11, the common subroutine (RDMSR_COMMON) can be called by both the microcode program for processing the RDMSR instruction 124 and the microcode program for processing the WRMSR instruction 124. Similarly, the common subroutine (WRMSR_COMMON) can be used to process both the microcode routine of the MCRR instruction 124 and the microcode routine used to process the WRMSR instruction 124. This has its advantages because a large number of operations can be performed by a common subroutine, so that only a relatively small number of microcodes 234 are needed to support ARM. MRRC/MCRR instruction 124. In addition, the routine for processing the MRRC/MCRR instruction 124 is used to determine that a preset coprocessor number has been specified (eg, coprocessor 4) and that a preset coprocessor register address has been specified ( For example, (0,7,15,0)), otherwise, the microcode will branch to the routine that handles access to other registers, such as non-specific model registers, coprocessor registers. In one embodiment, the program also determines that the microprocessor 100 is not in the ARM ISA user mode; otherwise, the microcode will generate an exception. In addition, the routine determines that the function of launching the ARM ISA program to access the particular model register 122 has been initiated; otherwise, the microcode treats the MRRC/MCRR instruction 124 as not performing any operations. Then step 1026 is performed.

In step 1026, execution pipeline 112 is executed at step 1014. The microinstruction 126 is executed to execute the MRRC/MCRR instruction 124. That is, in the case of the MRRC instruction 124, the microinstruction 126 copies the value in the particular model register 122 to the R2:R0 register, and the address of the particular model register 122 is in the R1 register. Internally, conversely, in the case of the MCRR instruction 124, the microinstruction 126 copies the value in the R2:R0 register to the particular model register 122, and the address of the particular model register 122 is at R1. The scratchpad is specified. It ends after step 1026 is performed.

Although the embodiment of the MRRC/MCRR instruction 124 has been disclosed in Figures 9 through 11, the embodiment described above further provides the functionality of the ARM MCR/MRC instruction 124 to access the lower 32 bits of the particular model register 122. . Further, although the embodiment has disclosed that the particular model register 122 is accessed via the MRRC/MCRR/MCR/MRC instruction 124, other embodiments, such as using the ARM ISA LDC/STC instruction 124, access specific Model register 122 is also contemplated in the present invention. That is, the data is read from memory or stored in memory rather than from the ARM ISA Universal Scratchpad (read or stored).

It will be appreciated from the foregoing that an embodiment of the present invention provides an efficient mechanism for the ARM ISA program to access a particular model register 122 of the microprocessor 100. In other conceivable embodiments, each particular model register 122 has its own coprocessor register number, and the coprocessor register number is MRRC/MCRR in the ARM ISA coprocessor register space. The opc1 and CRm fields are specified. A disadvantage of this embodiment is that a relatively large number of registers may be consumed in the ARM ISA coprocessor register space. In addition, it may be necessary to significantly expand the existing microcode, which will consume the effective in the microcode read-only memory 234. space. In one such embodiment, the ECX value (or at least the lower bit) is broken up into pieces and distributed to the opc1 and CRm fields. The microcode combines the fragments into the original ECX values.

However, various embodiments of the present invention have been described in detail herein, and it should be fully understood how to implement and not be limited to these embodiments. Various other modifications and changes can be made by those skilled in the art in the light of the above-described embodiments of the invention. For example, the software can initiate devices and methods as described herein, such as function, manufacture, model, simulation, description, and/or testing. This can be achieved by using general programming languages (such as C and C++), Hardware Description Languages (HDL), or other available programs. Hardware Description languages (HDL) include Verilog. Hard description language such as HDL, VHDL. Such software can be executed in any known computer usable medium, such as tape, semiconductor, disk or optical disc (such as CD-ROM and DVD-ROM), network, cable, wireless network or other communication medium. . Embodiments of the apparatus and method described herein may be included in a smart core semiconductor and converted into hardware of an integrated circuit product, such as a microprocessor core (such as in a hardware description language) Implementation or setting). Furthermore, the devices and methods described herein can be implemented by a combination of hardware and software. Therefore, the present invention is not limited to the embodiments of the invention, but is defined by the scope of the following patents and equivalents. In particular, the present invention can be implemented in a commonly used microprocessor device. In the end, it will be appreciated that those skilled in the art will be able to devise themselves on the basis of the concept and the specific embodiments disclosed herein, and without departing from the scope of the invention. Other structures are carried out with the same purpose as the present invention.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

<p>100Microprocessor (Processing Core)</p><p>102 instruction cache</p><p>104 hardware instruction translator</p><p>106Scratch file</p><p>108 memory subsystem</p><p>112Execution pipeline</p><p>114Command Capture Unit and Branch Predictor</p><p>116ARM Program Counter (PC) Register</p><p>118x86 instruction index (IP) register</p><p>122Configuration register</p><p>124ISA Directive</p><p>126 microinstructions</p><p>128 Results</p><p>132instruction mode indicator</p><p>134Select address</p><p>136Environment mode indicator</p><p>202Instruction Formatter</p><p>204Simple Instruction Translator (SIT)</p><p>206Complex Instruction Translator (CIT)</p><p>212Multiplexer (mux)</p><p>222x86 Simple Instruction Translator</p><p>224ARM Simple Instruction Translator</p><p>232micro-program counter (micro-PC)</p><p>234microcode read-only memory</p><p>236microprogrammer (microsequencer)</p><p>235Instruction indirection register (IIR)</p><p>237microtranslator</p><p>242Format ISA instructions</p><p>244implementing microinstructions</p><p>246 Micro-instructions</p><p>248Select input</p><p>252 microcode address</p><p>254Read-only memory address</p><p>255ISA Command Information</p><p>302Pre-decoder</p><p>304Command byte array (IBQ)</p><p>306length decoders and ripple logic</p><p>308Multiplexer queue (mux queue, MQ)</p><p>312Multiplexer</p><p>314formatted instruction queue (FIQ)</p><p>322ARM instruction set status</p><p>401Micro-instruction queue</p><p>402register allocation table (RAT)</p><p>404instruction dispatcher</p><p>406reservation station</p><p>408instruction issue unit</p><p>412integer/branch unit</p><p>414media unit</p><p>416Load/store unit</p><p>418floating point unit</p><p>422reorder buffer (ROB)</p><p>424 execution unit</p><p>502ARM specific register</p><p>50486 specific register</p><p>506Shared register</p>

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an embodiment of a microprocessor embodying an x86 program set architecture and an ARM program set architecture machine language program.

Figure 2 is a block diagram showing the hardware command translator of Figure 1 in detail.

Figure 3 is a block diagram showing the instruction formatter of Figure 2 in detail.

Figure 4 is a block diagram showing the execution pipeline of Figure 1 in detail.

Figure 5 is a block diagram showing the scratchpad file of Figure 1 in detail.

Figure 6A is a flow chart showing the operational steps of the microprocessor of Figure 1.

Figure 6B is a flow chart showing the operational steps of the microprocessor of Figure 1.

Figure 7 is a block diagram of a dual core microprocessor of the present invention.

Figure 8 is a block diagram of another embodiment of a microprocessor embodying the x86 ISA and ARM ISA machine language programs of the present invention.

Figure 9 is a block diagram showing in detail the microprocessor accessing the specific model register of the microprocessor of Figure 1 by booting the x86 ISA and ARM ISA programs.

Figure 10 is a flow chart showing the instructions of the microprocessor of Figure 1 for accessing a particular model register.

Figure 11 is a schematic diagram of the instructions for accessing a particular model register by the virtual code processing of the microcode.