Multi-core microprocessor internal bypass bus

Internal bypass busbar for core processor

Multi-Core Microprocessor Internal Bypass Bus

[References in related applications]

The application of the priority of the present application is based on the U.S. Patent Provisional Application No. 61/426,470, filed on Dec. 12/22/2010, the name of the multi-core bypass bus (MULTI-CORE INTERNAL BYPASS BUS) The case as a whole is included in the case.

This application has the same filing date as the following US patent application filed in the same application, and each application is incorporated by reference in its entirety.

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The present invention relates to multi-core microprocessors, and more particularly to signal quality on a bus that is shared by multiple cores.

When one of the plurality of cores drives the processor bus, the inventors of the present invention observe that the quality of the signals received by the other cores of the multi-core microprocessor from the processor bus is unreliable, and the system is unreliable. All cores of the core microprocessor share a chipset by the processor bus, as detailed in Figures 1 and 2 below. Therefore, there is an urgent need for a method to solve the problem of poor signal quality.

In one embodiment, the present invention provides a microprocessor having a multi-core wafer. The wafer has a plurality of cores and the output signal of the core is coupled to the contact pads of the wafer. The wafer system is mounted on a package for coupling the contact pads of the wafer (and other wafers) to the pins of the package. The pins of the package couple the package to a processor bus, and the processor bus is coupled to a chip set.

The wafer has a bypass bus to enable complementary processing cores or complementary dual core pairs of the multi-core wafer to bypass the processor bus and to communicate directly with other cores. Here, "complementary" means that the core or dual core pair of the wafer is connected by a bypass bus. The bypass bus has a plurality of routing networks disposed on the wafer, and the routing network passes the complex output signals from each core or dual core pair to its corresponding complementary core or complementary dual core pair input. The bypass bus is isolated from the contact pads of the wafer or the pins of the multi-core microprocessor via the isolation of the intermediary bus interface logic, so the bypass bus does not transmit signals to the outside of the dual core wafer. In addition, the bypass bus line isolates the noise on the corresponding processor bus line by the protection of the intermediary bus interface logic.

In another embodiment, the bypass bus bar provides a bus bar corresponding to each processor bus bar. In each bypass processor bus line, a first one-way bypass bus line is used to provide signals from a first core (or first dual core pair) to a complementary second core (or second pair) The core pair), a second one-way bypass bus line is used to provide signals from the second core (or the second dual core pair) to the first core (or the first dual core pair).

In another embodiment, each core includes a bus interface circuit for improving bypass bus communication through the bypass line. In a typical processor bus communication, each core is coupled to a corresponding processor bus line to drive an output signal to the processor bus line or receive an input signal from the processor bus line. In order to improve two-way communication, the core bus interface circuit provides intermediate input and output bus line interface logic to couple the input and output signals of each core to the corresponding chip input/output contact pads.

In another embodiment, the intermediate output logic includes a busbar interface transistor coupled to the output signal line of the core. In another embodiment, a dual core pair shared chip input/output contact pad is output by performing a Boolean operation (such as OR) on the output signal of the dual core pair. The mediation input logic includes a bus line interface multiplexer for receiving, at its input, a chip drive signal on a corresponding processor bus line and a corresponding output signal of one of the same core or the same pair of cores.

In another embodiment, the bypass bus is coupled to the complementary core or dual core pair by wires or wires at each end point, wherein the ends of the wires or wires are coupled to the output or input signals of the core or dual core pairs. The line and the intervening bus interface interface logic, and the intervening bus line interface is logically coupled to the output or input signal line to the corresponding physical input/output contact pad. In another embodiment, the input end of each bypass bus line is coupled to the gate of the corresponding bus line interface transistor, and the output end of each bypass bus line is coupled to the corresponding bus line interface multiplexer. Input. The transistor and the multiplexer temporarily store the input and output signals from the bypass bus line of the corresponding processor bus.

In another embodiment, the present invention also provides a method of intercore communication of a multi-core chip. A bus interface of a core or dual core pair receives signals from a processor bus that connects the multi-core chip to the chipset, and a complementary core or dual core pair from the corresponding connected core or dual core pair to the multi-core chip (via bypass The signal of the corresponding bypass busbar connected to the busbar. The bypass bus does not transmit signals to the outside of the chip or receives the chipset drive signals from the processor bus, nor does it drive the signals on the processor bus to the chipset. One of the core or dual core pairs detects whether a core of the chipset or complementary core or complementary dual core pair is driving the processor bus. When a core of a complementary core or complementary dual core pair is driving a processor bus, the bus interface selects a signal from the bypass bus instead of a signal from the processor bus to drive the corresponding core input.

In another embodiment, each complementary core or dual core pair on a multi-core semiconductor wafer includes a complex intervening input logic multiplexer. Each of the mediation input logic multiplexers receives a control input signal and a plurality of selectable input signals and provides an output signal. A first selectable input is coupled to a corresponding one of the plurality of contact pads of the core, the corresponding contact pads being coupled to the processor bus. A second selectable input is coupled to the output of the core, and in the dual core pair, the output of the core is coupled to a Boolean logic. A third selection input is coupled to a corresponding bypass bus line for transmitting an output signal from the complementary core or a pair of cores, and one of the multiplexer selectable inputs is passed to the core. A control input is used to cause the multiplexer to select which one to use as its output. When the chipset drives the processor bus, the multiplexer selects the first input as its output. When the core or dual core pair drives the processor bus, the multiplexer selects the second input as its output. When one of the complementary core or complementary dual core pairs drives the processor bus, the multiplexer selects the third input as its output. The multiplexer output is coupled to the respective input signal lines of the transmit signal to the core or dual core pair.

In addition, each core or dual core pair includes a complex intermediate output logic transistor, and each of the intermediate output logic transistors has a gate, a source, and a drain. The source is grounded and the drain is coupled to the corresponding one of the input/output contact pads of the core or dual core pair. The gate is coupled to the output signal line of the core and driven by the output signal line of the core. In an embodiment of the dual core pair, the gate is coupled to an operational output signal line that performs a Boolean operation (eg, OR). The gate is further coupled to the second selection input of the corresponding intermediate output logic transistor, and coupled to the third selection input of the intermediate output logic transistor of the complementary core (or dual core pair) through the bypass bus line.

In order to solve the above problem of poor signal quality in a multi-core microprocessor, the inventors provide an internal bypass bus between two cores of a dual core microprocessor according to an embodiment, and in a quad core according to another embodiment An internal bypass bus is provided between the four cores of the microprocessor. However, a typical dual core microprocessor is described herein first to make the embodiments of the present invention easier to understand.

Figure 1 is a schematic illustration of an electronic system 100 including a conventional dual core microprocessor package. The electronic system 100 has a dual core microprocessor package that is coupled to the chip set 144 by a processor bus 142. The dual core microprocessor 102 has two processing cores, core 0 106A and core 1 106B, collectively referred to as core 106. Wafer set 144 includes known circuitry such as a memory controller for controlling system memory and a bus bridge for bridging processor bus 142 to surrounding busses such as ISA, PCI, PCI-Express, and the like.

Core 0 106A and core 1 106B each include a plurality of blocks for executing instructions of a stored program, such as an instruction fetch unit, an instruction decode unit, a general purpose and special purpose register, an address generation unit, and a fast The memory, the execution unit, the retire unit, and the bus interface are used as the interface between the core and the processor bus 142. Core 106 has a variety of architectural features, such as sequential or non-sequential execution, scalar or super-scalar architecture, complex instruction set computer (CISC) giant structure or reduced instruction set computer (RISC) micro structure.

As shown, core 0 106A and core 1 106B are each located on a separate semiconductor wafer 104, while two wafers 104 of dual core microprocessor 102 are included in a single package. Core 0 106A and core 1 106B each include a plurality of contact pads 108 for transmitting signals from core 0 106A and core 1 106B internal circuitry to processor bus 142, and signals from processor bus 142 Transfer to core 0 106A and core 1 106B. The contact pad of core 0 106A is contact pad 108A, core 1 The contact pad of 106B is contact pad 108B. The dual core microprocessor package includes a substrate on which the wafer 104 is located, the substrate having a plurality of interconnects between the contact pads 108 of the core 106 and the pins 112 of the dual core microprocessor package, wherein The interconnects are used to connect the dual core microprocessor 102 to other components of the electronic system 100, such as to the chipset 144 via a motherboard. Although the contact pads 108 shown in FIG. 1 are only located on one side of the wafer 104, the contact pads 108 are typically located on the other side of the wafer 104. Moreover, while the wafer 104 shown in FIG. 1 has only three contact pads 108, the wafer 104 typically has hundreds of contact pads 108. As shown in FIG. 1, the contact pads 108A/108B of the core 106 are coupled to the same pin 112 because the dual core microprocessor package system connects them to the processor bus 142 with a single set of pins 112; The core 0 106A and the core 1 106B are both coupled to the shared pin 112, wherein the pin 112 is used to connect the dual core microprocessor package to the processor bus 142.

2 is a schematic diagram of the bus interface interface circuit 200 of the exemplary dual core microprocessor 102 of FIG. The bus interface circuit 200 includes a contact pad 108A coupled to a pin 112 of the external processor bus 142, the contact pad 108A being a physical location for attaching the connector to the pin 112 of the dual core microprocessor package; That is, contact pad 108A does not include any active electronic devices. The contact pad 108A is also coupled to the signal 208A. The signal 208A is coupled to the drain of the transistor 204A. The source of the transistor 204A is grounded, and the gate of the transistor 204A is used to receive the signal 206A from the core 0 106A. The signal 206A can be a data signal, an address signal or a control signal for providing a value to the contact pad 108A via the signal 208A for driving to the signal of the corresponding processor bus 142. Thus, although Figure 2 shows only the configuration of a single signal for processor bus 142, each signal of processor bus 142 has the same configuration. The bus interface circuit 200 includes a multiplexer 202A having two inputs. The input 0 of the multiplexer 202A receives the signal 208A, and the input 1 of the multiplexer 202A receives the signal 206A. The output of the multiplexer 202A outputs a signal 205A to a core 0 106A for use as a core 0. An input for 106A. The signal 205A can be a data signal, a bit address signal or a control signal corresponding to one of the signals of the processor bus 142. Signal 205A can pass values from other processing units (core 1 106B or wafer set 144) of electronic system 100 through contact pads 108A and signals 208A. In addition, signal 205A can pass the value from core 0 106A through signal 206A to snoop its cache memory. The selection signal 207A is used to cause the multiplexer 202A to select the input of the multiplexer 202A to provide the signal 205A at the output in the manner shown in Table 1.

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The bus bar interface circuit 200 includes a contact pad 108B coupled to the pin 112 of the external processor bus 142. The contact pad 108B is also coupled to the signal 208B. The signal 208B is coupled to the drain of the transistor 204B, and the transistor 204B. The source is grounded. The gate of the transistor 204B is configured to receive the signal 206B from the core 1 106B. The signal 206B can be a data signal, an address signal or a control signal for providing a value through the signal 208B and the contact pad 108B to be driven. To the signal corresponding to the processor bus 142. The bus interface circuit 200 includes a multiplexer 202B having two inputs. The input 0 of the multiplexer 202B receives the signal 208B, and the input 1 of the multiplexer 202B receives the signal 206B. The output of multiplexer 202B outputs signal 205B to core 1 106B for use as an input to core 1 106B. The signal 205B can be a data signal, a bit address signal or a control signal corresponding to one of the signals of the processor bus 142. Signal 205B can pass values from another processing unit (core 0 106A or chipset 144) of electronic system 100 through contact pad 108B and signal 208B. In addition, the signal 205B can be transmitted from the core 1 through the signal 206B. The value of 106B is to spy on its cache memory. The selection signal 207B is used to cause the multiplexer 202B to select the input of the multiplexer 202B in the manner shown in Table 2 to provide the signal 205B at the output.

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Although not shown in FIG. 2, an end point resistor can be coupled to each of the contact pads 108A and 108B. The fuse can be coupled between the interrupt resistor and the power source. To selectively couple the interrupt resistors to contact pads 108A and 108B, the fuses can be selectively blown or retained during the manufacture of the microprocessor.

The inventor has found that the signal quality of the signal 208A is poor when the core 1 106B drives the processor bus 142. Conversely, when the core 0 106A drives the processor bus 142, the signal quality of the signal 208B is also poor, both of which make the system unreliable. . Therefore, there is a great need for a way to solve this problem.

3 is a schematic diagram of an electronic system 300 including a dual core processor package in accordance with an embodiment of the present invention. The electronic system 300 includes a wafer set 144 and a processor bus 142 similar to those shown in FIG. The electronic system 300 also includes a dual core microprocessor package that is coupled to the chip set 144 by a processor bus 142. The dual core microprocessor 302 includes two processing cores, core 0 306A and core 1 306B, collectively referred to as core 306.

Core 306 is similar to core 106 of Figure 1, however, the construction of core 306 of Figure 3 is as follows. Unlike the core 106 of the dual core microprocessor 102 shown in FIG. 1, the core 306 of the dual core microprocessor 302 shown in FIG. 3 is located in a single semiconductor wafer 304 in a dual core microprocessor package. That is, the manufacturer of the dual-core microprocessor 302 of FIG. 3 is fabricated by fabricating a plurality of wafers 304 in a matrix arrangement on a semiconductor wafer, and then cutting the wafers 304 into solid blocks. That is, the dual-core microprocessor 102 shown in FIG. 1 mounts two physical wafers 104 on a package substrate, and the two physical wafers 104 are connected by signal wires on the package substrate. Together, the dual core microprocessor 302 of FIG. 3 is a single physical die 304 having one of the cores 306A and 306B. Moreover, as with the dual core microprocessor 102 of FIG. 1, the cores 306A and 306B of the dual core microprocessor 302 each include contact pads 108A and 108B that are coupled to corresponding pins 112 of the processor bus 142, and core 306A. The contact pads 108A and 108B of 306B are coupled through the substrate wires and the corresponding pins 112, as shown in the third figure.

In one embodiment, the dual core microprocessor 302 of FIG. 3 having a single wafer 304 is designed in the manner described in Patent No. 61/426,470, "Improving the Mask Set to Produce a Multi-Core Wafer" (CNTR.2528). And manufacturing. Briefly, the manufacturer designs a first mask set to print a set of single core wafers (such as the single core wafer 104 of FIG. 1) in accordance with the method proposed in CNTR.2528. The first mask set defines a plurality of cut lines for separating the single core wafers, and the cut lines define a seal ring surrounding each dual core wafer. The manufacturer modifies a portion of the reticle of the first reticle set to a second reticle set that can be used to print a set of dual core wafers (such as the dual core wafer 304 of FIG. 3). The manufacturer removes at least one of the cut lines of the first mask set, and the corresponding modified portion of the first mask set defines a bypass bus 309 (inter-core communication line 212 in CNTR.2528). Next, the manufacturer fabricates the wafer using the second mask set and cuts the dual core wafer 304 along the remaining cut lines to produce the dual core wafer 304.

The bypass busbar 309 connects adjacent cores 306A and 306B on the wafer, the cores 306A and 306B being separated by a pre-designed cutting line, but the cutting line is replaced by a bypass busbar 309 such that the two cores 306 Communication is possible during operation. Since core 0 306A is connected to core 1 306B by bypass bus 309, core 0 306A and core 1 306B can be considered complementary. Because the bypass bus 309 is not connected to the contact pads 108, the bypass bus 309 does not transmit signals to the outside of the dual core wafer 304.

4 is a schematic diagram of a bus interface interface circuit 400 of the dual core microprocessor 302 of FIG. Busbar interface circuit 400 having a single wafer 304 is modified from busbar interface circuit 200 of FIG. 2 to accommodate bypass busbar 309 and to provide improved signal quality for processor busbar 142.

The busbar interface circuit 400 of Fig. 4 is similar in many places to the busbar interface circuit 200 of Fig. 2, and the number of components is similar. However, the following will be described for different places.

In Fig. 4, a multiplexer 402A having three inputs replaces the multiplexer 202A having two inputs in Fig. 2. The third input of the multiplexer 402A in FIG. 4 is the input terminal 2, and the input terminal 2 is coupled to the bypass bus signal 309A, wherein the bypass bus signal 309A is the signal 206B from the core 1 306B. The select input of multiplexer 402A receives select signal 407A, and select signal 407A is used to cause multiplexer 402A to select the input of multiplexer 402A in the manner shown in Table 3.

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Similarly, multiplexer 402B having three inputs replaces multiplexer 202B having two inputs of FIG. In FIG. 4, the third input of the multiplexer 402B is referred to as the input terminal 2, and the input terminal 2 is coupled to the bypass bus signal 309B, wherein the bypass bus signal 309B is the signal from the core 0 306A. 206A. The select input of multiplexer 402B receives select signal 407B, and select signal 407B is used to cause multiplexer 402B to select the input of multiplexer 402B in the manner shown in Table 4.

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An advantage that can be seen from FIG. 4 is that when core 0 306A drives processor bus 142, core 1 306B can monitor the value driven by core 0 306A directly from internal bypass bus 309B instead of transmitting signals. 208B is monitored by external processor bus 142 because the quality of the signal monitored from external processor bus 142 is much worse than the quality of the signal monitored from internal bypass bus 309B; when core 1 306B is driven At bus 142, core 0 306A can monitor the value driven by core 1 306B directly from internal bypass bus 309A, rather than being monitored by external processor bus 142 via signal 208A, due to bus 142 from external processor. The monitored signal quality will be much worse than the quality of the signal monitored from the internal bypass bus 309A.

Another benefit is that the embodiments of Figures 3 and 4 can provide a dual core microprocessor with improved signal quality by means of an internal bypass bus and avoid the need for additional contact pads to establish between the two cores. Bypass busbars, in the design of a limited pad-limited, the need for additional contact pads is a particularly useful benefit.

In one embodiment, the data and address signals on the processor bus 142 are two-frequency signals and quad-frequency signals corresponding to the control signals of the processor bus 142. The inventors have observed that the signal quality of the signal 208A is poor when the core 1 106B drives the processor bus 142. Conversely, when the core 0 106A drives the processor bus 142, the signal quality of the signal 208B is also poor, especially for the double frequency signal. The data of the quadruple frequency signal and the address signal are even more so. However, the signal quality of the single signal (ie, the normal bus clock speed) control signal is relatively reliable, and the control logic of the bus interface circuit 400 that generates the selection signal 407 can be used to observe the control signal of the processor bus 142 at a single speed. In order to reliably determine which cell (ie, core 0 306A, core 1 306B, or chipset 144) is driving processor bus 142.

Four core embodiment

Figure 5 is a schematic illustration of an electronic system 500 including a conventional dual core microprocessor package. The electronic system 500 is similar to the electronic system 300 of FIG. 3; however, the dual core microprocessor 502 having a single wafer 504 of FIG. 5 is different from the dual core microprocessor 302 having a single wafer 304 of FIG. The single wafer 504 includes only a single contact pad 108A for corresponding to each pin 112 of the processor bus bar 142. That is, core 0 506A of dual core microprocessor 502 of FIG. 5 shares a set of contact pads 108A with core 1 506B, rather than dual core microprocessors 302 of FIG. 3 each having contact pads 108A and 108B. Thus, core 0 506A and core 1 506B can be a dual core pair. The dual core microprocessor 502 of FIG. 5 having a single wafer 504 can include a cache memory shared by core 0 506A and core 1 506B.

Figure 6 is a schematic illustration of a bus interface interface circuit 600 of a conventional dual core microprocessor 502 according to Figure 5. Bus interface circuit 600 includes contact pads 108A that are coupled to pins 112 of external processor bus 142. The contact pad 108A is coupled to the signal 208, and the signal 208 is coupled to the drain of the transistor 204, and the source of the transistor 204 is grounded. The gate of transistor 204 is for receiving an output signal 601 of OR gate 603 having two inputs, and the input of OR gate 603 receives signal 206A from core 0 506A and signal 206B from core 1 506B. When the core 0 506A drives the processor bus 142, the core 1 506B generates a signal 206B having a false value, so that the core 0 506A can control the output signal 601, the transistor 204, and the pin 112 of the OR gate 603. The output value is connected to the processor bus 142. Conversely, when core 1 506B drives processor bus 142, core 0 506A generates a signal 206A with an error value to cause core 1 506B can control the output signal 601 of the OR gate 603, the output value of the transistor 204, the pin 112, and the processor bus 142. Each of the output signals 206A and 206B can be a data signal, an address signal or a control signal for providing a value to the contact pad 108A via the signal 208 for being driven to a corresponding signal of the processor bus 142. Therefore, although FIG. 6 only shows the configuration of a single signal of the processor bus 142, each signal of the processor bus 142 has the configuration shown in FIG.

The bus interface circuit 600 further includes a multiplexer 602 having two inputs. The multiplexer 602 receives the signal 208 at the input 0 and receives the output signal 601 at the input 1. The output of the multiplexer 602 provides the signal 205A and the signal 205B to the core 0 506A and the core 1 506B as the input signals of the core 0 506A and the core 1 506B, respectively. The signals 205A and 205B may be data signals, address signals or control signals corresponding to one of the signals of the processor bus 142. Signals 205A and 205B can pass values from another processing unit (wafer set 144) of electronic system 500 through contact pads 108A and signals 208. In addition, the signal 205A and the signal 205B can pass the value from the core 1 506B through the OR gate 603 and the output signal 601, or transmit the value from the core 0 506A through the OR gate 603 and the output signal 601 to snoop the cache memory. The selection signal 607 controls the multiplexer 602 to select the input of the multiplexer 602 in the manner shown in Table 5 to provide the signal 205A.

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Figure 7 illustrates an electronic system 700 in accordance with an embodiment of the present invention. The electronic system 700 includes a quad core microprocessor package. The electronic system 700 includes a wafer set 144 and a processor bus 142, similar to the wafer set 144 and processor bus 142 shown in FIG. Electronic system 700 includes a quad core microprocessor package coupled to chip set 144 by processor bus 142. The quad core microprocessor 702 includes four processing cores, collectively referred to as core 706, which are core 0 706A, core 1 706B, core 2 706C, and core 3 706D, respectively.

Core 0 706A forms a dual core pair with core 1 706B, similar to a dual core pair formed by core 0 506A and core 1 506B. In detail, core 0 706A shares a set of contact pads 108A with core 1 706B that are coupled to pins 112 of corresponding processor busbars 142 via substrate wires. Similarly, core 2 706C shares a set of contact pads 108B with core 3 706D that are coupled to pins 112 of corresponding processor busbars 142 through substrate wires. The four cores 706 of the quad core microprocessor 702 are all located on a single wafer 704.

The manufacturer of the core microprocessor 702 of FIG. 7 is fabricated in a matrix arrangement on a semiconductor wafer to fabricate a plurality of wafers 704, which are then diced into solid blocks. In one embodiment, the quad core microprocessor 702 of FIG. 7 having a single wafer 704 is designed and fabricated in the manner described in CNTR.2528. That is, the manufacturer designs a first reticle set for printing a set of dual core wafers (such as the dual core wafer 504 of FIG. 5). The first mask set defines a cut line to separate the dual core wafer, and the cut line defines a seal ring surrounding each dual core wafer. The manufacturer replaces a portion of the photomask of the first mask group with at least one cutting line of the first mask group by using the bypass bus bar 709 to be corrected to the second mask group, and the second mask group can be used for printing A set of quad core wafers (such as the core wafer 704 of FIG. 7) is shown. The bypass bus 709 includes inter-core communication lines to connect adjacent dual core pairs or dual core groups on the wafer, wherein the dual core pairs or dual core groups are pre-designed to be separated by the cutting lines. Once the cutting line is removed and the mask set is modified to define the bypass bus 709, the four cores can communicate via the bypass bus 709 during operation. Next, the manufacturer fabricates the wafer using the second mask set and cuts the quad core wafer 704 along the remaining cut lines to produce a quad core wafer 704.

Because the dual core pair formed by core 0 706A and core 1 706B is connected to the dual core pair formed by core 2 706C and core 3 706D via bypass bus 709, the dual core pair formed by core 0 706A and core 1 706B It is complementary to the dual core pair formed by core 2 706C and core 3 706D. Since the bypass bus 709 is not connected to the contact pad 108, the bypass bus 709 does not transmit signals to the outside of the quad core wafer 704.

Figure 8 is a schematic diagram of the bus interface interface circuit 800 of the core microprocessor 702 according to Figure 7. The busbar interface circuit 800 of the single wafer 704 is a modified busbar interface circuit 600 of FIG. 6 to accommodate the bypass busbar 709 and provide improved signal quality for the processor busbar 142.

The busbar interface circuit 800 of Fig. 8 is similar to the busbar interface circuit 600 of Fig. 6, and is similar to the busbar interface circuit 400 of Fig. 4 at other locations, such as the number of components used. The differences are described below. The OR gate 603 of Fig. 6 is an OR gate 603A in Fig. 8, and the output signal 601 of Fig. 6 is an output signal 601A in Fig. 8. The signal 208 of Figure 6 is signal 208A in Figure 8 (as shown in Figure 4). The transistor 204 of Fig. 6 is the transistor 204A in Fig. 8 (as shown in Fig. 4). Further, a multiplexer 802A having three inputs (such as the multiplexer 402A having three inputs as shown in FIG. 4) replaces the multiplexer 602 having two inputs of FIG. 8 is the same as FIG. 4, the third input of the multiplexer 802A is the input terminal 2, and the input terminal 2 is coupled to the bypass bus signal 709A, wherein the bypass bus signal 709A is coupled to the number 601B, output signal 601B has the same function as output signal 601A, except that output signal 601B is related to core 2 706C and core 3 706D, as discussed below. The select input of the multiplexer 802A receives the select signal 807A, and the select signal 807A is used to cause the multiplexer 802A to select the input of the multiplexer 802A in the manner shown in Table 6.

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The bus interface circuit 800 of FIG. 8 also includes a bus interface circuit of the core 2 706C and the core 3 706D, which is a mirror copy of the bus interface interface of the core 0 706A and the core 1 706B. That is, for core 2 706C and core 3 706D, bus interface interface circuit 800 includes contact pads 108B that are coupled to pins 112 of external processor bus 142. The contact pad 108B is coupled to the signal 208B, wherein the signal 208B is coupled to the drain of the transistor 204B, and the source of the transistor 204B is grounded. The gate of transistor 204B is used to receive an operational output signal 601B of OR gate 603B having two inputs. The input of OR gate 603B receives signal 206C from core 2 706C and signal 206D from core 3 706D, which is similar to signals 206A and 206B of corresponding core 0 706A and core 1 706B. The bus interface circuit 800 includes a multiplexer 802B having three inputs. The input 0 of the multiplexer 802B receives the signal 208B, the input 1 receives the output signal 601B, and the input 2 receives the bypass bus signal 709B. The bypass bus signal 709B is coupled to the output signal 601A. The select input of multiplexer 802B receives signal 807B to cause multiplexer 802B to select the input of multiplexer 802B in the manner shown in Table 7.

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The multiplexer 802B outputs the signal 205C to the core 2 706C as the input signal of the core 2 706C, and outputs the signal 205D to the core 3 706D as the input signal of the core 3 706D. Signals 205C and 205D are similar to signals 205A and 205B of core 0 706A and core 1 706B.

It can be seen from Fig. 8 that when core 0 706A or core 1 706B drives processor bus 142, core 2 706C or core 3 706D can be monitored directly from internal bypass bus 709B by core 0 706A The value driven by the core 1 706B, rather than the signal 208B, is monitored by the external processor bus 142, and the quality of the signal monitored from the external processor bus 142 is better than that monitored from the internal bypass bus 709B. The signal quality is poor. When the core 2 706C or the core 3 706D drives the processor bus 142, the core 0 706A or the core 1 706B can directly monitor the value driven by the core 2 706C or the core 3 706D from the internal bypass bus 709A. Instead of being monitored by external processor bus 142 via signal 208A, the quality of the signal monitored from external processor bus 142 is much worse than the quality of the signal monitored from internal bypass bus 709A.

It should be noted that the term "signal" as used in the specification herein refers to a circuit component and refers to a wire for transmitting a digital electronic signal.

Although only dual core and quad core microprocessors are described herein including internal bypass busses for improving the quality of the processor bus signal, in other embodiments a multi-core microprocessor may be utilized in the same manner to improve The quality of the processor bus, such as a six-core or eight-core microprocessor.

In addition, although in the above embodiments, the inter-core communication line is used to couple from the output end of each core or each dual core pair to the input end of the processor bus and the complementary core or a dual core pair, and Two-way communication. However, in other embodiments, the inter-core communication lines are only coupled from one core or a pair of core pairs to other cores, and vice versa. In addition, the inter-core communication lines in other embodiments are only provided to the input and output of the selected processor bus.

It should be noted that the inter-core communication lines in the specification are referred to as "bypass busbars", and the communication lines between each core of one core or one pair of core pairs to another core or another dual core pair may be It is called a recognizable "bypass bus". In addition, the combination of two or more groups, including one group from one direction (the first core to the second core) and the other group from the opposite direction (ie, the second core to the first core) may also be a "bypass bus". Or "multiple bypass busbars".

The present invention has been described above with reference to the preferred embodiments. However, it is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. For example, in addition to hardware (eg, coupled to or within a central processing unit, microprocessor, microcontroller, digital signal processor, processor core, system chip, or any other device), Software (eg, computer readable code, code, or any form of instruction, such as an original language, a target language, or a mechanical language) can be implemented, for example, to store the software in a computer usable (eg, readable) medium. For example, such software may enable functions to perform, manufacture, manufacture, model, simulate, or test the devices and methods referred to herein, for example, in a conventional programming language (eg, C or C++), a hardware description language ( Such as Verilog HDL, VHDL) or other programs to complete; such software can be installed on any computer-usable media, such as semiconductors, disks or optical discs (such as CD-ROM, DVD-ROM, etc.). Embodiments of the present invention include a method of providing a microprocessor by providing software that describes the design of a microprocessor and transmitting the software as a computer data signal through a communication network (including the Internet and the regional network) Road) transmitted out. The apparatus and method of the present invention can also be applied to a semiconductor intellectual property core (semiconductor intellectual property) Core), for example, a microprocessor core (implemented in HDL), and then converted into a hardware in an integrated circuit. In addition, the apparatus and method of the present invention can also be implemented by a combination of hardware and software. Therefore, the present invention should not be limited to the disclosed embodiments, and the scope of the present invention is defined by the scope of the appended claims. The present invention is implemented in a microprocessor device, and the microprocessor device is applied to a general computer.

<p>100, 300, 500, 700. . . electronic system</p><p>200, 400, 600, 800. . . Bus interface circuit</p><p>102, 302, 502. . . Dual core microprocessor</p><p>106A, 306A, 506A, 706A. . . Core 0</p><p>106B, 306B, 506B, 706B. . . Core 1</p><p>108A, 108B. . . Contact pad</p><p>112. . . Pin</p><p>142. . . Processor bus</p><p>144. . . Chipset</p><p>202A, 202B, 402A, 402B, 602, 802A, 802B. . . Multiplexer</p><p>204A, 204B, 204. . . Transistor</p><p>205A, 205B, 205C, 205D, 206A, 206B, 206C, 206D, 208A, 208B, 208. . . Signal</p><p>207A, 207B, 407A, 407B, 607, 807A, 807B. . . Select signal</p><p>309, 309A, 309B, 709, 709A, 709B. . . Bypass bus signal</p><p>601, 601A, 601B. . . Output signal</p><p>603, 603A, 603B. . . OR gate</p><p>702. . . Quad core microprocessor</p><p>706C. . . Core 2</p><p>706D. . . Core 3</p>

Figure 1 is a schematic illustration of an electronic system having a conventional dual core microprocessor package;

Figure 2 is a schematic diagram of the bus interface circuit of the conventional dual core microprocessor of Figure 1;

Figure 3 is a schematic illustration of an electronic system having a dual core microprocessor package in accordance with the present invention;

Figure 4 is a schematic diagram of the bus interface circuit of the dual core microprocessor of Figure 3;

Figure 5 is a schematic illustration of an electronic system having a conventional dual core microprocessor package;

Figure 6 is a schematic diagram showing the bus interface circuit of the conventional dual-core microprocessor of Figure 5;

Figure 7 is a schematic illustration of an electronic system having a quad core microprocessor package in accordance with the present invention;

Figure 8 is a schematic diagram of the bus interface circuit of the core microprocessor of Figure 7.