Vertical bus circuits, battery management systems, and methods for enabling signal transmission

Vertical bus circuit, battery management system and method for enabling signal transmission

VERTICAL BUS CIRCUITS, BATTERY MANAGEMENT SYSTEMS, AND METHODS FOR ENABLING SIGNAL TRANSMISSION

The invention relates to a bus circuit, in particular to a vertical bus circuit used in a battery management system.

Lithium batteries are now widely used in environmentally friendly vehicles (for example, electric vehicles and hybrid vehicles). The operating voltage of a single battery cell in a lithium battery is about 3 to 4 volts. However, electric vehicles and hybrid electric vehicles usually require a voltage higher than 100 volts, so multiple battery cells in series are usually used to drive electric vehicles and hybrid electric vehicles.

In battery management, a large number of battery cells are divided into one or more battery packs, and an Analog Front End (AFE) device is coupled to each battery pack to obtain the status of each battery pack or battery cell , For example, voltage, current, and temperature. Then, a digital signal representing the state of the battery pack or battery cell is transmitted to the microprocessor to perform different functions, such as battery protection. In this way, a communication bus between the microprocessor and each analog front-end device is required.

FIG. 1 shows a schematic diagram of a battery management system 100 with an opto-coupler vertical bus in the prior art. The analog front-end devices 122, 124, and 126 are respectively coupled to the battery packs 112, 114, and 116 for obtaining the status of each battery cell in the battery pack. The optocoupler modules 132, 134, and 136 establish a communication bus between the analog front-end equipment 122, 124, and 126 and a central electronic control unit (Central Electronics Control Unit, CECU) 140. Every channel in the bus, That is, each optical coupler module contains two optical couplers.

Since optocouplers are relatively expensive and require a current driving capability of several hundred milliamps, the traditional battery management system 100 based on optocoupler vertical buses has high cost and high power consumption.

In order to solve the above technical problems, the present invention provides a vertical bus circuit, including: a plurality of bus modules, a plurality of signals are transmitted between the plurality of bus modules, wherein the plurality of bus modules share A plurality of common potentials, wherein each of the bus bar modules includes a signal path and two input/output (I/O) devices powered by a first potential and a second potential, and wherein the signal path is aligned with The signal transmission between the two I/O devices can be enabled, and the multiple common potentials can enable the multiple signal transmission between the multiple busbar modules.

The present invention also provides a battery management system, including: a plurality of devices coupled to a battery including a plurality of battery cells, the plurality of devices can obtain the state of the plurality of battery cells, wherein each device is coupled to A group of the plurality of battery units, and use different voltages; and a control unit, coupled to a first device of the plurality of devices, the control unit passes through the first device and the plurality of devices A target device communication in, wherein the voltages used by the multiple devices are between a voltage used by the first device and a voltage used by the target device.

The present invention also provides a method for enabling signal transmission, including: a first bus module in a first bus module among a plurality of bus module modules A signal is transmitted between the same potential and a second common potential; and the signal is transmitted between the first bus module and a second bus module of the plurality of bus modules, wherein the first The bus bar module and the second bus bar module share the second common potential.

The embodiments of the present invention will be described in detail below. Although the present invention will be described in conjunction with embodiments, it should be understood that this does not mean that the present invention is limited to these embodiments. On the contrary, the present invention is intended to cover various changes, modifications and equivalents defined within the spirit and scope of the present invention defined by the scope of the appended patent application.

In addition, in the following detailed description of the present invention, a large number of specific details are clarified to provide a comprehensive understanding of the present invention. However, those skilled in the art should understand that the present invention can also be implemented without these specific details. In other instances, the conventional methods, processes, components, and circuits are not described in detail, so as to highlight the gist of the present invention.

The following detailed descriptions are expressed in terms of procedures, logic blocks, steps, and other symbols representing the operations of data bits in the computer memory. These descriptions and expressions are the most effective ways for people with ordinary knowledge in the field of data processing technology to convey the essence of their work. In the present invention, a program, a logic block, a step, or the like, is deemed to be guided by a step or instruction in its own consistent sequence to produce a desired result. These steps require physical manipulation of physical quantities (manipulation). Although it is not necessary, these physical quantities are usually in the form of electrical or magnetic signals to be stored, transmitted, and transmitted in computer systems. Combine, compare, etc.

However, these similar terms are all related to the appropriate physical quantities, and are merely marked on these physical quantities for easy identification. Unless particularly emphasized, it is obvious from the following description that in the present invention, these "transmitting", "issuing", "accessing", "converting", and "using (" The terms "using)", "powering", etc. refer to the actions and steps of a computer system or other similar electronic computing devices. These actions and steps will represent the physical (electronic) ) The quantity is processed and converted into other data similar to the physical quantity in the memory or register of the computer system or other such as information storage, transmission or display device.

The embodiment of the present invention uses general text to describe computer-executable instructions that exist in a computer-usable medium (for example, a program module) and are executed by one or more computers or other devices. Generally speaking, program modules perform specific tasks or perform specific abstract data types. Program modules include routines, programs, objects, components, data structures, and so on. The functions of the program modules will be combined or distributed due to various implementations.

For example, the computer-usable media may include computer storage media and communication media, but not limited to this. Computer storage media include volatile/immutable, removable/non-removable computer storage media implemented in any manner or technology to store, for example, computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), electronically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, optical CD-ROM, DVD or other optical storage, cassettes, tape, floppy disk, or other magnetic storage or other media that can be used to store data, but Not limited to this.

The communication medium can use computer-readable instructions, data structures, program modules or other modulating data on the data signal, such as carrier waves or other transmission mechanisms, and includes any information transmission medium. The term "modulated data signal" means a signal that has one or more sets of characteristics, or is changed by an information encryption method such as encryption on the signal. For example, communication media include wired networks or wired media connected by direct lines, or wireless media such as acoustic, radio frequency (RF), infrared, or other wireless media, but not limit. Combinations of the above-mentioned media are also included in the scope of computer-readable media.

In addition, in the following detailed description of the present invention, in order to provide a complete understanding of the present invention, a large number of specific details are provided. However, those skilled in the art will understand that the present invention can also be implemented without these specific details. In some other examples, well-known methods, procedures, components, and circuits are not described in detail, so as to highlight the gist of the present invention.

FIG. 2 shows a schematic diagram of a vertical bus circuit 200 according to an embodiment of the invention. The vertical bus circuit 200 includes three bus modules 220, 230, and 240, and a plurality of resistors 262, 264, 266, and 268. As shown in FIG. 2, the structure of the busbar modules 220, 230, and 240 is similar. Although FIG. 2 shows three busbar modules, the present invention is not limited to this. In other embodiments, the vertical busbar circuit 200 may include a greater or lesser number of busbar modules.

The bus modules 220, 230, and 240 can use different voltages. Taking the bus module 220 as an example, a bus signal is input from the input terminal 212 of the bus module 220 and transmitted to the bus module 230. At the input terminal 212 of the bus module 220, the low potential voltage is V₀, The high potential voltage is V₁. When the bus signal is transmitted to the node 214 of the bus module 230, the low potential voltage is V₂, The high potential voltage is V₃, Where V₂And V₃Different from V₀And V₁. Similarly, the bus signal can be transmitted from the bus module 230 to the bus module 240.

The bus modules 220, 230, and 240 transmit bus signals in an upward direction (refer to the direction of FIG. 2). For example, in the vertical bus circuit 200, the bus 220 is a bottom bus module, and the bus module 240 is a top bus module. A bus signal is input from the input terminal 212 of the bus module 220 and transmitted to the bus module 240, and finally output from the output terminal 218 of the bus module 240.

In one embodiment, the bus module 220 includes an uplink signal path 222, inverters 272 and 294, and a field effect transistor 284. In an embodiment, the upstream signal path 222 includes field effect transistors 223, 224, 225, 226, 227, and 228, and an inverter 229. The bus module 230 includes an uplink signal path 232, inverters 274 and 296, and a field effect transistor 286. The upstream signal path 232 includes field effect transistors 233, 234, 235, 236, 237, and 238, and an inverter 239. The bus module 240 includes an uplink signal path 242, inverters 276 and 298, and a field effect transistor 288. The upstream signal path 242 includes field effect transistors 243, 244, 245, 246, 247, and 248, and an inverter 249.

Upstream signal path in bus module 220, 230 and 240 222, 232, and 242 convert the bus signal from a low level to a high level. For example, the upstream signal path 222 in the bus module 220 changes the bus signal from a low level (VDD=V₁, GND=V₀) To high potential (VDD=V₃, GND=V₂)。

In one embodiment, the inverter 294 and the field effect transistor 284 in the bus module 220, the resistor 264 and the inverter 274 in the bus module 230 transfer the bus signal from the bus module 220 to The bus module 230. Similarly, the inverter 296 and the field effect transistor 286 in the bus module 230, the resistor 266, and the inverter 276 in the bus module 240 transfer the bus signal from the bus module 230 to the bus module. Group 240.

When the bus signal input to the input terminal 212 of the bus module 220 is in a high state or the voltage of the bus signal at the input terminal 212 is V₁, The field effect transistor 227 is turned off, the field effect transistor 228 is turned on, and the voltage of the node 252 is pulled down. The gate voltage of the field effect transistor 223 is pulled down to turn on the field effect transistor 223. In this way, the voltage at the node 256 of the drain of the field-effect transistor 223 is pulled high, and through the inverter 294, the voltage of the gate of the field-effect transistor 284 is pulled low to turn off the field-effect transistor 284. The field effect transistor 284 is coupled to the resistor 264, and the output state at the node 214 is a high potential (the voltage is V₃) Bus signal.

On the other hand, when the bus signal of the input terminal 212 is in the state low level or the voltage of the bus signal of the input terminal 212 is V₀, The field effect transistor 228 is turned off, the field effect transistor 227 is turned on, and the voltage of the node 256 is pulled down. Next, the gate voltage of the field effect transistor 284 is pulled up to turn on the field effect transistor 284. The field effect transistor 284 is coupled to the resistor 264, The output state at node 214 is low potential (voltage is V₂) Bus signal.

In an embodiment, field effect transistors 225 and 226 may be added to reduce the full swing of the corresponding nodes 256 and 252, respectively. In this way, the voltage of nodes 256 and 252 varies from V₃Full swing to V₂. Therefore, the power consumption can be reduced and the transmission speed of the bus signal can be increased.

Therefore, the bus signal can be transmitted from the input terminal 212 of the bus module 220 to the node 214. Similarly, the bus signal can be transmitted from the node 214 of the bus module 230 to the node 216, and then, through the bus module 240, output at the output terminal 218. In other words, the bus signal goes from a low voltage potential (VDD=V₁, GND=V₀) Is converted to a high voltage potential (VDD=V₇, GND=V₆). In this way, when the state of the bus signal input at the input terminal 212 is high, the state of the bus signal output at the output terminal 218 is high, that is, OUT=1; when the state of the bus signal input at the input 212 When the state of is a low potential, the state of the bus signal output at the output terminal 218 is a low potential, that is, OUT=0.

FIG. 3 shows a schematic diagram of a vertical bus circuit 300 according to an embodiment of the invention. The vertical bus circuit 300 includes three bus modules 320, 330, and 340, and a plurality of resistors 362, 364, 366, and 368. As shown in FIG. 3, the busbar modules 320, 330, and 340 are similar. Although FIG. 3 shows three busbar modules, the present invention is not limited to this.

The bus module 320, 330, and 340 can use different voltages. Taking the bus module 320 as an example, a bus signal is input from the input terminal 312 of the bus module 320 and is transmitted to the bus module 330. At the input terminal 312 of the bus module 320, the low potential voltage is V₆, The high potential voltage is V₇. When the bus signal is transmitted to the node 314 of the bus module 330, the low potential voltage is V₄, The high potential voltage is V₅. Similarly, the bus signal can be transmitted to the bus module 340 by the bus module 330.

The bus modules 320, 330, and 340 transmit bus signals in a downward direction (refer to the direction of FIG. 3). For example, in the vertical bus circuit 300, the bus module 320 is a top bus module, and the bus module 340 is a bottom bus module. A bus signal is input from the input terminal 312 of the bus module 320, is transmitted to the bus module 340, and is output from the output terminal 318 of the bus module 340.

In one embodiment, the bus module 320 includes a downstream signal path 322, inverters 372 and 394, and a field effect transistor 384. In an embodiment, the downstream signal path 322 includes field effect transistors 323, 324, 325, 326, 327, and 328, and an inverter 329. The bus module 330 includes a downstream signal path 332, inverters 374 and 396, and a field effect transistor 386. The downstream signal path 332 includes field effect transistors 333, 334, 335, 336, 337, and 338, and an inverter 339. The bus module 340 includes a downstream signal path 342, inverters 376 and 398, and a field effect transistor 388. The downstream signal path 342 includes field effect transistors 343, 344, 345, 346, 347, and 348, and an inverter 349.

The downstream signal paths 322, 332, and 342 in the bus modules 320, 330, and 340 convert the bus signal from a high potential to a low potential. For example, the downstream signal path 322 in the bus module 320 changes the bus signal from a high potential (VDD=V₇, GND=V₆) Is converted to a low potential (VDD=V₅, GND=V₄)。

In one embodiment, the inverter 394 and the field effect transistor 384 in the bus module 320, the resistor 364, and the inverter 374 in the bus module 330 transfer the bus signal from the bus module 320 to The bus module 330. Similarly, in one embodiment, the inverter 396 and the field effect transistor 386 in the bus module 330, the resistor 366, and the inverter 376 in the bus module 340 transfer the bus signal from the bus module 330 is passed to the bus module 340.

When the state of the bus signal input to the input terminal 312 of the bus module 320 is high (i.e. IN=1) or the voltage of the bus signal input to the input terminal 312 is V₇, The field effect transistor 328 is turned off, and the field effect transistor 327 is turned on, so the voltage of the node 356 is pulled up. Then, the gate voltage of the field effect transistor 384 is pulled down to turn off the field effect transistor 384. The field effect transistor 384 is coupled to the resistor 364 to output a bus signal at the node 314, and the state of the bus signal is high (the voltage is V₅)。

On the other hand, when the state of the bus signal input to the input terminal 312 is low (ie IN=0) or the voltage of the bus signal input to the input terminal 312 is V₆, The field effect transistor 327 is turned off, and the field effect transistor 328 is turned on, so the voltage of the node 352 is pulled up. The gate voltage of the field effect transistor 323 is pulled up to turn on the field effect transistor 323. In this way, the voltage at the node 356 of the drain of the field effect transistor 323 is pulled down, and the gate voltage of the field effect transistor 384 is pulled up through the inverter 394 to turn on the transistor 384. The field effect transistor 384 is coupled to the resistor 364 to output a bus signal at the node 314, and the state of the bus signal is Low potential (voltage is V₄)。

In one embodiment, field effect transistors 325 and 326 are added to reduce the full voltage swing of nodes 356 and 352, respectively. In this way, the voltages of nodes 356 and 352 change from V₅Full swing to V₄. Therefore, the power consumption is reduced and the transmission speed of the bus signal is improved.

Therefore, the bus signal is transmitted from the input terminal 312 to the node 314 through the bus module 320. Similarly, the bus signal is transmitted from the node 314 to the node 316 through the bus module 330, and then output from the output terminal 318 through the bus module 340. In this way, when the state of the bus signal input to the input port 312 is high, the state of the output signal at the output terminal 318 is high, that is, OUT=1; when the state of the bus signal input to the input 312 is low , The state of the output signal of the output terminal 318 is low, that is, OUT=0.

FIG. 4 shows a schematic diagram of a vertical bus circuit 400 according to an embodiment of the invention. The battery 410 includes three battery packs 412, 414, and 416. In the example of FIG. 4, the vertical bus circuit 400 is a single-wire bus, and includes three bus modules 420, 430, and 440, and a plurality of resistors 462, 464, 466, and 468. In one embodiment, each bus module 420, 430, and 440 are the same and can be integrated into one chip.

Although the vertical bus circuit 400 is coupled to the battery 410 and is used to transmit signals in the battery management system, the present invention is not limited to this. Although FIG. 4 shows three busbar modules, the present invention is not limited to this.

Each battery pack 412, 414, and 416 includes a plurality of battery cells coupled to each other in series. Modular battery 410 provides eight voltage V₀, V₁, V₂, V₃, V₄, V₅, V₆And V₇. In one embodiment, V₁And V₀between Voltage difference, V₃And V₂The voltage difference between V₅And V₄The voltage difference between and V₇And V₆The voltage differences between are all equal. The voltage difference may be equal to the voltage of one battery cell in a battery pack, or it may be equal to the sum of the voltages of several battery cells in a battery pack.

In the example of FIG. 4, the bus module 420 includes signal paths and input/output (I/O) devices 426 and 428. Similarly, the bus module 430 includes signal paths and I/O devices 436 and 438. The bus module 440 includes signal paths and I/O devices 446 and 448. In an embodiment, the signal path in the bus module 420 may include an upstream signal path 422 and a downstream signal path 424. Similarly, the signal path in the bus module 430 includes an upstream signal path 432 and a downstream signal path 434. The signal path in the bus module 440 includes an upstream signal path 442 and a downstream signal path 444.

In one embodiment, the upstream signal paths 422, 432, and 442 are similar to the upstream signal paths 222, 232, and 242 shown in FIG. In one embodiment, the downstream signal paths 424, 434, and 444 are similar to the downstream signal paths 322, 332, and 342 shown in FIG.

In another embodiment, the vertical bus circuit 400 is a two-wire bus, and each bus module includes two upstream signal paths, two downstream signal paths, and four I/O devices.

Advantageously, the bus bar modules 420, 430, and 440 share multiple common potentials. In addition, multiple common potentials enable signal transmission between the bus modules 420, 430, and 440. For example, the I/O devices 426 and 428 in the bus module 420 are respectively determined by the potential (VDD=V₁, GND=V₀) And potential (VDD=V₃, GND=V₂)powered by. In the bus module 430 I/O devices 436 and 438 are determined by the potential (VDD=V₃, GND=V₂) And potential (VDD=V₅, GND=V₄)powered by. Therefore, the bus module 420 and 430 share the potential (VDD=V₃, GND=V₂), the potential enables signal transmission between the bus modules 420 and 430.

In one embodiment, the voltage of one battery cell in the battery pack is used as a common potential, or the voltage sum of a plurality of battery cells in the battery pack is used as a common potential. In other words, the voltage of at least one battery in a battery pack is used as a common potential.

In the example of FIG. 4, the I/O device 426 includes an inverter 472 similar to the inverter 272 shown in FIG. 2, an inverter 498 similar to the inverter 398 shown in FIG. The field effect transistor 388 shown in FIG. 3 is similar to the field effect transistor 488. The I/O devices 428, 436, 438, 446, and 448 are similar to the I/O device 426 and will not be repeated here. Advantageously, as described in FIGS. 2 and 3, the signal path of each bus module enables signal transmission between two I/O devices in the bus module.

The nodes 402, 404, 406, and 408 in the bus modules 420, 430, and 440 are used as I/O ports. As mentioned earlier, the bus signal of each node can be transmitted in the upstream and downstream directions. For example, the bus signal of the node 402 can be transmitted to the nodes 404, 406, and 408, and the bus signal can also be transmitted from the nodes 404, 406, and 408 and received at the node 402. Thus, for a single-wire bus, each bus module 420, 430, and 440 uses two I/O ports (for example, the nodes 402 and 404 of the bus module 420). In another embodiment, for a two-wire bus, the bus module uses four I/O ports. Therefore, the number of pins of the chip of the bus module can be reduced.

I/O devices are all open-drain. In this way, I/O devices are relatively flexible and can be internal integrated circuits (I²C), Serial Peripheral Interface (SPI) or other types of bus. In addition, the vertical bus circuit 400 does not generate power consumption in a static state. The bus signal transmitted in each bus module of the vertical bus circuit 400 is a differential signal. For example, in the upstream signal path 422, the turn-on or turn-off of the field effect transistor 423 is determined by the voltage difference between the node 452 and the node 456. In this way, relatively fast signal transmission speed and better tolerance can be obtained.

As described above, the voltage of a battery cell or voltages of a plurality of battery cells of each battery pack 412, 414, and 416 is provided to enable signal transmission between the bus modules. In this way, the full swing of the bus signal is within the range of one or more battery cell voltages. Advantageously, when the sum of the voltages of multiple battery cells is used to enable signal transmission between the busbar modules, the full swing of the busbar signal can be reduced. Therefore, better fault tolerance of the bus signal can be obtained.

Since the operating voltage of each node is within the range of the supply voltage of the I/O device, the nodes 402, 404, 406, and 408 do not need to withstand the transient state of overvoltage. As shown in Figure 4, the range of the supply voltage is the voltage of a battery cell. For example, the operating voltage of the node 402 is within the voltage range of the battery cell 482 in the battery pack 412, from V₀To V₁。

FIG. 5 shows a schematic diagram of a vertical bus circuit 500 according to another embodiment of the present invention. The components with the same reference numerals in FIG. 5 as those in FIG. 4 have similar functions. The battery 410 includes three battery packs 412, 414, and 416. In the embodiment shown in FIG. 5, the vertical bus circuit 500 is a single-wire bus The bus bar includes three bus bar modules 520, 530, and 540, and a plurality of resistors 462, 464, and 466. In an embodiment, each bus module 520, 530, and 540 are the same and can be integrated into a chip.

Although the vertical bus circuit 500 is coupled to the battery 410 and is used to enable signal transmission in the battery management system, the present invention is not limited to this. Although FIG. 5 shows three busbar modules, the present invention is not limited to this.

In the embodiment shown in FIG. 5, the bus module 520 includes a signal path, a voltage regulator (for example, a low-dropout regulator LDO) 552, and I/O devices 426 and 428. Similarly, the bus module 530 includes a signal path, a voltage regulator 554, and I/O devices 436 and 438. The bus module 540 includes a signal path, a voltage regulator 556, and I/O devices 446 and 448. In an embodiment, the signal path of the bus module 520 includes an upstream signal path 422 and a downstream signal path 424. Similarly, the signal path of the bus module 530 includes an upstream signal path 432 and a downstream signal path 434. The signal path of the bus module 540 includes an upstream signal path 442 and a downstream signal path 444.

In another embodiment, the vertical bus circuit 500 is a two-wire bus, and each bus module includes two upstream signal paths, two downstream signal paths, and four I/O devices.

Advantageously, the bus bar modules 520, 530, and 540 share multiple common potentials. In addition, multiple common potentials enable signal transmission between the bus modules 520, 530, and 540. For example, the I/O devices 426 and 428 in the bus module 520 are respectively determined by the potential (VDD=V₁, GND=V₀) And potential (VDD=V₃, GND=V₂)powered by. In the bus module 530 I/O devices 436 and 438 are determined by the potential (VDD=V₃, GND=V₂) And potential (VDD=V₅, GND=V₄)powered by. Therefore, the bus module 520 and 530 share the potential (VDD=V₃, GND=V₂), the potential enables signal transmission between the bus modules 520 and 530.

In one embodiment, each common potential is provided by the voltage of a battery cell in each battery pack and the output voltage of the voltage regulator. For example, voltage V₄Is the positive terminal voltage of the battery cell 494 in the battery pack 414, the voltage V₂It is the positive terminal voltage of the battery cell 492 in the battery pack 412. Voltage V₄Is provided to the voltage regulator 554 of the bus module 530, and the voltage regulator 554 outputs an output voltage V₃. In this way, the output voltage V₃And voltage V₂It is provided to enable the bus signal transmission between the bus modules 530 and 520.

Advantageously, as described in FIGS. 2 and 3, the signal path of each bus module enables signal transmission between two I/O devices in the bus module, which will not be repeated here.

The output voltages of the voltage regulators 552, 554, and 556 are relatively stable and can provide relatively stable power, so as to enable the bus signal transmission in the vertical bus circuit 500. In this way, the vertical bus circuit 500 will not be affected by the voltage fluctuations of the battery cells due to rapid charging or discharging, and therefore is more reliable.

The maximum number of battery cells in each battery pack 412, 414, and 416 is the maximum drain-source voltage V allowed by the field-effect transistor in the bus module coupled to the battery pack._dsIt is determined by the output voltage of the voltage regulator in the top bus module. For example, as shown in Figure 5, the maximum drain allowed by the transistors 425 and 427 in the bus module 520 is -Source voltage V_dsEqual to V₃And V₂The difference plus the voltage provided by the battery pack 412, where V₃And V₂The difference is the output voltage of the voltage regulator 554 in the bus module 530. In this way, the maximum number of battery cells in the battery pack 412 can be expressed by equation (1): N=(V_ds-V_LDO)/V_cell (1)

Among them, N is the maximum number of battery cells in the battery pack 412, and V_dsMaximum allowable drain-source voltage V for transistors 425 and 427_ds, V_LDOIs the output voltage of the voltage regulator 554 in the bus module 530, V_cellIs the battery cell voltage.

FIG. 6 shows a schematic diagram of a vertical bus topology 600 of a battery management system according to an embodiment of the present invention. Vertical bus topology 600 for I²C bus application. The vertical bus topology 600 includes bus modules 620, 630, and 640. The busbar modules 620, 630, and 640 are coupled to the battery packs 612, 614, and 616, respectively. In this way, the busbar modules 620, 630, and 640 use different voltages.

Advantageously, the bus bar modules 620, 630, and 640 share multiple common potentials. In one embodiment, the voltage of one battery cell in each battery pack 612, 614, and 616 is used as a common potential. For example, the battery cell 604 in the battery pack 612 is used as a common potential shared by the busbar modules 620 and 630. The battery cell 606 in the battery pack 614 is used as a common potential shared by the busbar modules 630 and 640. The common potential enables signal transmission between the bus modules 620, 630, and 640. For example, the voltage of the battery unit 604 enables signal transmission between the bus modules 620 and 630.

As mentioned above, each bus module 620, 630 and 640 adopts Bus protocol (for example, I²C bus protocol) to communicate with other bus modules.

Although FIG. 6 shows three busbar modules, the present invention is not limited to this.

Or, in an embodiment, the sum of the voltages of two or more battery cells in each battery pack 612, 614, and 616 is used as a common potential to enable signal transmission, thereby obtaining better signal full swing and better The fault tolerance.

FIG. 7 shows a schematic diagram of a vertical bus topology 700 of a battery management system according to another embodiment of the present invention. Vertical bus topology 700 for I²C bus application. The vertical busbar topology 700 includes busbar modules 720, 730, and 740. The busbar modules 720, 730, and 740 are coupled to the battery packs 712, 714, and 716, respectively. In the example shown in FIG. 7, the bus modules 720, 730, and 740 include voltage regulators 752, 754, and 756, respectively. In this embodiment, the voltage regulator may be a low dropout regulator.

Although FIG. 7 shows three busbar modules, the present invention is not limited to this.

Advantageously, the bus bar modules 720, 730, and 740 share multiple common potentials. In addition, the common potential enables signal transmission between the bus modules 720, 730, and 740. Each common potential is provided by the positive terminal voltage of one battery cell in each battery pack 712, 714, and 716 and the output voltage of the voltage regulator. For example, the positive terminal voltage of the battery cell 704 in the battery pack 714 is provided to the voltage regulator 754, and the voltage regulator 754 outputs an output voltage. In this way, the output of the voltage regulator 754 The output voltage and the positive terminal voltage of the battery 702 in the battery pack 712 provide a common potential shared by the busbar modules 720 and 730. As mentioned above, each bus module 720, 730, and 740 adopts a bus protocol (for example, I²C bus protocol) to communicate with other bus modules.

FIG. 8 shows a schematic diagram of a battery management system 800 according to an embodiment of the present invention. The battery management system 800 includes a battery 810, analog front-end devices 820, 830, and 840, and a central electronic control unit 860. The battery 810 includes battery packs 812, 814, and 816. The analog front-end devices 820, 830, and 840 are respectively coupled to the battery packs 812, 814, and 816. In this case, the analog front-end devices 820, 830, and 840 use the voltage provided by the battery packs 812, 814, and 816, respectively. In this way, the analog front-end devices 820, 830, and 840 use different voltages.

Although FIG. 8 shows three busbar modules, the present invention is not limited to this.

In an embodiment, the central electronic control unit 860 is coupled to the bottom analog front-end device 820 in the battery management system 800. Advantageously, the central electronic control unit 860 can communicate with the target analog front-end equipment through a combination of the analog front-end equipment 820 and the analog front-end equipment 820, 830, and 840. The combination of the above-mentioned analog front-end equipment 820, 830, and 840 uses a voltage between the voltage used by the analog front-end equipment 820 and the voltage used by the target analog front-end equipment. For example, the signal may be transmitted from the central electronic control unit 860, and transmitted to the analog front-end equipment 840 through the analog front-end equipment 820 and the analog front-end equipment 830. The voltage used by the analog front-end equipment 830 is between the voltage used by the analog front-end equipment 820 and the voltage used by the analog front-end equipment 840.

The common potential shared by the analog front-end devices 820, 830, and 840 enables the bus signal transmission between the analog front-end devices 820, 830, and 840. In one embodiment, the voltage of a battery cell in each battery pack 812, 814, and 816 is used as a common potential. For example, the voltage of the battery cells 804 in the battery pack 812 is used as a common potential, and the signal transmission between the analog front-end devices 820 and 830 is enabled.

Or, in an embodiment, the sum of the voltages of two or more battery cells of 812, 814, and 816 in each battery pack is used as a common potential, so as to enable signal transmission, thereby obtaining a better signal full swing sum. Better fault tolerance.

In one embodiment, the analog front-end devices 820, 830, and 840 are the same and can be integrated into one chip. In the embodiment of FIG. 8, the analog front-end device 820 includes a monitoring module 822, a bus module 824, an analog-to-digital converter (ADC) 826, a bus engine 828, and I/O devices (not shown). Similarly, the analog front-end equipment 830 includes a monitoring module 832, a bus module 834, an analog-to-digital converter 836, a bus engine 838, and I/O devices (not shown). The analog front-end equipment 840 includes a monitoring module 842, a bus module 844, an analog-to-digital converter 846, a bus engine 848, and I/O devices (not shown). In one embodiment, each bus module 824, 834, and 844 respectively includes an upstream signal path for transmitting bus signals in the upstream direction (for example, the upstream signal path 422 in FIG. 4), and a downstream direction transmission bus. The downlink signal path of the signal (for example, the downlink signal path 424 in FIG. 4).

The analog front-end devices 820, 830, and 840 are used to capture the status of the battery cells in the corresponding battery pack, and through the vertical bus and the central electronic control The control unit 860 communicates. In one embodiment, the vertical bus includes bus modules 824, 834, and 844, bus engines 828, 838, and 848, and I/O devices. The I/O devices in each analog front-end device are powered by different potentials. The bus module in each analog front-end device can transmit signals between I/O devices.

In one embodiment, taking the analog front-end device 820 as an example, the monitoring module 822 in the analog front-end device 820 selects a battery cell in the battery pack 812 and provides the status of the battery cell to the analog-to-digital converter 826. The analog-to-digital converter 826 of the analog front-end device 820 converts the state of the battery unit (which is an analog signal) into a digital signal, and transmits the digital signal to the bus engine 828. The bus engine 828 is a controller in the analog front-end equipment 820 and can communicate with the central electronic control unit 860.

Each of the analog front-end devices 820, 830, and 840 can communicate with the central electronic control unit 860 in a master mode or a slave mode. When the analog front-end device is working in the main mode, the bus engine of the analog front-end device sends out a signal and communicates with the central electronic control unit 860. For example, when the analog front-end equipment 840 is working in the main mode, the bus engine 848 sends a warning signal to the central electronic control unit 860. The warning signal is transmitted to the bus engines 838 and 828 through the vertical bus, and then to the central electronic control unit 860. When the analog front-end device is working in the slave mode, the central electronic control unit 860 sends a signal to communicate with the bus engine in the front-end analog device. For example, when the analog front-end equipment 840 is working in the slave mode, the signal from the central electronic control unit 860 is transmitted to the bus in the analog front-end equipment 820 through the vertical bus. Engine 828 is then transmitted to the bus engine 848 of the analog front-end equipment 840.

When the battery management system 800 adopts a two-wire bus protocol, each bus engine uses a three-wire bus to obtain better fault tolerance. As shown in Figure 8, there are three ports A, B, and C on the left side of the bus engine 828, and three ports A on the right side._i, B_iAnd C_i. For example, if ports A, B, A_iAnd B_iIt is set as the default port for transmitting bus signals, and if port B fails, port C can be used as a backup port for transmitting bus signals. In this way, better fault tolerance can be obtained. In one embodiment, when the battery management system 800 adopts a single-wire bus protocol, each bus engine uses two wires to obtain better fault tolerance. In other words, when the preset line cannot be used for some reasons, each bus engine uses a spare line instead of the preset line.

In one embodiment, the battery cells 802, 804, and 806 provide reference voltages for online diagnosis (identification of problems) and corrections. In other words, the common potential shared by the analog front-end devices 820, 830, and 840 can be used for online diagnosis and correction. More specifically, in one embodiment, the central electronic control unit 860 further includes an accurate analog-to-digital converter (not shown) for online diagnosis and calibration. The above-mentioned "precise analog-to-digital converter" or "precise converter" means that the analog-to-digital converter/converter converts a voltage to a value, and the difference between the value and the true value is less than a critical value. The voltage of the battery unit 802 is converted by the accurate analog-to-digital converter in the central electronic control unit 860 and the internal-to-digital converter 826 in the analog front-end device 820. If the two conversion results are different, the analog-to-digital converter 826 is corrected. Similarly, the voltage of the battery cell 804 passes through the corrected analog-to-digital converter 826 and the analog front-end equipment 830 The analog-to-digital converter 836 performs the conversion, and then diagnoses and corrects the analog-to-digital converter 836. Therefore, all analog-to-digital converters in the analog front-end devices 820, 830, and 840 can be diagnosed and corrected. Therefore, online diagnosis and correction can be implemented relatively easily in the battery management system 800.

An external precision reference voltage (not shown) can be used as the reference voltage described above to perform online diagnosis and correction of the analog-to-digital converter.

FIG. 9 shows a schematic diagram of a battery management system 900 according to another embodiment of the present invention. The components in FIG. 9 with the same component symbols as those in FIG. 8 have the same functions, and will not be repeated here. The battery management system 900 includes a battery 810, analog front-end devices 920, 930, and 940, and a central electronic control unit 860. The battery 810 includes battery packs 812, 814, and 816. The analog front-end devices 920, 930, and 940 coupled to the battery 810 can obtain the status of the battery cells in the battery 810. The central electronic control unit 860 coupled to the analog front-end device 920 can communicate with the target analog front-end device among the analog front-end devices 920, 930, and 940.

Although FIG. 9 shows three busbar modules, the present invention is not limited to this.

In an embodiment, the analog front-end devices 920, 930, and 940 are the same and can be integrated into a chip. In one embodiment, the analog front-end equipment 920 includes a monitoring module 822, a bus module 824, an analog-to-digital converter 826, a bus engine 828, a voltage regulator 952, and an I/O device (not shown). Similarly, the analog front-end equipment 930 includes a monitoring module 832, a bus module 834, an analog-to-digital converter 836, a bus engine 838, a voltage regulator 954, and an I/O device (not shown). The analog front-end equipment 940 includes a monitoring module 842, a bus module 844, Analog-to-digital converter 846, bus engine 848, voltage regulator 956, and I/O devices (not shown). In an embodiment, the voltage regulators 952, 954, and 956 may be low-dropout regulators.

In one embodiment, the positive terminal voltage of a battery cell in each battery pack 812, 814, and 816 and the output voltage of the voltage regulators 952, 954, and 956 provide a common potential, so that the analog front-end devices 920, 930 and 940 bus signal transmission. For example, the positive terminal voltage of the battery cell 804 in the battery pack 812 and the output voltage of the voltage regulator 954 in the analog front-end device 930 provide a common potential, so as to enable signal transmission between the analog front-end devices 920 and 930.

In one embodiment, the voltage regulators 952, 954, and 956 provide reference voltages for online diagnosis and correction. In one embodiment, the central electronic control unit 860 further includes an accurate analog-to-digital converter (not shown) for online diagnosis and calibration. In this case, the output voltage of each voltage regulator is converted through a precise analog-to-digital converter and the analog-to-digital converters in the analog front-end devices 920, 930, and 940, which will not be repeated here.

An external precision reference voltage (not shown) can be used as the reference voltage described above to perform online diagnosis and correction of the analog-to-digital converter.

FIG. 10 shows a flowchart 1000 of a method for enabling signal transmission according to an embodiment of the present invention. FIG. 10 will be described in conjunction with FIG. 4.

In step 1002, the signal is at potential (VDD=V₁, GND=V₀) And potential (VDD=V₃, GND=V₂) Between transfers. The I/O device 426 in the bus module 420 is determined by the potential (VDD=V₁, GND=V₀)powered by. The I/O device 428 in the bus module 420 is determined by the potential (VDD=V₃, GND=V₂) powered by. The upstream signal path transmits signals from the I/O device 426 to the I/O device 428. The downstream signal path transmits signals from the I/O device 428 to the I/O device 426.

In step 1004, the signal is transmitted between the bus modules 420 and 430. The common potential shared by the bus module 420 and 430 (VDD=V₃, GND=V₂) Enable signal transmission between them.

The above specific embodiments and drawings are only common examples of the present invention. Obviously, various additions, modifications and substitutions can be made without departing from the spirit and protection scope of the present invention defined by the appended patent application. Those with ordinary knowledge in the technical field should understand that the present invention can be used in actual applications in terms of form, structure, layout, proportions, materials, elements, components and other aspects according to specific environment and work requirements without departing from the principles of the invention. Has changed. Therefore, the embodiments disclosed herein are only for illustration rather than limitation, and the scope of the present invention is defined by the scope of the attached patent application and its legal equivalents, and is not limited to the previous description.

<p>100Battery Management System</p><p>112, 114, 116Battery pack</p><p>122, 124, 126Analog front-end equipment</p><p>132, 134, 136Optical Coupler Module</p><p>140Central Electronic Control Unit</p><p>200Vertical bus circuit</p><p>212Input terminal</p><p>214node</p><p>218output</p><p>220Bus Module</p><p>222Upstream signal path</p><p>223~228Field Effect Transistor</p><p>229Inverter</p><p>230Bus Module</p><p>232Upstream signal path</p><p>233~238Field Effect Transistor</p><p>239Inverter</p><p>240Bus Module</p><p>242Upstream signal path</p><p>243~248Field Effect Transistor</p><p>249Inverter</p><p>252, 256node</p><p>262, 264, 266, 268Resistor</p><p>272, 274, 276Inverter</p><p>284, 286, 288Field Effect Transistor</p><p>294, 296, 298Inverter</p><p>300Vertical bus circuit</p><p>312Input terminal</p><p>314node</p><p>318output</p><p>320Bus Module</p><p>322Downstream signal path</p><p>325Field Effect Transistor</p><p>326Field Effect Transistor</p><p>323~328Field Effect Transistor</p><p>329Inverter</p><p>330Bus Module</p><p>332Downstream signal path</p><p>333~338Field Effect Transistor</p><p>339Inverter</p><p>340Bus Module</p><p>342Downstream signal path</p><p>343~348Field Effect Transistor</p><p>349Inverter</p><p>352node</p><p>356node</p><p>362, 364, 366, 368Resistor</p><p>372, 374, 376Inverter</p><p>384, 386, 388Field Effect Transistor</p><p>394, 396, 398Inverter</p><p>400Vertical bus circuit</p><p>402, 404, 406, 408node</p><p>410Battery</p><p>412, 414, 416Battery pack</p><p>420Bus module</p><p>422Upstream signal path</p><p>423Field Effect Transistor</p><p>424Downstream signal path</p><p>425Field Effect Transistor</p><p>426Input/Output (I/O) Equipment</p><p>427Field Effect Transistor</p><p>428Input/Output (I/O) Equipment</p><p>430Bus module</p><p>432Upstream signal path</p><p>434Downstream signal path</p><p>436,438Input/Output Device</p><p>440Bus Module</p><p>442Upstream signal path</p><p>444Downstream signal path</p><p>446,448Input/Output Device</p><p>452, 456node</p><p>462, 464, 466, 468Resistor</p><p>472Inverter</p><p>482Battery Unit</p><p>488Field Effect Transistor</p><p>492,494Battery unit</p><p>498Inverter</p><p>500Vertical bus circuit</p><p>520Bus module</p><p>530Bus module</p><p>540Bus Module</p><p>552, 554, 556Voltage regulator</p><p>600Vertical Bus Topology</p><p>604,606Battery unit</p><p>612, 614, 616Battery pack</p><p>620Bus Module</p><p>630Bus Module</p><p>640Bus module</p><p>700Vertical Bus Topology</p><p>702, 704Battery unit</p><p>712, 714, 716Battery pack</p><p>720Bus Module</p><p>730Bus Module</p><p>740Bus Module</p><p>752, 754, 756Voltage regulator/low dropout regulator</p><p>800Battery Management System</p><p>802, 804, 806Battery unit</p><p>810Battery</p><p>812, 814, 816 battery pack</p><p>820Analog front-end equipment</p><p>822Monitoring Module</p><p>824Bus Module</p><p>826Analog-to-digital converter</p><p>828Bus Engine</p><p>830Analog front-end equipment</p><p>832Monitoring Module</p><p>834Bus Module</p><p>836Analog to Digital Converter</p><p>838Bus Engine</p><p>840Analog front-end equipment</p><p>842Monitoring Module</p><p>844Bus Module</p><p>846Analog-to-digital converter</p><p>848Bus Engine</p><p>860Central Electronic Control Unit</p><p>900Battery Management System</p><p>920, 930, 940Analog front-end equipment</p><p>952, 954, 956Voltage regulator</p><p>1000Method flow</p><p>1002, 1004step</p>

The technical method of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious. Among them: FIG. 1 shows a schematic diagram of a battery management system of an optically coupled vertical busbar in the prior art.

FIG. 2 shows a schematic diagram of a vertical busbar circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a vertical bus circuit according to an embodiment of the invention.

FIG. 4 shows a schematic diagram of a vertical bus circuit according to an embodiment of the invention.

FIG. 5 shows a schematic diagram of a vertical bus circuit according to another embodiment of the present invention.

Fig. 6 is a schematic diagram of a vertical bus topology of a battery management system according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a vertical bus topology of a battery management system according to another embodiment of the present invention.

Fig. 8 shows a schematic diagram of a battery management system according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of a battery management system according to another embodiment of the present invention.

FIG. 10 shows a flowchart of a method for enabling signal transmission according to an embodiment of the present invention.