First in first out device and method thereof

First in first out device and implementation method thereof

First in first out device and method thereof

The present invention relates to a First In First Out (FIFO) device, and more particularly to a first in first out device for spanning different power domains.

In a digital circuit, a clock signal (or simply a clock signal) is usually used to define a time reference for data movement in a circuit, and to enable a component driven by a clock signal in the circuit to receive a clock signal. The clock tree is usually used from one of the clock signals or its source to be used by the internal components of the integrated circuit (IC), but the clock tree is generated before and after the generation. There will be a delay between the pulse signals, so the data retention time (Hold Time) must be adjusted accordingly.

With the increasing awareness of environmental protection, if the IC is under Power Down or Power Saving, its low power consumption requirements for ICs are becoming more and more demanding. The current technology is to divide IC cutting into ICs. Different power domains (Power Domain). As shown in FIG. 1A, the IC is divided into three different power domains PD1 to PD3, and the power domains PD1 to PD3 each have their corresponding power supplies P1 to P3. In the Power Down or Power Saving state, only the power domain required to perform the enabling action and the corresponding power source are retained to achieve the minimum power consumption requirement.

Please refer to Figure 1B. Figure 1B shows some of the circuits in different power domains. As shown in FIG. 1B, 10 and 11 in the figure represent a virtual buffer or delay unit for indicating the delay between the clock tree generated by the source clock and the source clock. The buffer or delay units 10 and 11 in the figure are only delay diagrams of the clock tree, non-true buffers or delay units, and the buffers of the actual clock tree are not labeled.

The source terminal (power domain PD1) in FIG. 1B is provided with an input register 13 that receives the input signal In and is driven by the source clock SC through the first clock signal TC1 generated by the delay unit 10, and inputs the signal In. The data is transmitted from the input register 13 to the output buffer 15 of the back end, and an output signal Out is output. The lines of the first clock signal TC1 and the second clock signal TC2 output by the delay units 10 and 11 can be generated by clock tree synthesis. The ideal first clock signal TC1 and the second clock signal TC2 will be substantially equal (close to alignment), as shown in the timing below in FIG. 1B.

However, even if the voltages originally planned by different independent power domains are the same, in fact, because of the different power consumption of different power domains, the voltage of the power domain will produce different voltage drops, and the clock tree will have different delay time changes. As shown in Fig. 1C, in order to encounter the above problem, since there is still data transmission in different power domains, if the data is transmitted synchronously, it will be time-consuming due to different power consumption of different power domains. The delay time of the pulse tree changes. It can be understood from the timing below the 1C figure that since the supply voltage of the power domain PD1 is higher than the power domain PD2, the first clock signal TC1 is faster than the second clock signal TC2 (as indicated by the dotted line), and maintenance is maintained. The status of the time violation (Hold Time Violation).

On the contrary, please refer to the 1D picture. It can be seen from the timing below the 1D picture that when the supply voltage of the power domain PD2 is higher than the power domain PD1, the second clock signal TC2 will be faster than the first clock signal TC1 (such as the dotted line). As shown in the table), a Set Up Time Violation condition will also occur.

One of the objectives of the present invention is to provide a First In First Out (FIFO) device and method that solves Set Up Time Violation or hold time due to voltage differences across different power domains. The status of the Hold Time Violation.

An embodiment of the present invention provides a first-in first-out device that spans a first power domain and a second power domain, wherein the first in first out device receives an input signal, and the first in first out device includes a plurality of inputs. A register, a first controller, a multiplexer, a second controller, and an output register. a plurality of input buffers belonging to the first power domain for receiving the input signal, and each input buffer has a first output data; the first controller belongs to the first power domain, and is configured to The sequence is such that the input buffer is input, and a start signal is generated; the multiplexer is coupled to the input register, receives the first output data, and outputs the first output data according to the sequence to generate a second output data; the second controller The second power domain receives the start signal through a non-synchronous interface, and generates a control signal according to the start signal to control the multiplexer to output the second output data; the output register belongs to the second power domain for receiving Second output data. The first power domain operates according to a first clock signal, the second power domain operates according to a second clock signal, and the second clock signal is out of synchronization with the first clock signal.

An embodiment of the present invention provides a method for implementing a first-in first-out device that spans a first power domain and a second power domain, and includes the steps of: receiving an input signal by using a plurality of input registers, wherein the input Each of the registers has a first output data; a first controller is configured to input the register according to an order, and generate a start signal; and the first output data is received by the multiplexer according to a multiplexer Outputting the first output data sequentially to generate a second output data; receiving a start signal through a non-synchronous interface by a second controller, and generating a control signal according to the start signal to control the multiplexer output second Outputting data; and receiving the second output data by an output register.

Wherein, the plurality of input registers and the first controller belong to the first power domain; the multiplexer, the second controller, the asynchronous interface and the output register belong to the second power domain; and the first power domain is based on The first clock signal operates, the second power domain operates according to a second clock signal, and the second clock signal is out of synchronization with the first clock signal.

Please refer to FIG. 2A. FIG. 2 is a schematic diagram of an embodiment of a first in first out (FIFO) device 200 of the present invention. The FIFO device 200 includes the power domains PD1 and PD2, and the power domains PD1 and PD2 are different because the originally planned supply voltages are different or the originally planned supply voltages are the same but different due to different voltage drops. The supply voltage is not the same.

In this embodiment, the FIFO device 200 includes input registers 201-203, a first controller 204, a multiplexer 205, a second controller 206, an output register 207, delay units 208a-208b, and a non-synchronized interface 209. . In one embodiment, the first controller 204 and the input registers 201-203 are disposed in the power domain PD1; and the multiplexer 205, the second controller 206, the output register 207, the delay unit 208b, and the asynchronous interface 209 is set in the power domain PD2.

Note here that the delay units 208a, 208b indicate delays caused by the source clock signal SC being different due to the difference in voltage between the two power domains or the load (line length, etc.). Therefore, the clock signals between the source clock signal SC and the clock signal of the clock tree and the different power domains of the clock tree are not synchronized and have a phase difference (for example, the source clock signal SC and the clock signal of the clock tree) It can be the same frequency but has a phase difference, so it can be regarded as out of sync). Since the power consumption difference between the power domain PD1 and the PD2 is different or the originally planned supply voltage is different, the delay of the clock tree changes with the supply voltage difference between the power domains PD1 and PD2. Therefore, the power domain PD1 operates according to the first clock signal PS1, and the power domain PD2 operates according to the second clock PS2. The first clock signal PS1 and the second clock signal PS2 are clock trees generated by the source clock signal SC.

Please note that the input registers 201-203 and the first controller 204 are driven by the first clock signal PS1, and the second controller 206 and the output register 207 are driven by the second clock signal PS2.

The input buffers 201-203 are configured to receive an input signal IS, wherein the input signal IS can be a single bit or contain multi-bit data, and the invention is not limited thereto, and the input register 201 is input. ~203 respectively generate first output data OS1~OS3. The input registers 201-203 are respectively coupled to the input ends of the multiplexer 205.

The first controller 204 is coupled to the input registers 201-203, and drives the input registers 201-203 in a predetermined sequence to sequentially write the data of the input signals into the input registers 201-203.

When the first controller 204 generates a start signal ES and transmits it to the second controller 206, it indicates that the first controller 204 has started to operate. Since the first controller 204 belongs to the power domain PD1 and the second controller 206 belongs to the power domain PD2, the second controller 206 receives the start signal ES through the asynchronous interface 209.

The second controller 206 generates a control signal CS according to the start signal ES to control the multiplexer 205 to generate the first output data OS1~OS3. After the second controller 206 receives the start signal ES, the multiplexer 205 is driven by the control signal to sequentially output the first output data OS1~OS3. The output register 207 receives the first output data OS1~OS3 to generate a second output material OS4.

In an embodiment of the invention, the input registers 201-203 and the output register 207 are D-type flip-flops (D Flip-Flop). In addition, the first controller 204 includes a first counter 204a, and the second controller 206 includes a second counter 206a. The first counter 204a and the second counter 206a count according to the source clock signal SC, and the second counter 206a counts from a starting value (for example, zero) after the second controller 206 receives the start signal ES. The first controller 204 and the second controller 206 control the order in which the input registers 201 to 203 read the input signals IS according to the values counted by the first counter 204a and the second counter 206a, respectively.

Figure 2B is a schematic diagram showing the asynchronous interface of one embodiment of the present invention. The asynchronous interface 209 can be implemented in one example by a secondary flip-flop.

Please refer to the 2C and 2D diagrams at the same time. FIG. 2C shows a timing diagram of an implementation of the FIFO device of the present invention (assuming that the supply voltage of the power domain PD1 is higher than the supply voltage of the power domain PD2), and FIG. 2D shows an implementation of the FIFO device of the present invention. Timing diagram (assuming that the supply voltage of the power domain PD2 is higher than the supply voltage of the power domain PD1).

As shown in FIG. 2C, in the present embodiment, the three sets of input buffers 201-203 in the FIFO device 200 are sequentially stored in the register 201 by the control of the first controller 204. 203. For example, when T=0, the count value of the first counter is 0. At this time, the first controller controls the register 201 to read the input signal IS (D00). When T=1, the count value of the first counter is 1, the first controller controls the register 202 to read the input signal IS (D01), and the register 201 outputs the data OS1 (D00). When T=2, the count value of the first counter is 2, the first controller controls the register 203 to read the input signal IS (D02), and the register 201 outputs the data OS1 (D00) and the register 202. Output data OS2 (D01). Then, when T=3, the count value of the first counter returns to 0. At this time, the first controller controls the register 201 to read the input signal IS (D10), and the register 201 outputs the data OS1 (D00). The register 202 outputs the data OS2 (D01), and the register 203 outputs the data OS3 (D02), and so on. Therefore, the three sets of input registers 201 to 203 sequentially read the input signals IS and sequentially output the output signals. Since the FIFO device 200 has three sets of input registers 201-203, the output of each set of input registers can be maintained for three cycles.

In order to enable the input signal IS to be smoothly transmitted from the power domain PD1 to the power domain PD2, an embodiment of the present invention controls the output of the multiplexer 205 by the asynchronous interface 209 and the first controller 206. The detailed operation principle is as follows.

In FIG. 2C, the supply voltage of the power domain PD1 is higher than the supply voltage of the power domain PD2. Therefore, the first clock signal PS1 will advance the second clock signal PS2. Additionally, according to an embodiment, the non-synchronous interface 209 is comprised of a two-stage D-type flip-flop. The asynchronous interface 209 can sample the initial signal ES output by the first controller 204 according to the second clock signal PS2 and output it to the second controller 206. For example, when T=0 in FIG. 2C, the asynchronous interface 209 is sampled by the second clock signal PS2 to the start signal ES output by the first controller 204, and then transmitted to the second controller 206 when T=1. The second counter 206a of the second controller 206 starts counting by 0. Meanwhile, the second controller 206 also controls the multiplexer 205 to output its output data OS1 (D00). Next, when T=2, the output register 207 outputs its output data OS4 (D00). In this way, when the supply voltage of the power domain PD1 is higher than the supply voltage of the power domain PD2, the input signal IS(D00) entering the FIFO device 200 at T=0 can be output by the power domain PD2 when T=2. In other words, after the second counter 206 in the FIFO device 200 is triggered by the start signal ES, counting (0~2) according to the second clock signal PS2 is started, so that the second controller 206 controls the multiplexer 205 to sequentially ( 0~2) Output data D00~Dnm of the output registers 201~203. Finally, the output is further output by the output register 207. Therefore, the architecture of the present invention can solve the problem of the hold time between the first clock signal PS1 of the power domain PD1 and the second clock signal PS2 of the power domain PD2. It should be noted that, in this embodiment, the first-in first-out device 200 has three input registers 201-203, and the second output data OS4 generated by the output buffer 207 is behind the input signal IS by at least two first clocks. The clock period of the signal PS1. In another embodiment, the first-in first-out device 200 may also have more than three input registers, but the more the input registers, the longer the second output data OS4 will fall behind the input signal IS.

The difference between the 2D and 2C is that the supply voltage of the power domain PD1 is lower than the supply voltage of the power domain PD2, so the second clock signal PS2 is ahead of the first clock signal PS1. Due to the time relationship of the asynchronous interface 209 sampling the start signal ES, the second counter 206a will actually lag behind the first counter 204a for two cycles. Therefore, the input signal IS (D00) entering the FIFO device 200 at T=0 can be output from the power domain PD2 when T=3. Under this design, it can be seen from the timing diagram that the output register 207 can still correctly access the data stored in the three-stage input registers 201-203. Therefore, the problem of the setup time between the first clock signal PS1 of the power domain PD1 and the second clock signal PS2 of the power domain PD2 can be solved. It should be noted that, in the embodiment, the first-in first-out device 200 has three input registers 201-203, and the second output data OS4 generated by the output buffer 207 is behind the input signal IS by at least three first clocks. The clock period of the signal PS1. In another embodiment, the first-in first-out device 200 may also have more than three input registers, but the more the input registers, the longer the second output data OS4 will fall behind the input signal IS.

Please refer to FIG. 3, which shows a schematic diagram of a first-in first-out device spanning a first power domain and a second power domain according to an embodiment of the invention. The difference between the first in first out device 300 and the first in first out device 200 is that the source clock signal SC can also belong to another power domain PD3, and the first clock signal PS1 and the second clock signal PS2 are based on the source clock. The clock generated by the signal SC, but each of the three is driven by a different power source, and the rest of the operation principle is the same as the foregoing, and will not be further described herein. Please refer to FIG. 4, which shows a cross-first power domain (Power) according to an embodiment of the invention. The method for implementing the first-in first-out device of the second power domain includes the following steps: Step S401: receiving an input signal by using a plurality of input buffers, wherein each of the input registers has a first output Data step S402: using a first controller to enable the input registers according to an order, and generating a start signal; and step S403: receiving a start through a non-synchronized interface by using a second controller a signal, and a control signal is generated according to the start signal to control the multiplexer to output the second output data. Step S404: receiving, by a multiplexer, the first output data, and outputting the first output data according to the sequence. The second output data is received by the output buffer; and the second output data is received by the output buffer; wherein the plurality of input registers and the first controller belong to the first power domain; the multiplexer and the second The controller, the asynchronous interface and the output register belong to the second power domain; and the first power domain operates according to a first clock signal, and the second power domain is operated according to a second clock signal And the second power supply when the first clock signal and the clock signal may be unsynchronized or different phases. In an embodiment, the second clock signal PS2 and the first clock PS1 signal are respectively clock signals generated according to the source clock signal SC.

In summary, the first-in-first-out (FIFO) device of the present invention spans two power domains by using a plurality of registers in the first power domain to temporarily store the input signals in sequence, so that each input is input. The storage period of the signal is increased, so that the circuitry in the second electrical domain can have a relatively large amount of time to read the data from the scratchpad. Therefore, it solves the situation of Set Up Time Violation and Hold Time Violation caused by different voltages across different power domains.

<p>200, 300. . . First in first out device</p><p>13, 201~203. . . Input register</p><p>204, 206. . . Controller</p><p>205. . . Multiplexer</p><p>15,207. . . Output register</p><p>208a, 208b, 10, 11. . . Delay unit</p><p>209. . . Asynchronous interface</p><p>PD1~PD3. . . Power domain</p><p>P1~P3. . . Supply voltage</p><p>S301~S305. . . step</p>

Figure 1A shows a schematic diagram of the IC divided into different power domains.

Figure 1B is a schematic illustration of the prior art in an ideal state.

FIG. 1C is a schematic diagram of the prior art power supply domain PD1 when the supply voltage is higher than the power supply domain PD2.

FIG. 1D is a schematic diagram of the prior art power supply domain PD2 when the supply voltage is higher than the power supply domain PD1.

Fig. 2A is a schematic view showing an embodiment of the first-in first-out device of the present invention.

2B is a schematic diagram of a non-synchronous interface of an embodiment of the present invention.

Figure 2C shows a timing diagram of an implementation of the FIFO device of the present invention (the supply voltage of the power domain PD1 is higher than the supply voltage of the power domain PD2).

Figure 2D shows a timing diagram of an implementation of the FIFO device of the present invention (the supply voltage of the power domain PD2 is higher than the supply voltage of the power domain PD1).

Figure 3 is a schematic illustration of an embodiment of the first-in first-out device of the present invention.

Figure 4 is a flow chart showing an embodiment of the FIFO device of the present invention.