Solid state lighting devices and associated methods of manufacturing

Solid state lighting device and related manufacturing method

SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS OF MANUFACTURING

The technology of the present invention generally relates to solid-state lighting (SSL) devices and related manufacturing methods.

SSL devices generally use semiconductor light emitting diodes (LED), organic light emitting diodes (OLED) and/or polymer light emitting diodes (PLED) instead of electric wires, a plasma or a gas as the illumination source. FIG. 1A is a cross-sectional view of a part of a conventional indium gallium nitride (InGaN) LED 10. As shown in FIG. 1A, the LED 10 includes a silicon substrate 12 arranged one above the other in order, an N-type gallium nitride (GaN) material 14, an InGaN material 16 (and/or InGaN/GaN multiple quantum wells) and a P-type GaN material 18. The LED 10 also includes a first contact 20 on the P-type GaN material 18 and a second contact 22 on the N-type GaN material 14.

One disadvantage of the LED 10 in FIG. 1A is that the coefficient of thermal expansion (TEC) between the GaN/InGaN materials 14, 16 and 18 and the silicon substrate 12 is different and can cause the LED 10 to bow under thermal stress and/or bend in other ways. song. This bowing or deflection may cause the GaN/InGaN materials 14, 16 and 18 of the LED 10 to fracture and/or have other structural defects.

Another disadvantage of LED 10 is that the silicon substrate 12 usually includes silicon wafers with a Si(1,1,1) lattice orientation instead of their silicon wafers with a Si(1,0,0) lattice orientation. . FIG. 1B is a schematic perspective view of a part of the silicon lattice, which illustrates both the Si(1,1,1) and Si(1,0,0) lattice orientations. It is believed that the epitaxial growth of GaN/InGaN materials 14, 16 and 18 prefers a hexagonal lattice structure provided by Si(1,1,1) wafers. However, Si(1,1,1) wafers are more expensive than commonly used Si(1,0,0) wafers. Therefore, several improvements in the reliable and cost-effective manufacturing of LEDs can be expected.

Various embodiments of the microelectronic substrate with LEDs formed thereon and related manufacturing methods are described below. The term "microelectronic substrate" is used throughout the text to include substrates on and/or in which microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. The term "silicon" usually refers to having a lattice spacing of 5.430710<img file="TWI463558B_D0001.tif" he="50" id="i0001" img-content="character" img-format="tif" inline="no" orientation="portrait" wi="41" />A single crystal silicon material with a face-centered prismatic cube structure. The term "silicon (1,0,0)" and the term "silicon (1,1,1)" usually refer to the crystal lattice orientation (1,0,0) and (1,1) defined by the Miller index, respectively ,1). One of the discussions on the Miller Index can be found in the Handbook of Semiconductor Silicon Technology by William C. O'Mara, the disclosure of which is incorporated herein by reference in its entirety. Those familiar with the related art will also understand that the technology of the present invention may have additional embodiments, and that the technology of the present invention may be practiced without some details of the embodiments described below with reference to FIGS. 2A to 5B.

2A and 2B are cross-sectional views of a portion of a microelectronic substrate 100 undergoing a surface modification process according to an embodiment of the present technology. In the embodiment shown in FIGS. 2A and 2B, the microelectronic substrate 100 includes a silicon material with Si(1,0,0) orientation. In other embodiments, in addition to or instead of the silicon material with Si(1,0,0) orientation, the microelectronic substrate 100 may also include sapphire (Al₂O₃), silicon nitride (SiN) and/or other suitable substrate materials.

As shown in FIG. 2A, an initial stage of the process may include depositing a mask material 102 on a surface 101 of the microelectronic substrate 100. In one embodiment, the mask material 102 includes silicon oxide (SiO₂) And/or silicon nitride (SiN). In other embodiments, the mask material 102 may include a photoresist and/or other suitable mask materials deposited by spin coating and/or other suitable deposition techniques.

Then, the process may include patterning the deposited mask material 102 via photolithography and/or other suitable techniques. Subsequently, certain portions of the patterned mask material 102 can be removed by wet etching, plasma etching, laser ablation, and/or other material removal techniques. As shown in FIG. 2A, removing selected portions of the mask material 102 forms a mask having openings 104 through which selected portions of the surface 101 of the microelectronic substrate 100 are exposed.

As shown in FIG. 2B, the process may include forming hexagonal crystals on the surface 101 of the microelectronic substrate 100 by removing material from the exposed portion of the surface 101 (eg, etching the microelectronic substrate 100 through the opening 104). Grid plane. In the illustrated embodiment, the microelectronic substrate 100 includes a Si(1,0,0) wafer that can react with an alkaline anisotropic etchant (e.g., having a pH greater than about 12) as follows:

<i>Si</i> +4(<i>OH</i>^- )→<i>Si</i> (<i>OH</i> )₄ +4<i>e</i>^-

Examples of anisotropic etchants may include tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), ammonium hydroxide (NH₄OH), ethylenediaminecatechol (EDP) and/or another suitable anisotropic etchant. In other embodiments, the process may include treating the exposed portion of the surface 101 with other suitable types of etchant based on the specific material of the microelectronic substrate 100.

Without being bound by theory, it is believed that TMAH and other anisotropic etchants can etch silicon substrates along different crystal planes at different material removal rates. For example, it is believed that TMAH can be removed from Si(1,0 ,0) The silicon material is removed from the plane. Therefore, the Si(1,1,1) plane can serve as an etching stop layer when etching silicon material in the Si(1,0,0) plane. Therefore, treating the exposed portion of the surface 101 of the microelectronic substrate 100 with an alkaline etchant can form a plurality of recesses 111 with Si(1,1,1) plane 106. The mask material 102 can then be removed by wet etching, laser ablation, and/or other suitable techniques.

By controlling various parameters of the material removal operation, the recessed portion 111 can have certain contours. For example, as shown in FIG. 2B, the individual recessed portion 111 may include two adjacent Si(1,1,1) planes 106 extending from the surface 101 toward the microelectronic substrate 100 and intersecting each other at a bonding surface 107 A "zigzag" pattern is formed when a long etching cycle is used. Two adjacent Si(1,1,1) planes 106 may form an angle of about 72°. In other embodiments, as shown in FIG. 2C, if the etching cycle is shortened, the individual recessed portion 111 may include two adjacent Si(1,1,1) planes 106 extending from the surface 101 toward the microelectronic substrate 100 and the intermediate A Si(1,0,0) plane 105 between two Si(1,1,1) planes 106. The first and second planes 106 form an angle of approximately 54° and 126° with respect to the Si(1,0,0) plane 105. In any of the foregoing embodiments, the individual recessed portion 111 may extend to a depth d from the surface 101 in the microelectronic substrate 100.

In some embodiments, the process includes adjusting the etching parameters to control the depth d and/or the final shape of the individual recesses 111. The etching parameters may include a concentration of an etchant, an etching temperature, an etching period, adding suitable additives and/or other suitable etching parameters. In some embodiments, the depth d may be large enough (e.g., greater than about 100 microns) so that the GaN/InGaN materials 116 and 118 (FIG. 3A to FIG. 3C) formed later do not coalesce on the microelectronic substrate 100. As discussed in more detail below with reference to FIGS. 3A to 3C. For example, in these embodiments, each of the GaN/InGaN materials 116 and 115 may have an independent substantially constant thickness. In other embodiments, the depth d may be sufficiently small (for example, less than about 1 micron) so that the GaN/InGaN material formed later is indeed coalesced on the microelectronic substrate 100, as described in more detail below with reference to FIGS. 4A to 4C Discourse. In these embodiments, one or more of the GaN/InGaN materials may have a varying thickness. In further embodiments, the depth d may have other desired values to partially coalesce the GaN/InGaN material formed later.

3A to 3C are cross-sectional views of a portion of the microelectronic substrate 100 that has undergone a process of forming a non-planar LED structure according to an embodiment of the present technology. As shown in FIG. 3A, the process may include forming an LED structure 108 on the surface 101 of the microelectronic substrate 100 having the recessed portion 111. In one embodiment, forming the LED structure 108 may include sequentially depositing an N-type GaN material 114 (for example, doped with silicon), an InGaN material 116, and a P-type GaN material 118 (for example, Doped with magnesium). In other embodiments, forming the LED structure 108 may also include depositing gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium phosphide ( III) (GaP), zinc selenide (ZnSe), boron nitride (BN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum gallium indium nitride (AlGaInN) and/or other suitable semiconductors At least one of the materials. The technology used to form the LED structure 108 may include metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy, and/or other suitable technologies.

In the illustrated embodiment of FIG. 3A, the LED structure 108 includes a non-planar first surface 120 and a second surface 122 each having a zigzag pattern. The first surface 120 and the second surface 122 generally conform to the zigzag pattern of the Si(1,1,1) plane 106 on the surface 101 of the substrate. Without being bound by theory, it is believed that the zigzag pattern of the first surface 120 and the second surface 122 can at least reduce the deflection of the GaN/InGaN materials 114, 116, and 118 relative to the microelectronic substrate 100 under thermal stress. It is believed that the difference in TEC between the GaN/InGaN materials 114, 116, and 118 and the substrate 100 can generate tensile stress along the first surface 120 and the second surface 122 (as indicated by arrows 124a and 124b). As shown in FIG. 3A, the zigzag pattern forces the tensile stresses 124a and 124b to be at least partially opposite to each other along both sides of the zigzag pattern. Therefore, the tensile stresses 124a and 124b may at least partially cancel each other (e.g., in the horizontal plane X) to reduce the bowing of the materials 114, 116, and 118 and/or otherwise deflection.

As shown in FIG. 3B, the process may then include removing a bottom portion 103 of the microelectronic substrate 100 via a mechanical process (such as back grinding and/or other suitable techniques). As shown in FIG. 3C, the process may also include removing the remaining microelectronic substrate 100 from the LED structure 108 via wet etching, dry etching, and/or other suitable techniques. The process may further include forming the first contact 20 and the second contact 22 for the P-type GaN material 118 and the N-type GaN material 114, respectively, and/or other subsequent processing operations.

4A and 4B are cross-sectional views of a portion of the microelectronic substrate 100 that has undergone a process of forming a partially planar LED structure according to an embodiment of the present technology. Fig. 4C is a partial enlarged cross-sectional view of a part of the planar LED in Fig. 4B. As shown in FIG. 4A, the process may include sequentially depositing an N-type GaN material 114 (e.g., doped with silicon), an InGaN material 116, and a P-type GaN material 118 (e.g., , Doped with magnesium) to form an LED structure 108 on the microelectronic substrate 100. In the illustrated embodiment, the N-type GaN material 114 coalesces while being formed on the microelectronic substrate 100. Therefore, the thickness of the N-type GaN material 114 is not constant so that it has a substantially flat surface 115 opposite to the microelectronic substrate 100. In other embodiments, the InGaN material 116 and/or the P-type GaN material 118 may coalesce to have a substantially planar surface (not shown in the figure). The process may then include removing a bottom portion of the microelectronic substrate 100 via backgrinding and removing from the LED structure 108 via wet etching, dry etching, and/or other suitable techniques as discussed above with reference to FIGS. 3B and 3C The remaining microelectronic substrate 100 is used to produce the LED structure 108 as shown in FIG. 4B.

It is believed that coalescing at least one of the GaN/InGaN materials 114, 116, and 118 can reduce a row density of the LED structure 108. The term "difference" usually refers to a crystal defect or irregularity within a crystal structure. For example, as shown in FIG. 4C, the N-type GaN material 114 includes a first differential row 126a and a second differential row 126b on both sides of the zigzag pattern. It is believed that during the deposition of the N-type GaN material 114, surface tension and/or other physical/chemical interactions can cause the first differential row 126a and the second differential row 126b to bend toward each other and here the two differential rows 126a and 126b When the Burgers vector has different signs, it forms a loop. Therefore, none of the first differential row 126a and the second differential row 126b will extend all the way to the surface 115 of the N-type GaN material 114 to reduce the differential row density of the N-type GaN material 114.

The several embodiments of the LED 108 discussed above with reference to FIGS. 2A to 5B may have an increased light-emitting surface area compared to conventional LEDs. For example, as shown in FIGS. 2B and 2C, the recessed portion 111 can increase the surface area on which the LED structure 108 (FIG. 3A to FIG. 3C) can be formed. Therefore, without increasing the occupied area of the LED structure 108, the LED structure 108 can have an increased light emitting area.

Although it is discussed above that the LED structure 108 has at least one surface with a zigzag pattern, in other embodiments, the LED structure 108 can also have other surface patterns. For example, as shown in FIG. 5A, by adjusting a width of the mask material 102 (FIGS. 2A and 2B), the concave portions 111 can be separated from each other by a plane portion 115 of the N-type GaN material 114, and InGaN and P-type GaN materials 116 and 118 may generally conform to N-type GaN material 114. Therefore, the LED structure 108 may include a non-planar first surface 120 and a second surface 122. In another embodiment, as shown in FIG. 5B, at least one of InGaN and P-type GaN materials 116 and 118 may be coalesced on N-type GaN material 114. Therefore, the LED structure 108 may include a substantially planar first surface 120 and a non-planar second surface 122. In other embodiments, the LED structure 108 may have other suitable surface patterns.

In some embodiments, the process may also include forming a mirror layer (such as aluminum, not shown in the figure) and a supporting structure (such as silicon and/or silicon oxide materials) on the first surface 120 of the LED structure 108. (Not shown in the figure) (Figures 3A to 3C). In a further embodiment, the process may include depositing a buffer material (for example, aluminum oxide, aluminum nitride, etc.) and/or other suitable materials on the surface of the microelectronic substrate 100 before forming the N-type GaN material 114 on the microelectronic substrate 100 Material (Figure 3A).

Based on the foregoing, it will be understood that specific embodiments of the technology of the present invention have been described herein for the purpose of illustration, but various modifications can be made without departing from the present invention. In addition to or in place of the elements of other embodiments, many of the elements of one embodiment can be combined with these other embodiments. Therefore, the present invention is only limited by the scope of the attached patent application.

<p>10. . . Conventional Indium Gallium Nitride (InGaN) Light Emitting Diode</p><p>12. . . Silicon substrate</p><p>14. . . N-type gallium nitride (GaN) material</p><p>16. . . Indium Gallium Nitride (InGaN) material</p><p>18. . . P-type gallium nitride (GaN) material</p><p>20. . . First contact 20</p><p>twenty two. . . Second contact 20</p><p>100. . . Microelectronic substrate</p><p>101. . . surface</p><p>102. . . Mask material</p><p>103. . . Bottom part</p><p>104. . . Opening</p><p>105. . . Si(1,0,0) plane</p><p>106. . . Si(1,1,1) plane</p><p>107. . . Joint surface</p><p>108. . . Light-emitting diode structure</p><p>111. . . Recessed part</p><p>114. . . N-type gallium nitride (GaN) material</p><p>115. . . surface</p><p>116. . . Indium Gallium Nitride (InGaN) material</p><p>118. . . P-type gallium nitride (GaN) material</p><p>120. . . First surface</p><p>122. . . Second surface</p><p>124a. . . Tensile stress</p><p>124b. . . Tensile stress</p><p>126a. . . First Poor</p><p>126b. . . Second poor</p>

Fig. 1A is a cross-sectional view of a part of an LED according to the prior art.

FIG. 1B is a schematic perspective view of a part of the silicon lattice, which illustrates the orientation of the Si(1,1,1) and Si(1,0,0) lattices.

2A to 2C are cross-sectional views of a part of a microelectronic substrate undergoing a surface modification process according to an embodiment of the present technology.

3A to 3C are cross-sectional views of a part of a microelectronic substrate undergoing a process of forming a non-planar LED structure according to an embodiment of the present technology.

4A to 4C are cross-sectional views of a part of a microelectronic substrate undergoing a process of forming a part of a planar LED structure according to an embodiment of the present technology.

5A and 5B are cross-sectional views of a part of a microelectronic substrate undergoing a process of forming an additional LED structure according to an embodiment of the present technology.