Compound semiconductor substrate, semiconductor device, and process for producing the semiconductor device

Compound semiconductor substrate, semiconductor device and manufacturing method thereof

The present invention relates to a compound semiconductor substrate with a semiconductor substrate, a semiconductor device and a manufacturing method thereof, in particular to a compound semiconductor substrate with a group III-V compound semiconductor substrate, a semiconductor device and a manufacturing method thereof.

In recent years, the industry has made full use of the various characteristics of semiconductors, led by compound semiconductors, to further expand its application range. Compound semiconductors are particularly suitable for use in manufacturing high-speed devices, optical communication devices and even microwave devices for epitaxial growth of base substrates.

When a semiconductor (including compound semiconductor) is used as the base substrate for the above-mentioned epitaxial growth, the surface of the semiconductor must be a mirror without warpage. Therefore, after the so-called "pre-processing" such as cutting, grinding, and etching of the semiconductor single crystal block, the resulting wafer is usually mirror-polished.

As this mirror polishing, for example, a method is known in which the surface of the semiconductor wafer is polished with an abrasive containing colloidal silica (for example, Patent Document 1 below), and then cleaned with pure water.

However, there is a disadvantage that it is difficult to obtain a good yield rate for devices made of a laminated body formed by disposing an epitaxial layer on a semiconductor substrate obtained by the above-mentioned method. Therefore, there is an urgent need to develop a semiconductor substrate that can overcome the above-mentioned disadvantages. .

Patent Document 1: Japanese Patent Laid-Open No. 64-87147

Patent Document 2: Japanese Patent No. 3183335

Patent Document 3: Specification of US Patent No. 6488767

Patent Document 4: Specification of US Patent No. 6951695

Patent Document 5: Japanese Patent Laid-Open No. 2006-310362

Patent Document 6: Japanese Patent No. 2599250

<p>In the above-mentioned Patent Document 2, it is speculated that the Si deposited (accumulated) on the interface between the epitaxial layer and the InP substrate may cause defects in the device having a multilayer structure of the epitaxial layer/InP substrate. On this basis, the present invention proposes The Si concentration at the interface between an epitaxial layer and the substrate is 8×10¹⁷cm^-3The following laminated body.</p><p>Among them, the Si on the epitaxial layer/substrate interface will form a high-resistance layer. This high-resistance layer will reduce the electrical characteristics of the substrate or the device characteristics of the device made from the substrate. The Si is suppressed at a low level.</p><p>After painstaking research, the inventor found a new technology that can reduce the resistance on the interface by reducing Si.</p><p>That is, the object of the present invention is to provide a compound semiconductor substrate, a semiconductor device, and a manufacturing method thereof that reduce the resistance at the interface between the epitaxial layer and the substrate.</p>

<p>The compound semiconductor substrate of the present invention is composed of a group III nitride and has a surface layer on the surface. The surface layer contains 200×10 in terms of Cl.¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less are converted to O.</p><p>After painstaking research, the inventors found that when the surface layer of the compound semiconductor substrate contains Cl, it is converted to 200×10¹⁰Solid/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less in terms of O can suppress the increase of Si at the interface between the compound semiconductor substrate and the epitaxial layer formed thereon, thereby reducing Resistance on the interface.</p><p>Also, it is preferable that the surface layer contains 300×10 in terms of Cl¹⁰Pcs/cm²Above and 8000×10¹⁰Pcs/cm²The above-mentioned chlorides below.</p><p>Furthermore, it is preferred that the surface layer contains the above-mentioned oxide in an amount of 5.0 at% or more and 12.0 at% or less in terms of O.</p><p>In addition, the surface roughness (RMS) of the surface layer may be 3 nm or less, more preferably 1 nm or less, and more preferably 0.3 nm or less.</p><p>In addition, the density of scratches with a depth of 10 nm or more and 100 nm or less from the surface may be 2 strips/cm or less, more preferably 1.2 strips/cm or less.</p><p>In addition, it may be that the depth from the surface is 2 nm or more and 20 nm or less, and the density of the processing pits with a diameter of 0.2 μm or more and 5 μm or less is 50×10⁵Pcs/cm²The following state.</p><p>In addition, the maximum depth of the scratches on the surface in the circular area of the central part other than the peripheral part except the width of 5 mm may be 100 nm or less.</p><p>In addition, it can be a form where the latent damage density on the surface is 40 strips/cm or less.</p><p>In addition, it may be an aspect in which a process-deteriorated layer is provided on the surface, and the thickness of the process-deteriorated layer is 20 nm or less.</p><p>In addition, the semiconductor substrate may have a structure in which low dislocation density regions and high dislocation density regions are alternately arranged.</p><p>In addition, it may be a aspect in which the flat surface area ratio of the semiconductor substrate is 60% or more.</p><p>In addition, it may further have an epitaxial layer formed on the surface layer and composed of a group III nitride.</p><p>The method of manufacturing a compound semiconductor substrate of the present invention is to form a surface layer on the surface of a compound semiconductor substrate composed of a group III nitride, and the surface layer contains 200×10 in terms of Cl.¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less are converted to O.</p><p>After painstaking research, the inventors found that the surface of the compound semiconductor substrate contains 200×10¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and the surface layer of oxides of 3.0at% or more and 15.0at% or less in terms of O can reduce Si on the interface between the compound semiconductor substrate and the epitaxial layer formed thereon, thereby reducing Resistance on the interface.</p><p>In addition, the surface roughness (RMS) of the surface layer may be 3 nm or less.</p><p>In addition, it may be the following aspect: in a chamber where there is a compound containing Si element and at least one element from the group consisting of C, N, and O, dry etching is performed on the surface of the compound semiconductor substrate using a chlorine-based gas, And the surface layer is formed.</p><p>In addition, it may be the following aspect: dry etching system reactive ion etching, the etching conditions are as follows: the pressure in the chamber is set to P (Pa), the gas flow rate is set to Q (sccm), and the chamber volume is set to V ( L) satisfies the relationship of the following formula:</p><p>0.05PV/Q3.0.</p><p>In addition, it may be the following aspect: the compound semiconductor substrate whose surface has been polished is subjected to surface treatment using a solution containing a chlorine compound to form a surface layer. When the value of the reduction potential is set to y(mV), the relationship of the following 2 formulas is satisfied:</p><p>-50x+1000&lt;y&lt;-50x+1800(1x6) ... (1)</p><p>-50x+800&lt;y&lt;-50x+1500(8.5x14) ... (2)</p><p>Its viscosity is above 2mPas and below 30mPas.</p><p>In addition, it can be the following aspect: the solution containing the chlorine-based compound is a solution of a compound composed only of any element of H, C, O, N, and Cl, and pure water, and the surface treatment system uses a compression rate of 1.5% or more And the polishing pad below 20%, with 30g/cm²Above and 800g/cm²Grind under the following pressure.</p><p>In addition, it may be an aspect in which an epitaxial layer composed of a group III nitride is formed on the surface layer.</p><p>The semiconductor device of the present invention includes: a compound semiconductor substrate composed of a group III nitride and having a surface layer on the surface, and the surface layer contains 200×10 in terms of Cl.¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0 at% or more and 15.0 at% or less in terms of O, and the compound semiconductor substrate has an epitaxial layer formed on the above-mentioned surface layer and composed of a group III nitride; and forming An electrode on at least one of the upper surface and the lower surface of the compound semiconductor substrate.</p><p>After painstaking research, the inventors found that the surface of the compound semiconductor substrate contains Cl converted to 200×10¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less in terms of O can reduce Si on the interface between the compound semiconductor substrate and the epitaxial layer formed thereon, thereby reducing the amount of Si on the interface resistance.</p><p>The method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device including a compound semiconductor substrate composed of a group III nitride. The manufacturing method includes the following steps: a surface layer is provided on the surface and the surface layer contains Cl converted 200×10¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²A step of forming an epitaxial layer composed of a group III nitride on the above-mentioned surface layer of the above-mentioned compound semiconductor substrate of the chloride and O converted into an oxide of 3.0at% or more and 15.0at% or less; and in the above compound The step of forming an electrode on at least one of the upper surface and the lower surface of the semiconductor substrate.</p><p>After intensive research, the inventors and others found that it is composed of group III nitrides, has a surface layer on the surface, and the surface layer contains Cl as 200×10¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and compound semiconductor substrates with oxides of 3.0at% or more and 15.0at% or less in O conversion form an epitaxial layer, which can reduce Si on the interface between the compound semiconductor substrate and the epitaxial layer, thereby enabling Reduce the resistance on the interface.</p><p>Furthermore, the amount of Si on the surface layer of the compound semiconductor substrate is preferably 0.3 at% or less, more preferably 0.2 at% or less.</p><p>The compound semiconductor substrate of the present invention has a Cl atom concentration of 5×10 at the interface between the base substrate made of III nitride and the epitaxial layer.¹⁵Pcs/cm³Above and 1×10¹⁸Pcs/cm³The following ones.</p><p>The compound semiconductor substrate of the present invention has an O atom concentration of 5×10 at the interface between the base substrate made of III nitride and the epitaxial layer.¹⁶Pcs/cm³Above and 1×10¹⁸Pcs/cm³The following ones.</p><p>The compound semiconductor substrate of the present invention has a Si atom concentration of 1×10 at the interface between the base substrate composed of III nitride and the epitaxial layer.¹⁵Pcs/cm³Above and 5×10¹⁹Pcs/cm³The following ones.</p><p>The semiconductor device of the present invention includes: the above-mentioned compound semiconductor substrate, and an electrode formed on at least one of the upper surface and the lower surface of the compound semiconductor substrate.</p><p>Furthermore, the above-mentioned Patent Documents 3 and 4 disclose that by using SiO₂Abrasive grain to Al_xGa_yIn_zThe surface of N is subjected to chemical mechanical polishing (CMP) to obtain a smooth surface with a surface roughness (RMS) of less than 1nm. However, there is no mention of reducing impurities on the surface, and there is no related record of controlling the composition of the surface layer. Moreover, Patent Document 5 discloses the following: by controlling the pH value and oxidation-reduction potential of the CMP polishing liquid, the polishing speed can be increased and the processed deterioration layer can be reduced. However, there is no mention of reducing the impurities on the surface, and there is no related record of controlling the composition of the surface layer. Furthermore, the aforementioned Patent Document 6 discloses that when the surface of the GaN substrate is dry-etched with a chlorine-based gas, a Si wafer is present in the device, and the surface of the GaN substrate can be processed relatively smoothly. However, there is no mention of reducing impurities on the surface, and there is no related record of controlling the composition of the surface layer.</p>

<p>According to the present invention, it is possible to provide a compound semiconductor substrate, a semiconductor device, and a manufacturing method thereof that reduce the resistance at the interface between the epitaxial layer and the substrate.</p>

Hereinafter, with reference to the accompanying drawings, a detailed description will be given of the best mode for carrying out the present invention. Furthermore, the same or equivalent elements are marked with the same symbols, and related repetitive descriptions are omitted.

FIG. 1 is a schematic cross-sectional view of a compound semiconductor substrate 10 of the first embodiment. As shown in FIG. 1, the compound semiconductor substrate 10 has a configuration in which a surface layer 12 is formed on the surface of one side.

The compound semiconductor substrate 10 is made of a group III nitride (for example, GaN, AlN, InN, AlGaN, InGaN). When it is made of GaN, it is grown by HVPE (Hydride Vapor Phase Epitaxy) method, molten salt method, and ammonia thermal method; when it is made of AlN, it is grown by HVPE method, sublimation method, Molten salt method for growth. InN is grown by the HVPE method.

The surface layer 12 is a layer containing chlorides and oxides, for example, made of Al_xGa_yIn_zN_aO_bCl_c(x+y+z=1, a+b+c=1) structure.

The compound semiconductor substrate 10 is a substrate on which the required semiconductor layer is epitaxially grown, and the quality of the surface of the substrate is more important. Different from the quality of the monolithic crystal, the surface quality is easily affected by the surface composition, roughness, and processing deterioration layer. In particular, when it is used to produce light-emitting devices such as LEDs and semiconductor lasers, it is important that a layer with high resistance (hereinafter referred to as a high-resistance layer) is not formed on the interface between the substrate and the epitaxial layer grown thereon. If the resistance of the light-emitting element becomes higher, the luminous efficiency will decrease. Especially when a large current is applied, the luminous efficiency will be significantly reduced.

Here, the so-called process-deteriorated layer refers to a layer in which the crystal lattice is disordered in the region on the surface side of the crystal formed by grinding or polishing of the crystal surface. The cross-section of the crystal fractured on the cleavage plane can be confirmed by TEM observation. Its existence and its thickness. The thickness of the processed deterioration layer is preferably 20 nm or less, more preferably 10 nm or less. If the thickness of the processed modified layer is thick, the morphology and crystallinity of the epitaxial growth will decrease.

The inventors newly discovered that by suppressing the abundance of Si on the surface 10a of the compound semiconductor substrate 10, and allowing the Cl and O elements to exist on the compound semiconductor substrate 10 in the form of chlorides and oxides, the above can be suppressed. The formation of high resistance layer.

Specifically, the inventors discovered that the surface layer 12 on the surface 10a of the compound semiconductor substrate 10 contains 200×10 in terms of Cl.¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less in terms of O can suppress the formation of the high-resistance layer. Furthermore, it is preferable that the surface layer 12 contains 300×10¹⁰Pcs/cm²Above and 8000×10¹⁰Pcs/cm²The following chlorides, preferably containing 400×10¹⁰Pcs/cm²Above and 5000×10¹⁰Pcs/cm²The following chlorides. Moreover, it is preferable that the surface layer 12 contains an oxide of 5.0 at% or more and 12.0 at% or less in terms of O, and more preferably an oxide of 7.0 at% or more and 10.0 at% or less.

The surface roughness Ry of the compound semiconductor substrate 10 is preferably 30 nm or less. Here, the so-called surface roughness Ry refers to the extraction of a standard area of 10μm square (10μm×10μm=100μm) from the roughness surface along the direction of its average surface.², The same below), the sum of the height of the highest protrusion and the depth of the lowest recess relative to the average surface of the extracted part. By making the surface roughness Ry 30 nm or less, an epitaxial layer with good morphology and crystallinity can be formed on the main surface. From the above viewpoint, the surface roughness Ry is more preferably 10 nm or less.

The surface roughness RMS of the compound semiconductor substrate 10 is preferably 3 nm or less. Here, the so-called surface roughness Ra refers to extracting a portion of a standard area of 10μm square from the roughness surface along the direction of its average surface, and dividing the total absolute value of the deviation between the average surface of the extracted portion and the measured surface by the standard The average value calculated by the area. By making the surface roughness Ra 3nm or less, an epitaxial layer with good morphology and crystallinity can be formed. From the above viewpoint, the surface roughness RMS is more preferably 1 nm or less.

On the compound semiconductor substrate 10, the density of scratches with a depth of 10 nm or more and 100 nm or less from the surface is preferably 2 strips/cm or less, more preferably 1.2 strips/cm or less. Scratch density is evaluated based on the number of crossed scratches per unit length as linear density. Scratches are linear recesses on the surface, and the density of scratches can be controlled according to polishing conditions and dry etching conditions. If the scratch density is high, the quality of the morphology and crystallinity during epitaxial growth will decrease. The scratch density can be evaluated with an optical interference roughness meter and a differential interference microscope.

On the compound semiconductor substrate 10, the density of the processed pits with a depth of 2 nm or more and 20 nm or less and a diameter of 0.2 μm or more and 5 μm or less from the surface is preferably 50×10⁵/Pcs/cm²the following. The diameter of the processing pit is usually 0.5 μm or more and 2 μm or less. The density of the processing pit is better than 20×10⁵/Pcs/cm²Below, the better is 10×10⁵/Pcs/cm²the following. The processing pits are the tiny depressions on the surface, and the pit density can be controlled by grinding conditions and dry etching conditions. It is different from the depression in the dislocation concentration part of the crystal. If the pit density is high, the quality of the morphology and crystallinity during epitaxial growth will decrease. The pit density can be evaluated with an optical interference roughness meter, a differential interference microscope, and an SEM.

On the compound semiconductor substrate 10, it is preferable that the density of latent flaws observed by ultraviolet fluorescence observation or cathodoluminescence (hereinafter referred to as CL) observation is 40 strips/cm or less. The density of latent injuries is evaluated based on the number of intersecting latent injuries per unit length as the linear density. When the density of latent damage is less than 40 strips/cm, an epitaxial layer with better morphology and crystallinity can be formed, and therefore a semiconductor device with better characteristics can be obtained. From the above point of view, the density of latent injuries is more preferably 10 bars/cm or less. Here, the latent injury can be observed by ultraviolet fluorescence observation or CL observation.

The so-called ultraviolet fluorescence observation means that the excitation light of high energy (low wavelength) which is more sufficient than the band gap of the III nitride crystal on the compound semiconductor substrate 10 is incident, and the band gap of the III nitride crystal is observed. Corresponding energy (wavelength) fluorescence. For example, as the excitation light, mercury bright line (wavelength: 337nm) or He-Cd laser (wavelength: 325nm) is used to observe the fluorescence of GaN crystals (wavelength: 365nm). When the III-nitride crystal is observed by ultraviolet fluorescence, fluorescence can be observed in the crystal area with good surface condition; while the fluorescence is not observed in the area of the processed deterioration layer with crystal disorder, and it can be observed to appear black The latent injury of the linear shadow.

In the process of UV fluorescence observation, the observation can also be performed in the state where the III nitride crystal is fixed to the crystal holder for surface treatment, so the III nitride in each step of the surface treatment of the III nitride crystal can be observed The surface state of the crystal makes it easy to grasp the problems in each step. In addition, in UV fluorescence observation, by using a combination of a UV fluorescence microscope and an optical microscope (especially a differential interference microscope), the same field of view can be observed comparatively, so it is possible to comparatively observe the unevenness information of the surface such as scratches. , And latent injuries and other information inside the processed surface layer.

CL observation refers to the observation of visible light or light having a wavelength close to the visible wavelength region after irradiating a III nitride crystal with an electron beam as excitation light. When performing cathodoluminescence observation of III-nitride crystals, light is observed in the crystal area with good surface condition, but no light is observed in the area of the processed deterioration layer with disordered crystals, and a black straight line can be observed. Shadow's latent injury.

By combining the CL observation device and SEM (Scanning Electron Microscope), high magnification observation can be performed, and finer latent injuries can be observed. Comparing the CL image with the SEM image, it is possible to compare and observe the unevenness information of the surface such as scratches and the information inside the processed surface layer such as latent damage.

Hereinafter, the manufacturing procedure of the compound semiconductor substrate 10 will be described with reference to FIG. 8.

First, after the crystal of the group III nitride is grown, the crystal is subjected to peripheral processing to be formed, thereby obtaining a bulk of the group III nitride. Then, the obtained block is cut with a wire saw or a blade saw to obtain a group III nitride compound semiconductor substrate 10. Furthermore, in order to flatten the surface 10a of the compound semiconductor substrate 10, a polishing process (grinding) or a grinding process is performed.

When grinding, you can use diamond, SiC, BN, Al₂O₃, Cr₂O₃, ZrO₂Etc. as a hard abrasive stone; during grinding, diamond, SiC, BN, Al can be used₂O₃, Cr₂O₃, ZrO₂As a common abrasive for hard abrasive grains. The abrasive can be selected according to the mechanical action/characteristics. For example, in order to increase the polishing rate, high hardness and large particle size abrasive particles are used; in order to smooth the surface roughness or reduce the deterioration layer produced during processing, use low hardness and small particle size abrasive particles. In addition, in order to shorten the polishing time and obtain a smooth surface, it is preferable to adopt a multi-stage polishing that changes from a larger abrasive grain to a smaller abrasive grain.

Then, the surface 10a of the compound semiconductor substrate 10 after the grinding process is subjected to surface polishing. As the surface polishing treatment, CMP or dry etching is performed in order to reduce the roughness or remove the process-deteriorated layer. In dry etching of nitrides such as GaN, it is effective to use a chlorine-based gas. When a chlorine-based gas is used, a higher etching rate can be obtained, and a surface layer 12 containing chloride can be formed on the surface. As the chlorine-based gas, for example, Cl can be used₂, HCl, CCl₄, BCl₃, SiCl₄, SiHCl₃Wait. Furthermore, by adjusting the type and flow rate of the gas, the pressure in the chamber, and the etching power, the amount of chlorine in the surface layer 12 can be controlled, and the pit density of the surface layer 12 can also be controlled.

The plane orientation of the surface 10a of the compound semiconductor substrate 10 is preferably the Wurtzite type structure C plane, A plane (11-20), R plane (10-12), M plane (10-10), (20 Any of -21) plane, S plane (10-11), (11-21) plane, (11-22) plane, (11-24) plane. Compared with the Ga surface of the C surface, the chemical durability of surfaces other than the Ga surface of the C surface is lower, so the CMP rate can be effectively increased.

When the compound semiconductor substrate 10 has a wurtzite structure, it has polarity in the [0001] direction (c-axis direction). At this time, the c-axis is referred to as a polarity axis. In addition, the plane perpendicular to the polar axis (c-axis) is called a polar plane. That is, the polar plane is defined as the plane that polarizes in the direction perpendicular to this plane. In addition, the plane parallel to the polar axis is called a non-polar plane. In addition, the surface obliquely crossing the polar axis is called a semipolar surface. Semiconductor devices such as LEDs and LDs (laser diodes) using compound semiconductor substrates 10 whose main surfaces are non-polar surfaces (for example, M surface, A surface, etc.) can achieve higher luminous efficiency, and even if the applied The blue shift of the emission wavelength (that is, the shift to the shorter wavelength side) at the current density of the current will also be suppressed. In addition, during the manufacturing process of the semiconductor device, when an epitaxial layer with good crystal quality is to be grown on the main surface 10a of the compound semiconductor substrate 10, and the doping amount of In in the InGaN layer is increased, the main surface 10a is more The good ones are the semipolar planes, namely (20-21) plane, S plane, R plane, (11-21) plane, (11-22) plane, (11-24) plane. Furthermore, from the viewpoint of the crystal quality and the amount of In mixed, there may be an off angle of 15° or less with respect to each plane orientation. In addition, when fabricating LD, the end face of the resonator is preferably a cleavable M-face or C-face, so it is better to use a main face perpendicular to the M-face (for example, A face, (11-21) face) , (11-22) plane, etc.) or a compound semiconductor substrate 10 perpendicular to the C plane (for example, M plane, A plane, etc.). Furthermore, from the perspective of cleavage, it is possible to form an off angle of less than 5° with respect to each plane orientation.

Furthermore, as surface polishing, soft abrasive grains can be used for polishing, so as to further reduce the surface roughness and reduce the processing deterioration layer. As soft abrasive grains, selected from ZrO can be used₂, SiO₂, CeO₂, MnO₂, Fe₂O₃, Fe₃O₄, NiO, ZnO, CoO, Co₃O₄, GeO₂, Ga₂O₃, In₂O₃Into the grain. In order to improve the cleaning performance of the polishing, the metal elements of the abrasive particles are preferably those with higher ionization tendency, and those with higher ionization tendency than H can be removed by cleaning with higher efficiency. In addition, by adding a surfactant to the polishing liquid, the residue of abrasive grains can be suppressed. When it is desired to reduce the metal elements in the surface layer 12, it is effective to use a polishing liquid that does not contain abrasive particles after polishing with abrasive particles. When you want to remove SiO₂At this time, it is effective to use hydrofluoric acid for cleaning after polishing.

In order to form a surface layer of the desired composition, a solution containing no abrasive particles can be used in the above-mentioned surface treatment. The chemical effect of the surface treatment solution can be adjusted by pH or oxidation-reduction potential. When a chlorine-containing acid such as HCl is used to adjust the pH value, the chlorine concentration of the surface layer 12 can be controlled. Furthermore, the oxidation-reduction potential can be increased by using an oxidizing agent, thereby increasing the polishing rate and controlling the oxygen concentration on the surface.

Here, when the pH value is set to x and the value of the oxidation-reduction potential is set to y (mV), under the acidic condition of 1x6, it is preferable to

-50x+1000&lt;y&lt;-50x+1800,

And under alkaline conditions of 8.5x14, it is better

-50x+800&lt;y&lt;-50x+1500.

The above-mentioned oxidant is not particularly limited. From the viewpoint of increasing the oxidation-reduction potential, hypochlorous acid, hypochlorites such as sodium hypochlorite and calcium hypochlorite, and chlorinated isocyanates such as trichloroisocyanuric acid are preferred. Chlorinated isocyanurates such as uric acid, sodium dichloroisocyanurate, permanganates such as potassium permanganate, dichromates such as potassium dichromate, bromate such as potassium bromate, and thiosulfuric acid such as sodium thiosulfate Salt, ammonium persulfate, potassium persulfate and other persulfates, nitric acid, hydrogen peroxide, ozone, etc. By using a chlorine-based oxidant, a surface layer 12 containing chloride can be formed on the polished substrate. As the chlorine-based oxidant, there are sodium hypochlorite, sodium dichloroisocyanurate, trichloroisocyanuric acid, and the like.

By controlling the viscosity of the surface treatment solution, the chlorine concentration or oxygen concentration of the surface layer can be controlled. The viscosity of the surface treatment fluid is preferably 2mPas or more and 30mPas or less, more preferably 5mPas or more and 10mPas or less. When the viscosity of the solution is lower than 2mPas, the chlorine concentration or oxygen concentration of the surface layer is higher than the above-mentioned expected value. When the viscosity of the solution is higher than 30mPas, the chlorine concentration or oxygen concentration of the surface layer is lower than the above-mentioned expected value. Furthermore, the viscosity of the solution can be adjusted by adding high-viscosity organic compounds such as ethylene glycol or inorganic compounds such as diaspore.

When the surface 10a of the compound semiconductor substrate 10 is to be etched into a flat surface, it is effective to make it contain Si-based gas or Si chips, but when the ratio of Si is high, there is an amount of Si attached to the surface of the substrate after dry etching Will increase the problem. Therefore, by using SiC, Si₃N₄, Si_6-zAl_zO_zN_8-zA compound containing Si element and at least one element from the group consisting of C, N, and O can etch the surface 10a into a flat surface, and can suppress the adhesion of Si. For the etched substrate 10, by reducing the area ratio of SiC, the residue of Si on the surface 10a can be reduced. Furthermore, by adjusting the gas flow rate, the pressure in the chamber, and the etching power, the residual Si can be reduced, and the etching rate can be reduced.

Furthermore, in order to obtain a better surface layer 12, it is preferable that the above dry etching adopts reactive ion etching, and the etching conditions are as follows: the pressure in the chamber is set to P (Pa), and the gas flow rate is set to Q(sccm), when the chamber volume is set to V(L), the relationship of 0.05PV/Q3.0 is satisfied. When PV/Q is less than 0.05, the amount of oxygen decreases, the amount of chlorine increases, and the surface roughness increases. On the other hand, when PV/Q is greater than 3.0, the amount of oxygen increases and the amount of chlorine decreases.

As described above, the inventors discovered that when grinding or surface polishing is performed, the compound semiconductor substrate 10 is formed on the compound semiconductor substrate 10 on which the surface layer 12 containing chloride and oxide is formed. The Si at the interface between the epitaxial layers will be reduced, and the resistance at the interface can be reduced.

Furthermore, the angle formed by the substrate surface 10a of the compound semiconductor substrate 10 and one of the above-mentioned crystallographic planes of the wurtzite structure, that is, the off angle is preferably 0.05° or more and 15° or less, more preferably 0.1° Above and below 10°. The larger the off angle, the better the removal effect of abrasive particles. If the off angle is set to 0.05° or more, the defects of the epitaxial layer can be reduced; if it is set to 15° or less, it is easy to form an epitaxial layer with good morphology and crystallinity on the compound semiconductor substrate 10. If the separation angle exceeds 15°, a step-like step difference is likely to be formed on the epitaxial layer. The greater the off angle, the greater the removal effect of abrasive particles. By forming a good epitaxial film, the semiconductor device fabricated by the compound semiconductor substrate 10 can achieve high efficiency, high power, and long life.

As described above, by forming an epitaxial layer with good morphology and crystallinity on the surface 10a of the compound semiconductor substrate 10, a semiconductor device with high characteristics can be obtained. In addition, by setting the above-mentioned off angle, the polishing speed can be increased, and the dislocation concentration portion of the substrate can be suppressed from being preferentially removed, and the generation of dents can be suppressed, so that a smooth surface can be easily obtained.

Furthermore, regarding the composition of the surface layer 12, Si and Cl can be measured by TXRF analysis (Total Reflectance Fluorescence X-ray Analysis) or AES (Oujie Electronic Spectroscopy Analysis). The TXRF can perform high-precision evaluation of 1 atomic layer on the surface. O can be determined by AES or XPS. The AES has a resolution of 0.1%. The difference between the composition of the surface layer 12 part of the compound semiconductor substrate 10 and other parts can be evaluated by analyzing the depth direction by SIMS (Secondary Ion Mass Spectrometry). In addition, the difference in the composition of the epitaxial growth layer, interface, and base substrate can also be evaluated by SIMS.

In addition, as shown in FIG. 2, it may also be a compound semiconductor substrate 10A in which an epitaxial layer 14 is laminated on the surface 10 a of the compound semiconductor substrate 10. The epitaxial layer 14 may be composed of, for example, group III nitride GaN. For the compound semiconductor substrate 10A, the resistance at the interface between the semiconductor substrate 10 and the epitaxial layer 14 formed thereon can actually be reduced.

The compound semiconductor substrate 10A includes: it is composed of a group III nitride and the surface contains 200×10 in terms of Cl¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and converted to O are 3.0 pcs/cm²The compound semiconductor substrate 10 of the oxide of the above and 15.0at% or less, and at least one group III nitride layer epitaxially grown on the surface of the compound semiconductor substrate 10 are emitted by the PL (photoluminescence) method The intensity of light (PL intensity) is high.

In the compound semiconductor substrate 10A, the concentration of Cl atoms at the interface between the base substrate 10 composed of group III nitride (GaN) and the epitaxial layer 14 is preferably 5×10¹⁵Pcs/cm³Above and 1×10¹⁸Pcs/cm³Below, better is 1×10¹⁶Pcs/cm³Above and 5×10¹⁷Pcs/cm³the following.

In the compound semiconductor substrate 10A, the concentration of O atoms at the interface between the base substrate 10 made of group III nitride (GaN) and the epitaxial layer 14 is preferably 5×10¹⁶Pcs/cm³Above and 1×10¹⁸Pcs/cm³Below, better is 1×10¹⁷Pcs/cm³Above and 5×10¹⁷Pcs/cm³the following.

In the compound semiconductor substrate 10A, the concentration of Si atoms at the interface between the base substrate 10 composed of group III nitride (GaN) and the epitaxial layer 14 is preferably 1×10¹⁵Pcs/cm³Above and 5×10¹⁹Pcs/cm³Below, better is 1×10¹⁵Pcs/cm³Above and 1×10¹⁹Pcs/cm³the following

In the compound semiconductor substrate 10A, the concentration of H atoms at the interface between the base substrate 10 composed of group III nitride (GaN) and the epitaxial layer 14 is preferably 2×10¹⁷Pcs/cm³Above and 1×10¹⁸Pcs/cm³the following.

Thereby, the resistance at the interface between the semiconductor substrate 10 and the epitaxial layer 14 formed thereon can be reduced.

As a different embodiment of the compound semiconductor substrate 10A, it can also be a compound semiconductor substrate 10A as shown in FIG. 3. In the compound semiconductor substrate 10A in FIG. 3, on the surface layer 12 of the n-type GaN crystal substrate (compound semiconductor substrate) 10, at least one group III nitride layer grown by epitaxial growth is provided in sequence: The n-type semiconductor layer has an n-type GaN layer 14a with a thickness of 1 μm and an n-type Al with a thickness of 150 nm_0.1Ga_0.9N layer 14b, light-emitting layer 14c, and p-type Al with a thickness of 20 nm as a p-type semiconductor layer_0.2Ga_0.8The N layer 14d and the p-type GaN layer 14e with a thickness of 150 nm. Here, the light-emitting layer has four barrier layers with a thickness of 10 nm formed by a GaN layer and three layers with a thickness of 3 nm formed by Ga_0.85In_0.15A multiple quantum well structure formed by alternating layers of wells formed by the N layer.

When the compound semiconductor substrate 10A shown in FIG. 3 is manufactured, at least one group III nitride layer is epitaxially grown on the surface layer 12 of the compound semiconductor substrate 10, so that the intensity of the light emitted by the PL method can be obtained ( PL intensity) high compound semiconductor substrate 10A. More specifically, for example, an n-type GaN crystal substrate (compound semiconductor substrate) 10 is set in a MOCVD device, and the n-type GaN crystal substrate 10 is placed on the surface layer 12 by MOCVD (metal organic chemical vapor deposition) method. Sequentially make the n-type GaN layer 14a, n-type Al_0.1Ga_0.9N layer 14b, light emitting layer 14c, p-type Al_0.2Ga_0.8The N layer 14d and the p-type GaN layer 14e are epitaxially grown.

Furthermore, as shown in FIG. 4, predetermined electrodes 32A and 32B are formed on the above-mentioned compound semiconductor substrates 10 and 10A, whereby the semiconductor device 30 can be obtained. By metal evaporation or the like, one of the electrodes 32A is formed on the epitaxial layer 14 and the other electrode 32B is formed on the back surface 12b of the semiconductor substrate 10. The formation of the electrodes 32A and 32B can be appropriately changed as needed, and they are formed on at least any one of the semiconductor substrate 10 and the epitaxial layer 14.

The semiconductor device 30 is a compound semiconductor substrate composed of a group III nitride and having a surface layer 12 on the surface. The surface layer 12 contains 200×10 in terms of C1.¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²The following chlorides and oxides of 3.0at% or more and 15.0at% or less in terms of O. The semiconductor device 30 includes: a compound semiconductor having an epitaxial layer 14 formed on the surface layer 12 and composed of a group III nitride The substrate 10A and the electrodes formed on the upper surface 10c and the lower surface 10b of the compound semiconductor substrate 10A have high luminous intensity.

As a different embodiment of the semiconductor device 30, the semiconductor device 30 as shown in FIG. 5 can also be used. In the semiconductor device 30 in FIG. 5, on the surface layer 12 of the n-type GaN crystal substrate (compound semiconductor substrate) 10, at least one group III nitride layer for epitaxial growth is provided in sequence: as an n-type semiconductor N-type GaN layer 14a with a thickness of 1 μm and n-type Al with a thickness of 150 nm_0.1Ga_0.9N layer 14b, light-emitting layer 14c, and p-type Al with a thickness of 20 nm as a p-type semiconductor layer_0.2Ga_0.8The N layer 14d and the p-type GaN layer 14e with a thickness of 150 nm. Here, the light-emitting layer has four barrier layers with a thickness of 10 nm formed by a GaN layer and three layers with a thickness of 3 nm formed by Ga_0.85In_0.15A multiple quantum well structure formed by alternating layers of wells formed by the N layer.

In the compound semiconductor device 30, the second electrode (p Side electrode) 32A, and on the other main surface of the compound semiconductor substrate 10, a first electrode (n-side electrode) 32B is provided.

Furthermore, in the semiconductor device 30 including an LED (light emitting diode, the same below), the second electrode (p-side electrode) 32A is joined to the conductor 36A by the solder layer 34, and the first electrode (n-side electrode) 32B is joined to the conductor 36B by the wire 38.

When the semiconductor device 30 shown in FIG. 5 is manufactured, the following steps are included: at least one group III nitride layer is epitaxially grown on the surface layer 12 of the compound semiconductor substrate 10; and on the outermost layer of the group III nitride layer, and An electrode is formed on at least one surface of the compound semiconductor substrate 10. In this way, the semiconductor device 30 can be obtained with a better yield. More specifically, for example, an n-type GaN crystal substrate 10 is set in a MOCVD apparatus, and the n-type GaN crystal substrate 10 is sequentially formed on the surface layer 12 of the n-type GaN crystal substrate 10 by the MOCVD (metal organic chemical vapor deposition) method. GaN layer 14a, n-type Al_0.1Ga_0.9N layer 14b, light emitting layer 14c, p-type Al_0.2Ga_0.8The N layer 14d and the p-type GaN layer 14e are epitaxially grown.

Then, an n-side electrode 32B with a diameter of 100 μm was formed as a first electrode on the other main surface 10b of the n-type GaN crystal substrate 10. On the other hand, a p-side electrode 32A is formed as a second electrode on the p-type GaN layer 14e. The above-mentioned laminated body is made into a 400 μm square or 2 mm square wafer to obtain an LED (Light Emitting Diode).

After that, the p-side electrode 32A and the conductor 36A are joined by the solder layer 34, and the n-side electrode 32B and the conductor 36B are joined by the wire 38, and a semiconductor device 30 including an LED can be obtained.

Furthermore, a compound semiconductor substrate 10B as shown in FIG. 6 may be used instead of the above-mentioned compound semiconductor substrates 10 and 10A. In the growth process of III-nitride crystals, in order to reduce the dislocation density in the crystals, SiO with openings is sometimes formed on the base substrate₂Wait for the mask layer, and grow III-nitride crystal facets thereon (for example, Japanese Patent Laid-Open No. 2003-165799, Japanese Patent Laid-Open No. 2003-183100, etc.).

The compound semiconductor substrate 10B is a GaN substrate having a striped structure in which low dislocation density regions 18A and high dislocation density regions 18B are alternately arranged linearly extending in the same direction (the Y direction in FIG. 6). The high dislocation density region and the low dislocation density region in the compound semiconductor substrate (hereinafter, also referred to as a group III nitride crystal) 10B can be observed by CL observation (S-4300 manufactured by Hitachi, Ltd.).

The compound semiconductor substrate 10B can be manufactured according to the following procedure.

First, as shown in FIG. 7(a), a striped mask layer 22 is patterned on a specific single crystal substrate 20. Next, as shown in FIG. 7(b), on the single crystal substrate 20 on which the mask layer 22 is formed, the GaN layer 24 is epitaxially grown by the vapor growth method. As the vapor phase growth method, HVPE method, MOCVD method, VOC method, MBE method, sublimation method, etc. can be used. If the GaN layer 24 is grown in a thick film by facet growth, the mask layer 22 will be covered by the GaN layer 24, so that a GaN layer with a high dislocation density region 18B formed in a portion corresponding to the mask layer 22 can be obtained twenty four. The high dislocation density region 18B is a part (stripe core) where crystal defects (threading dislocations) of the GaN layer 24 are concentrated and the defect density is significantly higher than other parts.

Furthermore, the high dislocation density region 18B can be not only the above-mentioned stripe structure, but also a square structure in which the stripes are perpendicular to each other as shown in FIG. 8 or a dot-like structure in which dots are regularly arranged as shown in FIG. 9. Such a square structure or a dot structure is the same as the stripe structure, and the shape of the high dislocation density region 18B can be controlled according to the patterned shape of the mask layer 22 on the single crystal substrate 20 as the base substrate.

In the above-mentioned group III nitride crystal 10B grown by the facet growth method, the surface of the low dislocation density region is the surface of Ga atoms, and the surface of the high dislocation density region is the surface of N atoms. Therefore, the chemical polishing speed of the surface of the high dislocation density region is faster than that of the surface of the low dislocation density region. Therefore, if chemical polishing such as CMP or polishing without abrasive grains is performed on the surface of the III-nitride crystal 10B including the high dislocation density region and the low dislocation density region, the degree of depression of the surface of the high dislocation density region will be higher than that of the low dislocation density region. The surface area of the area is larger.

After the group III nitride crystal grows, the crystal is processed on the periphery to shape it, and a block of the group III nitride can be obtained. Then, the resulting block is cut parallel to the substrate surface (XY plane) with a wire saw or a blade saw, and the surface 10a is flattened by grinding (grinding) or grinding to obtain the above-mentioned surface layer 12. Thereby, a compound semiconductor substrate 10B as shown in FIG. 4 can be obtained.

Next, the flat surface area of the compound semiconductor substrate 10B will be described with reference to FIG. 10.

The flat surface area of the low dislocation density region 18A of the compound semiconductor substrate 10B is defined as the highest point P on the surface of the low dislocation density region 18A₀Or the highest line L₀To the outer edge of the low dislocation density region 18A, set points P at intervals of a fixed distance of 10 μm₁, Point P₂,...Point P_k-1, Point P_k(Here, k is a positive integer), there is any point P that satisfies the following conditions_kArea of the surface: passing through point P_k-1With point P_k, And the highest point P on the surface of the low dislocation density region 18A₀Or the highest line L₀The inclination angle θ formed by the standard plane Q tangent to the surface (approximately a curved surface) is less than 0.1°.

Such a flat surface area continuously exists from the center of the surface of the low dislocation density area 18A to the outer edge. In order to easily remove the high dislocation density region 18B during polishing, the outer edge portion of the low dislocation density region 18A located near the high dislocation density region 18B is removed prior to the center portion of the low dislocation density region 18A, and the shape becomes loose. Therefore, the above-mentioned inclination angle θ will increase, resulting in an area of 0.1° or more. In addition, the ratio (percentage) of the area S2 of the flat surface region of the low dislocation density region 18A to the area of the entire surface S1 of the low dislocation density region 18A is defined as the flat surface region ratio (unit: %).

The flat surface area ratio (=S2/S1×100) is preferably 60% or more, and more preferably 80% or less. More than 90% is better.

When the compound semiconductor substrate 10B is subjected to CMP and polishing without abrasive grains, the compressibility of the polishing pad is preferably 1.5% or more and 20% or less. If the compression rate of the polishing pad is less than 1.5%, the surface roughness RMS and Ry of the surface layer 12 will increase. If the compression rate of the polishing pad is greater than 20%, the effect of the surface will be reduced, and the depression of the surface of the high dislocation density region 18B of the compound semiconductor substrate 10B will increase, and the flat surface area of the surface of the low dislocation density region 18A will decrease. Small. From the above point of view, the compressibility of the polishing pad used in the polishing step is more preferably 3% or more and 10% or less.

From the above point of view, the polishing pad is preferably formed of polyurethane, polyester, polyether, polycarbonate, etc., in the form of suede, non-woven fabric, foam, and the like.

Here, in this specification, the compressibility of the polishing pad is defined by the following formula, that is, the initial load W is applied to the polishing pad₁After 1 minute, the thickness of the polishing pad is set to T₁, Increase the load to W₂After 1 minute, the thickness of the polishing pad is set to T₂Hour,

Compression rate (%)=(T₁-T₂)/T₂ ×100。

When calculating the compression ratio, the initial load W₁The system is set to 100g, the load is W₂The system is set to 1600g.

For soft polishing pads, more selective removal of stripe cores, and the core depth and the degree of looseness of the core periphery become larger. In addition, the shape of the outer periphery of the substrate becomes looser. On the other hand, for hard pads, the surface quality of the substrate will decrease.

The pressure of CMP and grinding without abrasive particles is preferably 30g/cm²Above and 800g/cm²Below, 100g/cm is better²Above and 600g/cm²the following. If the pressure is small, the polishing rate is not sufficient in practical applications; if the pressure is large, the surface quality of the substrate will be degraded. In addition, the ratio of the flat surface area on the surface of the low dislocation density area 18A is reduced.

The chemical action of the polishing liquid can be adjusted by the pH value of the solution or the oxidant. The pH value is preferably 1 or more and 6 or less, or 8.5 or more and 14 or less, more preferably 1.5 or more and 4 or less, or 10 or more and 13 or less. By adding an oxidant, the oxidation-reduction potential can be increased, and the effect of removing abrasive particles can be improved. In the alkaline region, the stripe core will be removed more selectively. When the oxidation-reduction potential is high, the core depth or flat surface area ratio will decrease.

When adjusting the pH value, in addition to mineral acids such as hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, formic acid, acetic acid, citric acid, malic acid, tartaric acid, succinic acid, phthalic acid, maleic acid, and fumaric acid can be used. And other organic acids, as well as KOH, NaOH, NH₄In addition to alkalis such as OH, organic bases, and amines, salts such as sulfates, carbonates, and phosphates may also be used. The pH value can also be controlled by adding an oxidizing agent.

By using organic acid when adjusting the pH value of the slurry, compared with inorganic acid and inorganic salt, the impurity removal effect can be improved at the same pH value. Among the organic acids, dicarboxylic acids (dicarboxylic acids) are preferred.

Example

According to the following examples and comparative examples, the present invention will be further described in detail.

(Example 1)

(1-1) Grinding the surface of n-type GaN crystal

The n-type GaN crystal (dopant: Si) grown by the HVPE method was sliced along a plane parallel to the (0001) plane to obtain an n-type GaN crystal substrate with a diameter of 50 mm and a thickness of 0.5 mm. Using wax, the c-plane ((000-1) plane) on the N-atom plane side of the n-type GaN crystal substrate (nitride crystal) was adhered to a ceramic crystal holder. A pressure plate with a diameter of 380 mm is installed on the polishing device. While the slurry containing diamond abrasive particles is supplied to the pressure plate from the slurry supply port, the pressure plate is rotated around the rotating shaft and the plumb Place the n-type GaN crystal substrate on the crystal holder to press the n-type GaN crystal substrate against the platen, while rotating the n-type GaN crystal substrate with the rotation axis of the crystal holder as the center. The c surface and (0001 surface) are ground.

Here, as the platen, a copper platen or a tin platen is used. Three types of diamond abrasive grains with grinding particle diameters of 9 μm, 3 μm, and 2 μm are prepared, and the grinding is performed, and the grinding particle diameter is gradually reduced. The grinding pressure is set to 9.8kPa (100gf/cm²) Above and 49kPa (500gf/cm²) Hereinafter, the rotation speeds of the n-type GaN crystal substrate (nitride crystal 1) and the platen are both set to 30 times/min or more and 100 times/min or less. Through the above-mentioned grinding, the surface of the n-type GaN crystal substrate becomes a mirror surface.

(1-2) CMP on the surface of n-type GaN crystals

As shown in FIG. 11, a polishing pad 42 is provided on a platen 41 with a diameter of 380 mm installed on the polishing device 40, and a slurry 44 with abrasive grains dispersed therein is supplied to the polishing pad 42 from the slurry supply port 43. , While the polishing pad 42 is rotated about the rotation axis R1, and the plumb 46 is placed on the crystal holder 45 to press the n-type GaN crystal substrate 10 against the polishing pad 42, while the n-type GaN crystal substrate 10 By rotating around the rotation axis R2 of the crystal holder 45, CMP is performed on the surface of the n-type GaN crystal 10 (the c-plane on the side of the Ga atom surface, the (0001) plane).

Here, as the slurry, it is produced by the following method, namely, Al with a particle size of 2μm₂O₃(Mohs hardness is 9) The particles are dispersed in water as abrasive grains, so that Al₂O₃The content reaches 5% by mass, and sodium dichloroisocyanurate (hereinafter referred to as DCIA-Na) is added as an oxidizing agent, and HNO is added₃As a pH adjuster, the pH value is adjusted to 1 or more and 4.5 or less, and the oxidation-reduction potential is adjusted to 1000 mV or more and 1500 mV or less to prepare a slurry. In addition, as the polishing pad, a polyurethane suede pad (Supreme RN-R manufactured by NITTA HAAS Co., Ltd.) was used, and a stainless steel pressure plate was used as the pressure plate system. The grinding pressure is set to 9.8kPa (100gf/cm²Above and 78kPa(800gf/cm²) Hereinafter, the rotation speeds of the n-type GaN crystal substrate and the polishing pad are both set to 30 times/min or more and 120 times/min or less.

The evaluation of the surface roughness Ry and the surface roughness Rms of the n-type GaN crystal substrate was performed by AFM (Atomic Force Microscope) observation within the range of 10 μm×10 μm on the surface of the n-type GaN crystal substrate. In addition, the oxygen content of the surface layer was evaluated by AES, and the chlorine content was evaluated by TXRF.

(1-3) Grinding without abrasive grains on the surface of n-type GaN crystals

Using the same polishing device as the above CMP, a solution without abrasive particles is used for polishing without abrasive particles. The polishing liquid system is produced by adding trichloroisocyanuric acid (hereinafter referred to as TCIA) as an oxidizing agent, adding HCl as a pH adjuster, adjusting the pH to 1 or more and 2.5 or less to reduce the oxidation-reduction potential Adjust to 1200mV or more and 1500 or less to make a polishing liquid. In the polishing liquid, the viscosity is adjusted to 2mPas or more and 10mPas or less by adding ethylene glycol. As the polishing pad, a non-woven pad (compression rate of 3.0%) is used; as the platen, a surface-treated aluminum platen is used. The grinding pressure is set to 39kPa (400gf/cm²) Above and 78kPa (800gf/cm²) Below, the rotation speeds of the n-type GaN crystal substrate and the polishing pad are both set to 80 times/min or more and 100 times/min or less.

(1-4) Fabrication of semiconductor devices containing n-type GaN crystal substrates

The n-type GaN crystal substrate after CMP is set in the MOCVD device, and one main surface (the (0001) surface after CMP) side of the n-type GaN crystal substrate is sequentially formed by the MOCVD method: The n-type semiconductor layer has an n-type GaN layer (dopant: Si) with a thickness of 1 μm and an n-type Al with a thickness of 150 nm_0.lGa_0.9N layer (dopant: Si), light-emitting layer, p-type Al with a thickness of 20 nm as a p-type semiconductor layer_0.2Ga_0.8An N layer (dopant: Mg) and a p-type GaN layer (dopant: Mg) with a thickness of 150 nm were obtained to obtain a compound semiconductor substrate including an epitaxial growth layer. Here, the light-emitting layer has a barrier layer formed of 4 GaN layers with a thickness of 10 nm and 3 layers of Ga with a thickness of 3 nm._0.85In_0.15A multiple quantum well structure formed by alternating layers of wells formed by the N layer. The surface roughness and PL intensity of the epitaxial growth layer were evaluated. For PL intensity evaluation, a He-Cd laser with a wavelength of 325nm was used as the excitation light source to evaluate the intensity at a wavelength of 460nm. In addition, the composition of the interface between the base substrate and the epitaxial growth layer was analyzed by SIMS.

Then, a Ti layer with a thickness of 200nm, an Al layer with a thickness of 1000nm, a Ti layer with a thickness of 200nm and an Au layer with a thickness of 2000nm are formed on the other main surface ((000-1) plane) side of the n-type GaN crystal substrate The layered structure was used as the first electrode and heated in a nitrogen atmosphere to form an n-side electrode with a diameter of 100 μm. On the other hand, a layered structure consisting of a Ni layer with a thickness of 4 nm and an Au layer with a thickness of 4 nm was formed on the p-type GaN layer as the second electrode, and heated in an inert gas atmosphere to form the p-side electrode. After the semiconductor substrate was made into a 400 μm square and 2 mm square wafer, the p-side electrode and the conductor were joined by a solder layer formed of AuSn. Furthermore, the n-side electrode and the conductor are joined by wires to obtain a semiconductor device having a structure as an LED.

The luminous power of the obtained LED was measured under the conditions of 20mA, 40mA, and 4A using an integrating sphere. The optical power of the light-emitting element was measured as follows. A predetermined current is applied to the light-emitting element placed in the integrating sphere, and the measurement is performed with a detector that receives the light converged by the light-emitting element. As the light-emitting element corresponding to each semiconductor substrate, two wafer sizes of 400μm square and 2mm square were fabricated, and currents of 20mA, 40mA, and 4A were applied according to various chip sizes. The results are shown in the table in Figure 13.

In the samples 1 to 13 shown in the table in Figure 13, the oxygen content is within the range of 3.0at% or more and 15.0at% or less, and the chlorine content is 200×10¹⁰Pcs/cm²Above and 12000×10¹⁰Pcs/cm²Samples 3 to 11 in the following range have obtained good device characteristics (optical power). On the other hand, in samples 1 and 2, the optical power decreased due to the small amount of oxygen and chlorine; in samples 12 and 13, the optical power decreased due to the large amount of oxygen and chlorine. Especially, when the input current is large, the optical power drops significantly.

The result of SIMS analysis is: in sample 2, the concentration of Cl atom is 2×10¹⁵Pcs/cm³, The concentration of O atoms is 2×10¹⁶Pcs/cm³, The concentration of Si atoms is 1×10²⁰Pcs/cm³, The concentration of H atoms is 1×10¹⁷Pcs/cm³. In sample 3, the concentration of Cl atoms is 5×10¹⁵Pcs/cm³, The concentration of O atoms is 5×10¹⁶Pcs/cm³, The concentration of Si atoms is 5×10¹⁹Pcs/cm³, The concentration of H atoms is 2×10¹⁷Pcs/cm³. In sample 6, the concentration of Cl atoms is 1×10¹⁷Pcs/cm³, The concentration of O atoms is 2×10¹⁷Pcs/cm³, The concentration of Si atoms is 5×10¹⁷Pcs/cm³, The concentration of H atoms is 5×10¹⁷Pcs/cm³. In sample 9, the concentration of Cl atoms is 1×10¹⁸Pcs/cm³, The concentration of O atoms is 1×10¹⁸Pcs/cm³, The concentration of Si atoms is 1×10¹⁹Pcs/cm³, The concentration of H atoms is 1×10¹⁸Pcs/cm³. In sample 13, the concentration of Cl atoms is 1×10¹⁹Pcs/cm³, The concentration of O atoms is 1×10¹⁹Pcs/cm³, The concentration of Si atoms is 1×10²⁰Pcs/cm³, The concentration of H atoms is 5×10¹⁸Pcs/cm³ 。

When sample 3, sample 6, and sample 9 whose interface composition is within a good range, good device characteristics can be obtained. When sample 2 and sample 13 whose interface composition is not in the good range are used, the optical power decreases.

(Example 2)

For samples 14-19 shown in the table in FIG. 14, n-type GaN crystals grown by the melt method were used. Slicing and grinding are the same as in Example 1. By selecting Al in CMP₂O₃The size of the abrasive grains, and SiO is used in the later steps₂The abrasive grains are subjected to CMP to control the surface roughness and scratch density. About Al₂O₃The particle size of the abrasive grains was 0.5 μm in sample 15, 1 μm in sample 16, 2 μm in sample 17, 4 μm in sample 18, and 5 μm in sample 19. For sample 14, Al with a particle size of 1μm is used₂O₃After the abrasive particles are subjected to CMP, colloidal silica with a particle size of 50 nm is used for CMP. The content of silicon is 10wt%. The grinding without abrasive grains is the same as in Example 1. When the surface layer composition is within the proper range and the surface roughness is within the good range of samples 14-17, good device characteristics can be obtained. When samples 18 and 19 with larger surface roughness are used, the surface roughness of the epitaxial layer is larger and the PL intensity is lowered. In addition, the light power of the LED is reduced. Good device characteristics can be obtained when using samples 14-16 with scratch density in a good range. When samples 17-19 with higher scratch density are used, the surface roughness of the epitaxial layer is larger and the PL strength is lowered. Therefore, the light power of the LED is reduced.

(Example 3)

For samples 20 to 23 shown in the table in FIG. 15, an AlGaN substrate containing 5% Al was grown by the HVPE method, and after CMP, the surface was treated by dry etching (DE). CMP is the same as in sample 14. As shown in FIG. 12, as the DE apparatus 50, an RIE (Reactive Ion Etching) apparatus having parallel plate type electrodes 52A and 52B in a vacuum chamber 51 is used. The volume of the vacuum chamber 51 is 20L. The material of the substrate support table 53 is SiC. Etching gas system uses Cl₂, The flow rate is 30sccm. In an environment with a pressure of 4.0Pa, dry etching is performed with a power above 50W and below 200W (PV/Q=2.67). Good device characteristics can be obtained when using samples 20-22 with the composition of the surface layer in the proper range and good pit density. When the sample 23 with a larger pit density is used, the surface roughness of the epitaxial layer is larger and the PL strength is lowered. Therefore, the light power of the LED is reduced.

(Example 4)

For samples 24 to 27 shown in the table in Fig. 16, AlN substrates grown by sublimation were used. CMP is the same as in sample 14. After CMP, the surface treatment is performed by dry etching. The device has the same structure as that of the sample 20. Etching gas uses BCl₃, The flow rate is 50sccm. In an environment with a pressure of 3.0Pa, dry etching is performed with a power above 50W and below 150W (PV/Q=1.2). Good device characteristics can be obtained when using samples 24 to 26 whose surface layer composition is in an appropriate range and the thickness of the processed metamorphic layer is good. When the sample 27 with a larger thickness of the processed metamorphic layer is used, the surface roughness of the epitaxial layer is larger and the PL strength is lowered. Therefore, the light power of the LED is reduced.

(Example 5)

For samples 28 to 31 shown in the table in FIG. 17, an n-type GaN crystal (dopant: O) with the M-plane as the main surface was used as the base substrate, and the M-plane was used as the main surface by the HVPE method. The n-type GaN crystal (dopant: O) grows. The slicing was carried out at an angle of 15° from the main surface of the crystal in the direction of the (0001) plane to obtain an n-type GaN crystal substrate having an off angle of 15° from the M plane (inclined by 75° from the C plane in the direction of the M plane). The size is 50mm in diameter x 0.5mm in thickness. For this substrate, use Cr₂O₃After CMP of abrasive grains, SiO is used again₂The abrasive grains are subjected to CMP. Cr₂O₃The particle size of the abrasive grains is 1μm, and the concentration of the abrasive grains is 10%. SiO₂The particle size of the abrasive grains is 100nm, and the concentration of the abrasive grains is 15%. Add H to the slurry₂O₂As an oxidizing agent and adding HCl as a pH adjuster, the pH is adjusted to 1 or more and 2 or less, and the oxidation-reduction potential is adjusted to 950 mV or more and 1050 mV or less. For grinding without abrasive particles, the same equipment and solution as in Example 1 were used. The polishing pad is made of hard polyurethane (with a compression rate of 1.5%). The polishing conditions are the same as in Example 1. When the surface layer composition is within the appropriate range and the potential damage density is good, the sample 28~30 can obtain good device characteristics. When the sample 31 with a larger latent damage density is used, the surface roughness of the epitaxial layer is larger and the PL strength is lowered. Therefore, the light power of the LED is reduced.

(Example 6)

For the samples 32 to 35 shown in the table in Fig. 18, a GaN substrate with a stripe structure in which high dislocation density regions and low dislocation density regions are arranged alternately in a straight line was used, using ZrO₂After the abrasive grain is CMP, Fe is used₂O₃The abrasive grains are subjected to CMP. ZrO₂The diameter of the abrasive grains is 500nm, and the concentration of abrasive grains is 10%. Fe₂O₃The particle size of the abrasive grains is 500nm, and the concentration of the abrasive grains is 5%. Sodium hypochlorite is added as an oxidizing agent and malic acid is added as a pH adjuster to the slurry, and the pH is adjusted to 2 or more and 3 or less, and the oxidation-reduction potential is adjusted to 1300 mV or more and 1400 mV or less. For the grinding without abrasive grains, the same equipment and solution as in Example 1 were used. The polishing pad is made of suede pad (compression rate 12%). The grinding device is the same as in Example 1. Grinding pressure is 15kPa (150gf/cm²) Above and 88kPa (900gf/cm²) Below, the rotation speeds of the n-type GaN crystal substrate and the polishing pad are both 40 times/min or more and 80 times/min or less. When the surface layer composition is in the proper range and the flat surface area ratio is good sample 33~35, good device characteristics and yield are obtained. When the sample 32 with a small flat surface area ratio is used, the light power of the LED is reduced. In turn, the yield rate is reduced.

(Example 7)

For the samples 36 to 47 shown in the table in FIG. 19, the substrate subjected to the same CMP treatment as that of the sample 15 uses an ICP-RIE device to perform dry etching on the surface of the GaN substrate. Etching gas system uses Cl₂. The volume V of the processing chamber of the equipment used, the pressure P of dry etching, the gas flow rate Q, the calculated PV/Q, the bias power, the antenna power, and the material of the substrate support table are shown in the table. The value of PV/Q is more appropriate and the substrate support table uses Si-based compounds, namely SiC, Si₃N₄When the samples 36 and 37 are used, a good surface layer can be formed. When using the sample 38 whose material of the support stand is Si, there is a problem that the amount of Si in the surface layer is large. The material of the support table does not contain Si but Al₂O₃In the case of sample 39, there is a problem that the roughness of the surface layer increases. When samples 38 and 39 are used, the light power of the LED is reduced.

Adopt substrate support table using SiC or Si₃N₄And when the PV/Q is more suitable for samples 41~46, a good surface layer is obtained. When a compound semiconductor substrate with a good surface layer is used, good device characteristics are obtained. When the sample 40 with SiC and low PV/Q is used on the substrate support table, there is a problem that the amount of oxygen in the surface layer decreases and the amount of chlorine increases. The roughness of the surface layer is also increased, and the substrate support table is used to use Si₃N₄In addition, for sample 47 with a large PV/Q, there is a problem that the amount of oxygen in the surface layer increases while the amount of chlorine decreases. When samples 30 and 47 are used, the light power of the LED is reduced.

(Example 8)

For the samples 48 to 58 shown in the table in Fig. 20, an n-type n-type with a square structure in which high dislocation density regions and low dislocation density regions are alternately arranged, and high dislocation density regions and low dislocation density regions are alternately arranged in the vertical direction The GaN substrate (dopant: Si) is grown by the HVPE method. After grinding with diamond abrasive grains with a particle size of 2μm and a tin platen, use the solution shown in the table without abrasive grains to grind the substrates in samples 48 to 56. In addition, when samples 57 and 58 were used, ultrasonic cleaning was performed. The viscosity of the solution is 10mPas. When using samples 49-52 and samples 54-58 whose pH value and oxidation-reduction potential of the solution are both within the appropriate range, a surface layer with a good composition can be obtained. In sample 48 where the pH value of the solution is less than 1, the amount of oxygen and chlorine on the surface increases. Furthermore, the surface roughness increases. When sample 53 with a pH value greater than 6, the amount of oxygen and chlorine on the surface is reduced.

(Example 9)

For the samples 59 to 67 shown in the table in FIG. 21, an n-type GaN substrate (dopant: O) with a dot-shaped structure including high dislocation density regions regularly arranged in dots was used, which was performed by the HVPE method. growing up. After grinding the GaN substrate using diamond abrasive grains with a particle size of 3μm and a tin-bismuth alloy (2% tin) platen, use the solution shown in the table without abrasive grains for the substrates of samples 59~64 To grind. Also, when using samples 65 to 67, ultrasonic cleaning was performed. The viscosity of the solution is 20mPas. A surface layer with a good composition can be obtained when the sample with the pH value of the solution and the oxidation-reduction potential in the proper range is 60~63. When sample 59 with a solution pH value less than 8.5 is used, the amount of oxygen and chlorine on the surface decreases. When sample 64 with a higher redox potential of the solution is used, the amount of oxygen and chlorine on the surface increases. Furthermore, the flat surface area ratio decreases.

(Example 10)

For the samples 68 to 81 shown in the table in FIG. 22, an n-type AlGaN substrate with a stripe structure in which high dislocation density regions and low dislocation density regions are arranged alternately in a straight line was used to grow by the IIVPE method. After grinding with SiC abrasive grains and a non-woven pad, the surface of the substrate is polished with the solution, pad and conditions without abrasive grains shown in the table. The viscosity of the solution is 30mPas. The pH value and the oxidation-reduction potential of the solution are in the proper range, so a surface layer with a good composition is obtained. When using samples 69-73 and 76-80 whose compressibility and pressure of the pad are in the proper range, good surface roughness and flat surface area ratio can be obtained. When the sample 70 with a lower pad compression rate is used, the surface roughness increases. When the sample 74 with a higher pad compression rate was used, the flat surface area ratio decreased. When the sample 75 with a lower pressure is used, there are residues of abrasive grains of SiC, resulting in an increase in the amount of Si. When sample 81 with a higher pressure was used, the surface roughness increased and the flat surface area ratio decreased.

(Example 11)

The n-type GaN crystal (dopant: O) grown by the HVPE method was sliced in a plane parallel to the (0001) plane to obtain an n-type GaN crystal substrate with a diameter of 100 mm and a thickness of 0.8 mm. Grinding was performed using the same method as that of sample 15, and then CMP treatment was performed. After that, the polishing liquid having the viscosity shown in the table in FIG. 23 was used to perform polishing without abrasive grains. The viscosity of the polishing liquid can be adjusted by the amount of diaspore added. To the polishing liquid, TCIA was added as an oxidizing agent, and malic acid was added as a pH adjuster, and the pH was adjusted to 2, and the oxidation-reduction potential was adjusted to 1400 mV. When using samples 83~87 with the viscosity of the polishing liquid in the proper range, a surface layer with a good composition can be obtained. When the sample 82 with the viscosity of the slurry lower than 2mPas is used, the amount of oxygen and chlorine on the surface will increase. In addition, the surface roughness increases. When sample 88 with a solution viscosity higher than 30mPas is used, the amount of oxygen and chlorine on the surface will decrease.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made. For example, as long as the semiconductor substrate and the epitaxial layer are composed of a group III nitride semiconductor, they are not limited to GaN or AlN, and may be other semiconductor materials.

<p>10, 10A, 10B. . . Compound semiconductor substrate</p><p>12. . . Surface layer</p><p>14. . . Epitaxial layer</p><p>18A. . . Low dislocation density area</p><p>18B. . . High dislocation density area</p><p>30. . . Semiconductor device</p><p>32A, 32B. . . electrode</p>

Figure 1 is a schematic cross-sectional view showing a compound semiconductor substrate in an embodiment of the present invention;

2 is a schematic cross-sectional view of a compound semiconductor substrate that is different from the compound semiconductor substrate shown in FIG. 1;

3 is a schematic cross-sectional view of a compound semiconductor substrate that is different from the compound semiconductor substrate shown in FIG. 2;

4 is a schematic cross-sectional view showing the semiconductor device of the embodiment of the present invention;

5 is a schematic cross-sectional view of a semiconductor device that is different from the semiconductor device shown in FIG. 4;

FIG. 6 is a plan view of a semiconductor device that is different from the semiconductor substrate shown in FIG. 1 in a different aspect;

7(a) and 7(b) are diagrams showing the manufacturing sequence of the semiconductor shown in FIG. 6;

FIG. 8 is a plan view of a semiconductor substrate that is different from the semiconductor substrate shown in FIG. 6;

FIG. 9 is a plan view of a semiconductor substrate that is different from the semiconductor substrate shown in FIG. 6;

10 is a diagram showing the flat surface area of the compound semiconductor substrate shown in FIG. 6, FIG. 10(a) is a plan view, and FIG. 10(b) is a cross-sectional view on the line VIIIB-VIIIB of (a);

Figure 11 is a schematic configuration diagram of a polishing device in an embodiment of the present invention;

Figure 12 is a schematic configuration diagram of a dry etching apparatus in an embodiment of the present invention;

Figure 13 is a table showing the data of Example 1 of the present invention;

Figure 14 is a table showing the data of Example 2 of the present invention;

Figure 15 is a table showing the data of Example 3 of the present invention;

Figure 16 is a table showing the data of Example 4 of the present invention;

Figure 17 is a table showing the data of Example 5 of the present invention;

Figure 18 is a table showing the data of Example 6 of the present invention;

Figure 19 is a table showing the data of Example 7 of the present invention;

Figure 20 is a table showing the data of Example 8 of the present invention;

Figure 21 is a table showing the data of Example 9 of the present invention;

Figure 22 is a table showing the data of Example 10 of the present invention; and

Fig. 23 is a table showing data of Example 11 of the present invention.