Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

Co-aligned trench structure and method for optical and electron beam lithography manufacturing levels

TRENCH STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS

The present invention relates to the field of semiconductor manufacturing, in particular to an alignment target and method for co-alignment of hybrid optics and electron beam lithography manufacturing levels.

In order to manufacture integrated circuits, the various lithography definition manufacturing levels must be aligned with each other. In optical lithography, a layer of photoresist on a substrate is exposed to actinic radiation through a patterned photomask, where the patterned photoresist is aligned with an alignment target on the substrate. The structure manufactured in the early lithography process step is used as the alignment target of the alignment mark on the photomask. In contrast, electron beam lithography is a direct-write process without a photomask, and the electron beam is scanned across an electron beam resist layer. At each manufacturing level, the electron beam must be marked as a reference structure. Generally speaking, optical lithography is fast, but it cannot print images on very small pitches. Electron beam lithography can print images on very small pitches, but it is slow. The method of combining the advantages of these two technologies is hindered by the fact that electron beam lithography systems cannot mark current optical alignment structures. Therefore, there is a need for an alignment target and method for co-alignment of optical and electron beam lithography manufacturing levels.

One aspect of the present invention is a method comprising forming an electron beam alignment target in a substrate, and after forming the electron beam alignment target, forming an optical alignment target in the substrate corresponding to the electrons in the substrate Beam at the target A position, the optical alignment target is located at a predetermined position in the substrate; a resist layer is formed on the substrate; a photomask is aligned with the optical alignment target or the electron beam alignment target, the photomask has A first pattern of light-transmissive and opaque areas, the first pattern represents a first set of features of a manufacturing level of an integrated circuit; the resist layer is exposed to actinic radiation through the photomask to form selectivity The exposed area is in the resist layer, the opaque area substantially blocks actinic radiation, and the light-transmissive area substantially transmits actinic radiation; corresponding to the position where the electron beam is aimed at the target, a home position of an electron beam is set. ); Expose the photoresist to the electron beam in the second pattern to form the electron beam exposure area in the resist layer, the second pattern represents a second set of features of the manufacturing level of the integrated circuit; and develop the resist layer , To transfer the first and second patterns to a resist pattern of the resist layer.

The second aspect of the present invention is the first aspect, and the optical alignment target is one of the first set of features.

The third aspect of the present invention is that the first aspect further includes: transferring the resist pattern to the substrate or to a layer formed on the substrate.

The fourth aspect of the present invention is the middle of the first aspect. The step of aligning the mask to the optical alignment target or the electron beam alignment target includes setting an alignment mask corresponding to the optical alignment target or the electron beam alignment target, respectively. On the mask.

The fifth aspect of the present invention is the first aspect, (i) exposing the resist layer to actinic radiation is performed before exposing the resist layer to electron beams; or (ii) exposing the photoresist to electron beams This is done before exposing the resist layer to actinic radiation.

The sixth aspect of the present invention is that the first aspect further includes: dividing the surface of the substrate into a virtual electron exposure field (virtual electron exposure field); And each area of the substrate corresponding to the position in the field of electron beam exposure.

The seventh aspect of the present invention is the first aspect. The area occupied by the electron beam alignment target measured along the top surface of the substrate is an area occupied by the optical alignment target measured along the top surface of the substrate. 25 to 100 times the area.

Lithography alignment is defined as a process in which different structures of integrated circuits that are related to each other and located on a substrate are positioned in a horizontal direction (such as an xy position). The horizontal direction is defined as any direction parallel to the top surface of the substrate. The manufacturing level of the integrated circuit is defined as the level in which a group of patterned structures related to the integrated circuit are simultaneously formed in or on the substrate. The manufacturing level can include two or more lithography steps.

Optical lithography (hereinafter referred to as photolithography) by The resist layer is exposed to actinic radiation (such as ultraviolet light) through a photomask to form resist features and a pattern of spacers in the resist layer. The photomask has light-transmitting and opaque (for Actinic radiation) area corresponding to the pattern area. The lithography alignment relies on setting the image of the alignment mark on the photomask corresponding to the image of the alignment target on the substrate, and moving the photomask corresponding to the substrate, or moving the substrate corresponding to the photomask, so that the photomask ( And the pattern on the mask) is aligned with the substrate (and the structure on the substrate). Optical alignment targets have limited depths (such as about 30 nanometers to about 100 nanometers), small horizontal dimensions (such as about 10 nanometers to about 100 nanometers), and have low atomic weight (such as silicon ) Of the manufacturing structure.

By turning off and turning on the electron beam when the electron beam is scanned through the resist layer by a direct writing process, the electron beam lithography forms an image in the resist layer on the substrate (irradiated by the electron beam). The alignment of the electron beam lithography relies on setting a position on the substrate, which corresponds to the starting position of the electron beam in the electron beam exposure machine, and uses a scanning electron microscope (SEM) to image the backscattered electrons. Therefore, the xy position directly on the substrate in the electron beam path can be determined at any specific time. The electron beam alignment target according to the embodiment of the present invention presents a large topographical contrast (large and deep) with respect to the surrounding substrate area to increase the number of backscattered electrons. The backscattered electrons are used to generate supply Mark the SEM image of the electron beam.

Photoresist is defined as a polymer composition that undergoes a chemical reaction that changes its solubility in the developer when exposed to actinic ultraviolet radiation. Electron beam stoppers are defined as changes when exposed to electron beams It is a kind of polymer composition of the chemical reaction of its solubility in the developer. Resist is defined as a polymer composition that undergoes a chemical reaction that changes its solubility in the developer when exposed to actinic ultraviolet radiation or electron beams. When referring to photoresist or electron beam resist at any time later, it can be replaced by resist.

Although the embodiment of the present invention uses a silicon-on-insulator (SOI) substrate for illustration, the embodiment of the present invention can also be applied to a bulk silicon substrate. The bulk silicon substrate does not contain a buried oxide (BOX) layer. In the industry, the common name for semiconductor substrates, bulk silicon, or SOI is "wafer", and the terms "substrate" and "wafer" can be used interchangeably in industry. The terms "integrated circuit" and "integrated circuit chip" can be used interchangeably.

1A to 1K are cross-sectional views illustrating the fabrication of an electron beam alignment target, an optical alignment target and an exemplary field effect transistor (FET) on the same substrate according to an embodiment of the present invention. In FIG. 1A, the SOI substrate (or wafer) 100 includes a main body (or handle) 105, a BOX layer 110 on top of the main body, and a silicon layer 115 on top of the BOX layer. The BOX layer 110 includes silicon dioxide. In one example, the main body 105 is single crystal silicon. In one example, the silicon layer 115 is single crystal silicon. In one method, SOI wafers are formed by implanting oxygen ions into single crystal silicon wafers and tempering to form a buried silicon dioxide layer. In another method, SOI wafers are formed by oxidizing the top surfaces of two silicon wafers, placing the oxidized surfaces in contact, tempering to bond the wafers together, and then by, for example, chemical mechanical polishing ( CMP) to remove the wafer Remove the silicon from the bottom of one.

A first cushion layer 120 is formed on the top surface of the silicon layer 115. A second cushion layer 125 is formed on the top surface of the first cushion layer 120. A hard mask layer 130 is formed on the top surface of the second cushion layer 125. In one example, the first cushion layer 120 is silicon dioxide. In one example, the second pad layer 125 is silicon nitride. In one example, the hard mask layer 130 is silicon dioxide. In one example, the BOX layer 110 is about 50 nanometers to about 300 nanometers thick. In one example, the silicon layer 115 is about 30 nanometers to about 200 nanometers thick. In one example, the first cushion layer 120 is about 2 nanometers to about 20 nanometers thick. In one example, the second cushion layer 125 is about 5 nanometers to about 150 nanometers thick. In one example, the hard mask layer 130 is about 50 nanometers to about 145 nanometers thick.

In FIG. 1B, a patterned photoresist layer 135 is formed on the top surface of the hard mask layer 130, and an opening 140 is lithographically formed in the photoresist layer to expose the hard mask layer at the bottom of the opening. Mask layer area. This lithography step defines the position and horizontal shape of the electron beam to be aligned to the target afterwards.

In FIG. 1C, a patterned photoresist layer 135 (see FIG. 1B) is used to etch the hard mask layer 130 to form an opening 145 in the hard mask layer, and the photoresist layer is removed. In addition, any photoresist layer 135 remaining after the hard mask layer 130 is etched can also be left and completely consumed by the operations described in FIG. 1D later, or the photoresist layer can be removed after these operations. Of the second cushion 125 An area is exposed at the bottom of the opening 145.

In FIG. 1D, the trench 150 is formed by etching through the second cushion layer 125, the first cushion layer 120, the silicon layer 115, and the BOX layer 110 into the main body 105. In the example where the first pad layer 120 and the BOX layer 110 are silicon dioxide and the second pad layer 125 is silicon nitride, two examples of the etching trench 150 will now be provided. In the first method, in the first step, use CF₄The trench 150 is etched by reactive ion etching (RIE) as a reactive gas. In the second method, four steps are used. In the first step, the department uses CHF₃RIE as a reactive gas etches through the second cushion layer 125 and the first cushion layer 120. In the second step, RIE using HBr as a reactive gas is used to etch through the silicon layer 115. In the third step, use CHF₃RIE as a reactive gas etches through the BOX layer 110. In the fourth step, RIE using HBr as a reactive gas is used to etch into the main body 105. As shown in FIG. 1D, during the etching of the trench 150, all the hard mask 130 is removed (see FIG. 1C), and most of the second underlayer 120 is removed. However, in an extreme example, a hard mask layer 130 and all the first and second pad layers 120 and 125 may remain after etching the trench 150, while in the opposite extreme example, at least one layer of the first pad The layer 120 should remain to protect the top surface of the silicon layer 115 from being attacked during the etching of the trench 150. As previously mentioned, any remaining photoresist layer 135 (see FIG. 1C) is removed at this time.

In Figure 1E, any remaining hard mask layer (see Figure 1C) and the first The first and second pad layers 120 and 125 (see FIG. 1D) are removed (such as by wet etching or a combination of wet etching and RIE) to form an electron beam alignment target 155. The electron beam alignment target 155 extends to a depth into the main body 105 under the BOX layer 110. The electron beam alignment target 155 extends from the top surface 160 of the silicon layer 115 to a depth D1 and has a horizontal geometry with at least a minimum width W1 in the horizontal direction. In an example, W1 is from about 5 microns to about 100 microns, and D1 is about 1 micron or more. Therefore, the electron beam alignment target 155 includes a relatively wide and deep (compared to the optical alignment targets and semiconductor devices discussed later) that the trench structure extends into the main body 105 under the BOX layer 110.

The electron beam aiming target 155 scatters more electrons along the sidewall edge of the trench forming the aiming target than backwards from the bottom of the trench forming the aiming target. Because the electron beam is aimed at the large circumference of the target 155 and the large trench depth, it presents a large topographical contrast to the adjacent area of the substrate 100 in the SEM mode.

In FIG. 1F, a new first underlayer 165 is formed on all exposed surfaces of the silicon layer 115 and on all exposed surfaces of the electron beam alignment target 155. Then a new second cushion layer 170 is formed on all exposed surfaces of the first cushion layer 165. In one example, the first cushion layer 165 is silicon dioxide. In one example, the second pad layer 170 is silicon nitride. In one example, the first cushion layer 165 is about 2 nanometers to about 20 nanometers thick. In one example, the second cushion layer 170 is about 5 nanometers to about 150 nanometers thick.

As shown in FIG. 1G, the optical alignment target can be formed at this time, or can be formed simultaneously with the first selectively defined manufacturing level. In an example, the first selectively defined manufacturing level is a dielectric filling trench insulation level, as shown in FIG. 1H.

In FIG. 1G, the optical alignment target 175 is formed in the silicon layer 115 by a lithography process. The lithography process includes coating a photoresist layer, and resisting the photoresist through a photomask aligning the electron beam alignment target 155. The layer is exposed, the exposed photoresist layer is developed to pattern the photoresist layer, then the first pad layer 165 and the second pad layer 170 are etched into the silicon layer 115, and then the photoresist layer is removed. In one example, when the second pad layer 170 is silicon nitride, CHF can be used₃RIE as a reactive gas etches the second underlayer. In one example, when the first underlayer 165 is silicon dioxide, CHF can be used₃RIE as a reactive gas etches the first underlayer. In one example, RIE using HBr as a reactive gas can be used to etch into the silicon layer 115. The first cushion layer 165 and the second cushion layer 170 protect the electron beam alignment target 155 in the subsequent process steps.

The optical alignment target 175 extends from the top surface 160 of the silicon layer 115 to a depth D2 and has a horizontal geometry with at least a minimum width W2 in the horizontal direction. In an example, W2 is from about 100 nanometers to about 5000 nanometers, and D2 is from about 10 nanometers to about 500 nanometers. In the example shown in FIG. 1G, D2 may be equal to but not greater than the thickness of the silicon layer 115. In the first example, the optical alignment target 175 includes a relatively narrow and shallow (compared to the electron beam alignment target 155) trench extending into the silicon layer 115, but does not contact the BOX layer 110. In the second example, the optical alignment target 205 includes a relatively narrow and shallow (and electrical The trench of the beamlet alignment target 155 extends into the silicon layer 115 and contacts the BOX layer 110. In an example, the value of W2 is 5 to 10 times the value of W1, and the surface area occupied by the electron beam alignment target 155 is 25 to 100 times the surface area occupied by the optical alignment target 175.

In FIG. 1H, a shallow trench isolation (STI) 180 is formed to pass through the first cushion layer 165, the second cushion layer 170, the silicon layer 115 and down to the BOX layer 110. In one example, the first area of the STI structure can be formed by a lithography process of aligning the electron beam alignment target 155, and the second area of the STI structure can be formed by aligning the electron beam of the electron beam alignment target 155. Formed by the lithography process. Both lithography processes include lithography defining STI patterns in the resist, etching trenches penetrating the first pad layer 165, second pad layer 170, and silicon layer 115, removing the resist layer, and depositing an insulator 185 to overflow Fill up the trench, and then implement CMP. The insulator 185 is also filled in the electron beam alignment target 155 and the optical alignment target 175. In one example, the insulator 185 is a CVD oxide. In one example, the insulator 185 is tetraethyl silicate (TEOS) oxide. On the SOI substrate, the STI extends to completely contact the BOX layer 110. In the case of a bulk silicon substrate, STI extends a set distance into the bulk silicon substrate.

As mentioned above, the optical alignment target can be defined by the electron beam lithography process or the lithography step of forming the STI 180 at the same time. The optical alignment target 175 will have a depth D2 equal to the depth of the STI 180 (as shown in FIG. 1D).

In FIG. 1I, the etching is followed by a selective lithography step to remove the insulator 185 from the electron beam alignment target 155 without etching to the STI 180.

As shown in FIG. 1H, the insulator 185 is left to fill the optical alignment target 175. On the other hand, the insulator can also be removed from the optical alignment target 175 in the same step of removing the insulator from the electron beam alignment target 155. In addition to insulators.

In FIG. 1J, CMP and wet etching/cleaning are performed to remove the first and second pad layers from the silicon layer 115 during the fabrication of the gate stack for forming the FET. In FIG. 1K, the FET 190 includes a source/drain 195 on the opposite side of the channel region 200, a gate electrode 210 separated from the channel region by a gate dielectric 205, and a selective spacer 215 formed. After that, the in-layer dielectric layer 220 is formed, and the source/drain contacts 225 are electrically connected, and the gate electrode contact 230 is electrically connected to be formed in the in-layer dielectric layer. In one example, the contacts 225 and 230 are formed by a damascene process.

The damascene process is a process of forming line trenches, via holes or contact openings in the dielectric layer, depositing electrical conductors with sufficient thickness to fill the trenches on the top surface of the dielectric, and performing a CMP process to remove excess conductors , And make the surface of the conductor and the surface of the dielectric layer coplanar to form damascene lines, vias or contacts.

Generally speaking, an additional dielectric layer with electrically conductive lines and via holes is formed on the dielectric layer 220 to connect individual semiconductor devices to integrated circuits.

In the manufacture of FET 190, specific features of the FET and contacts can be formed using the electron beam lithography step of the electron beam alignment target 155, and specific features of the FET and contacts can be formed using the lithography step of the optical alignment target 175 . All electron beam lithography steps use an electron beam to aim the target 155. The most common is that the optical alignment target 175 is used in the lithography step, or other optical targets formed after the optical alignment target 175 are used. These subsequently formed optical alignment targets can be aligned with the electron beam alignment target 155, the optical alignment target 175, or other optical alignment targets that have been aligned with the optical alignment target 175. The FET 190 is not based on the size ratio of the electron beam alignment target 155 or the optical alignment target 175. In one example, the FET 190 has a horizontal area of about 36,000 (eg, 60×600) nanometers square, which is about 3 to about 300 times smaller than the horizontal area of the electron beam alignment target 155.

FET 190 should be regarded as an example of a device that can be formed in/on the substrate 100, including but not limited to diodes, bipolar transistors, silicon germanium transistors, other heterojunction transistors, resistors, capacitors, and induction Device. It can also be understood here that there are many lithographic manufacturing steps required to produce semiconductor structures, and many lithographic manufacturing steps required to connect these devices to form integrated circuits, as well as aligning electron beam alignment targets 155, optical All the lithography steps of aligning the target 175 or both will refer to the description of FIG. 3 below.

Figure 2 illustrates various geometric shapes of electron beam alignment targets that can be adopted according to embodiments of the present invention. In Figure 2, the illustrated horizontal geometry (that is, the upper View, plan) The electron beam is aimed at the target. The electron beam aiming target 155A is a square shape with a side length of W1 on each side. The electron beam aiming target 155B is rectangular with a short side and a side length of W1. The electron beam aiming target 155C has an "L" shape, and the length of the "foot" with "L" is W1. The electron beam aiming target 155D has a cross shape, and the searching degree of each crossed arm is W1. The electron beam aiming target 155E is a square ring with each outer side length W1.

Now, the size of the largest optical domain is about 20 mm by about 20 mm, and the size of the largest electronic domain that can be printed is about 0.3 mm by 0.3 mm. In the example of a single integrated circuit chip of approximately 10 mm by 10 mm, only one optical exposure field and approximately 1200 corresponding electron beam exposure fields are required. In many cases, when the optical exposure field is sufficiently larger than the wafer size, many wafers can be printed with the same optical exposure field at the same time.

At present, the minimum pitch of patterns that can be printed by lithography is about 200 nanometers, and the minimum pitch of patterns that can be printed by electron beam lithography is about 70 nanometers. Therefore, even when the layer contains a small number of features with a pitch less than 200 nanometers, electron beam lithography must be used. For the manufacturing level including the pattern pitch that can be printed by lithography and the pattern that can not be printed by lithography but the patterns can be printed by electron beam lithography, the advantage is that the lithography process is used to print the lithography printable area, and the electronic The beam lithography process prints areas where lithography cannot be printed, instead of printing all manufacturing levels with electron beam lithography.

Figure 3 is an exemplary integrated circuit chip according to one of the embodiments of the present invention The top view illustrates the horizontal optical relationship between the optical and electron beam exposure fields and between the optical and electron beam alignment targets. In FIG. 3, the exposure area 300 is divided into multiple (four as shown in FIG. 3) integrated circuit chips, and each integrated circuit chip includes an optical alignment target 175. Each integrated circuit chip 305 is substantially divided into multiple (four as shown in FIG. 3) electron beam exposure regions 310. However, not every electron beam exposure field 310 includes an electron beam alignment target 155, only in the selected electron beam exposure field.

Only those electron beam exposure fields where the electron beam lithography process will be performed will contain the electron beam alignment target 155. In those areas where the electron beam is not aimed at the target 155, only the lithography process will be implemented. However, it can be understood that the lithography process can be implemented in the electron beam exposure field including the electron beam alignment target 155.

The top view of the integrated circuit 305 in FIG. 3 is also the plan view, graphic design or layout of the known integrated circuit 305, and the electron beam alignment target 155, the optical alignment target 175, and all the integrated circuit structures and integrated bodies The features of all manufacturing levels of the circuit 305 (not shown in FIG. 3) are positioned corresponding to the position of the electron beam alignment target 155 (and therefore corresponding to the optical alignment target 175 and corresponding to each other), and have a set of XY coordinates , Drawn on the floor plan.

It should be noted here that each electron beam exposure field 310 containing the electron beam aiming target 155 does not need to be printed by electron beam lithography, only those lithography are not The printable pattern spacing needs to be printed by electron beam microphotography. However, as mentioned earlier, all the electron beam alignment targets 155 used in the different levels of manufacturing are manufactured together at the beginning of the manufacturing process. Examples of manufacturing levels on integrated circuits that can include areas that use electron beam lithography include, but are not limited to, STI levels (because silicon regions are defined as STI regions), gate electrode levels of FETs, and diodes The emitter level, the contact level (the interconnection level between the device and the first real line level), and the first line level.

4 is a flow chart of manufacturing an integrated circuit using optical and electron beam lithography according to an embodiment of the present invention. In step 320, an electron beam alignment target is formed in the semiconductor substrate in all regions of the integrated circuit wafer that will be processed by electron beam lithography at any lithography definition manufacturing level.

In step 325, the first optical alignment target is selectively formed in the substrate that is aligned with the electron beam alignment target. If the optical alignment target is not formed in step 320, at the first time of any step 335A, 335B, or 335C, the electron beam alignment target is aligned with the first lithography level integrated circuit image to form the optical alignment target.

Then in step 330, a resist layer is coated on the substrate. After that, step 335A, 335B, or 335C of the method is performed. If the method implements step 335A or 335B, a double exposure resist (that is, a resist that can be exposed by electron beam or light) is used. If the method implements step 335C, a double exposure resist or photoresist (that is, resist for light exposure) can be used.

In step 335A, the electron beam lithography exposure using the electron beam to align the target is performed, and then the lithography exposure using the optical alignment target formed in advance or the electron beam to align the target is performed. Step 340 is implemented after this method.

In step 335B, the lithography exposure using the optical alignment target formed first or the electron beam alignment target is performed, and then the electron beam lithography exposure using the electron beam alignment target is performed. Step 340 is implemented after this method.

In step 335C, lithography exposure using the optical alignment target formed previously or the alignment target using an electron beam is performed. Step 340 is implemented after this method.

In step 340, the resist is exposed, developed, etched, ion implanted, or other processes are performed, and then the resist is removed. If this is the first lithographic definition manufacturing level of the integrated circuit wafer (as defined in the STI level), and if the first optical alignment target has not been formed, step 340 defines the first optical alignment target in the substrate. If the first optical alignment target is formed in step 345, it can be defined by electron beam lithography or lithography.

In step 345, it is determined whether another lithography is needed to define the manufacturing level. If another manufacturing level is required, the method returns to step 330, otherwise, the lithography-defined manufacturing level of the integrated circuit chip is completed.

However, if a single layer of resist is exposed selectively and with electron beams, it can be Implement two "resist" processes at the same manufacturing level. In the first example, the electron beam lithography process is implemented by using electron beam resist and electron beam to align the target, develop the electron beam resist, and transfer the pattern in the electron beam resist to the substrate or the layer on the substrate middle. Afterwards, the photolithography process is carried out by using photoresist and electron beam to align the target or optically align the target, develop the photoresist and transfer the pattern in the photoresist to the substrate or the layer on the substrate. In the second example, the photolithography process is performed by using photoresist and electron beam to align the target or optical aligning target, develop the photoresist, and transfer the pattern in the photoresist to the substrate or the layer on the substrate. After that, the electron beam lithography process is implemented by using electron beam resist and electron beam to align the target, develop the electron beam resist, and transfer the pattern in the electron beam resist to the same substrate or a layer on the substrate.

Therefore, the embodiments of the present invention provide an alignment target and method for co-alignment of optical and electron beam lithography manufacturing levels.

The above description of the embodiments of the present invention is provided to understand the present invention. It can be understood that the present invention is not limited to the foregoing specific embodiments, but can be understood by those skilled in the art that various modifications can be included without departing from the scope of the present invention. , Permutation and replacement. Therefore, it is intended that the following application scope covers all modifications and changes within the spirit and scope of the present invention.

<p>100SOI substrate</p><p>105Main body</p><p>110BOX layer</p><p>115Silicon layer</p><p>120First cushion</p><p>125Second cushion</p><p>130Hard mask layer</p><p>135patterned photoresist layer</p><p>140, 145 opening</p><p>150Ditch</p><p>155, 155A, 155B, 155C, 155D, 155EElectron beam aiming at the target</p><p>160Top surface</p><p>165New first cushion</p><p>170New second cushion</p><p>175Optical alignment target</p><p>180Shallow Trench Isolation (STI)</p><p>185Insulation</p><p>190FET</p><p>195Source/Drain</p><p>200Access area</p><p>205Gate Dielectric</p><p>210Gate electrode</p><p>215Interstitial Wall</p><p>220In-layer dielectric layer</p><p>225,230Contact</p><p>300, 310Exposure domain</p><p>305Integrated Circuit Chip</p><p>310Electron beam exposure field</p>

The claims of the application provide the features of the present invention. However, the present invention itself can be best understood by referring to the detailed description of the following illustrative embodiments and the accompanying drawings, in which: FIGS. 1A to 1K illustrate cross-sectional views of manufacturing an electron beam alignment target, an optical alignment target, and an exemplary field-effect transistor on the same substrate according to an embodiment of the present invention; FIG. 2 illustrates the possibility of an embodiment according to the present invention Various geometric shapes of the electron beam alignment target are adopted; FIG. 3 is a top view of an exemplary integrated circuit chip according to an embodiment of the present invention, illustrating the relationship between the optical and electron beam exposure fields and the optical and electron beam alignment targets The spatial relationship between them; and FIG. 4 is a flow chart of manufacturing an integrated circuit using both optical and electron beam lithography according to an embodiment of the present invention.