Unit cell of nonvolatile memory device and nonvolatile memory device having the same

Unit cell of non-volatile memory device and non-volatile memory device with same

UNIT CELL OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE HAVING THE SAME

The present invention relates to semiconductor design technology; more specifically, it relates to one-time programmable (OTP) unit cells and non-volatile memory devices having the same.

The present invention claims the priority of Korean Patent Application No. 10-2008-0013045 filed on February 13, 2008, which is incorporated herein by reference.

Because one-time programmable (OTP) memory devices have non-volatile characteristics that retain the data stored in the memory cell even in the power-off state, these OTP memory devices are becoming widely used as alternatives Memory devices such as memory sticks, universal serial bus (USB) drives and hard disks.

Figure 1 is an equivalent circuit diagram of a conventional OTP unit cell.

Referring to FIG. 1, the conventional OTP unit cell includes an anti-fuse ANT_FS connected between a first input terminal A and node B and connected in series to node B and output terminal E (that is, the data output station in the read operation) Through the terminal) between the n-channel transistors NM1 and NM2.

In the following, a description will be given of the write/read operation of the conventional OTP unit cell.

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<b>Write operation</b>

First, ground node B. Then, the high voltage VPP is applied to the first input terminal A, and the logic low level L corresponding to the ground voltage is applied to the second input terminal C and the third input terminal D. Therefore, a high electric field is formed between the substrate and the gate of the anti-fuse ANT_FS including the MOS transistor, thereby breaking the gate insulating layer formed between the substrate and the gate. Therefore, the substrate and the gate of the anti-fuse ANT_FS are electrically short-circuited.

<b>Read operation</b>

After the write operation is completed, the power supply voltage VDD is applied to the first input terminal A, and the logic high level H corresponding to the power supply voltage VDD is applied to the second input terminal C and the third input terminal D. Therefore, a current path is formed from the first input terminal A through the anti-fuse ANT_FS and the first transistor NM1 and the second transistor NM2 to the input terminal E. Therefore, the power supply voltage VDD applied to the first input terminal A is transferred to the output terminal E, so that the power supply voltage VDD is detected.

However, the conventional OTP unit cell illustrated in FIG. 1 has the following limitations.

As described above, the current path (ie, the data path) formed from the first input terminal A to the output terminal E during the read operation must include the first transistor NM1 and the second transistor NM2 connected in series. Therefore, the sum of the threshold voltages of the first transistor NM1 and the second transistor NM2 (that is, VDD-2Vt, where "Vt" represents the difference between the first transistor NM1 and the second transistor NM2 The final data detected through the output terminal E is output in the state of each threshold voltage). Therefore, the sensing margin of the data sensed through the output terminal E is degraded by the voltage drop, thereby causing a malfunction. This failure causes the degradation of the reliability of the read operation of the OTP unit cell.

An embodiment of the present invention is directed to a unit cell of a non-volatile memory device and a non-volatile memory device having the unit cell. The non-volatile memory device can improve the data sensing tolerance in the read operation. This makes it possible to improve operational reliability.

According to an aspect of the present invention, a unit cell of a non-volatile memory device is provided, which includes: an anti-fuse connected between an output terminal and a ground voltage terminal; and a first switch unit connected to To the output terminal to transfer a write voltage to the output terminal; and a second switch unit connected to the output terminal to transfer a read voltage to the output terminal.

According to another aspect of the present invention, a unit cell of a non-volatile memory device is provided, which includes: an anti-fuse connected between a node and a ground voltage terminal; and a first switch unit connected to To the node to transfer a write voltage to the node; a second switch unit connected between the node and an output terminal; and a third switch unit connected to the output terminal to read The voltage is transferred to this output terminal.

According to another aspect of the present invention, a non-volatile memory device is provided, which includes: a cell array including a plurality of unit cells arranged in a matrix type; and a plurality of data lines, which are commonly connected to the unit cells An output terminal; and a plurality of sensor units, which include inverters configured to invert the voltages of the data lines, respectively.

According to another aspect of the present invention, a non-volatile memory device is provided, which includes: a cell array including a plurality of unit cells as in claim 1 arranged in a matrix type; a plurality of writing drive lines, which It is configured to select and control the first switch unit of the unit cell; a plurality of first read drive lines are configured to select and control the second switch unit of the unit cell; a plurality of data lines are connected to An output terminal of the unit cell; a plurality of third switch units configured to transfer the read voltage to the data line; a second read drive line configured to jointly select and control the The third switch unit; and a plurality of sensor units, which are configured to sense the voltage of the data line.

According to another aspect of the present invention, a non-volatile memory device is provided, which includes: a cell array including a plurality of unit cells as in claim 2 arranged in a matrix type; a plurality of write drive lines, which It is configured to select and control the first switch unit of the unit cell; a plurality of first read drive lines are configured to select and control the second switch unit of the unit cell; a plurality of data lines are connected to One output terminal of the unit cell; a second read drive line configured to jointly select and control the third switch unit of the unit cells; and a plurality of sensor units configured to sense The voltage of the data line.

Other objectives and advantages of the present invention can be understood from the following description and become apparent with reference to the embodiments of the present invention. Moreover, it is obvious to those who are familiar with the technology related to the present invention that the objectives and advantages of the present invention can be achieved by means and combinations as claimed.

The advantages, features, and aspects of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, and the description is set forth in the following. The present invention will now be described with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; the truth is, these embodiments are provided so that this disclosure will be comprehensive and complete, and will Those who are familiar with the technology can fully convey the concept of the present invention. The same reference numerals in the drawings represent the same elements, and therefore the description of these elements will be omitted for the sake of brevity. The term "transistor" as used herein includes any unit that operates as a switching unit according to a control signal input to the gate. Examples of transistors include junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET).

<b>Example 1</b>

2 is an equivalent circuit diagram of a unit cell of the non-volatile memory device according to the first embodiment of the present invention. 3A and 3B are circuit diagrams of the first switch unit SW1 illustrated in FIG. 2. 4A and 4B are circuit diagrams of the second switch unit SW2 illustrated in FIG. 2. 5A and 5B are circuit diagrams of the anti-fuse ANT_FS illustrated in FIG. 2. 6A and 6B are circuit diagrams illustrating the operating characteristics of the unit cell of the non-volatile memory device according to the first embodiment of the present invention.

Referring to FIG. 2, the unit cell of the non-volatile memory device according to Embodiment 1 of the present invention includes a terminal connected to the ground voltage terminal D and the output terminal C (that is, the terminal through which data is output in a read operation) Between the anti-fuse ANT_FS, a first switch unit SW1 connected between the first input terminal A and the output terminal C, and a second switch unit SW2 connected between the second input terminal B and the output terminal C.

As illustrated in FIGS. 3A and 3B, the first switch unit SW1 may include a transistor (ie, an active device) to transfer the write voltage input to the first input terminal A to the output terminal C. In this context, the transistor may be a low-voltage transistor or a high-voltage transistor. In addition, the transistor may be a p-channel transistor or an n-channel transistor. Preferably, the first switch unit SW1 includes a p-channel transistor whose driving capability is better than that of an n-channel transistor. In this case, the transistor has a drain connected to the first input terminal A, a source connected to the output terminal C, and a gate connected to the third input terminal E.

As illustrated in FIGS. 4A and 4B, the second switch unit SW2 is connected to the first switch unit SW1 in parallel from the viewpoint of the output terminal C. In addition, the second switch unit SW2 may include a transistor (ie, an active device) to transfer the read voltage input to the second input terminal B to the output terminal C. In this context, the channel type of the transistor can be the same as or different from the channel type of the transistor of the first switch unit SW1. In addition, the transistor has a drain connected to the second input terminal B, a source connected to the output terminal C, and a gate connected to the fourth input terminal F.

As illustrated in FIGS. 5A and 5B, the anti-fuse ANT_FS may include a transistor (that is, an active device) or a capacitor (that is, a passive device). In this context, the transistor may be a p-channel transistor or an n-channel transistor. In addition, the gate of the transistor is connected to the output terminal C, and the drain and source of the transistor are connected to each other and connected to the ground voltage terminal D in common. The capacitor has a first terminal (ie, the upper electrode) connected to the output terminal C and a second terminal (ie, the lower electrode) connected to the ground voltage terminal D.

Hereinafter, a description will be given of the operation of the unit cell of the non-volatile memory device according to Embodiment 1 of the present invention. For example, in this document, the first switch unit SW1 includes a p-channel transistor, and the second switch unit SW2 includes an n-channel transistor. The anti-fuse ANT_FS includes an n-channel transistor.

<tables><img file="twi463500b_d0002.tif" he="503" id="i0002" img-content="drawing" img-format="tif" inline="yes" orientation="portrait" wi="1977" /></tables>

This will be described with reference to Table 2 and FIGS. 6A and 6B. In this article, FIG. 6A is an equivalent circuit diagram illustrating the current path in a write operation, and FIG. 6B is an equivalent circuit diagram illustrating the current path in a read operation.

<b>Write operation</b>

First, ground the ground voltage terminal D. Then, the high voltage VPP is applied to the first input terminal A, and the logic low level L corresponding to the ground voltage is applied to the third input terminal E and the fourth input terminal F. In this situation, only the first switch unit SW1 including a p-channel transistor is turned on. Therefore, the first input terminal A and the output terminal C are electrically connected to each other, and the second input terminal B and the output terminal C are electrically disconnected from each other. Therefore, the high voltage VPP is transferred to the anti-fuse ANT_FS through the first switch unit SW1 to break the gate insulating layer formed between the substrate and the gate of the anti-fuse ANT_FS.

<b>Read operation</b>

After the write operation is completed, the power supply voltage VDD corresponding to the read voltage is applied to the second input terminal B, and the logic high level H corresponding to the power supply voltage VDD is applied to the third input terminal E and the fourth input terminal F . In this situation, only the second switch unit SW2 including an n-channel transistor is turned on.

Therefore, the second input terminal B and the output terminal C are electrically connected to each other, and the first input terminal A and the output terminal C are electrically disconnected from each other. Therefore, a current path is formed from the second input terminal B through the second switch unit SW2 to the anti-fuse ANT_FS.

In this case, because the gate insulating layer of the anti-fuse ANT_FS is broken, the output terminal C is electrically connected to the ground voltage terminal D via the anti-fuse ANT_FS. Therefore, the data corresponding to the ground voltage is output to the output terminal C sensed by the sensor unit.

<b>Example 2</b>

FIG. 7 is an equivalent circuit diagram of a unit cell of a non-volatile memory device according to the second embodiment of the present invention. 8A and 8B are circuit diagrams illustrating the operating characteristics of the unit cell of the non-volatile memory device according to the second embodiment of the present invention.

Referring to FIG. 7, the unit cell of the non-volatile memory device according to the second embodiment of the present invention basically includes an anti-fuse ANT_FS, a first switch unit SW1, and a second switch unit SW2, as in the implementation of the present invention The unit cell of the non-volatile memory device of Example 1.

In addition, the unit cell of the non-volatile memory device according to the second embodiment of the present invention further includes a third switch unit SW3 connected in series to the second switch unit SW2. Therefore, the first switch unit SW1 is connected in parallel to the second switch unit SW2 and the third switch unit SW3 connected in series to each other.

The first switch unit SW1 may include a transistor (ie, an active device) to transfer the write voltage to the input terminal of the anti-fuse ANT_FS connected to the node H. In this context, the transistor may be a p-channel transistor or an n-channel transistor. In this case, the transistor has a drain connected to the first input terminal A, a source connected to the node H, and a gate connected to the third input terminal E.

The second switch unit SW2 is connected between the output terminal C and the node H. Like the first switch unit SW1, the second switch unit SW2 may include a transistor (ie, an active device). In this context, the transistor may be a p-channel transistor or an n-channel transistor. In this case, the transistor has a drain connected to the output terminal C, a source connected to the node H, and a gate connected to the fourth input terminal F.

Like the second switch unit SW2, the third switch unit SW3 may include a transistor (ie, an active device) to transfer the read voltage to the output terminal C. In this context, the transistor may be a p-channel transistor or an n-channel transistor. In this case, the transistor has a drain connected to the second input terminal B, a source connected to the output terminal C, and a gate connected to the fifth input terminal G.

Meanwhile, the first to third switch units SW1, SW2, and SW3 may have the same channel type or may have different channel types. Preferably, the first switch unit SW1 and the third switch unit SW3 have a p-channel, and the second switch unit SW2 has an n-channel.

Hereinafter, a description will be given of the operation of the unit cell of the non-volatile memory device according to Embodiment 2 of the present invention. For example, in this document, the first switch unit SW1 and the third switch unit SW3 include a p-channel transistor, and the second switch unit SW2 includes an n-channel transistor. The anti-fuse ANT_FS includes an n-channel transistor.

<tables><img file="twi463500b_d0003.tif" he="492" id="i0003" img-content="drawing" img-format="tif" inline="yes" orientation="portrait" wi="2057" /></tables>

This will be described with reference to Table 3 and FIGS. 8A and 8B. In this text, FIG. 8A is an equivalent circuit diagram illustrating the current path in a write operation, and FIG. 8B is an equivalent circuit diagram illustrating the current path in a read operation.

<b>Write operation</b>

First, ground the ground voltage terminal D. Then, the high voltage VPP is applied to the first input terminal A, and the logic low level L is applied to the third input terminal E and the fourth input terminal F. In addition, the logic high level H is applied to the fifth input terminal G. In this situation, only the first switch is turned on.

Therefore, the first input terminal A and the node H are electrically connected to each other, and the second input terminal B and the node H are electrically disconnected from each other. Therefore, the high voltage VPP is transferred to the anti-fuse ANT_FS through the first switch unit SW1 to break the gate insulating layer formed between the substrate and the gate of the anti-fuse ANT_FS. That is, the gate electrode and the substrate are electrically short-circuited.

<b>Read operation</b>

After the write operation is completed, the power supply voltage VDD corresponding to the read voltage is applied to the second input terminal B, and the logic high level H is applied to the third input terminal E and the fourth input terminal F. Furthermore, the logic low level L is applied to the fifth input terminal G. In this situation, the second switch unit SW2 and the third switch unit SW3 are turned on.

Therefore, the second input terminal B and the node H are electrically connected to each other, and the first input terminal A and the node H are electrically disconnected from each other. Therefore, a current path is formed from the second input terminal B through the second switch unit SW2 and the third switch unit SW3 to the anti-fuse ANT_FS. In this case, because the gate insulating layer of the anti-fuse ANT_FS is broken, the output terminal C is electrically connected to the ground voltage terminal D via the second switch unit SW2 and the anti-fuse ANT_FS. Therefore, the data corresponding to the ground voltage is output to the output terminal C sensed by the sensor unit.

<b>Example 3</b>

9 is an equivalent circuit diagram of a unit cell of a non-volatile memory device according to Embodiment 3 of the present invention.

Referring to FIG. 9, in addition to the sensor unit SA connected to the output terminal C, the configuration and operation of the unit cell of the non-volatile memory device according to the third embodiment of the present invention and the non-volatile memory of the second embodiment The configuration and operation of the unit unit of the physical device are the same, and the description will be omitted for the sake of brevity.

The sensor unit SA includes an inverter that inverts the voltage output via the output terminal C in the read operation. In this context, the inverter includes a CMOS transistor in which the p-channel transistor and the n-channel transistor are connected in a complementary manner. Specifically, the source of the p-channel transistor and the drain of the n-channel transistor are connected to each other. In addition, the gates of the transistors are connected to each other. In addition, the drain of the p-channel transistor is connected to the power supply voltage VDD, and the drain of the n-channel transistor is connected to the ground voltage VSS.

Hereinafter, a description will be given of the cell array of the non-volatile memory device including one unit cell according to the above-described embodiment 1 to embodiment 3 of the present invention.

<b>Example 4</b>

FIG. 10 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 4 of the present invention.

Referring to FIG. 10, the memory cell array of the non-volatile memory device according to the fourth embodiment of the present invention includes a plurality of unit cells UC arranged in a matrix type. Herein, like the unit cell of Embodiment 1, the unit cell UC includes a switch unit SW1, a second switch unit SW2, and an anti-fuse ANT_FS connected in series to the first switch unit SW1 and the second switch unit SW2. For example, in the unit cell UC, the first switch unit SW1 includes a p-channel transistor, and the second switch unit SW2 includes an n-channel transistor.

In addition, the memory cell array of the non-volatile memory device according to the fourth embodiment of the present invention includes: a plurality of write drive lines WR_CT0 to WR_CTn (n: natural number), which are used to select the first switch of the unit cell UC Cell SW1; and a plurality of read drive lines RD_CT0 to RD_CTm (m: natural number), which are used to select the second switch unit SW2 of the unit cell UC.

The write drive lines WR_CT0 to WR_CTn extend in the column direction to be connected to the first switching unit SW1 of each of the unit cells UC arranged in the column direction, that is, the gate of the p-channel transistor. The read drive lines RD_CT0 to RD_CTm extend perpendicular to the write drive lines WR_CT0 to WR_CTn in the row direction to be connected to the second switch unit SW2 of each of the unit cells UC arranged in the row direction, that is, the n-channel electrical The gate of the crystal.

Furthermore, the memory cell array of the non-volatile memory device according to the fourth embodiment of the present invention includes data lines DL0 to DLn (n: natural numbers) and write voltage supply lines WRL0 to WRLm (m: natural numbers). In this text, the data lines DL0 to DLn transfer the read voltage to the respective unit cells UC in the read operation, and transfer the data output from the respective unit cells UC to the sensor cells SA0 to SAn in the read operation. (n: natural number). The write voltage supply lines WRL0 to WRLm transfer the write voltage to the respective unit cells UC in the write operation.

The data lines DL0 to DLn extend in the column direction to connect the input terminal of each of the sensor cells SA0 to SAn and the output terminal of each of the unit cells UC arranged in the column direction. The data line connects the second switch unit SW2 (preferably, the drain of the n-channel transistor) and the input terminals of the sensor units SA0 to SAn.

In the read operation, the data lines DL0 to DLn transfer the read voltage (that is, the power supply voltage VDD) transferred through the third switch unit SW3 to the second switch unit SW2, and transfer the data output from the second switch unit SW2 Transfer to the corresponding sensor units SA0 to SAn.

The write voltage supply lines WRL0 to WRLm extend in the row direction to be connected to the first switch unit SW1 of each of the unit cells arranged in the row direction, that is, the drain of the p-channel transistor. In the write operation, the write voltage supply lines WRL0 to WRLm transfer the write voltage (ie, the high voltage VPP) to the first switch unit SW1 of each of the unit cells UC arranged in the row direction.

Furthermore, the memory cell array of the non-volatile memory device according to the fourth embodiment of the present invention includes a plurality of sensor units SA0 to SAn, and the sensor units SA0 to SAn are respectively provided to the corresponding data lines DL0 to DL0 to DLn senses the data output through the corresponding data lines DL0 to DLn. The sensor units SA0 to SAn may include an inverter or a differential amplifier (refer to FIG. 11). Preferably, the sensor units SA0 to SAn include an inverter whose circuit structure is simple and is therefore advantageous in terms of occupied area and power consumption.

In addition, the memory cell array of the non-volatile memory device according to the fourth embodiment of the present invention includes a third switch unit SW3, and the third switch unit SW3 reads in response to the read operation signal RD_EN during a read operation. The voltage (ie, the power supply voltage VDD) is transferred to the corresponding data lines DL0 to DLn. Here, the third switch unit SW3 may include an n-channel transistor or a p-channel transistor. Preferably, the third switch unit SW3 includes a p-channel transistor with a driving capability better than that of an n-channel transistor.

Hereinafter, a description will be given of the writing/reading operation of the non-volatile memory device according to the fourth embodiment of the present invention. For example, in this article, a description will be given of the write/read operation of the unit cell UC connected to both the write drive line WR_CT0 and the read drive line RD_CT0.

<tables><img file="twi463500b_d0004.tif" he="719" id="i0004" img-content="drawing" img-format="tif" inline="yes" orientation="portrait" wi="2039" /></tables>

It will be described with reference to Table 4.

<b>Write operation</b>

First, ground one end of the anti-fuse ANT_FS. Next, the write voltage (that is, the high voltage VPP) is applied to the write voltage supply lines WRL0 to WRLm. In addition, the logic low level L is applied to the write drive line WR_CT0, and the logic high level H is applied to the other write drive lines WR_CT1 to WR_CTn. In addition, the logic level L is applied to the read drive lines RD_CT0 to RD_CTm.

In addition, the read operation signal RD_EN is applied in the logic high state. In this situation, only the first switch unit SW1 is turned on, so that the write voltage supply line WRL0 and the anti-fuse ANT_FS are electrically connected to each other. Therefore, the high voltage VPP applied via the write voltage supply line WRL0 is transferred to the anti-fuse ANT_FS via the first switch unit SW1. Therefore, the gate insulating layer formed between the substrate and the gate of the anti-fuse ANT_FS is broken by the high electric field.

<b>Read operation</b>

After the write operation is completed, the logic high level H is applied to the write drive line WR_CT0. In addition, the logic high level H is applied to the read drive line RD_CT0, and the logic low level L is applied to the other read drive lines RD_CT1 to RD_CTm. In addition, the read operation signal RD_EN is applied in the logic low state.

In this situation, the second switch unit SW2 and the third switch unit SW3 are turned on, so that the read voltage (ie, the power supply voltage VDD) is transferred to the corresponding data line DL0 through the third switch unit SW3. Therefore, a current path is formed from the data line DL0 through the second switch unit SW2 to the anti-fuse ANT_FS.

In this case, because the gate insulating layer of the anti-fuse ANT_FS is broken, the data line DL0 is electrically connected to the ground voltage terminal via the second switch unit SW2 and the anti-fuse ANT_FS. Therefore, the sensor unit SA0 senses the data corresponding to the ground voltage from the data line DL0.

<b>Example 5</b>

FIG. 11 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 5 of the present invention.

Referring to FIG. 11, except that the sensor units SA0 to SAn include a differential amplifier instead of an inverter, the memory cell array of the non-volatile memory device according to the fifth embodiment of the present invention has the same value as that of the fourth embodiment. The memory cell array of the non-volatile memory device has the same structure. In this article, the differential amplifier includes p-channel transistors PM1 and PM2 and n-channel transistors NM1, NM2, and NM3. The differential amplifier is operated by the bias signal BIAS to compare the reference voltage VREF with the data of the corresponding unit cell output from the corresponding data line and amplify it before output.

Except for the sensor units SA0 to SAn, other components are the same as those of the fourth embodiment, and therefore, detailed descriptions of these components will be omitted for the sake of brevity.

<b>Example 6</b>

FIG. 12 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 6 of the present invention.

Referring to FIG. 12, the memory cell array of the non-volatile memory device according to the sixth embodiment of the present invention includes a unit cell UC, and the unit cell UC includes a third switch unit SW3, which is different from the fourth embodiment. That is, although the third switch unit SW3 of the fourth embodiment is connected to the ends of the corresponding data lines DL0 to DLn (that is, the input terminals of the sensor units SA0 to SAn), the third switch unit SW3 of the sixth embodiment includes In the unit cell UC.

Except for the unit cell UC, other components are the same as those of the fourth embodiment, and therefore, detailed descriptions of these components will be omitted for the sake of brevity.

<b>Example 7</b>

FIG. 13 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 7 of the present invention.

Referring to FIG. 13, the memory cell array of the non-volatile memory device according to the seventh embodiment of the present invention includes a unit cell UC, and the unit cell UC includes not only the third switch unit SW3 but also sensor units SA0 to SAn, This is different from Embodiment 6. That is, although the sensor cells SA0 to SAn of the sixth embodiment are arranged at the ends of the corresponding data lines DL0 to DLn, the sensor cells SA0 to SAn of the seventh embodiment are included in the unit cell UC.

Therefore, unlike Embodiment 6, Embodiment 7 does not need to connect the output terminals of the plurality of unit cells UC arranged in the column direction to the plurality of data lines DL0 to DLn of the sensor cells SA0 to SAn. Therefore, the seventh embodiment can minimize the data loss, that is, the data loss due to the resistance value of the data line, and the data loss can be generated in the memory cell array structure including the data line according to the sixth and fifth embodiments , Which makes it possible to improve the data sensing tolerance.

Except for the unit cell UC, other components are the same as those of the fourth embodiment, and therefore, detailed descriptions of these components will be omitted for the sake of brevity.

<b>Example 8</b>

FIG. 14 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 8 of the present invention.

Referring to FIG. 14, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes a plurality of unit cells UC, and each of the plurality of unit cells UC includes a first switch unit SW1 and a Anti-fuse ANT_FS. For example, in the unit cell UC, the first switch unit SW1 includes a p-channel transistor, and the anti-fuse ANT_FS includes an n-channel transistor.

In addition, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes a plurality of second switch units SW2, and the plurality of second switch units SW2 are respectively arranged in corresponding rows to set the write voltage (also That is, the high voltage VPP) is transferred to the first switching unit SW1. Here, the second switch unit SW2 may include an n-channel transistor or a p-channel transistor, and transfer the high voltage VPP to the first switch unit SW1 in response to the write operation signals WR_EN0 to WR_ENn.

In addition, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes a plurality of read drive lines RD_CT0 to RD_CTm (m: natural number) for selecting the first switch unit SW1 of the unit cell UC . The read drive lines RD_CT0 to RD_CTm extend in the row direction to be electrically connected to the first switching unit SW1 of each of the unit cells UC arranged in the row direction, that is, the gate of the p-channel transistor.

Furthermore, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes data lines DL0 to DLn (n: natural number). In the read operation, the data lines DL0 to DLn transfer the read voltage to the output terminal N of each unit cell UC (that is, the connection between the first switch unit and the second switch unit), and in the read operation Transfer the data output from each unit unit UC to the sensor units SA0 to SAn (n: natural number).

The data lines DL0 to DLn extend in the column direction to connect the input terminal of each of the sensor cells SA0 to SAn and the output terminal of each of the unit cells UC arranged in the column direction. The data line connects the first switch unit SW1 (specifically, the drain of the p-channel transistor) and the input terminals of the sensor units SA0 to SAn. In the read operation, the data lines DL0 to DLn transfer the read voltage (that is, the power supply voltage VDD) transferred by the third switch unit SW3 to the first switch unit SW1, and the data output from the first switch unit SW1 The data is transferred to the corresponding sensor units SA0 to SAn.

In addition, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes a plurality of sensor units SA0 to SAn, and the sensor units SA0 to SAn are provided to the corresponding data lines DL0 to DL0 to SAn, respectively. DLn senses the data output through the corresponding data lines DL0 to DLn. The sensor units SA0 to SAn include an inverter having input terminals connected to the ends of the data lines DL0 to DLn.

In addition, the memory cell array of the non-volatile memory device according to the eighth embodiment of the present invention includes a third switch unit SW3, and the third switch unit SW3 responds to the read operation signal RD_EN to read the voltage (that is, The power supply voltage VDD) is transferred to the corresponding data lines DL0 to DLn. Here, the third switch unit SW3 may include an n-channel transistor or a p-channel transistor. Preferably, the third switch unit SW3 includes a p-channel transistor whose driving capability is better than that of an n-channel transistor.

Hereinafter, a description will be given of the writing/reading operation of the non-volatile memory device according to Embodiment 8 of the present invention. For example, in this article, a description will be given of the write/read operation of the unit cell UC selected by the read drive line RD_CT0 and the write operation signal WR_EN0.

<tables><img file="twi463500b_d0005.tif" he="449" id="i0005" img-content="drawing" img-format="tif" inline="yes" orientation="portrait" wi="2143" /></tables>

It will be described with reference to Table 5.

<b>Write operation</b>

First, ground one end of the anti-fuse ANT_FS. Then, the write operation signal WR_EN0 is applied in the logic low state, and other write operation signals WR_EN1 to WR_ENn are applied in the logic high state. In addition, the logic low level L is applied to the read drive line RD_CT0, and the logic high level H is applied to the other read drive lines RD_CT1 to RD_CTm. In addition, the read operation signal RD_EN is applied in the logic high state. Therefore, the write voltage (that is, the high voltage VPP) is transferred to the anti-fuse ANT_FS via the first switch unit SW1 and the second switch unit SW2. Therefore, the gate insulating layer formed between the substrate and the gate of the anti-fuse ANT_FS is broken by the high electric field.

<b>Read operation</b>

After the write operation is completed, the write operation signal WR_EN0 is applied in the logic high state. In addition, the logic low level L is applied to the read drive line RD_CT0, and the logic high level H is applied to the other read drive lines RD_CT1 to RD_CTm. In addition, the read operation signal RD_EN is applied in the logic low state.

In this situation, the first switch unit SW1 and the third switch unit SW3 are turned on, so that the read voltage (ie, the power supply voltage VDD) is transferred to the corresponding data line DL0 through the third switch unit SW3. Therefore, a current path is formed from the data line DL0 through the first switch unit SW1 to the anti-fuse ANT_FS. In this case, because the gate insulating layer of the anti-fuse ANT_FS is broken, the data line DL0 is electrically connected to the ground voltage terminal through the first switch unit SW1 and the anti-fuse ANT_FS. Therefore, the sensor unit SA0 senses the data corresponding to the ground voltage from the data line DL0.

The following effects can be achieved by the present invention including the configuration described above.

First, according to the present invention, the first and second switch units connected to the anti-fuse are connected in parallel to each other to transfer the write voltage and the read voltage to the anti-fuse through different paths. Therefore, the present invention minimizes the reading voltage loss in the reading operation and improves the sensing margin of the data sensed by the output terminal of the unit cell, thereby making it possible to improve the operation reliability.

Second, according to the present invention, an inverter is used to implement a sensor unit that senses the data output from the unit cell. Therefore, the present invention simplifies the circuit structure, thereby making it possible to reduce the occupied area and power consumption.

Although the present invention has been described in terms of specific embodiments, it will be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention as defined in the scope of the following patent applications.

<p>A. . . The first input terminal</p><p>ANT_FS. . . Antifuse</p><p>B. . . node</p><p>BIAS. . . Bias signal</p><p>C. . . Second input terminal/output terminal</p><p>D. . . Third input terminal/ground voltage terminal</p><p>DL0. . . Data line</p><p>DL1. . . Data line</p><p>DLn. . . Data line</p><p>E. . . Output terminal/Third input terminal</p><p>F. . . Fourth input terminal</p><p>G. . . Fifth input terminal</p><p>H. . . Logic high level/node</p><p>N. . . Output terminal</p><p>NM1n-. . . Channel Transistor/First Transistor</p><p>NM2n-. . . Channel Transistor/Second Transistor</p><p>NM3n-. . . Channel transistor</p><p>PM1p-. . . Channel transistor</p><p>PM2p-. . . Channel transistor</p><p>RD_CT0. . . Read drive line</p><p>RD_CT1. . . Read drive line</p><p>RD_CT2. . . Read drive line</p><p>RD_CTm. . . Read drive line</p><p>RD_EN. . . Read operation signal</p><p>SA. . . Sensor unit</p><p>SA0. . . Sensor unit</p><p>SA1. . . Sensor unit</p><p>SAn. . . Sensor unit</p><p>SW1. . . First switch unit</p><p>SW2. . . Second switch unit</p><p>SW3. . . Third switch unit</p><p>UC. . . Unit unit</p><p>VDD. . . voltage</p><p>VPP. . . high voltage</p><p>VREF. . . Reference voltage</p><p>VSS. . . Ground voltage</p><p>WR_CT0. . . Write drive line</p><p>WR_CT1. . . Write drive line</p><p>WR_CTn. . . Write drive line</p><p>WR_EN0. . . Write operation signal</p><p>WR_EN1. . . Write operation signal</p><p>WR_ENn. . . Write operation signal</p><p>WR_L0. . . Write voltage supply line</p><p>WRL1. . . Write voltage supply line</p><p>WRL2. . . Write voltage supply line</p><p>WRLm. . . Write voltage supply line</p>

Figure 1 is an equivalent circuit diagram of a conventional OTP unit cell.

2 is an equivalent circuit diagram of a unit cell of the non-volatile memory device according to the first embodiment of the present invention.

3A and 3B are circuit diagrams of the first switch unit SW1 illustrated in FIG. 2.

4A and 4B are circuit diagrams of the second switch unit SW2 illustrated in FIG. 2.

5A and 5B are circuit diagrams of the anti-fuse ANT_FS illustrated in FIG. 2.

6A and 6B are circuit diagrams illustrating the operating characteristics of the unit cell of the non-volatile memory device according to the first embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a unit cell of a non-volatile memory device according to Embodiment 2 of the present invention.

8A and 8B are circuit diagrams illustrating the operating characteristics of the unit cell of the non-volatile memory device according to the second embodiment of the present invention.

9 is an equivalent circuit diagram of a unit cell of a non-volatile memory device according to Embodiment 3 of the present invention.

FIG. 10 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 4 of the present invention.

FIG. 11 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 5 of the present invention.

FIG. 12 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 6 of the present invention.

FIG. 13 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 7 of the present invention.

FIG. 14 is an equivalent circuit diagram of a non-volatile memory device according to Embodiment 8 of the present invention.