Method for managing a plurality of blocks of a flash memory, and associated memory device and controller thereof

Method for managing multiple blocks of a flash memory and related memory device and controller

METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

The present invention relates to the access of a flash memory (Flash Memory), in particular to a method for managing a plurality of blocks of a flash memory, and related memory devices and their controllers.

In recent years, due to the continuous development of flash memory technology, various portable memory devices (such as memory cards that comply with SD/MMC, CF, MS, and XD standards) have been widely implemented in many applications. Therefore, the access control of the flash memory in these portable memory devices has become a very hot topic.

In terms of commonly used NAND-type flash memory, it can be mainly divided into two types of flash memory, single level cell (SLC) and multiple level cell (MLC). Each transistor used as a memory cell in a single-level cell flash memory has only two charge values, which are used to represent a logic value of 0 and a logic value of 1, respectively. In addition, the storage capacity of each transistor that is used as a memory cell in the multi-level cell flash memory is fully utilized. It is driven by a higher voltage to record in a transistor through different levels of voltage. Two sets of bit information (for example: 00, 01, 11, 10); theoretically, the recording density of a multi-level cell flash memory can reach more than twice the recording density of a single-level cell flash memory. It is very good news for the related industries of NAND flash memory that have encountered bottlenecks in the development process.

Compared with single-level cell flash memory, multi-level cell flash memory is cheaper in price and can provide larger capacity in a limited space, so multi-level cell flash memory quickly becomes the market. The portable memory devices on the market are competing to adopt the mainstream. However, the problems caused by the instability of multi-level cell flash memory have also surfaced one by one. For these many problems, although some solutions are provided in related technologies, it is always impossible to balance operation efficiency and system resource usage control. Therefore, no matter which solution is adopted, there will always be corresponding side effects. Therefore, there is a need for a novel method to strengthen the control of the data access of the flash memory, so as to balance the operation performance and the system resource usage control.

Therefore, one of the objectives of the present invention is to provide a method for managing a plurality of blocks of a flash memory (Flash Memory) and related memory devices and their controllers to solve the above-mentioned problems.

Another object of the present invention is to provide a method for managing a plurality of blocks of a flash memory, and related memory devices and their controllers, so as to achieve the best operating performance and dynamically reduce the operating burden.

Another object of the present invention is to provide a method for managing multiple blocks of a flash memory and related memory devices and their controllers, so as to dynamically avoid the problems of pure page link architecture and pure blockchain The structure of the problem. In addition, the portable memory device realized by using the present invention will have a longer service life.

A preferred embodiment of the present invention provides a method for managing a plurality of blocks of a flash memory. The method includes: dynamically determining an address for a logical block according to at least one criterion (Criterion) A link category, wherein the link category is selected from a plurality of predetermined link categories; and the link category and link information corresponding to the link category are recorded/updated for the logical block address.

While providing the above method, the present invention also correspondingly provides a memory device, which includes: a flash memory, the flash memory includes a plurality of blocks; and a controller for access (Access) The flash memory and manage the plurality of blocks, wherein the controller dynamically determines a link type for a logical block address according to at least one determination criterion, and the link type is selected from a plurality of A predetermined link type; wherein the controller records/updates the link type and the link information corresponding to the link type for the logical block address.

While providing the above method, the present invention also correspondingly provides a controller for a memory device, the controller is used to access a flash memory, the flash memory includes a plurality of blocks, the controller includes : A Read Only Memory (ROM), used to store a program code; and a microprocessor, used to execute the program code to control access to the flash memory and manage the plurality of areas Block; wherein the controller that executes the program code through the microprocessor dynamically determines a link type for a logical block address according to at least one criterion, and the link type is selected from a plurality of predetermined Link type; and the controller that executes the program code through the microprocessor records/updates the link type and the link information corresponding to the link type for the logical block address.

Please refer to Figure 1. Figure 1 is a schematic diagram of a memory device 100 according to a first embodiment of the present invention. The memory device 100 of this embodiment is especially a portable memory device (for example: compliant with SD/MMC, CF, MS, XD standard memory card). The memory device 100 includes: a flash memory (Flash Memory) 120; and a controller for accessing the flash memory 120, wherein the controller is, for example, a memory controller 110. According to this embodiment, the memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory system is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory 120. Please note that the program code 112C must also be stored in the buffer memory 116 or any form of memory.

In a typical situation, the flash memory 120 includes a plurality of blocks, and the controller (for example, the memory controller 110 that executes the program code 112C through the microprocessor 112) erases the flash memory 120 The operation of erasing data is erasing in units of blocks. In addition, a block can record a specific number of pages, and the controller writes data to the flash memory 120 in units of pages.

In practice, the memory controller 110, which executes the program code 112C through the microprocessor 112, can use its own internal components to perform many control operations, for example, the control logic 114 is used to control the access operations of the flash memory 120 ( Especially the access operation to at least one block or at least one page), the buffer memory 116 is used to perform the required buffer processing, and the interface logic 118 is used to communicate with a host device.

According to this embodiment, in addition to being able to access the flash memory 120, the controller can also properly manage the plurality of blocks. More specifically, when writing/updating data, the controller can dynamically determine a link type for a logical block address according to at least one criterion (Criterion), wherein the link type is selected from For a plurality of predetermined link types. In addition, the controller can record/update the link type and link information corresponding to the link type for the logical block address.

FIG. 2 is a flowchart of a method 910 for managing a plurality of blocks of a flash memory according to an embodiment of the present invention. This method can be applied to the memory device 100 shown in FIG. 1, especially the above-mentioned controller (for example, the memory controller 110 that executes the program code 112C through the microprocessor 112). In addition, the method can be implemented by using the memory device 100 shown in FIG. 1, especially by using the above-mentioned controller. The method is described as follows:

In step 912, the aforementioned controller (for example, the memory controller 110 that executes the program code 112C through the microprocessor 112) dynamically determines a link type for a logical block address according to at least one determination criterion. The link type is selected from a plurality of predetermined link types. For example, the plurality of predetermined link types include a first link type, a second link type, and a third link type. In particular, when the criterion indicates that the link between the logical page and the physical page is necessary, then under the control of the controller, the type of link involves the link between the logical page and the physical page (referred to as Page link); otherwise, the link type may only involve the link between the logical block and the physical block (referred to as the blockchain link for short). According to this embodiment, under the control of the controller, the link type can dynamically switch between the type of the page link and the type of the block link.

In step 914, the controller records/updates the link type and the link information corresponding to the link type for the logical block address. For example: when the link type is the first link type, the link information includes a physical block address. For another example: when the link type is the second link type, the link information includes a physical block address and current physical page location information, and the current physical page location information is used to point to the logic The location of the last physical page written to the block address. For another example: when the link type is the third link type, the link information includes page link information.

Figures 3 to 6 are schematic diagrams of the predetermined link types involved in the method shown in Figure 2 in an embodiment. Figures 3 and 4 correspond to the first and second links mentioned above, respectively. Types, and Figures 5 and 6 correspond to the third link type mentioned above. As shown in Figure 3, when the controller determines in step 912 that the link type is the first link type, under the control of the controller, the logical area represented by the logical block address The block is linked to a physical block, and all the logical pages 0, 1,..., and z of the logical block are respectively linked to the physical pages 0, 1,..., of the physical block. With z. Here, the first link type can be called "Direct Link".

In addition, as shown in Figure 4, when the controller determines in step 912 that the link type is the second link type, under the control of the controller, the logical block address represents The logical block is linked to a physical block, but only a part of the logical pages 1, 2,..., and x in the logical block are respectively linked to a part of the physical pages 1, 2,... of the physical block. , And x. Here, the second link type can be referred to as "Partial Direct Link".

In addition, when the controller determines in step 912 that the link type is the third link type, under the control of the controller, the logical block represented by the logical block address is selectively linked It is bound to one or more physical blocks, and the logical pages in the logical block are randomly linked to the physical pages of the physical block(s). Here, the third link type can be referred to as "Random Link". For example: the logical block shown in Figure 5 is linked to a physical block, and the logical pages 1, 2,..., and x in the logical block are randomly linked to the physical pages of the physical block 1, 2,..., and x (as indicated by the arrows in Figure 5). Another example: the logical block shown in Figure 6 is linked to two physical blocks, and the logical pages 0, 1, 2,..., and x in the logical block are randomly linked to Figure 6 The physical pages 0, 1,..., etc. of the physical block in the upper right corner and the physical pages 0, 1,..., and y of the physical block in the lower right corner of Figure 6 (as shown by the arrows in Figure 6) . In another embodiment, logical pages belonging to different logical block addresses (for example, logical page 3 of LB(p), logical page 7 of LB(q)) can also be randomly linked to bits belonging to the same physical block Different logical pages of the address (for example, logical pages 8, 9 of PBA(Y_0)).

Please note that in this embodiment, Figures 5 and 6 both correspond to the above-mentioned third link type. This is for illustrative purposes only, and is not a limitation of the present invention. According to a variation of this embodiment, the third link type can be further subdivided into at least two link types, respectively corresponding to the number of physical blocks linked to the logical block.

Figure 7 is a schematic diagram of the predetermined link types involved in an embodiment of the method shown in Figure 2 and the link information respectively corresponding to the predetermined link types, wherein the predetermined link types Type(1), Type(2), and Type(3) respectively represent the above-mentioned first, second, and third link types. In this embodiment, the link information corresponding to the predetermined link type Type (1) includes a physical block address and an index pointing to the physical block address. For example: for the logical block address LB(0), the link type is the predetermined link type Type(1), and the link information corresponding to the predetermined link type Type(1) includes the physical block address PBA (X_0) and an indicator pointing to the physical block address PBA (X_0). Similarly, for the logical block address LB(i), when i=3, 4,..., or n, the link type is the predetermined link type Type(1), which corresponds to the predetermined link The link information of the type Type (1) includes the physical block address PBA (X_i) and the pointer to the physical block address PBA (X_i).

In addition, the link information corresponding to the predetermined link type Type (2) includes current physical page location information and a physical block address, and includes pointers to the current physical page location information and/or the physical block address . For example: for the logical block address LB(2), the link type is the predetermined link type Type(2), and the link information corresponding to the predetermined link type Type(2) includes the current physical page location information Current_PPage And the physical block address PBA (X_2), and also includes pointers to the current physical page location information Current_PPage and/or physical block address PBA (X_2). Especially in this embodiment, the current physical page location information Current_PPage shown in Figure 7 is arranged before the physical block address PBA(X_2), and the indicator for the logical block address LB(2) points to the current physical Page location information Current_PPage. This is for illustrative purposes only, and is not a limitation of the present invention. According to a variation of this embodiment, the current physical page location information Current_PPage can be arranged after the physical block address PBA(X_2), and the indicator for the logical block address LB(2) can point to the physical block address PBA(X_2).

In addition, the link information corresponding to the predetermined link type Type (3) includes page link information and an index pointing to the page link information. For example: for the logical block address LB(1), the link type is the predetermined link type Type(3), and the link information corresponding to the predetermined link type Type(3) includes a logical physical page link Table 730 and an index pointing to the logical entity page link table 730. As shown in Figure 7, the controller records/updates a physical block address PBA(Y) for the logical block address LB(1). In particular, in the logical physical page link table 730, the controller records/updates a corresponding physical page address for a logical page address LPage(j) belonging to the logical block address PBA(Y), so that In the future, data belonging to the logical block address LB(1) can be found, where j=0, 1,..., or (m-1). Therefore, the logical physical page link table 730 includes the physical block address PBA(Y) and the logical page addresses LPage(0), LPage(1), .. respectively corresponding to the logical block address LB(1). ., and LPage (m-1) of m physical page addresses. This is for illustrative purposes only, and is not a limitation of the present invention. According to a variation of this embodiment, the physical block address PBA(Y) can be placed (stored in) outside the logical physical page link table 730. According to another variation of this embodiment, the logical physical page link table may include more than one physical block address.

FIG. 8 is a schematic diagram of the predetermined link types involved in another embodiment of the method shown in FIG. 2 and the link information corresponding to the predetermined link types. This embodiment is a variation of the embodiment shown in FIG. 7, in which the above-mentioned logical entity page link table 730 is replaced with a logical entity page link table 830. In the logical physical page link table 830, the controller records/updates a physical block address and a physical page corresponding to a logical page address LPage(j) belonging to the logical block address LB(1) Address, where j=0, 1,..., or (m-1). In particular, the controller records/updates a complex array of physical block addresses and physical page addresses in the logical physical page link table 830, so that data belonging to the logical block address LB(1) can be found in the future, where the The plurality of physical block addresses may be different from each other. For example, the plurality of physical block addresses may include physical block addresses PBA(Y_1), PBA(Y_7), PBA(Y_3), etc. As shown in Figure 8, each row (or item) of the logical physical page link table 830 includes a set of physical block addresses and physical page addresses, and each row (or item) from top to bottom corresponds to The logical page addresses LPage(0), LPage(1),..., and LPage(m-1) belonging to the logical block address LB(1). The similarities between this embodiment and the foregoing embodiments/variations will not be repeated.

One of the advantages of the present invention is that, for the selection of the link type, the method and the related memory device and its controller of the present invention can dynamically change the mode and the domain of the link type of the home page according to the writing behavior of the host device. Switch between the types of block links, so the method of the present invention and the related memory device and its controller can achieve the best operating performance and dynamically reduce the operating burden. For example, when the main device writes a certain logical block continuously and completely, the "direct link" mode is applicable to the type of link; and when the main device continuously and partially writes to a certain logical block When a logical block is written, the "partial direct link" mode is applicable to the type of link; and if the main device writes a logical block continuously in the initial stage, and then changes its write The behavior, such as changing to write randomly, can dynamically change from the mode of "partial direct link" to the mode of "random link" in terms of link type. In addition, compared with the conventional technology, the method of the present invention and the related memory device and its controller not only have better performance, but also can dynamically avoid the problems of the pure page link architecture and the pure block link architecture. In addition, the portable memory device realized by using the present invention will have a longer service life.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

<p>100. . . Memory device</p><p>110. . . Memory controller</p><p>112. . . microprocessor</p><p>112C. . . Code</p><p>112M. . . Read-only memory</p><p>114. . . Control logic</p><p>116. . . Buffer memory</p><p>118. . . Interface logic</p><p>120. . . Flash memory</p><p>730,830. . . Logical entity page linked list</p><p>910. . . Method for managing multiple blocks of a flash memory</p><p>912,914. . . step</p><p>Current_PPage. . . Current physical page location information</p><p>LB(0), LB(1), LB(2), LB(3),...,LB(n). . . Logical block address</p><p>LPage(0),LPage(1),...,LPage(m-1). . . Logical page address</p><p>PBA(X-0), PBA(X-2), PBA(X_3),..., PBA(X_n), PBA(Y). . . Physical block address</p><p>Type(1), Type(2), Type(3). . . Types of scheduled links</p>

FIG. 1 is a schematic diagram of a memory device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a method for managing a plurality of blocks of a flash memory according to an embodiment of the present invention.

Figures 3 to 6 are schematic diagrams of predetermined link types involved in the method shown in Figure 2 in an embodiment.

FIG. 7 is a schematic diagram of the predetermined link types involved in an embodiment of the method shown in FIG. 2 and the link information corresponding to the predetermined link types.

FIG. 8 is a schematic diagram of the predetermined link types involved in another embodiment of the method shown in FIG. 2 and the link information corresponding to the predetermined link types.