Three dimensional chip stacking package structure

Three-dimensional stacked chip packaging structure

THREE DIMENSIONAL CHIP STACKING PACKAGE STRUCTURE

The present invention relates to a packaging structure, and more particularly to a packaging structure of stacked chips.

The emerging technology of the semiconductor industry, 3DIC, refers to vertically overlapping the chips and connecting them with through-silicon vias (TSV) technology. This method aims to shorten the wires between the chips, reduce the size of the components, and increase the operating bandwidth. 3DIC technology can effectively increase product performance, reduce power consumption, reduce costs, reduce size, and integrate heterogeneous ICs to help build a complete three-dimensional stacked chip architecture.

3DIC uses through silicon vias to connect the electrical properties between the ICs to provide a very high-density vertical stack, making the distance between the two dies only tens of microns. With the development of solder ball packaging technology in a more refined direction, the maintenance of reliability brings The challenge is getting bigger and bigger. The smaller solder ball pitch means that the surface area of each connection is smaller. Compared with the case of using larger solder balls and having a looser pitch, this in turn will concentrate mechanical stress on a smaller area, causing degradation and heat. The cycle will generate mechanical stress on the solder joints. If the package/solder joints are not properly engineered, the solder joints may break.

The solution used in traditional chip packaging is to use underfill technology under surface mount components. The appropriate choice of primer material can fill the gap between the IC and the carrier, but how can the stacked chips be properly glued? Filling has become a major problem at present.

The present invention provides a stacked chip packaging structure. The packaging structure includes a substrate, at least one chip stack disposed on the substrate, a retaining wall structure on the substrate, and a primer filling the chips stacked on each other in the chip stack between. The retaining wall structure is close to at least one side of the chip stack, and the retaining wall structure has at least one slope surface extending from the middle height of the chip stack to the substrate.

In order to make the above-mentioned features of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The invention relates to an integrated stacked chip packaging unit structure and its related manufacturing process, so that the gap between each layer of the stacked chip can be fully filled with primer, can protect and improve the reliability of each solder ball joint of the stacked chip, and reduce mechanical stress and heat. A situation where stress is concentrated on the contact and causes a fracture.

The "chip" in the specification of this case includes all current known chips in the field of electronics or semiconductor technology, preferably, but not limited to, thinned chips, memory chips or high-frequency chips.

FIG. 1 is a three-dimensional schematic diagram of a stacked chip package structure according to an embodiment of the present invention. 2 is a schematic side view of a stacked chip package unit structure according to an embodiment of the present invention. FIG. 3 is a three-dimensional schematic diagram of a stacked chip package structure according to another embodiment of the present invention.

Figure 1 shows the package structure 10 before the primer is filled and includes a plurality of stacked chips 110 on a substrate 100 (the figure shows that four chips are stacked on top of each other to form a chip stack 110A, but the actual number of stacked chips is not limited to 4) A plurality of bumps 120 located between the chips 100 and at least one sloped retaining wall structure 200 disposed on the substrate 100. A plurality of chips 110 are stacked on the substrate 100 and electrically connected to each other through bumps 120 in a flip chip manner. Setting the wafer stacking direction (that is, the thickness direction of the wafer) as the first direction D1 is also the so-called vertical direction, and the direction perpendicular to the first direction and extending along one side of the wafer 110 is the second direction D2, which is perpendicular to the first direction. 1. The second direction is the third direction D3. The substrate 100 is, for example, a printed circuit board or a semiconductor substrate with one or more layers of circuits, or an interposer made of silicon or glass.

The retaining wall structure 200 with a slope is located on the side of the stacked chip 110, between the chip stacks 110A and close to the stacked chip 110. The retaining wall structure 200 is a triangular column structure with right-angled triangle sides and has at least one The slope surface 200S, whose slope surface 200S extends obliquely from the top layer of the stacked chip stack 110A along one side of the chip (the second direction D2) to the substrate 100, and the slope (inclination) of the slope surface is the same as that of the retaining wall structure 200 The height in the first direction D1 is divided by the length of the retaining wall structure 200 extending in the second direction D2.

Since the slope surface 200S of the retaining wall structure 200 extends from the top layer of the stacked chip stack 110A to the substrate 100, this slope surface 200S is used as a primer flow channel during primer filling and pouring, so that the primer can be filled along the slope The surface 200S flows (the flow direction of the primer is shown by the arrow). FIG. 2 shows the package structure 10 after filling the primer. The primer 130 flowing along the slope surface 200S of the retaining wall structure 200 fills the gap between the stacked chips 110 by capillary action to complete the primer filling.

Here, the retaining wall structure 200 is located on the side of the stacked chip 110 and close to the stacked chip 110. However, those skilled in the art can understand that there may be slight gaps between the retaining wall structure and the stacked chip in actual production, which is not a close fit. Or sealed state. The wall structure 200 shown in the figure is equal to the upper surface of the uppermost layer of the stacked wafer stack 110A, but its height only needs to be higher than or equal to the uppermost gap between the uppermost wafer of the stacked wafer stack 110A and the lower wafer. Yes, so the so-called "upper layer" here refers to the height range of the gap between the uppermost chip and the uppermost layer.

FIG. 3 only shows a part of the package structure 10 before the primer is filled. Although the figure only shows a chip stack 110A to facilitate the description of the retaining wall structure 200, the actual package structure 10 may include a plurality of chip stacks 110A. . The retaining wall structure 200 in FIG. 3 is a triangular column structure with triangular sides and has two slope surfaces 200S. The slope surfaces 200S extend from the uppermost layer of the stacked chip stack 110A to the substrate 100 respectively. Taking the side surface of the retaining wall structure 200 as an isosceles triangle as an example, the slope surface 200S extends diagonally from the top layer of the stacked chip stack 110A to the substrate 100 along one side of the chip (either along or against the second direction D2). The slope (inclination) is the height of the retaining wall structure 200 in the first direction D1 divided by half of the extension length of the retaining wall structure 200 in the second direction D2. When the primer is filled and poured, the two slope surfaces 200S are used as primer flow channels, so that the primer can flow along the two slope surfaces 200S during filling (the flow direction of the primer is shown by the arrow). The slope surface 200S of the retaining wall structure 200 has an included angle θ with the horizontal plane (defined as the surface 100a of the substrate 100). The included angle θ is between 0 and 90 degrees and varies according to the shape of the retaining wall structure and the height of the stacked chip stack.

FIG. 4 only shows the package structure 10 before the primer is filled, including one or more chip stacks 110A. In FIG. 4, the retaining wall structure 200 can be divided into a connected trapezoidal body part 200A and a triangular body part 200B, which are respectively close to the two sides of the chip stack 110A. The trapezoidal body part 200A is a three-dimensional structure with a trapezoidal side surface and has a slope surface 200AS, and the triangular body part 200B connected to it is a triangular column structure with a triangular side surface and has a slope surface 200BS. The slope surface 200AS extends diagonally from the top layer of the stacked wafer stack 110A along one side of the chip (second direction D2), turns, and continues to extend to the substrate 100 along the other side of the chip (third direction D3) with the slope surface 200BS. Taking the side surface of the retaining wall structure 200A/200B as a right triangle as an example, the slopes (inclinations) of the two slope surfaces 200AS and 200BS can be different or the same. When filling and pouring the primer, the two connected slope surfaces 200AS/200BS are used as primer flow channels, so that the primer can flow along the two slope surfaces 200AS/200BS when filling (the flow direction of primer is shown by the arrow).

FIG. 5 only shows the package structure 10 before the primer is filled, including one or more chip stacks 110A. In FIG. 5, the retaining wall structure 200 can be divided into an unconnected triangular body part 200A' and a triangular body part 200B', which are respectively close to the two sides of the chip stack 110A. The triangular body part 200A' is a triangular column structure with triangular sides and has a slope surface 200AS'. The slope surface 200AS' extends diagonally from the uppermost layer of the stacked chip stack 110A along one side of the chip (the second direction D2) to the substrate 100 . The triangular body part 200B' separated therefrom is another triangular column structure with triangular sides and has a slope surface 200BS'. The slope surface 200BS' extends diagonally from the middle layer of the stacked chip stack 110A to the substrate 100 along the other side of the chip (the third direction D3). The slopes (inclinations) of the two slope surfaces 200AS' and 200BS' are different. When the primer is filled and poured, one of the two slope surfaces 200AS'/200BS' can be selectively used as the primer flow channel. For example, first select the slope surface 200BS' to fill the gap between the next two layers of wafers, and the primer flows along the slope surface 200BS' during filling (the flow direction of the primer is shown by the arrow). Afterwards, the same or different primer materials can be selected, and another primer can flow along the slope surface 200AS' to fill the gap between the upper wafers.

In this way, different primer materials can be provided for different functional chips or different size chips, so as to provide better packaging functions.

In the embodiment of this case, the retaining wall structure is close to at least one side or two sides of the stacked chip stack, but of course, the retaining wall structure can also be designed to be close to the three sides or four sides of the stacked chip stack. Similarly, the retaining wall structure in the embodiment of this case is designed to have a slope surface to help fill the primer, but it is also understandable that the retaining wall structure 200 can also be designed to have a stepped ramp 200L (as shown in the figure) 6A-6B) is arranged close to the side of the stacked chip stack 110A in a similar configuration to the above-mentioned embodiment, and the same mechanism is used to help the primer filling.

The package structure or method shown in this case is particularly suitable for stacked package structures that use through silicon vias to connect chips. Because the die pitch is narrow, and the general primer filling method is difficult to fill completely, the use of the retaining wall structure of this case can help The bottom glue is completely filled, and the package structure is strengthened.

Generally speaking, the material of the primer can be a thermosetting polymer such as epoxy resin, cyanate resin and acrylic resin. The material used to form the retaining wall structure 200 in this case can be a high thixotropy (thixotropy) plastic material, such as high thixotropy epoxy resins. Generally speaking, when such epoxy resins are subjected to shearing force At this time, its viscosity can be reduced to more than 50% of the original. When the shearing force stops, the epoxy resin will immediately return to its original viscosity characteristics, so that it can be classified as a highly thixotropic epoxy resin. In this case, the viscosity range of the high-shakeability adhesive material of the retaining wall structure 200 is 100,000cps~1,300,000cps, which should be higher than the viscosity of the base colloidal material, and its range is about 5000cps~25,000cps.

Since the retaining wall structure is formed of a highly volatile plastic material, it can be formed by, for example, dispensing or molding. If it is formed by a dispensing method, a dispenser can be used for rapid mass production, which is compatible with the current manufacturing process.

If the stacked chip package structure in this case needs to be singulated or diced in the subsequent process, because the retaining wall structure is formed of a highly volatile plastic material, this retaining wall structure can also be diced without damaging the overall structure of the stacked chip stack Of course, it will not damage the package structure or chip contacts.

In this case, a high tremor denaturation colloid was used to make the retaining wall structure, and at least two different high tremor denaturation adhesives were evaluated to test the feasibility of the dispensing method to form the retaining wall structure. The results are shown in Table 1.

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<tables><img file="twi424552b_d0002.tif" he="813" id="i0002" img-content="drawing" img-format="tif" inline="yes" orientation="portrait" wi="1946" /></tables>

It turns out that the ideal shape of the retaining wall can only be obtained by selecting the appropriate diameter of the dispensing pinhole. When the diameter of the dispensing pinhole is between 0.8 and 1.6mm, the height of the retaining wall formed by it can be between 0.5 and 1.5mm. The height of the retaining wall structure formed by dispensing can be greater than 1mm, even as high as 2mm. Therefore, the retaining wall structure formed by the glue dispensing method is indeed high enough and can be stably close to the side of the wafer stack.

The above embodiments provide a package structure with stacked chips. By integrating the barrier structure into the package structure, the primer can be completely filled and the bubbles or voids remaining during the primer filling can be avoided, and the reliability of the package structure can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

<p>10Stacked chip package structure</p><p>100Substrate</p><p>110chip</p><p>110Achip stack</p><p>120 bump</p><p>130 Primer</p><p>200Retaining wall structure</p><p>200ATrapezoidal body part</p><p>200B, 200A', 200B'Triangular body part</p><p>200S, 200AS, 200BS, 200AS', 200BS'Slope surface</p><p>200LSlopes</p><p>D1First direction</p><p>D2Second direction</p><p>D3Third party</p>

FIG. 1 is a three-dimensional schematic diagram of a stacked chip package structure according to an embodiment of the present invention.

2 is a schematic side view of a stacked chip package unit structure according to an embodiment of the present invention.

3 is a partial perspective view of a stacked chip package structure according to another embodiment of the invention.

4 is a partial perspective view of a stacked chip package structure according to another embodiment of the invention.

5 is a partial perspective view of a stacked chip package structure according to another embodiment of the invention.

6A-6B are three-dimensional schematic diagrams of a retaining wall structure according to another embodiment of the present invention.