Master-slave critical conduction mode power converter

Master-slave critical conduction mode power converter

MASTER SLAVE CRITICAL CONDUCTION MODE POWER CONVERTER

[related application]

The present application is hereby incorporated by reference in its entirety by reference in its entirety in its entirety in its entirety in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire Switcher "under the right.

The present invention is generally directed to systems for supplying power to a load, and more particularly to such systems for using a plurality of power sources to produce a high output, uniform power source.

There are several issues in the construction of power switchers. These biggest problems are that it is difficult to generate noise-free output power without introducing noise into the input power. The traditional techniques that lead to this problem are well known but complex and expensive. Conventional power switchers regularly introduce various components of the input current to generate power loss. Moreover, prior art power switchers typically do not present a simple resistive load for this power input.

The power factor correction (PFC) boost switch prior art design includes two conventional methods of minimizing the chopping current problem. Figure 5 depicts a simplified diagram of a prior art power factor correction boost switcher 500. The two methods for systems like Figure 5 are discontinuous mode (DM) and continuous mode (CM).

In the switch 500, an alternating current (AC) voltage is supplied to the V._ACThe system is coupled across the input of a full wave bridge rectifier BR. A first output of the bridge rectifier BR is coupled to the first terminal of the inductor L. The second terminal of the inductor L is coupled to the drain of the transistor switch M and the anode of the diode D. The cathode of diode D is coupled to the first terminal of output capacitor C. A second output of the bridge rectifier BR is coupled to the sense resistor R_SENSEThe first terminal. Sense resistor R_SENSEThe second terminal, the source of the transistor switch M and the second terminal of the output capacitor C, are each coupled to a ground node. Is formed in the sensing resistor R_SENSEVoltage signal at the first terminal - I_SENSERepresents the boost switch 500 from the supply voltage V_ACThe current. Because signal-I_SENSEBy crossing the resistor R that is referenced to ground_SENSEThe voltage drop is formed, so it is the negative electrode. Switch control voltage signal V_SWIt is applied to the gate of the transistor switch M and controls the transistor switch M to be either conductive (switch closed) or non-conductive (switch open).

When the switch M is turned off, current flows from the bridge rectifier BR through the inductor L and the switch M. In this case, the diode D is output voltage V._OUTReverse bias. The current flowing through the inductor L stores energy as a magnetic field coupled to the inductor L. When the switch M is turned on, the stored energy is transferred to the output capacitor C by the current flowing through the diode D. In this case, the diode D is biased in the forward direction. The energy stored in the output capacitor C forms an output voltage V that can be used to drive the load, such as the second power supply stage across the capacitor C._OUT. Energy from source V_ACThe rate of transfer to capacitor C is based on the switch control signal V._SWThe work cycle depends on it.

The boost switch 500, which is depicted in FIG. 5, controls the point at which the switching of the transistor switch M occurs, so that the boosting switch 500 draws the AC supply voltage V._ACThe current is substantially the same as the supply voltage V_ACThe supplied voltage is in phase and can control the duty cycle of the transistor switch M to make the output voltage V_OUTCan be maintained at a fixed level. Voltage V_OUTAnd voltage-I_SENSEIt is monitored to control the switch.

When the boost switch 500 is operated in the continuous mode, the current flowing through the inductor L is maintained above zero. Therefore, when the switch M is turned off, the current passes through the diode D. The energy stored in the junction with the diode D produces a limited recovery time for the diode D, so that the diode D does not momentarily close. Furthermore, the energy stored in the junction with the diode D is discharged via the switch M when it is turned off. The final high level of current in switch M can result in excessive power dissipation and premature failure of switch M. Since this current high level occurs every time the switch M is cycled, the switching frequency is limited. Since the boost switch typically produces a regulated voltage of approximately 400 volts across the output capacitor C, this pair of boost switches that drive the second power supply stage are particularly true. Again, because of work Rate factor correction boost switcher 500 controls the switching occurrence time to supply voltage V_ACThe voltages and currents provided are in phase with each other, so if the switch 500 is operated in a discontinuous mode, the problem of the current being boosted in the switch M cannot be conventionally caused by causing the current in the diode D to be filled before the switch M is turned off. Zero to avoid.

When operating in the discontinuous mode, the switch 500 typically amplifies causing the current through L to drop to a minimum of zero, while simultaneously increasing the maximum current value. This discontinuous mode switch is allowed to extend the range of current values to mean that the average value of the current in L remains fixed regardless of the mode of operation. Although this current conservation causes the switch to achieve less loss switching and improve the efficiency of the discontinuous mode switch, it does not introduce chopping into the input and output currents.

Prior art systems have attempted to reduce the chopping effect by using the above design complex switcher, modifying its relative phase and combining its output power. Each switch phase is modified relative to other switches such that the switch chopping components can be deleted from each other. This device is depicted in Figure 6.

It is known to eliminate input chopping from the system to supply the load power. It is known in the art to implement input chopping current cancellation by coupling two power supplies in parallel and providing a switching frequency of the 180 degree phase difference between the two power supplies. The prior art system 20 shown in Figure 6 provides for eliminating input chopping currents in this manner. The system 20 includes a first boost type power switch 21 (a first power supply) including a pulse width modulation (PWM) controller 22, a field effect transistor power switch M1, an inductor L1, a rectifier D1 and A filter capacitor C1. The power switch 21 operates in a known manner and will not be further described herein. The power supplied to the load 26 by the first power switch 21 is regulated by the feedback network 27 and the pulse width modulation controller 22, the output of which is coupled to the gate of the field effect transistor power switch M1. The voltage divider formed by the resistors R3 and R4 of the feedback network 27 divides the output voltage of the first power switch 21 and compares the divided output voltage with the reference voltage V in the amplifier U6._REF3. The output voltage from amplifier U6 is then coupled to the control input of pulse width modulation controller 22 to adjust the ON time of power switch M1.

The system 20 further includes a second boost type power switch 23 (a second power supply) including a pulse width modulation controller 24, a field effect transistor power switch M2, an inductor L2, a rectifier D2 and a filter. Capacitor C2. Power switch 23 is in a known manner The operation is not further explained here. The power supplied to the load 26 by the second power switch 23 is regulated by the feedback network 27 and the pulse width modulation controller 24, the output of which is coupled to the gate of the field effect transistor power switch M2. The output voltage from amplifier U6 is also coupled to the control input of pulse width modulation controller 24 to adjust the ON time of power switch M2.

It is also known that the inductors L1 and L2 flowing through the power switches 21 and 23 have rectangular waveforms, respectively. The fixed frequency oscillator 25 is directly coupled to the clock input of the pulse width modulation controller 22 and the clock input of the pulse width modulation controller 24 via the returner N2, thereby providing a clock waveform of a phase difference of 180 degrees. The pulse width modulation controllers 22 and 24 are provided. As a result, the rectangular current waveforms of the inductors L1 and L2 have a phase difference of 180 degrees. Therefore, the rectangular composition of the input current is eliminated, leaving only the DC component of the input current. The circuit of Figure 6 does not address the problem of equalizing the current or power to the load 26. Furthermore, since the two power supply components are not the same, some micro phase difference is generated. A chopping current is generated that is sufficient to avoid applying this circuit to a high power device.

It is known to combine variable frequency power supplies to supply power to a load, and further use phase detection to equalize the current supplied to each load by a power source, and to eliminate the input current chopping that the system draws. Figure 7 shows a block diagram depicting a system 30 for supplying power to a load 36. System 30 includes first and second power sources 31 and 32 that are coupled together at their inputs and that supply power to the same load 36. Each of the power sources 31 and 32 is a variable frequency power source having a switching frequency and a relationship between power supplies supplied to a load. For example, each of the power sources 31 and 32 may have a relationship between its switching frequency and a power source that is supplied to one of linear or non-linear loads. At the same time, each power source can also have its switching frequency and the relationship between the DC power supplies supplied to a load, so the power supply and the switching frequency are increased or decreased in the same direction or in the opposite direction, so the power supply and the switching frequency are reversely changed. Power supplies 31 and 32 of system 30 have similar relationships between their switching frequency and the power supplies supplied to load 36. As shown in Fig. 7, the first and second power sources 31 and 32 can be coupled in parallel with each other.

Referring to Figure 7, the system further includes feedback networks 33 and 34 coupled to first and second power sources 31 and 32, respectively. The first feedback network 33 couples the output voltage of a portion of the first power source 31 to the control terminal CTRL of the first power source 31 to change the first power source 31. First switching frequency f_Sw1Thereby, the power supplied from the first power source 31 is adjusted to the load 36. Similarly, the second feedback network 34 couples the output voltage of a portion of the second power source 32 to the control terminal CTRL of the second power source 32 to change the second switching frequency f of the second power source 32._Sw2Thereby, the power supplied from the second power source 32 is adjusted to the load 36.

The phase detecting device 35 provides a first switching frequency f representing the first power source 31._Sw1And a second switching frequency f of the second power source 32_Sw2The error signal of the phase difference between the two. First switching frequency f_Sw1It is coupled from the first power source 31 and supplied to the input of the phase detecting device 35. Similarly, the second switching frequency f_Sw2It is coupled from the second power source 32 and supplied to the other input of the phase detecting device 35. The error signals provided by phase detection device 35 are coupled to feedback networks 33 and 34. The result is the first and second switching frequency f_Sw1, f_Sw2Being locked into each other.

Moreover, since the first and second power sources 31 and 32 have a similar relationship between their switching frequency and the power source supplied to the load, the power source supplied to the load 36 by the first power source 31 is substantially equal to being supplied by the second power source 32. Power to load 36. In Fig. 7, the power supply to the load 36 by the first and second power sources 31 and 32 is substantially equalized, meaning that the power supplies 31 and 32 are coupled in parallel with each other and thus apply the same voltage to the load 36, so The current supplied to the load 36 by the second power sources 31 and 32 is also substantially equalized.

The circuit of Figure 7 is designed to lock the relative phases of the two power supplies at 180 degree intervals. Unfortunately, because the duty cycle of the two power supplies is not always 50%, the phase is not always the opposite. Furthermore, the apparatus of Figure 7 loses phase lock at the regulation loop limit, which results in complete loss of input ripple current cancellation and can produce audible noise from the device.

SUMMARY OF THE INVENTION The present invention is directed to a system and method for supplying a load using a plurality of power supplies, wherein the power supplies are arranged in a master-slave configuration in which output power is modulated from a power supply characteristic to a desired characteristic.

The invention can be implemented in all critical conduction mode (CCM) switches, including buck, boost, boost-buck, and reverse in AC/DC and DC/DC power switches and in insulated and non-insulated configurations. Forward type switcher.

In some applications, it includes power supplies that are expected to be used for output power in excess of 300 watts. The Power Factor Correction (PFC) front-end is a power supply system with the following characteristics: full range of input voltage, variable frequency operation, excellent input current ripple cancellation, and minimal interference with good current sharing of the input power system. The present invention provides for the simplification and mitigation of these desired characteristics and production improvements of the system. Moreover, the present invention avoids the use of bulky and ineffective components that appear in many prior art devices, such as sensing resistors.

The present invention relates to a system and method for using a plurality of power sources to supply a coherent power supply to a load. The system and method involve touching a power source to turn off the main power source, which further involves using a phase detector to adjust the slave power off for the optimum power characteristics. In another feature, the present invention uses a local voltage controlled oscillator (VCO) when activated. In this embodiment, the main power-on is locked to the local voltage controlled oscillator. This frequency is controlled to be the same as the main power frequency. Furthermore, the local voltage controlled oscillator has a symmetrical output waveform. From the power system is activated to the local voltage controlled oscillator output falling edge, which is substantially 180 degrees out of phase with the rising edge (which is in phase with the main power supply). Therefore, the power-on is substantially 180 degrees out of phase with the main power-on. This solution minimizes input and output chopping current.

<p>A, RC input</p><p>BRBridge rectifier</p><p>C output capacitor</p><p>C1Filter Capacitor</p><p>C2Filter Capacitor</p><p>CTRL control terminal</p><p>D diode</p><p>D1Rectifier</p><p>D2Rectifier</p><p>f_Sw1First switching frequency</p><p>f_Sw2Second switching frequency</p><p>I_SENSEVoltage signal</p><p>LInductors</p><p>L1, L2 inductance</p><p>MCrystal Switch</p><p>M1, M2 field effect transistor power switch</p><p>N2 returning device</p><p>PWM pulse width modulation</p><p>R3, R4 resistors</p><p>R_SENSESensor Resistors</p><p>Q output</p><p>U6Amplifier</p><p>V_ACAC voltage supply</p><p>V_OUTThe output voltage</p><p>V_REF3reference voltage</p><p>V_SWSwitch control voltage signal</p><p>20Previous technical system for eliminating input chopping current</p><p>21First boost type power switcher</p><p>22, 24 PWM controller</p><p>23Second step-up power switcher</p><p>25Fixed Frequency Oscillator</p><p>26 load</p><p>27Responsible network</p><p>30System for supplying power to load 36</p><p>31First power supply</p><p>32second power supply</p><p>33First feedback network</p><p>34Second feedback network</p><p>35 phase detection device</p><p>36load</p><p>100System for supplying power to a load in accordance with the characteristics of the present invention</p><p>102 Input</p><p>104Combined output</p><p>110Main power supply</p><p>112, 132 power input</p><p>114, 134 Current sensing output</p><p>116, 136 power output</p><p>118, 138 Internal monostable drive</p><p>122, 142 Internal monostable delay device</p><p>124, 144 Internal monostable output</p><p>130From the power supply</p><p>131Delayed institutions</p><p>160 phase detector</p><p>180 reverser</p><p>200Power supply for mains and slaves</p><p>210Voltage input</p><p>220, 260 output of power supply 200</p><p>230Voltage output</p><p>240, 250 input of power supply 200</p><p>270, 272 inductors</p><p>274Operational Amplifier</p><p>276monostable</p><p>278Switch</p><p>280 diode</p><p>300A system of an alternative embodiment of the invention</p><p>301Enter</p><p>302 Output</p><p>310, 318, 350, 358 inductors</p><p>312, 352 diode</p><p>314, 354 switch</p><p>316, 356 monostable</p><p>320, 360Operational Amplifier</p><p>322delay device</p><p>380, 382 filter</p><p>392Adder</p><p>395Returning network</p><p>397Return signal</p><p>400System of the preferred embodiment of the invention</p><p>410Oscillator circuit</p><p>420 phase detector</p><p>430 voltage divider</p><p>440Oscillator</p><p>450 reverser</p><p>500Previous Technical Power Factor Correction Boost Switcher</p>

Figure 1 is a block diagram of a system for supplying power to a load in accordance with the characteristics of the present invention.

Figure 2 further depicts the system composition of Figure 1.

Figure 3 shows a functional diagram of an alternate embodiment of the present invention.

Figure 4 is a diagram showing the function of a preferred embodiment of the present invention.

Figure 5 shows the prior art power supply.

Figure 6 shows a prior art power supply front end using two parallel power supply power factor corrections.

Figure 7 shows a prior art power supply front end with two parallel power supply power factor corrections equalized by a phase-locked loop.

Reference will now be made in detail to the preferred embodiments embodiments While the invention has been described in connection with the embodiments, it is understood that In contrast, the present invention is intended to cover the scope of the accompanying claims. The alternatives, modifications and equivalents of the spirit and scope of the invention are defined. In the following detailed description of the invention, reference to the claims However, it should be noted that the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail and may obscure the features of the invention.

1 is a block diagram of a system 100 for supplying power to a load in accordance with the features of the present invention. The system includes two power sources, a main power source 110 and a slave power source 130. Each power supply system comprises the following components for the main power source 110 and the slave power source 130: power input 112, 132; current sense output 114, 134; power output 116, 136; internal monostable driver 118, 138; internal monostable Delay means 122, 142; and internal monostable outputs 124, 144. Main power supply 110 is coupled to power supply 130 to provide power switching at input 102 of system 100 to be supplied to power output at system 100, while providing minimum interference at input 102 and combined output 104. .

As is known in the art, in system 100, when main power source 110 and slave power source 130 are turned on, they are switched by a power supply and only supply power to their outputs 116, 136. Both power supplies are controlled by an internal monostable without a picture or an internal switch (not shown). The internal monostable drivers 118, 138 determine the switching state by supplying a supply drive actuation. When a voltage is supplied to the internal monostable drivers 118, 138, each monostable supply voltage to the internal switches and internal monostable outputs 124, 144. The voltage supplied by the internal monostable current is continued in accordance with the delay determined by the internal monostable delay devices 122,142. The relationship between the main power source 110 and the slave power source 130, the switch and the internal monostable voltage supply is such that when the monostable supply voltage or "on" is turned on, the open relationship is turned off, and the corresponding voltage supply is "off". However, the internal monostable output 124 of the main power source 110 and the internal monostable driver 138 of the slave power source 130 include an inverter 180, which means that the internal monostable from the power source 130 is driven substantially to the main power source 110. The internal monostable has a phase difference. In summary, the power supplies 110 and 130 are configured such that the received signals of the drivers 118, 138 cause the power supply to be turned off, and the voltage is supplied to the time interval determined by the delay circuit drivers 122, 142. Output 124, 144.

When the main power source 110 is in the off configuration state, the power source supplied to the input 112 is stored, and when it is in the on configuration, the power source is supplied to the output 116 and then to the combination. Output 104 and then to a load without illustration. At the same time, the signal from the combined output 104 is coupled to the internal monostable delay device 122, wherein the current system is stored to drive the delay device when monostable active. The main power source 110 is in a self-resonant configuration: when the current in the main power source 110 is zero, the signal from the current sense output 114 is transmitted to the monostable driver 118. This signal is selectively fed via the delay mechanism 131 to utilize the natural resonant delay in the current through the zero point. The monostable then supplies the voltage, turning off the main power supply 110 and simultaneously providing a voltage to the monostable output 124. The monostable state is supplied with this voltage for a time interval in accordance with the delay circuit 122. Delay circuit 122 is charged by the output power of system 100.

Signals from monostable output 124 are coupled to monostable driver 138 of slave power source 130 via inverter 180. Therefore, when the main power source 110 is switched to the off position, the slave power source 130 is then switched to the on position. The power source 130 is configured to use a feedback mechanism to adjust the time it is maintained in the open position. The power source 130 is maintained in the on position for a period of time determined by the delay circuit 142. The delay circuit 142 is charged by using the output power of the system 100, the monostable output 144, and the feedback loop of the current sensor output 142. This feedback loop is operable to cause the slave power source 130 to not shut down unless the current from the power source 130 is substantially near zero. The signal from monostable output 144 and the signal from current sensor output 142 are compared to phase detector 160. The output of phase detector 160 is added to the current proportional to the output power of system 100 and the combination is supplied to delay circuit 142. The voltage output of phase detector 160 represents the zero current offset that occurs from power supply 130 when turned off. This error signal provides a negative feedback to modulate the duty cycle from the power supply 130 such that the shutdown occurs when a substantial zero current occurs in the slave power source 130.

The main power source 110 is in a self-resonant configuration: having a switching state depending on the feedback from the combined output 104 and from its current sensor 114. The switching state from the power supply 130 is controlled by the monostable output of the main power source 110 and the feedback of the combined output 104 of the modified adjustment derived from the comparison of the current sensor 134 and the monostable output 144. In this method, the switching state from the power source 130 is reverse coupled to the state of the main power source 110, and the duty cycle from the power source 130 is optimized to match the switching state.

A power supply externally supplied via input 102 is coupled in parallel to main power source 110 via input 112 and to parallel power source 130 via input 112. When the main power source 110 is on When the position is turned on, the slave power source 130 is in the off position. A power supply coupled to input 112 and stored in main power source 110 is supplied at output 116 and then to combined output 104. At the same time, the input 132 is coupled to the slave power source 130 and stored in the slave power source 130, while no power is supplied to the output 136. When the current in the main power source 110 reaches zero, the system is coupled from the current sensor output 114 to the monostable device 118, which switches the main power source 110 to the off position, which is the time determined by the sustain delay circuit 122. length. At the same time, the signal is coupled from the monostable output 124 to the monostable device 138, which is switched from the power source 130 to the on position. The power source 130 is maintained at the open position for a length of time determined by the delay circuit 142. The delay length is modulated by the negative feedback mechanism over the complex switching cycle process, wherein the offset to the optimal delay length adjusts the power supplied to the delay length circuit 142. At the same time, the main power source 110 is maintained in the off state in accordance with the delay circuit 122. Because the delay circuits 122, 142 are powered by the same source, they can be configured to shut down from the power source 130 and then briefly turn the main power source 110 on.

2 is a functional block diagram of the main power source 110 of FIG. 1 and the power source 200 of the slave power source 130. The power supply 200 includes a voltage input 210, a voltage output 230, a monostable 276, an operational amplifier 274, a switch 278, an inductor 270, a diode 280, and an inductor 272. The voltage coupled to voltage input 210 is supplied to inductor 272, which senses the induced current in inductor 272. If switch 278 is open and the supplied current is in the correct direction, current from inductor 272 is forward biased to diode 280 and transmitted via voltage output 230. If switch 278 is turned off, the current from inductor 270 is shorted to ground and diode 280 is reverse biased.

The state of switch 278 is determined by the Q output of monostable 276. The Q output can assume two states and is preset to a state that, when monostable receives a voltage on the A input, pushes the Q output to a second state that maintains the time determined by the monostable RC input. The A input and RC input for monostable 276 are determined by inputs 240 and 250 of power supply 200, respectively. The monostable Q output is supplied as the output 260 of the power supply 200.

The induced current induced in inductor 272 is coupled to one of operational amplifiers 274, and the other input to operational amplifier 274 is grounded. Operational amplifier 274 The output is coupled to the output 220 of the power supply 200.

Figure 3 is a functional block diagram of an alternate embodiment of the present invention. The system 300 of Figure 3 operates substantially similar to the system 100 of Figure 1. System 300 is coupled to receive power at input 301 and to supply power at output 302. The power signal from input 301 is coupled to a parallel power source, one for the master and one for the slave.

The power signal is coupled to inductor 310, where it senses the induced current in inductor 318. The signal is based on one of two paths from the inductor 310 depending on the state of the switch 314: if the switch is on, the signal passes through the diode 312 and then to the output 302; if the switch is turned off, the signal will be grounded via the switch 314. The sensed signal is supplied from inductor 318 as an input to one of operational amplifiers 320. The other input of operational amplifier 320 is shorted to ground. The output of operational amplifier 320 is coupled via delay device 322 to activate input A of monostable 316.

The power signal is also coupled to the slave power source. The power signal is coupled to inductor 350, where it senses the induced current in inductor 350. The signal is based on one of two paths from inductor 350 depending on the state of switch 354: if the switch is open, the signal passes through diode 352 and then to output 302; if the switch is turned off, the signal will be grounded via switch 354. The sensed signal is supplied from inductor 358 as an input to one of operational amplifiers 360. The other input of operational amplifier 360 is coupled to ground. The output of operational amplifier 360 is coupled to a feedback network 395 that can control the slave power source. The operation of network 395 will be discussed below after a more thorough description of the monostable 316, 356 operation of the main power supply.

The monostable 316, 356 has an output Q and two inputs A and RC. The output Q can assume two states, one for stability and one for float. The switching from the steady state floating state occurs when the monostable receives the signal on the input A, and the duration in which the output Q is maintained in the floating state is determined by the input RC. When the input RC is short-circuited to ground, the state of the output Q is switched back to the steady state. In system 300, a common method of switching timing is to connect a resistor and a capacitor network to the RC input. When the output Q is in a floating state, the power stored in the capacitor is diverged across the resistor until the RC input is shorted to ground, thus determining the time during which the output Q is in a floating state.

The combined output of the master and slave supplied to output 302 is also supplied as the master and slave. Grant a signal. The feedback signal 397 passes through the filter 380 and then passes through the filter 382 and the adder 392. The output of filter 382 is coupled to the input RC of monostable 316. Therefore, the duration in the floating state is determined by filter 382 in monostable 316. Monostable 316 drives the state of switch 314 via output Q. The state of the output Q and the switch 314 are determined by the monostable 316. At the same time, the output Q system is supplied to input A of the monostable 356 from the power supply.

Due to the specifications of the switches 314, 354, the effect of coupling the output Q of the monostable 316 to the input A of the monostable 356 will result in the switch 314 being turned off and then the switch 354 being turned on. Therefore, the opening of the power source can be activated by switching the main power source. However, the actual duty cycle from the power supply and mains is not a mirror image, so the input and output ripple currents are not completely eliminated. Furthermore, the feedback mechanism that determines the switching cycle has a correction factor that can be adjusted to these duty cycles. These feedback agencies will be detailed.

The feedback network 395 from the power supply determines the input A and RC of the correct signal monostable 356 based on the output of the operational amplifier 360 and the output Q of the monostable 356. Again, network 395 controls the signal from output Q of monostable 356 to switch 354. The feedback network 395 performs two independent operations on the inputs from the operational amplifier 360 and the monostable 356, which produce two independent outputs.

To form the first output, the feedback network 395 can compare the output Q of the monostable 356 with the phase between the outputs of the operational amplifier 360. The output Q system causes the monostable 356 to implement a switching event from the power supply, and the output of the operational amplifier 360 can represent the amount of current emerging from the power supply. This phase comparison can calculate the signal representative deviation of the expected switching time from the optimum switching time from which the current in the power supply is substantially zero.

The second output is the result of the output Q of the monostable 356 and the operation of the AND gate 390 on the output of the operational amplifier 360. The operation will produce an output that does not touch the switching event unless the current from the power supply is substantially less than or equal to zero.

The first output signal of the feedback network 395 is transmitted to the adder 392 via the filter 384. Adder 392 combines this first output and feedback signal 397. The output of this adder is supplied to filter 386 and subsequently to the input RC of monostable 356.

Therefore, the output Q that switches to monostable 356 is output Q from monostable 316. It is determined that the floating state duration is determined by the signal determined by the feedback signal 397 and the first output of the feedback network 395.

The second output signal of the feedback network 395 is coupled to control the slave power switch 354. The switching state from the power supply is determined by the output Q of the monostable 356 combined with the logic and gate 390 and the output of the operational amplifier 360. Therefore, no switching event is triggered unless the current from the power supply is substantially less than or equal to zero.

The effect of the feedback network 395 provides the ability to correct the expected switching time from the power source. As mentioned above, this expected switching time is directly triggered by turning off the main power. However, lack of feedback network 395, switch 354 can be turned off from an unacceptable current level in inductor 350. This may cause damage to the switch 354. The feedback network 395 can provide two functions: first, it prevents the switch 354 from being turned off at an unacceptable current level; and second, it corrects the duty cycle from the current, causing it to occur toward its shutdown event occurring in the current from the power supply. The best time point.

Figure 4 shows a functional diagram of a system 400 in accordance with a preferred embodiment of the present invention. The system 400 is the same as the system 300 of FIG. 3, but with the oscillator circuit circuit 410 between the output Q of the monostable 316 and the input A of the monostable 356.

Oscillator circuit 410 includes a voltage controlled oscillator 440 having a 50% duty cycle to generate a touch signal that is transmitted to input A of monostable 356. The control signal coupled to the oscillator 440 is modulated such that the frequency of the oscillator 440 is substantially the same as the frequency of the output Q of the monostable 316. Moreover, when the signal from oscillator 440 is activated to exit the leading edge of the signal, it is substantially in phase with the signal of output Q of monostable 316. This signal is inverted and coupled to input A of monostable 356 such that the final output Q of monostable 356 is substantially 180 degrees out of phase with the output Q of monostable 316.

In oscillator circuit 410, the output Q of monostable 316 is coupled to phase detector 420, where it is compared to the output of voltage controlled oscillator 440. The final output of phase detector 420 is proportional to the error between the two input signals. This input is coupled to voltage divider 430 and subsequently to oscillator 440. The result is a feedback network in which the output signal of the driveable oscillator is in phase with the output Q leading edge of the monostable 316. Thus, the output of oscillator 440 is also inverted by inverter 450 and coupled to input A of monostable 356. This operation effectively activates monostable 356 at a point that is 180 degrees out of phase with the signal of output Q of monostable 316.

Due to the specifications of the switches 314, 354, a 180 degree phase difference in the signal at the output Q of the coupled monostable 316, 356 produces this effect: the switch 314 is turned off and then the switch 354 is turned on. Therefore, the opening of the power source can be activated by switching the main power source.

System 400 produces better input and output current ripple cancellation than system 300. As mentioned above, the main power supply and the slave power supply do not match. In order not to damage the circuit components, the duty cycles of the main power source and the slave power source do not have to be mirror images of each other. Therefore, the main power supply and the slave power signal cannot completely eliminate the chopping of each other.

The local oscillator 400 provides fixed corrections to the main power supply and from the power supply duty cycle, driving them toward a 50% and 180 degree phase difference. This correction is the best elimination. In contrast, system 300 does not have this correction. Thus, system 400 has enhanced chopping cancellation for system 300. The present invention has been described in terms of specific embodiments in the details of the embodiments of the invention. References to specific embodiments and details are not intended to limit the scope of the appended claims. The skilled artisan will appreciate that the embodiments selected for the description can be modified without departing from the spirit and scope of the invention.