Methods for fabricating a stressed mos device

Method for manufacturing stressed MOS device

METHODS FOR FABRICATING A STRESSED MOS DEVICE

The present invention generally relates to a method of manufacturing a stressed MOS device, and more specifically, to a method of manufacturing a stressed MOS device and maintaining the stress and stress induced increase in these devices.

Most modern integrated circuits (ICs) are implemented by using a plurality of interconnected field-effect transistors (FETs) (also known as metal oxide semiconductor field-effect transistors or MOS transistors for short). The MOS transistor includes a gate electrode as a control electrode, and a source electrode and a drain electrode that are separated so that current can flow between the source electrode and the drain electrode. The control voltage applied to the gate electrode controls the current flowing through the channel between the source and drain.

MOS transistors are a majority carrier device as opposed to bipolar transistors. The gain of MOS transistor is usually determined by transconductance (g_m) Is defined as being proportional to the mobility of the majority carrier in the transistor channel. The current carrying capacity of a MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of majority carriers (holes) in P-channel MOS transistors can be increased by applying compressive longitudinal stress to the channel. The mobility of majority carriers (electrons) in N-channel MOS transistors can be increased by applying tensile lateral stress to the channel. In silicon MOS transistors, stress inducing materials such as SiGe can be appropriately embedded in the silicon substrate of the transistor to apply these stresses to the channels of the MOS transistor. These stresses are caused by the lattice mismatch between SiGe and the main silicon material. The stress inherent in SiGe is redistributed into the adjacent area of the main substrate, that is, redistributed into the channel area of the MOS transistor. Unfortunately, one of the problems with embedded SiGe technology is the mechanical stability of the SiGe layer. At elevated temperatures, the inherent stress in the SiGe layer relaxes due to the generation of dislocation. In turn, the reduction in stress causes a reduction in the increase in stress-induced mobility, thereby deteriorating device performance.

Therefore, it is desirable to provide a method for manufacturing a stressed MOS device that prevents stress relaxation. Furthermore, from the following detailed description and the scope of the attached patent application, combined with the accompanying drawings and the above-mentioned technical fields and prior art, other desirable features and characteristics of the present invention will become clear.

The present invention provides a method of manufacturing a stressed MOS device in and on a semiconductor substrate. The method includes the following steps: forming a gate electrode covering a semiconductor substrate, and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench being formed to be aligned with the gate electrode. Selectively grow stress-inducing material in the first trench and the second trench, and implant conductivity-determining impurity ions into the stress-inducing material to form a source region in the first trench and in the second trench A drain region is formed in the trench. After the ion implantation step, a mechanical hard material layer is deposited on the stress inducing material to maintain the induced stress in the substrate.

The following detailed description is only illustrative in nature, and is not intended to limit the present invention or the application and use of the present invention. Furthermore, it is not intended to limit the present invention by any theory presented or implied in the foregoing technical field, prior art, summary of the invention, or the following detailed description.

Figures 1 to 6 show a stressed MOS device 30 and method steps for manufacturing such a MOS device according to various embodiments of the present invention. In this exemplary embodiment, the stressed MOS device 30 is exemplified by a single P-channel MOS transistor. An integrated circuit formed from a stressed MOS device such as device 30 can include a large number of these transistors, and can also include unstressed P-channel MOS transistors and stressed and unstressed N-channel MOS transistors. Crystal.

Various steps in manufacturing MOS transistors are known. Therefore, for the sake of brevity, many conventional steps will be briefly described here or omitted altogether without providing details of the known manufacturing process. Although the term "MOS device" appropriately refers to a device having a metal gate electrode and an oxide gate insulator, the term will be used throughout the text to refer to anything that is located on a gate insulator (regardless of whether it is an oxide or other insulator) The conductive gate electrode (regardless of whether it is a metal or other conductive material) semiconductor device, the gate insulator is located on the semiconductor substrate.

As shown in FIG. 1, the manufacturing of the stressed MOS device 30 according to an embodiment of the present invention begins with the provision of a semiconductor substrate 36. The semiconductor substrate is preferably a single crystal silicon substrate, where the term "silicon substrate" as used herein includes relatively pure silicon materials generally used in the semiconductor industry. Here, the semiconductor substrate 36 will alternatively be referred to as a silicon substrate or a semiconductor substrate, which is for ease of discussion and not as a limitation. The silicon substrate 36 can be a bulk silicon wafer, or a thin layer of silicon on an insulating layer (usually known as silicon-on-insulator or SOI), and the insulating layer is made of a silicon carrier Supported by the wafer, but shown here as a large silicon wafer without limitation. Preferably, the silicon wafer has a (100) or (110) orientation, and at least one of the wafers will be manufactured Part of the MOS device 30 is doped with N-type impurity dopants (for example, N well). The N well can be doped to an appropriate conductivity, for example by ion implantation. A shallow trench isolation is formed. (STI) (not shown) in the semiconductor substrate to electrically isolate individual devices as required by the circuit function performed. As is known, there are many methods for forming STI, so it is not necessary to describe in detail here This method. Generally speaking, STI involves etching a shallow trench into the surface of a semiconductor substrate, and then filling the shallow trench with an insulating material. After the shallow trench is filled with an insulating material, the surface is usually planarized, for example, By chemical mechanical planarization (CMP).

The gate insulator layer 60 is formed on the surface of the silicon substrate 36. The gate insulator may be thermally grown silicon dioxide formed by heating a silicon substrate in an oxidizing environment, or may be a deposited insulator such as silicon oxide, silicon nitride, high dielectric constant insulators such as HfSiO, and the like. The deposited insulator can be deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The gate insulator material is typically 1 to 10 nanometers (nm) thick. According to an embodiment of the present invention, a polysilicon layer 62 is deposited on the gate insulator layer. The polysilicon layer is preferably deposited as undoped polysilicon, and subsequently doped with impurities by ion implantation. For example, a hard mask material layer 64 of silicon oxide, silicon nitride, or silicon oxynitride can be deposited on the surface of polysilicon. Polysilicon materials can be deposited to a thickness of about 100 nm by LPCVD of hydrogen-reducing silane. The hard mask material can also be deposited to a thickness of about 50 nm by LPCVD.

The hard mask layer 64 and the underlying polysilicon layer 62 are patterned by photolithography to form a P-channel MOS transistor gate electrode 66, as shown in FIG. The gate electrode 66 covers the portion of the semiconductor substrate 36 that will form the channel 68 of the P-channel MOS transistor 30. Can be used for example in Cl or HBr/O₂Plasma etching in chemistry is used to etch polysilicon in a desired pattern, and it can be used for example in CHF₃, CHF₄, Or SF₆In chemistry, plasma etching is used to etch hard masks. According to an embodiment of the present invention, after the gate electrode is patterned, a thin layer of silicon oxide 70 is thermally grown on the opposite sidewall 72 of the gate electrode 66 by heating the polysilicon in an oxidizing environment. The layer 70 can be grown to a thickness of about 2 to 5 nm. The gate electrode 66 and the layer 70 can be used as ion implantation masks to form the source and drain extension regions of the MOS transistor (not shown). The conditions and methods that may be required to form multiple source and drain regions are known, but are not closely related to the present invention, and therefore need not be described here.

According to an embodiment of the present invention, as shown in FIG. 3, the sidewall spacers 80 are formed on the opposite sidewalls 72 of the gate electrode 66. The sidewall spacer can be formed by depositing a layer of spacer material such as silicon nitride, silicon oxide, etc. on the gate electrode, and then etching the layer anisotropically by, for example, reactive ion etching. The sidewall spacer 80, the gate electrode 66, and the hard mask on top of the gate electrode are used as an etching mask to be etched in the silicon substrate separated by the P-channel gate electrode 66 and self-aligned to the P-channel gate electrode The grooves 82 and 84 of 66. The grooves intersect at the end of the channel 68. These grooves can be used, for example, by Cl or HBr/O₂Chemical plasma etching to etch. Preferably, each groove has a depth of about 0.04 to 0.2 μm.

As illustrated in Figure 4, the trench is filled with a layer 90 of stress-inducing material. The stress-inducing material can be any single crystal material that can be grown on a silicon substrate having a lattice constant different from that of silicon. The difference in the lattice constants of the two juxtaposed materials generates stress at the interface between the two materials, and the stress is redistributed in the main material. Preferably, the stress-inducing material causes the silicon host to elastically deform, so that the silicon is stressed, but it maintains a perfect crystal without defects. Defects can cause a reduction or slowdown in stress. The stress-inducing material can be, for example, a single crystal silicon germanium (SiGe) having approximately 10 to 25 atomic percent of germanium, or a substitution of carbon containing approximately 1 to 4 atomic percent and preferably less than about 2 atomic percent. Of carbon single crystal silicon. Preferably, the stress-inducing material is epitaxially grown by a selective growth process. The method of epitaxially growing these materials on a silicon body in a selective manner is known and need not be explained here. For example, in the case of SiGe, SiGe has a larger lattice constant than that of silicon, and this situation causes a compressive longitudinal stress in the transistor channel 68. The compressed longitudinal stress increases the mobility of the holes in the channel 68, thereby enhancing the performance of the P-channel MOS transistor.

After the stress-inducing material is grown in the trenches 82 and 84, P-type conductivity determining ions are then implanted in the stress-inducing material (as indicated by the arrow 86) to form the source region 92 of the P-channel MOS transistor 30 And drain area 94, as shown in Figure 5. To become electrically active, the implanted ions must be annealed, and this annealing is usually performed immediately after the implantation is completed. However, the increased temperature causes inherent stress relaxation in SiGe or other stress-inducing materials, which is due to the relationship between the dislocation of nucleates on the surface and the generation of steps on the surface of SiGe.

According to the embodiment of the present invention, as shown in FIG. 6, the relaxation of the stress in the channel 68 is prevented by depositing a layer 96 with high mechanical strength on the surface of the stress inducing material. The high mechanical strength layer delays step formation and prevents dislocations from accumulating and spreading on the surface of the stress-inducing material. Lay a layer of high mechanical strength before annealing or any other high temperature steps of ion implantation. After layer 96 is laid, the device can withstand high temperatures and will maintain stress. The layer 96 may be capable of being deposited at a relatively low temperature and having a Young's modulus (Young's modulus) greater than, preferably much greater than the Young's modulus of the stress-inducing material. For example, it is used for SiGe with a Young's coefficient of approximately 150 GPa, silicon nitride (Young's coefficient of approximately 350 GPa), silicon carbide (Young's coefficient between approximately 400 and 750 GPa), and diamond-like carbon ( The Young's coefficient is as high as 800 GPa) is a suitable material for layer 96. As used herein, low temperature refers to any temperature below about 600°C, and high temperature refers to any temperature above about 900°C. The layer 96 can be deposited by CVD, LPCVD, or PECVD. For example, a silicon nitride layer can be deposited by PECVD at a temperature of about 450°C by a plasma-enhanced reaction of dichlorosilane and ammonia. In a similar situation, you can use vapor-phase SiCl₄And methane at 550°C to deposit silicon carbide, and can use Ar, H₂, SiH₄And C₂H₂The mixed gas is deposited at 200°C to deposit PECVD diamond-like carbon. According to an alternative embodiment of the present invention (not shown), it may be advantageous to first provide a pad oxide layer having a thickness of, for example, 2 to 5 nm under the layer 96 of high mechanical strength. The pad oxide layer is used to prevent, for example, any reaction between silicon nitride and the underlying semiconductor material.

Known steps (not shown) can be used, such as depositing a layer of dielectric material on the layer 96, etching openings through the dielectric material and layer 96 to expose portions of the source and drain regions, and A metallization extending through the opening to make electrical contact with the source and drain regions is formed to complete the stressed MOS device 30. Further layers of interlayer dielectric materials, additional interconnect metallization layers, etc. can also be applied and patterned to achieve proper circuit functions of the implemented integrated circuit.

Although at least one implementation example has been presented in the above detailed description of the present invention, it should be understood that there are many variations. It should also be understood that the implementation examples or implementation examples are used as examples only, and are not intended to limit the scope, application, or configuration of the present invention in any manner. To be precise, the above detailed description will provide a convenient way for those who are familiar with the technology to implement the implementation example or implementation examples. It should be understood that various changes can be made in the configuration of functions and elements without departing from the scope of the present invention proposed in the appended patent application and its legal equivalent scope.

<p>30. . . MOS device</p><p>36. . . Semiconductor substrate, silicon substrate</p><p>60. . . Gate insulator layer</p><p>62. . . Polysilicon layer</p><p>64. . . Hard mask layer, hard mask material layer</p><p>66. . . Gate electrode</p><p>68. . . aisle</p><p>70. . . Silicon oxide thin layer</p><p>72. . . Sidewall</p><p>80. . . Sidewall spacer</p><p>82, 84. . . Groove</p><p>86. . . Arrow</p><p>90. . . Stress-inducing material layer</p><p>92. . . Source region</p><p>94. . . Drain region</p><p>96. . . High mechanical strength layer</p>

The present invention is described above in conjunction with the following drawings, in which similar component symbols indicate similar components, and among them: Figures 1 to 6 schematically show cross-sections of stressed MOS devices and their manufacturing methods according to various embodiments of the present invention picture.