Virtual time apparatus used in time evaluation on virtual platform and its method

Virtual time device and method for time evaluation on virtual platform

The present invention relates to a virtual time device and method thereof, in particular to a virtual time device and method that analyzes the instruction stream executed on a virtual platform based on a mathematical model and a simulator, and then estimates the virtual execution time of the executed instruction stream.

In terms of hardware platform design and optimization, performance analysis tools play a very important role. In recent years, virtual platforms have provided a working environment for software designers by simulating hardware functions. In the early stage, the software designed by it can be operated and evaluated on the expected hardware platform. Among them, high-speed functional simulator based virtual platforms, such as QEMU, are widely used in software development without the need for hardware. However, because QEMU lacks a timing device on the virtual platform, it is The accuracy of the performance evaluation of the software to be developed cannot be improved, which in turn makes it difficult for software designers to develop real-time application software and to evaluate the overall system performance. The conventional performance analysis tool uses an instruction set architecture simulator or an electronic system-level simulation tool with high accuracy but relatively slow processing speed. simulation tool) to evaluate the performance of a single application software, but the above method only focuses on the simulation of the hardware, and there is no way to further analyze the performance of the application software, so when using this method to evaluate the software performance, only provide The overall performance data of the software when it is running, and it is not possible to profile a specific program alone. In addition, the conventional performance analysis tools are only suitable for simplified embedded operating systems, which also limit the application scope of the developed software and hardware.

In view of the problems caused by conventional performance analysis tools for software performance evaluation and software behavior analysis on the virtual platform, the inventors actively proceeded to develop in order to improve the above-mentioned existing shortcomings. After continuous testing and hard work, finally The invention was developed. The main purpose of the present invention is to provide a virtual time device for time evaluation on a virtual platform, which is operated on a virtual platform that simulates a target hardware platform on an operating platform, which is used on the virtual platform The virtual time device for time evaluation includes a front-end analysis module, a time estimation module, a counter module and a time interpreter. The front-end analysis module is used to analyze the instruction stream executed on the virtual platform. The time estimation module has at least one time model and is connected to the front-end analysis module. The time estimation module calculates the virtual execution time of the instruction stream according to the corresponding time model. The counter module is connected to the front-end analysis module, and is used to record the virtual execution time, the number of virtual cycles, various performance-influencing events and performance-related information on the virtual platform. The time interpreter is respectively connected to the time estimation module and the counter module to manage the flow of instructions executed on the virtual platform and receive information from the time estimation module , And use the information to update the virtual execution time, the number of virtual cycles, various performance-influencing events, and performance-related information stored in the counter module. Another object of the present invention is to provide a method for time evaluation on a virtual platform, which is applied to a virtual platform that simulates a target hardware platform on an operating platform. The method includes: Step A: Obtain performance-related information of a command stream executed on a virtual platform; step B: use the performance-related information to calculate the virtual execution time of the command stream; and step C: store the virtual execution time and the performance-related information. With the above structure and method, the virtual execution time of the instruction stream executed on the virtual platform can be calculated, and then the calculated virtual execution time can be used as a timestamp to mark the virtual execution of events that occur on the virtual platform Time, and used to analyze the behavior of the software and hardware interaction in the system.

<p>(1)Virtual time device for time evaluation on virtual platform</p><p>(10)Front-end analysis module</p><p>(11)Mathematical model</p><p>(111)The first mathematical model</p><p>(112)The second mathematical model</p><p>(12)Simulator</p><p>(121)Pipeline Simulator</p><p>(122)Cache Simulator</p><p>(123)Dynamic Random Access Memory Simulator</p><p>(124)Disk Simulator</p><p>(20)Time Estimation Module</p><p>(200)Time Model</p><p>(201)First Time Model</p><p>(202)Second Time Model</p><p>(203)The Third Time Model</p><p>(204)Fourth Time Model</p><p>(30)Counter Module</p><p>(31)Virtual Time Tag Counter</p><p>(32)Event counter</p><p>(40)Time Interpreter</p><p>(601)Step A</p><p>(602)Step B</p><p>(603)Step C</p><p>(604)Step D</p><p>(605)Step E</p>

The first figure is a diagram of the device architecture of the present invention. The second figure is a detailed structure diagram of the device of the present invention. The third figure is a flow chart of the method of the present invention. The fourth figure is a detailed method flowchart of the present invention.

In order to enable those skilled in the art to understand the purpose of the present invention, the preferred embodiments of the present invention are described in detail as follows in conjunction with the drawings. Please refer to Figures 1 and 2. The virtual time device (1) for time evaluation on a virtual platform of the present invention is operated on a virtual platform (not shown in the figure), and the virtual platform is an operating platform (Figure (Not shown) on a target hardware platform (not shown in the figure). The virtual time device (1) used for time evaluation on a virtual platform of the present invention includes: a front-end analysis module (10), a time estimation module (20), a meter Counter module (30) and a time interpreter (40). The front-end analysis module (10) includes at least one mathematical model (11) and/or at least one simulator (12) for simulating the operation of the target hardware platform to analyze the instruction flow executed on the virtual platform. The time estimation module (20) has at least one time model (200) and is connected to the front-end analysis module (10), and the time estimation module (20) calculates the instruction stream according to the corresponding time model Virtual execution time. The counter module (30) is connected to the front-end analysis module (10), and is used to record the virtual execution time, the number of virtual cycles, various performance-influencing events and performance-related information on the virtual platform. The time interpreter (40) is respectively connected to the time estimation module (20) and the counter module (30) to manage the instruction flow executed on the virtual platform and receive from the time estimation module ( 20) The information sent, and the virtual execution time, the number of virtual cycles, various events affecting performance and performance-related information stored in the counter module (30) are updated with the information. Among them, the mathematical model (11) receives measurement information (such as instruction counts of different types of instructions) obtained from the specifications of the virtual platform, the operating platform, or the target hardware platform and the estimated event. of instructions), user instruction counts (user instruction counts) and clock cycle time length), the mathematical model (11) can be a linear mathematical model or a nonlinear mathematical model. In this embodiment, the mathematical model (11) includes a first mathematical model (111) and a second mathematical model (112). In this embodiment, the at least one simulator (12) includes a pipeline simulator (121), a cache simulation Device (122), a dynamic random access memory simulator (123) and a disk simulator (124). The pipeline simulator (121) is used to simulate the pipeline execution of the CPU of the target hardware platform; the cache simulator (122) is used to simulate the CPU of the target hardware platform The cache memory (cache memory); the dynamic random access memory simulator (123) is used to simulate the dynamic random access memory (Dynamic Random Access memory) of the target hardware platform Memory, DRAM); The disk simulator (124) is used to simulate the disk of the target hardware platform. The time model (200) is connected to the mathematical model (11), or the time model (200) is connected to the simulator (12), or the time model (200) is connected to the mathematical model (11) and the simulationDevice(12) Link. In this embodiment, the time model (200) may include a first time model (201), a second time model (202), a third time model (203), and a fourth time model (204). Wherein, the first time model (201) is connected with the first mathematical model (111), and the virtual execution time is calculated according to the analysis result of the first mathematical model (111); the second time model (202) Is connected with the pipeline simulator (121), and the virtual execution time is calculated according to the simulation result of the pipeline simulator (121); the third time model (203) is connected with the second mathematical model (112) and the The cache simulator (122) is connected, and the virtual execution time is calculated according to the analysis result of the second mathematical model (112) and the cache simulator (122); the fourth time model (204) is related to the first Two mathematical model (112), the pipeline simulator (121), the cache simulator ( 122), the dynamic random access memory simulator (123) and the disk simulator (124) are connected, and according to the second mathematical model (112), the pipeline simulator (121), the cache simulator (122), the dynamic random access memory simulator (123) and the disk simulator (124) analyze the results to calculate the virtual execution time, analyze the memory read mode and recognition speed of the target hardware platform Take the number of errors. In this embodiment, the first mathematical model (111) used by the first time model (201) is based on a linear mathematical model, and individual commands are obtained according to a catalog from the specification data sheet of the target hardware platform The number of clock cycles (C_C) (cycle counts of each instruction) and the length of the clock cycle time, the number of clock cycles (C_C) Calculate the virtual execution time. The second time model (202) analyzes and estimates the virtual execution time by simulating the central processing unit pipeline. The second mathematical model (112) connected to the third time model (203) and the fourth time model (204) is based on the method of linear regression model, based on the results obtained on the virtual platform and the target hardware platform The measurement information of the event is used to construct a linear regression model. For example, the second mathematical model (112) used by the third time model (203) obtains the cycle counts of each program and the length of the clock cycle time from the target hardware platform . The number of clock cycles is regarded as a dependent variable (Y) and the number of user instructions (user instruction counts) is regarded as an independent variable (N_i) (independent variables), and then analyze the relationship between the number of clock cycles and the number of user instructions to construct a linear regression model, the clock cycle Number (Y) and user command number (N_i) Can be expressed by the following formula :<img file="TWI411925B_D0001.tif" wi="403" he="215" img-format="tif" img-content="character" orientation="portrait" inline="no" />Among them, Y is the number of clock cycles, i is the type of instruction, Ni is the number of instructions in the i-th instruction category, and P_iIs a linear regression model to describe Y and N_iThe parameters of the mappings. The cache simulator (122) in the third time model (203) obtains the number of cache misses and the number of cache accesses to provide the second The additional independent variable of the mathematical model (112): the number of cache misses (C_M) And the number of cache accesses (C_A) To describe the relationship between the number of clock cycles and the number of user commands, the number of cache errors, and the number of cache accesses, thereby improving the accuracy of the virtual execution time. The third time model can be expressed by the following formula:<img file="TWI411925B_D0002.tif" wi="1104" he="259" img-format="tif" img-content="character" orientation="portrait" inline="no" />Where P_iWith P_C1With P_C2It is a linear regression model to describe Y and N separately_iWith C_MWith C_AThe parameters of mappings. The third time model (203) is based on the independent variable (N_i) (Such as the number of user commands) and the number of cache errors (C_M) And the number of cache accesses (C_A) Is input to the linear regression model to predict the dependent variable (Y) (the number of clock cycles), and then the dependent variable Y is multiplied by the length of the clock cycle to calculate the virtual execution time of the program. The fourth time model (204) has the same principle as the third time model (203), but the fourth time model (204) uses the additional pipeline simulator (121) and the dynamic random access memory simulator (123) And the disk emulator (124) To obtain the performance information of the memory system and the disk system. Although the first time model (201), the third time model (203), and the fourth time model (204) all use the linear mathematical model as the basis to calculate the virtual execution time, but in the first time model The first mathematical model (111) of (201), the relationship between the number of clock cycles and the number of user commands is derived from the number of clock cycles of each command in the specification data of the target hardware platform (C_C); and the parameters of the second mathematical model (112) used in the third time model (203) and the fourth time model (204) are obtained by linear regression. Generally speaking, the first time model (201) has the fastest execution speed, but its accuracy is poorer than other time models, and is suitable for simple programs that are executed on target hardware platforms that are not equipped with cache memory; The second time model (202) is the same as the first time model (201). It is suitable for target hardware platforms that are not equipped with cache memory, but because it simulates the pipeline execution of the central processing unit, its accuracy is relatively high. High, but slower; both the third time model (203) and the fourth time model (204) are suitable for system-level performance evaluation under the condition that the target hardware platform includes an operating system. However, since the third time model (203) only simulates the operation of the cache memory, the time information provided is not as accurate as that of the fourth time model (204), but its execution speed is compared with that of the fourth time model (204). 204). On the other hand, the fourth time model (204) simulates the operation of external memory and disk, so it can more accurately simulate diversified programs (such as file access programs). Furthermore, for the same program to perform performance evaluation on the same target hardware platform, the first, second, third, and fourth time models (201, 202, 203, 204) In descending order of accuracy, the first time model (201), the second time model (202), the third time model (203), and the fourth time model (204), and the second time model (204) The time model (202) and the third time model (203) should be of the same level, depending on the type of program, there will be different results. In addition, the execution speeds of the first, second, third, and fourth time models (201, 202, 203, 204) in descending order are: the first time model (201), the third time model (203), the second time model (202), and the fourth time model (204). The counter module (30) further includes a virtual time stamp counter (31) and an event counter (32), wherein the virtual time stamp counter (31) is used to record the number of virtual cycles on the virtual platform; the The event counter (32) is used to record various events that affect performance, such as the number of load instructions, the number of stored instructions, and/or the number of arithmetic instructions; the event counter (32) is also used to record performance-related information, such as virtual execution Time, the number of memory accesses and the number of recorded activities in the Translation Lookaside Buffer (Translation Lookaside Buffer) activities) and/or the number of memory accesses and recorded activities of components such as main memory. The counter module (30) can also transmit the number of virtual cycles, various performance-influencing events, and performance-related information to external application software and performance analysis tools for further analysis and application by users. In addition, the virtual time device (1) for time evaluation on a virtual platform of the present invention further includes a user interface (not shown in the figure), on the one hand, it is used to allow the user to determine the time estimation module (20) The time model (200), on the other hand, allows the user to determine the corresponding mathematical model (200) in the time model (200) 11) and/or simulator (12). Therefore, the user can adjust the execution speed and accuracy of the virtual time device (1) used for time evaluation on the virtual platform of the present invention according to actual needs. Furthermore, the user can also select the target hardware platform for evaluation. , And then understand the performance data of the program on various target hardware platforms (such as the virtual execution time of the program) and analyze the interaction between the system behavior and the software and hardware. Please refer to the first and third figures. The method for time evaluation on a virtual platform of the present invention is applied to a virtual platform (not shown in the figure), and the virtual platform is on an operating platform (not shown in the figure) To simulate a target hardware platform (not shown in the figure), the method includes: Step A (601): Obtain performance-related information of the instruction stream executed on the virtual platform; this step uses the time used on the virtual platform of the present invention The front-end analysis module (10) of the evaluated virtual time device (1) analyzes the instruction stream executed on the virtual platform, and obtains the performance-related information of the instruction. The performance-related information includes all the performance information that can be used to evaluate a system , Such as the number of clock cycles, the number of user commands and the length of the clock cycle time; Step B (602): Use the performance-related information to calculate the virtual execution time of the instruction stream; this step is used in the virtual platform of the present invention The time estimation module (20) of the virtual time device (1) of the upper time evaluation calculates the virtual execution time of the executed instruction based on the performance-related information; and step C (603): store the virtual execution time and The performance-related information; this step uses the counter module (30) of the virtual time device (1) of the present invention for time evaluation on a virtual platform to store the calculated virtual execution time and the obtained performance-related information. Please refer to the first, second and fourth figures. The method of the present invention for time evaluation on a virtual platform further includes: Step D (604): It is executed at step Before step A (601), decide whether to simulate part or all of the components of the target hardware platform, and determine whether step A (601) should obtain the performance related from the virtual platform, the operating platform, or the target hardware platform Information; this step is that the user uses the user interface of the virtual time device (1) for time evaluation on a virtual platform of the present invention to determine the time model (200) of the time estimation module (20), and determine the time Mathematical model (11) and/or simulator (12) corresponding to model (200); and step E (605): is executed after step C (603) to transmit virtual execution time and performance related information to an external Application software or a performance analysis tool; this step uses the counter module (30) of the virtual time device (1) for time evaluation on a virtual platform of the present invention to transmit the virtual execution time and the performance-related information to the external Application software and the performance analysis tool are available for users to make further analysis and applications. Obviously, according to the description in the above embodiment, the present invention may have many modifications and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can also be widely implemented in other embodiments. The above are only preferred embodiments of the present invention, and are not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications completed without departing from the spirit of the present invention should be included in the following patent applications Within range.