Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Supports time-based multiplex error correction coding for memory change burst operations and memory components

Invention field

The present invention generally relates to digital memory systems, components, and methods, and more particularly relates to memory system components that can multiplex error correction encoding data during burst memory transactions.

Background of the invention

Digital processors such as microprocessors use computer memory subsystems to store data and processor instructions. Some processors communicate directly with memory, while others use dedicated controller chips and often form part of a "chipset" to access memory.

Conventional computer memory subsystems are often implemented using memory modules. Referring to the computer system 100 shown in FIG. 1, the processor 120 crosses the front bus 125 to communicate with the memory controller/hub (MCH) 130, and the memory controller/hub 130 couples the processor 120 to each peripheral Device. One of the peripheral devices is the system memory, shown as the memory module MM0. Although memory does not need to be arranged on such a module in each system, multiple modules are used in multiple systems to allow modules to be replaced with larger capacity modules and/or additional memory card slots can be added Module (not shown in the figure) to allow memory expansion. When connected, the memory module MM0 can be addressed from the MCH 130 whenever the MCH 130 announces an appropriate signal on the address/command (ADD/CMD) bus 150. The data transmission between the MCH 130 and one of the memory modules takes place on the data bus 140.

Typically, a memory module is built using a plurality of semiconductor memory elements, and individual elements store part of each data word stored on the module. For example, the memory module MM0 displays 5 dynamic random access memory (DRAM) components, namely DRAM0 to DRAM4. Each DRAM element receives the same address and command signal from the ADD/CMD bus 150. Each DRAM component is connected to the signal (DQ<i>n</i>) A subset of lines, DRAM0 is connected to the 16th bus line DQ0-DQ15, DRAM1 is connected to DQ16-DQ31, DRAM2 is connected to DQ32-DQ47, DRAM3 is connected to DQ48-DQ63, and DRAM4 is connected to DQ64-DQ71. So during the data cycle, when 72-bit data is transmitted across the data bus 140, each DRAM is responsible for 16 bits, except for DRAM4, which is responsible for 8 bits (typically, the other 8DQ of DRAM4).<i>n</i>The input is simply unconnected, so half of the DRAM4 cannot be accessed). Each DRAM stores the allocated 72-bit word portion in the same chip location where each other DRAM stores its 72-bit word portion.

In the example in Figure 1, the size of each addressable data word is 72 bits. 64 bits are used to store data. The extra eight bits are used to store the ECC information corresponding to the 64-bit data with the same address. For example, DRAM4 can be dedicated to ECC storage, and DQ64-DQ71 are used to store and retrieve ECC information. Other systems can use other bus widths, and 36 bits are common. The bus is divided into 32 data bit channels and 4 ECC bit channels.

Multiple current memory devices and controllers provide a burst mode, which allows access to multiple sequentially stored data words with a single command. Figure 2 shows a timing diagram of 16-word burst mode data transmission using the ECC memory module MM0 of Figure 1. The MCH 130 supplies the module MM0 with the starting address, and the burst mode 16 read or write commands. When the command is a read command, the DRAM on the module MM0 reads the data storage cell connected to the word line containing the start address, and then drives the data from the start address and the data in 16 consecutive data cycles Data of 15 subsequent consecutive addresses on bus 140. The MCH 130 supplies write data through 16 continuous data cycles, receives, buffers, and writes to the continuous memory location on the word line (starting from the starting address) on the DRAM on the module MM0.

The function of DRAM4 is similar to all other DRAMs during these burst commands. DRAM4 does not need to know that its data may be used to perform the ECC function on the data stored on DRAM0 to DRAM3. For example, during the time slot T0, the data "A" and the ECC data "A" are transmitted, where "A" represents the data at the start address specified in the MCH 130. During the time slot T1, the data "B" and the ECC data "B" are transmitted, where "B" means the data of consecutive addresses after the "A" address.

Not all systems use the protection described in the previous section. The reason is that ECC protection requires a wider data bus. Usually, each memory bank requires additional memory chips (for example, DRAM4 and DQ64-DQ71 are not 64-bit non-ECC systems). Required). In addition, ECC can usually increase latency (due to the error checking function) and increase power consumption (due to the need for additional chips). As for the other aspects of the non-ECC system, it is the same as the previous description. For example, the memory controller must trust the data received from DRAM0-DRAM3 in the read operation to be intact. In this way, ECC memory modules and non-ECC memory modules are not interchangeable. Currently, there are more non-ECC systems manufactured than ECC systems, mainly due to the shortcomings listed above.

The present invention is a memory device, including: a memory cell array of one of a plurality of addressable segments configured to store data in a plurality of memory cells, each addressable segment is associated with at least one additional memory Somatic cell, when the associated addressable segment is read in at least one burst read mode, the additional memory cell is read from the memory cell array; and a burst control A device for controlling the burst sequence of the output data read from the first segment of the mountain among the addressable segments of the memory cells in a first burst read mode, the first burst The reading mode includes outputting data from the first segment through a first plurality of data periods, wherein during at least one of the first plurality of data periods, the data from the at least one associated with the first segment The data of an extra memory cell will be output.

Schematic description

The embodiment will be clearest by studying the following description with reference to the drawings. With the drawings: Figure 1 shows the processor and some memory system components of the prior art computer system; Figure 2 shows the data bus on the data bus in Figure 1 Timing diagram of data transmission in sending mode; Figure 3 contains a block diagram of the processor and several memory system components of the computer system according to an embodiment of the present invention; Figures 4A, 4B, 5, 6A, 6B, and 6C show that according to the present invention Several embodiments of the invention, a timing diagram of error-corrected burst mode data transmission; and Figure 7 contains a block diagram of a DRAM device according to an embodiment of the invention.

Detailed description of the preferred embodiment

This article describes a novel approach to provide ECC memory system components. This approach can avoid the need for dedicated ECC memory components and dedicated ECC bit channels, and allows interchangeability between ECC modules and non-ECC modules in at least some embodiments. Instead of dedicated ECC components and dedicated bit channels, the embodiment described in this article multiplexes ECC data and system data in time during burst mode transmission across data bit channels, and the memory controller and memory components are responsible for scheduling Ways to handle mixed data/ECC burst transmission. In some embodiments, the memory device is designed with ECC burst transmission mode and non-ECC burst transmission mode, allowing each mode to be used interchangeably in ECC systems and non-ECC systems, or even relying on ECC to protect certain critical data. Used interchangeably in systems that do not protect other data. The preferred embodiment uses a memory structure in which the ECC data does not occupy directly addressable memory space, but is stored in an internal addressable memory area associated with the addressable memory space.

As for the introduction of the embodiments, FIG. 3 shows the computer system 300 coupled with the processor 320 to the memory controller 330. The processor 320 and the memory controller 330 may be integrated on a single circuit, or may reside on a separate circuit connected by the front bus in a manner similar to that described in FIG. 1. The memory controller 330 is connected to the dual-mode memory module BMM0 through the address/command bus 350 and the data bus 340. The data bus 340 is shown as having 64-bit lines DQ0-DQ63, but this is merely an example, and other embodiments may use, for example, 16, 32, or 128 data bus line channels. The dual-mode memory module BMM0 contains four error-corrected mode (ECB) DRAMs, namely ECB-DRAM0, ECB-DRAM1, ECB-DRAM2, and CB-DRAM3, which will be further developed in the memory device embodiment of the present invention. The detailed description is as follows. In the system embodiment using the error-corrected burst mode, the memory controller 330 is designed to receive and transmit error-corrected burst mode data. However, in some system embodiments that only use the non-ECC burst mode of the prior art, the module BMM0 can be coupled to the prior art non-ECC memory controller.

The system-level functions of the memory controller 330 and ECB DRAM will be made clearer by examining the timing diagram of the error-corrected burst mode data transmission across the data bus 340. First, referring to Figures 4A and 4B, the 18 data periods T0-T17 of the "error-corrected burst mode 18A" are shown. In this example, these 18 data cycles are transmitted with the same 16 72-bit data words A to P transmitted by the prior art computer system 100 in Figure 2. Obviously, Figure 4 uses 64-bit channels and 18 data cycles for transmission instead of 72-bit channels and 16 data cycles as in the prior art. In addition, the ECC code of the data word is not transmitted at the same time as the data word, and the time configuration of the data is modified from Figure 2.

The order of reading data and writing data by BMM0 will be considered. First, check the data reading cycle T0 in Figure 4A. It can be seen that only ECC data is transmitted during T0. During the data period T0, ECC data A and C are transmitted from ECB-DRAM0. This ECC data corresponds to data A and data C respectively. Data A will be transmitted through all ECB-DRAM0 during data period T2, and data C All ECB DRAM will be used for data transfer during the data period T4. In addition, during the data period T0, ECC data E and G are transmitted through ECB-DRAM1. This ECC data corresponds to data E and data G respectively. Data E will be transmitted through all ECB DRAMs during data period T6. G will be transmitted by all ECB DRAMs during the data period T8. Similarly, during T0, ECB-DRAM2 and ECB-DRAM3 transmit ECC data I, K, M, and O. These ECC data are respectively the data transmitted by all ECB DRAMs during data periods T10, T12, T14, and T16. corresponding.

Secondly, check the data period T1, and it can be seen that only ECC data is transmitted during T1. The transmitted ECC data corresponds to the data to be transmitted during the rest of the odd data period such as T3, T5, T7, T9, T11, T13, T15, and T17.

When the memory controller 330 receives ECC data during T0 and T1, the memory controller 330 transmits the data to the ECC register bank 335 containing 16 8-bit ECC registers. In this way, when data is received by the memory controller 330 at T2, the ECC data "A" is retrieved from its register in the bank 335 and used to perform error correction on the data A. When the data is received by the memory controller 330 at T3, the ECC data "B" is retrieved from its register in the bank 335 and used to perform error correction on the data B. This process continues through the data cycle T17, at which time the ECC data "P" is read from the last ECC register and used to perform error correction on the data P. The error-corrected data words A to P are sent to the processor 320 via the memory controller 330, or sent to a number of other peripheral devices that request data with direct memory access (DMA) commands.

It is now known that if error correction is not required for data words A to P, the same data transmission in Figure 4 can be used, but without the first two data cycles.

For writing data into BMM0, the data cycle structure shown in Figure 4B is used in one embodiment. During the data period T0 to T15, the data words A to P are respectively transmitted to all ECB DRAMs. When the memory controller 330 prepares each data word for transmission, the memory controller 330 calculates the corresponding ECC data and stores the ECC data in one of the 16 ECC registers of the aforementioned bank 335. Then, during the data period T16, the ECC data A, C, E, G, I, K, M, and O are transferred to the ECB DRAM as shown. During the data period T17, the remaining ECC data B, D, F, H, J, L, N, and P are sent to the ECB DRAM as shown.

It must be understood that the special configuration of ECC data is for illustrative purposes only. For example, during the first ECC data period, the ECC data value A-H can be transmitted; and during the second ECC data period, the ECC data value I-P can be transmitted. As long as the memory controller 330 is consistent with reading and writing, any convenient configuration can be adopted. As will be described in detail later, in the described embodiment, the ECB DRAM only needs to understand the data cycle format, and does not need to understand how the ECC data is distributed among the various memory elements by the memory controller.

Figure 5 shows another burst mode 18B. In this burst mode, one ECC data cycle is alternately scattered with 8 data cycles. During this ECC data cycle, corresponding 8 cycles of individual ECC data are transmitted. In one embodiment, during the data period T0, the ECC data is transmitted corresponding to the data words A-H to be transmitted during the following eight periods T1-T8. However, during the data period T9, the ECC data is transmitted corresponding to the data word I-P, and then the data word I-P in the data period T10-T17. Note that Figure 5 is composed of two concatenated bursts of 9 data cycles, suggesting that this mode can also be used for burst mode 9 transmission that performs half of the transmission. In addition, the burst mode 18B can be modified for the write operation, so the data cycle of eight user data is transmitted first, and then a data cycle of ECC data corresponding to the data cycle of eight user data.

The foregoing timing embodiment shows the following situation. There is an integer relationship between the number of ECC values that can be transmitted in a data period and the burst length of the corresponding data. Figures 6A-6C show an embodiment that does not need to be true.

In Figure 6A, the memory controller 330 requests the error-corrected burst mode 5 transmission, which transmits one ECC data cycle and four user data cycles from the ECB DRAM. This transmission system is the same as the first five data periods in Fig. 5, but the data period is truncated after the data period T4. Note that the ECC data E-H received from ECB-DRAM2 and ECB-DRAM3 are "no problem" data. Although the ECC data E-H is sent by the memory controller 330 and loaded into the ECC register bank 335, the data It has never been used.

For this example, suppose the row address supplied to the ECB-DRAM is 0xC80, where 0x represents the hexadecimal notation, and the user data "A" is stored at the row address 0xC80 and a certain column address RA. ECC data "A" and "B" are related to row address RA and row address 0xC80-87 in ECB-DRAM0 memory. Retrieving any user data in the address range from the ECB-DRAM0 memory array also results in the slave and row address RA and row address 0xC8[0b0XXX] (the value in brackets here is binary (0b) notation , And "X" means no harm bit) ECC memory array element retrieves the ECC data "A" and "B". Similarly, the ECC data "I" and "J" are stored in the ECC memory array element associated with the row address RA and row address 0xC8[0b1XXX]. In the normal user ECC burst mode, the memory controller cannot explicitly address these ECC memory array elements, but understands that when user data addressed in the corresponding user space is supplied, these ECC memory array elements Will be accessed in ECC mode.

It should also be noted that if the burst is related across two ECCs (for example, a 4-word burst G-J is requested from Figure 4A), the memory system can be designed to increase the burst by one data period and provide two ECCs. Associated.

In each of Figures 6A, 6B, and 6C, the memory module BMM0 returns the same ECC data, but returns different user data. Depending on the low order bit of the row address, the memory controller will select which ECC data to use, and which ECC data will be ignored. For example, in Figure 6B, the starting row address is 0xC82, so the CC data returned from ECB-DRAM1 and ECB-DRAM2 will be used, while the ECC data returned from ECB-DRAM0 and ECB-DRAM3 will be ignored. In Figure 6C, the starting row address is 0xC84, so the ECC data sent back from ECB-DRAM2 and ECB-DRAM3 will be used.

Although other burst lengths are not shown, those skilled in the art can apply the aforementioned principles to, for example, burst length 3 (including one ECC data period) burst mode, and burst length 2 (including one ECC data period) burst mode. A single address sends user data, and any other unspecified burst length.

In some embodiments, user data and ECC data can also be written to include a number of invalid ECC data burst lengths. In one embodiment, the memory device includes a data mask (DM) signal input, and the memory controller announces an appropriate mask line during the ECC data cycle to prevent writing to correspond to the written user data ECC location. For example, in Figure 6B, the memory controller can declare DM inputs to ECB-DRAM0 and ECB-DRAM3 during T0. Therefore, during T0, only ECB-DRAM1 and ECB-DRAM2 actually pick up ECC data, and the ECC Data is stored in ECC memory.

In another embodiment, the DM signal input does not exist or is not used to control the ECC data on the data bus. Instead, the module location register in the mode register set (MRS) of each memory device is used for the address planning of the memory device on the BMM0, or the option is hard-coded when the module is created . The logic of each memory device is compared with the requested row address range and the module location register to determine whether the ECC data supplied to the memory device should be written or ignored. For example, on ECB-DRAM0, the MRS module position register is programmed with the value 000 and 001. When the write burst row address range includes low-order address 000, ECB-DRAM0 will store the ECC data received at T0 in DQ0-DQ7 of its ECC memory space, otherwise it will not store the data. The similar logic of low order address 001 determines whether the ECC data received from DQ8-DQ15 at T0 will be stored in the ECC memory space.

A specific example of the ECB DRAM 700 is illustrated in the block diagram of FIG. 7. ECB DRAM 700 includes address and control logic 710, address register 720, column decoder 730, row decoder 740, burst/ECC controller/counter 750, I/O register, driver and receiver 760 , I/O gating and masking logic 770, sense amplifier 780, and memory cell array 790. Some blocks are familiar to those skilled in the art, but other blocks have been modified to match the error correction bursts described above. The following description focuses on the cooperation between the blocks and the novel functions that support error correction bursts.

The address and control logic 710, for example, receives a command from the memory controller in the signal input CMD. Typical commands include the ACTIVE command for selecting the word line in the memory cell array 790, the READ command specifying the row to be read from in the memory cell array 790, and the memory cell array 790 to be written. WRITE command, update command and various mode setting commands in each line in the.

During the ACTIVE command, the column address is received at the signal input ADD and latched by the address register 720. The column address is transmitted to the column decoder 730 by the signal from the address and control logic 710, and then used To activate the corresponding column of the memory cell array 790. The sense amplifier 780 reads and updates the column content of the memory cell array in response to the ACTIVE command.

During the READ command, the row address is received at the signal input ADD, and the address register 720 is latched. The row address is sent to the burst/ECC controller/counter 750 by a signal from the address and control logic 710. The burst/ECC controller/counter 750 will use the row address to control the data selection from the sense amplifier 780 during the data phase to be operated, and transmit the data through the I/O gating and mask logic 770 To I/O register and driver 760.

During the WRITE command period, during the write command period, the row address is received at the signal input ADD, and the address register 720 is latched. The row address is sent to the burst/ECC controller/counter 750 by a signal from the address and control logic 710. The burst/ECC controller/counter 750 will use the row address to control data from the I/O register and receiver 760 to the I/O gating and masking logic 770 during the data phase of the write operation.

During at least some mode setting commands, the mode register value is received on the signal input ADD and latched by the address register 720. The value of the mode register is transferred to the mode register 715. The mode register 715 is shown as part of the address and control logic 710 in FIG. In some embodiments, one of the values of the mode register is ECC MODE, and ECC MODE indicates whether the READ and WRITE burst commands will include additional data cycles for transmitting ECC data. The mode register value ECC MODE is supplied to the burst/ECC controller/counter 750, which will determine how the burst/ECC controller/counter 750 selects the data row during the read and write command data transmission.

The row decoder 740 selects n rows in the memory cell array 790 for data transfer between the I/O gating and masking logic 770 and the I/O register 760 in each read or write data cycle. The selected row is determined based on the address provided by the burst/ECC controller/counter 750 for the data period. For writing data, the row selection is also determined by one or more data mask (DM) inputs received together with the writing data. When the writing data instruction is masked, I/O gate control and mask The logic 770 blocks the transfer of the data to the memory cell array 790.

The I/O register, driver, and receiver 760 operate in a conventional manner, but the burst length can be adjusted by the burst/ECC controller/counter 750 to support ECC burst length and non-ECC burst length. During the write burst, the receiver 760 receives the I/O pins DQ1-DQ during each data cycle<i>n</i>The data and the data mask input of pin DM, where the data cycle is indicated by the strobe signal on the strobe I/O pin DQS, and the data received by the latch and the data mask are input to the I/O temporary The register is used to transfer to the I/O gating and masking logic 770. During the read burst, the I/O register 760 receives data from the I/O gating and masking logic 770, and the driver drives on DQ1-DQ<i>n</i>The data on the DQS and the strobe data on the DQS.

The configuration of the memory cell array 790 enables the ECB DRAM 700 to function in ECC mode and non-ECC mode. For every eight rows of data, there are also ECC rows. This configuration is used to illustrate the way in which the embodiments of the present invention can be implemented. Here, the addressable row segment is associated with additional ECC rows; other configurations and data to ECC row ratios are also possible, as long as the burst/ The ECC controller counter and row decoder can match these other configurations.

The further operation of the ECB DRAM 700 will now be described in conjunction with FIG. 6A. It is assumed that the ECB DRAM 700 is the ECB-DRAM0 referred to in the figure. First, in response to the ACTIVE command, the sense amplifier 780 reads data from a row of the memory cell array 790, which row is selected by the row decoder 730. The data read by the sense amplifier 780 includes ECC data obtained from the ECC row and user data obtained from the data row.

Secondly, assuming that the error correction burst mode 5 is selected, the row address 0xC80 supplied by the READ command is sent to the burst/ECC controller/counter 750 (note that although Figure 7 shows a memory bank, ECB DRAM 700 also There can be multiple rank groups, and several row address bits are used as the selected rank group). The burst/ECC controller/counter 750 first sends a signal to the row decoder 740 to select the ECC row associated with the row address 0xC80. Such signaling includes, for example, providing the starting line address 0xC80 on the CA, and at the same time declaring the ECC address cancellation signal ECC-AO. When the ECC-AO signal is declared, the row decoder 740 ignores the three low-order address bits appearing on the CA, and instead selects the ninth address associated with the external addressable segment 0xC80-87. The ninth address is not directly addressable through an external supply line address, but can be addressed internally by a line decoder in ECC mode. In this way, by addressing the corresponding data segment in the ECC mode, the memory controller can only indirectly address the ECC data.

The ninth address is selected, and the I/O gating and masking logic 770 transfers the data from the ECC row associated with the external row address 0xC80-87 to the I/O register and driver 760 in the data period T0. At Q1-DQ<i>n</i>Drive up.

Secondly, the burst/ECC controller/counter changes from the ECC address state to the data address state. Continue to supply the starting line address 0xC80 to the line decoder, but cancel the declaration of ECC-AO. This causes the row decoder 740 to select the data row associated with the external address to transmit to the I/O register and driver 760 via the I/O gating and masking logic 770 for use in DQ1 during the data period T1. -DQ<i>n</i>Drive up.

The burst/ECC controller/counter increments its internal row address to 0xC81, and repeats the operation described above to supply data to the data period T2. This process is repeated twice to complete the 5-data cycle burst read operation in Figure 6A.

When the mode register 715 indicates that the ECC mode cannot be operated, the burst/ECC controller/counter 750 has not entered the ECC address state, and has not declared ECC-AO. The data address status remains the same, causing data rows (but not ECC rows) to be read in a 4-data cycle burst read operation.

The operation in the error correction write burst mode is similar. In the appropriate data cycle, the burst/ECC controller/counter 750 declares ECC-AO to cause the ECC row associated with the data row segment to be indicated by the CA to be selected for writing. The length of the write burst is extended to match the additional data period in the data correction write burst mode. As explained above, the ECC data relies on the data mask signal DM to simplify the logic and allow the memory controller to determine which CC data will be written based on a detailed criterion.

The mode register method for indicating ECC mode and non-ECC mode has been explained. In such a system, unless it is changed by the memory controller, a mode (such as non-ECC) can be selected as the internal device. Another way to indicate ECC mode and non-ECC mode can provide two different commands. For example, depending on the data standard indicated by the processor, this method allows the memory controller to effectively mix ECC data bursts and non-ECC data bursts.

Although a 4-chip module and a 64-bit data bus are shown, it is only an example, and other numbers of chips or data bus widths can be used. For example, a 1-chip, 2-chip or 8-chip module can also be implemented according to the aforementioned principles. The module does not need to have a single row of memory components, for example, two rows of 8 chips can each be included in the module. The present invention can also be used in a system having a memory component mounted on the same circuit board as a processor using the memory component.

Those skilled in the art understand that the ideas taught in this article can be adjusted to specific uses in a variety of other advantageous ways. In particular, those skilled in the art understand that the specific embodiments described herein are selected from other implementations that will be apparent when studying this disclosure. For example, multiple temporal configurations of different user data and ECC data in the burst are all possible, even though part of the temporal configuration may mix ECC data and user data in part or all of the data cycle. Although the DRAM embodiments have been described, the principles described here are the same as applying the principles to memory cell configuration and data transfer rather than to memory types. These principles are equally applicable to other types of semiconductor memory. Such as static memory, flash memory, etc. The specific functional configurations of the element embodiments described herein provide a possible functional grouping, but these functions can be subdivided and/or combined in a variety of other combinations that fall within the scope of the accompanying patent application.

The purpose of the present invention is error correction coding. However, those skilled in the art understand that the auxiliary memory space used for ECC and the burst transfer data cycle can also be used to store and retrieve any auxiliary data. Processors and/or memory controllers are deployed with addressable memory address ranges. Associated auxiliary information.

Many of the features shown here are design options, and many other design options have been deleted because they belong to the technical scope of the industry and/or are based on various implementation decisions. These minor modifications are included in the scope of the embodiments of the present invention, and are intended to fall within the scope of the patent application.

The previous embodiment is for illustration only. Although the description may refer to "one", "one", "another", or "several" embodiments in several places, these terms do not necessarily mean that these descriptions refer to the same embodiment, or that these features only refer to the same embodiment. Apply to a single embodiment.

<p>100. . . computer system</p><p>120. . . processor</p><p>125. . . Front bus</p><p>130. . . Memory Controller / Hub (MCH)</p><p>140. . . Data bus</p><p>150. . . Address/Command (ADD/CMD) bus</p><p>300. . . computer system</p><p>320. . . processor</p><p>330. . . Memory controller</p><p>335. . . ECC register bank group</p><p>340. . . Data bus</p><p>350. . . Address/Command (ADD/CMD) bus</p><p>700. . . ECB DRAM</p><p>710. . . Address and control logic</p><p>715. . . Mode register</p><p>720. . . Address register</p><p>730. . . Column decoder</p><p>740. . . Row decoder</p><p>750. . . Burst/ECC Controller/Counter</p><p>760. . . I/O registers, drivers and receivers</p><p>770. . . I/O gating and masking logic</p><p>780. . . Sense amplifier</p><p>790. . . Memory cell array</p>

Figure 1 shows the processor and several memory system components of the prior art computer system; Figure 2 shows the timing diagram of burst mode data transmission on the data bus in Figure 1; Figure 3 contains an embodiment according to the present invention , A block diagram of the processor and several memory system components of the computer system; Figures 4A, 4B, 5, 6A, 6B, and 6C show the timing diagram of error-corrected burst mode data transmission according to several embodiments of the present invention And Figure 7 contains a block diagram of a DRAM device according to an embodiment of the present invention.