Thin film transistor array and fabricating method thereof

Thin film transistor array substrate and manufacturing method thereof

The present invention relates to a thin film transistor array substrate (Thin Film Transistor array, TFT array) and a manufacturing method thereof, and in particular to a thin film transistor array capable of increasing the storage capacitor (Cst) in each pixel Substrate and its manufacturing method.

In response to the rapid progress of the multimedia society, most of them benefited from the rapid progress of semiconductor devices or display devices. As far as displays are concerned, Cathode Ray Tubes (CRTs) have been monopolizing the display market in recent years due to their excellent display quality and economy. However, for the environment where individuals operate most terminals/display devices on the desk, or from the viewpoint of environmental protection, if the trend of energy saving is used to predict, cathode ray tubes still have many problems due to space utilization and energy consumption. The demand for light, thin, short, small, and low power consumption cannot effectively provide a solution. Therefore, TFT LCD (Thin Film Transistor Liquid Crystal Display) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market.

The thin film transistor liquid crystal display (TFT-LCD) is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate is composed of multiple arrays of thin film transistors and each thin film The transistor is composed of pixel electrodes corresponding to the configuration. The thin-film electrocrystalline system is used as the switching element of the liquid crystal display unit. In addition, in order to control individual pixel units, scan lines and data lines (date lines) are usually used to select specific pixels, and provide appropriate operating voltages to display the display corresponding to this pixel. material. In addition, a portion of the pixel electrode mentioned above is usually covered on the scan wiring or the common line to form a storage capacitor. In the prior art, common storage capacitors can be divided into Metal-Insulator-Metal (MIM) and Metal-Insulator-ITO (MII). Two architectures, the storage capacitor structure of the above two architectures will be described in detail below.

FIG. 1 is a schematic cross-sectional view of a storage capacitor with a conventional metal layer-insulation layer-metal layer (MIM) structure. Please refer to FIG. 1, in the conventional pixel structure, the storage capacitor Cst of the metal layer-insulation layer-metal layer (MIM) structure is usually formed by coupling the scan wiring or the common wiring 100 with the upper electrode 120 above it. It is worth noting that in the storage capacitor of the metal layer-insulation layer-metal layer (MIM) structure, the scan wiring or the common wiring 100 and the upper electrode 120 are electrically insulated from each other by the gate insulating layer 110, so the storage capacitance value Cst is related to the thickness of the gate insulating layer 110. In other words, the smaller the thickness of the gate insulating layer 110 is, the larger the storage capacitance value Cst is. In addition, the pixel electrode 140 is electrically connected to the upper electrode 120 through the contact window 132 in the protective layer 130.

FIG. 2 is a schematic cross-sectional view of a storage capacitor with a conventional metal layer-insulating layer-indium tin oxide layer (MII) structure. Please refer to FIG. 2, in the conventional pixel structure, the storage capacitor of the metal layer-insulating layer-indium tin oxide layer (MII) structure is usually coupled to the pixel electrode 230 above it by scanning wiring or common wiring 200 Become. The difference from the metal layer-insulating layer-metal layer (MIM) structure is that the scanning wiring or the common wiring 200 and the pixel electrode 230 in the storage capacitor of the metal layer-insulating layer-indium tin oxide layer (MII) structure Since the gate insulating layer 210 and the protective layer 220 are electrically insulated from each other, the storage capacitance value Cst is related to the total thickness of the gate insulating layer 210 and the protective layer 220. In other words, the smaller the total thickness of the gate insulating layer 210 and the protective layer 220 is, the larger the storage capacitance value Cst is.

In the conventional thin film transistor array substrate, if the storage capacitance value Cst is to be increased without affecting the aperture ratio, the thickness of the gate insulating layer 210 and/or the protective layer 220 must be reduced, but if the gate insulating layer is reduced The thickness of the layer 210 and/or the protective layer 220 may decrease the reliability of the thin film transistor.

The purpose of the present invention is to provide a thin film transistor array substrate, which can effectively increase the storage capacitance in each pixel.

Another object of the present invention is to provide a method for manufacturing a thin film transistor array substrate, which is compatible with the existing manufacturing process and can effectively increase the storage capacitance in each pixel.

To achieve the above or other objectives, the present invention provides a thin film transistor array substrate. The thin film transistor array substrate is composed of a substrate, a plurality of scanning wirings, a plurality of data wirings, a plurality of thin film transistors, an etching barrier layer and a plurality of Consists of a pixel electrode. Among them, the scanning wiring and the data wiring are arranged on the substrate to divide the substrate into a plurality of pixel regions. Each thin film transistor system is arranged in the corresponding pixel area, and is driven by the corresponding scan wiring and data wiring. The etching barrier layer is disposed above the scanning wiring, and the etching barrier layer has a plurality of openings. Each pixel electrode is arranged in the corresponding pixel area to be electrically connected to the corresponding thin film transistor, and part of each pixel electrode is coupled to the corresponding scan wiring through one of the openings. Storage capacitor.

In order to achieve the above or other objectives, the present invention provides a thin film transistor array substrate. The thin film transistor array substrate is composed of a substrate, a plurality of scanning wirings, a plurality of data wirings, a plurality of thin film transistors, a plurality of common wirings, and an etching. The barrier layer is composed of a plurality of pixel electrodes. Among them, the scanning wiring and the data wiring are arranged on the substrate to divide the substrate into a plurality of pixel regions. Each thin film transistor system is arranged in the corresponding pixel area, and is driven by the corresponding scan wiring and data wiring. The common wiring is arranged on the substrate and located between two adjacent scanning wirings. The etching barrier layer is disposed above the common wiring, and the etching barrier layer has a plurality of openings. Each pixel electrode is arranged in the corresponding pixel area to be electrically connected to the corresponding thin film transistor. Part of each pixel electrode is coupled to the corresponding common wiring through one of the openings. Storage capacitor.

The thin film transistor array substrate of the present invention, for example, further includes a gate insulating layer disposed between the etching barrier layer and the scanning wiring (or common wiring), and the gate insulating layer has a plurality of corresponding etching barrier layers. The depression of the opening.

The thin film transistor array substrate of the present invention, for example, further includes a semiconductor layer disposed between the etching barrier layer and the gate insulating layer. In addition, the thin film transistor array substrate of this embodiment, for example, further includes a protective layer disposed on the etching barrier layer and the gate insulating layer, and the protective layer exposes the opening of the etching barrier layer.

In a preferred embodiment of the present invention, the etching barrier layer includes, for example, a plurality of stripe patterns, and each stripe pattern is located above the corresponding scan wiring (or common wiring). In addition, the etching barrier layer may also include a plurality of frame-shaped patterns, and each frame-shaped pattern is located under the corresponding pixel electrode.

In a preferred embodiment of the present invention, the material of the pixel electrode is, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or other conductive materials.

To achieve the above or other objectives, the present invention provides a method for manufacturing a thin film transistor array substrate. First, a first patterned conductive layer is formed on a substrate. Then, a gate insulating layer and a semiconductor material layer are sequentially formed on the substrate and the first patterned conductive layer. Afterwards, an etching barrier layer located above the first patterned conductive layer is formed on a part of the semiconductor material layer. Then, an ohmic contact layer is selectively formed on the semiconductor material layer and the etching barrier layer, and then a conductive layer is formed, and the above-mentioned conductive layer, ohmic contact layer and semiconductor material layer are patterned to simultaneously form a second The patterned conductor layer and a plurality of semiconductor layers located under the etching barrier layer and the second patterned conductor layer. Then, a protective layer is formed on the substrate, and the protective layer above the partial area of the second patterned conductor layer is removed to form a plurality of contact windows, and the protective layer above the partial area of the first patterned conductor layer is removed at the same time Layer, etch barrier layer and semiconductor layer to form a plurality of openings. Finally, a plurality of pixel electrodes are formed on the substrate, and each pixel electrode is electrically connected to the second patterned conductor layer through a corresponding contact window, and a part of each pixel electrode is through a corresponding opening Coupled with the first patterned conductor layer to form a storage capacitor.

In a preferred embodiment of the present invention, before forming a conductive layer on the semiconductor material layer and the etching barrier layer, it further includes selectively forming an ohmic contact layer on the semiconductor material layer and the etching barrier layer.

In a preferred embodiment of the present invention, the method for forming the first patterned conductive layer is, for example, to first form a first conductive layer on the substrate, and then pattern the first conductive layer to form a plurality of scanning wirings and Most of the gates connected to the scanning wiring. In this embodiment, the etching barrier layer is formed above the gate electrode and the scan wiring.

In a preferred embodiment of the present invention, the method for forming the first patterned conductive layer is, for example, to first form a first conductive layer on the substrate, and then pattern the first conductive layer to form a plurality of scanning wirings, A plurality of gates connected to the scanning wiring, and a plurality of common wirings located between two adjacent scanning wirings. In this embodiment, the etching barrier layer is formed above the gate electrode and the common wiring.

In the manufacturing method of the thin film transistor array substrate of the present invention, while patterning the conductive layer and the semiconductor material layer, it further includes using the second patterned conductive layer as a mask to remove a part of the thickness of the etching barrier layer.

In the manufacturing method of the thin film transistor array substrate of the present invention, while forming the contact window, it further includes removing a part of the thickness of the gate insulating layer to form a plurality of recesses corresponding to the openings in the gate insulating layer.

In order to make the above and other objectives, features and advantages of the present invention more comprehensible, a preferred embodiment will be specifically described below in conjunction with the accompanying drawings.

FIG. 3 is a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. 3, the thin film transistor array substrate 300 of this embodiment is composed of a substrate 310, a plurality of scanning wiring 320, a plurality of data wiring 330, a plurality of thin film transistors 340, an etching barrier layer 350 and a plurality of pictures. The element electrode 360 is constituted.

In this embodiment, the substrate 310 is, for example, a glass substrate, a plastic substrate, or a substrate made of other materials. As shown in FIG. 3, the scan wiring 320 and the data wiring 330 are arranged on the substrate 310 to divide the substrate 310 into a plurality of pixel regions 312. In more detail, the scanning wires 320 are arranged on the substrate 310 parallel to each other, for example, the data wires 330 are also arranged on the substrate 310 parallel to each other, and the extending directions of the scanning wires 320 and the data wiring 330 are, for example, perpendicular to each other. The substrate 310 is divided into a plurality of rectangular pixel regions 312.

As shown in FIG. 3, each thin film transistor 340 is arranged in the corresponding pixel region 312, and is driven by the corresponding scan wiring 320 and data wiring 330. In more detail, the thin film transistor 340 is arranged adjacent to the intersection of the corresponding scan wiring 320 and the data wiring 330, that is, the thin film transistor 340 is arranged on a corner of the pixel area 312 . In this embodiment, the thin film transistor 340 is composed of, for example, a gate 342, a semiconductor layer 344 above the gate 342, and a source/drain 346. Among them, the gate electrode 342 is formed at the same time as the scan wiring 320, and the source/drain electrode 346 is formed at the same time as the data wiring 330, for example.

Please also refer to FIG. 3, the etching barrier layer 350 is disposed above the scan wiring 320, and the etching barrier layer 350 has a plurality of openings 352. In addition, each pixel electrode 360 is arranged in the corresponding pixel region 312 to be electrically connected to the corresponding thin film transistor 340, and a part of each pixel electrode 360 is through the etching barrier layer 350 The openings 352 are respectively coupled with the corresponding scan wiring 320 to form a storage capacitor, and the storage capacitor belongs to a storage capacitor of a metal layer-insulating layer-indium tin oxide layer (MII) structure, and there are details about the storage capacitor The cross-sectional structure will be described in detail later (FIGS. 6A to 6H). In view of the above, the material of the pixel electrode 360 is, for example, indium tin oxide, indium zinc oxide, or other conductive materials.

4A is a schematic top view of the etching barrier layer according to a preferred embodiment of the present invention, and FIG. 4B is a schematic top view of the etching barrier layer according to another preferred embodiment of the present invention. First, referring to FIG. 4A, in one embodiment of the present invention, the etching barrier layer 350 includes a plurality of strip patterns 350a, and each strip pattern 350a is located above the corresponding scan wiring 320. 4B, in another embodiment of the present invention, the etching barrier layer 350 includes a plurality of frame-shaped patterns 350b, and each frame-shaped pattern 350b is located under the corresponding pixel electrode 360.

FIG. 5 is a schematic top view of a thin film transistor array substrate according to another preferred embodiment of the present invention. 5, the thin film transistor array substrate 300' of this embodiment is composed of a substrate 310, a plurality of scanning wiring 320, a plurality of data wiring 330, a plurality of thin film transistors 340, a plurality of common wiring 370, an etching resist The barrier layer 350 and a plurality of pixel electrodes 360 are formed. Since the thin film transistor array substrate 300' of this embodiment is similar in structure to the thin film transistor array substrate 300 in FIG. 3, only the differences between the two are described in detail here.

Referring to FIG. 5, the common wiring 370 is disposed on the substrate 300 and is located between two adjacent scanning wirings 320. It should be noted that the common wiring 370 is formed at the same time as the scanning wiring 320. Since the storage capacitor on the thin film transistor array substrate 300' is structured on the common wiring 370, the etching barrier layer 350 needs to be disposed above the common wiring 370. The etching barrier layer 350 here also has a plurality of openings 352 to Part of the area of the pixel electrode 360 can be coupled to the corresponding common wiring 370 as a storage capacitor through the opening 352 of the etching barrier layer 350. The detailed cross-sectional structure of the storage capacitor will be described in detail later (FIGS. 6A to 6A). Figure 6H).

6A to 6H are schematic cross-sectional views of a manufacturing process of a thin film transistor array substrate according to a preferred embodiment of the present invention. 6A, first, a first patterned conductive layer M1 is formed on a substrate 310. The material of the first patterned conductive layer M1 is, for example, aluminum or other metals.

When fabricating the thin film transistor array substrate 300 with a Cst on gate structure (shown in FIG. 3), the method for forming the first patterned conductive layer M1 is, for example, first forming a first conductive layer (not shown) (Shown) on the substrate 310, and then the first conductive layer is patterned to form a plurality of scan wirings 320 and a plurality of gates 342 connected to the scan wirings 320.

When manufacturing the thin film transistor array substrate 300' (shown in FIG. 5) with a Cst on common structure, the method for forming the first patterned conductive layer M1 is, for example, first forming a first conductive layer (Not shown) on the substrate 310, and then pattern the first conductor layer to form a plurality of scan wirings 320, a plurality of gates 342 connected to the scan wiring 320, and a plurality of scans located adjacent to each other The wire 370 is shared between the wires 320.

Next, referring to FIG. 6B, a gate insulating layer 380 and a semiconductor material layer 344' are formed on the substrate 310 and the first patterned conductive layer M1. The material of the gate insulating layer 380 is, for example, silicon oxide, silicon nitride, or other dielectric materials, and the material of the semiconductor material layer 344' is, for example, amorphous silicon.

Next, referring to FIG. 6C, an etching barrier layer 350 above the first patterned conductive layer M1 is formed on a part of the semiconductor material 344'. It is worth noting that when fabricating the thin film transistor array substrate 300 with a Cst on gate structure (shown in FIG. 3), the etching barrier layer 350 is formed on the gate 342 and the scan wiring 320 . When fabricating the thin film transistor array substrate 300 (shown in FIG. 5) with a Cst on common structure, the etching barrier layer 350 is formed on the gate 342 and the common wiring 370.

6D, then a conductive layer 382 is formed on the semiconductor material layer 344' and the etching barrier layer 350. The conductive layer 382 is, for example, a metal laminate of aluminum/molybdenum/aluminum (Al/Mo/Al) or Other suitable single or composite conductor layers. It is worth noting that, in order to improve the performance of the device, an ohmic contact layer 384 may be selectively formed before forming the conductive layer 382 to improve the contact characteristics between the conductive layer 382 and the semiconductor material layer 344'. In view of the above, the material of the ohmic contact layer 384 is, for example, an n-type doped amorphous silicon layer.

6E, the above-mentioned conductive layer 382, ohmic contact layer 384 and semiconductor material layer 344' are patterned to form a second patterned conductive layer M2 and a plurality of them located in the etching barrier layer 350 and the second patterned layer at the same time. The semiconductor layer 344 below the conductive layer M2. Similarly, the ohmic contact layer 384 will also be patterned, so that the ohmic contact layer 384 is only distributed under the second patterned conductive layer M2. In other words, the ohmic contact layer 384 and the second patterned conductor layer M2 will have the same pattern.

Please also refer to FIG. 6E, while patterning the above-mentioned conductive layer 384 and semiconductor material layer 344', the etching barrier layer 350 that is not covered by the second patterned conductive layer M2 will be removed by part of its thickness, as shown in FIG. As shown in A and B in 6E.

6F and 6G, a protective layer 390 is formed on the substrate 310, and the protective layer 390 over a portion of the second patterned conductive layer M1 is removed to form a plurality of contact windows 392, and the first The protective layer 390, the etching barrier layer 350, and the semiconductor layer 344 above a partial area of the patterned conductive layer M1 form a plurality of openings 394. In this embodiment, for example, the contact window 392 and the opening 394 are formed by lithography/etching. After the lithography/etching process, the contact window 392 will expose part of the second patterned conductive layer M1, and the opening 394 exposes the gate insulating layer 380 and even removes part of the thickness of the gate insulating layer 380 to form a plurality of recesses R corresponding to the openings 394 in the gate insulating layer 380. It is worth noting that due to the existence of the etching barrier layer 350, the gate insulating layer 380 will only be etched to form a recess R, and the gate insulating layer 380 will not be eroded or broken.

Finally, referring to FIG. 6H, a plurality of pixel electrodes 360 are finally formed on the substrate 310. Each pixel electrode 360 is electrically connected to the second patterned conductor layer M2 through a corresponding contact window 392, and each pixel electrode 360 is electrically connected to the second patterned conductor layer M2 through a corresponding contact window 392. Part of the area of the element electrode 360 is coupled to the first patterned conductive layer M1 through the corresponding opening 394 to form a storage capacitor. It is worth noting that the recess R formed on the surface of the gate insulating layer 380 will reduce the thickness of the gate insulating layer 380, thereby increasing the storage capacitance per unit area.

In summary, the thin film transistor array substrate and the manufacturing method thereof of the present invention have at least the following advantages: 1. In the thin film transistor array substrate of the present invention, the storage capacitance and aperture ratio can be further improved.

2. The manufacturing method of the thin film transistor array substrate of the present invention is compatible with the existing manufacturing process, and can effectively increase the storage capacitance value per unit area without greatly modifying the manufacturing process.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

<p>100, 200Scan wiring or shared wiring</p><p>110,210Gate insulation layer</p><p>120Upper electrode</p><p>130,220Protection layer</p><p>132Contact window</p><p>140,230Pixel electrode</p><p>300, 300'Thin Film Transistor Array Substrate</p><p>310Substrate</p><p>312Pixel area</p><p>320Scanning wiring</p><p>330Data wiring</p><p>340Thin Film Transistor</p><p>342Gate</p><p>344Semiconductor layer</p><p>344'Semiconductor material layer</p><p>346Source/Drain</p><p>350Etching barrier layer</p><p>350aStripe pattern</p><p>350bFrame pattern</p><p>352Open</p><p>360Pixel electrode</p><p>370Common wiring</p><p>380Gate insulation layer</p><p>382Conductor layer</p><p>384Ohm contact layer</p><p>390Protection layer</p><p>392Contact window</p><p>394Open</p><p>M1First patterned conductor layer</p><p>M2Second patterned conductor layer</p><p>RSag</p>

FIG. 1 is a schematic cross-sectional view of a storage capacitor with a conventional metal layer-insulation layer-metal layer (MIM) structure.

FIG. 2 is a schematic cross-sectional view of a storage capacitor with a conventional metal layer-insulating layer-indium tin oxide layer (MII) structure.

FIG. 3 is a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention.

4A is a schematic top view of an etching barrier layer according to a preferred embodiment of the present invention.

4B is a schematic top view of the etching barrier layer according to another preferred embodiment of the present invention.

FIG. 5 is a schematic top view of a thin film transistor array substrate according to another preferred embodiment of the present invention.

6A to 6H are schematic cross-sectional views of a manufacturing process of a thin film transistor array substrate according to a preferred embodiment of the present invention.