Display device employing time-division-multiplexed driving of driver circuits

Display device of time-sharing multiplex drive using drive circuit

The present invention relates to a display device using thin film transistors. Among the pixels with a thin film transistor and the display device arranged in a matrix structure, the liquid crystal display device uses liquid crystal, and the EL type display device uses electroluminescence.

FIG. 16 shows a first conventional liquid crystal display device using thin film transistors. In this liquid crystal display device, the thin film transistors are arranged in an array on one of the two oppositely transparent glass substrates (not shown in the figure), and a transparent opposite electrode is arranged on the other of the two oppositely transparent glass substrates. On. In addition to forming a display panel with two relatively transparent substrates, a liquid crystal display device requires a polarizer and a backlight as its constituent parts, but these constituent parts are not directly related to the present invention; therefore, in the following description, use One of the two substrates formed by thin film transistors is called a display panel.

In FIG. 16, the manufacturing on the display panel LCP is a plurality of scan lines GL extending horizontally and a plurality of drain lines DL extending linearly. The thin film transistor TFT is manufactured near the intersection of the scan line GL and the drain line DL. The gate of each of the thin film transistors is connected to the opposite one of the scan lines GL, and one of a drain and a source of each of the thin film transistors is connected to the drains One of the lines DL corresponds to one, and the other of the drain and source is connected to a pixel electrode. Each pixel has a plurality of pixels with a thin film transistor TFT and a pixel electrode are arranged in a matrix structure on the liquid crystal display panel LCP. The display in FIG. 16 is a pixel PXR displaying a red image, a pixel PXG displaying a green image, and a pixel PXB displaying a blue image, wherein these pixels are coupled to the relative scan lines GL in the pixels arranged in a matrix structure. A three-piece combination of the pixel PXR, the pixel PXG, and the pixel PXB can form a dot. In an actual display area DPA, the three-piece combination is formed by repeated construction.

In terms of display operation, the image signal supplied to the drain line DL is applied to the pixel electrode by selecting one of the scan lines GL, thereby turning on the thin film transistor TFT connected to the selection scan line GL. As a result, a liquid crystal inserted between the pixel electrode and the opposite electrode can be driven, and the light transmission between the pixel electrode and the opposite electrode can be controlled; as a result, a display can be produced.

The scan line GL extends outside the display area DPA formed by using pixels arranged in a matrix configuration, and is coupled to the gate drivers VSR outside the left and right ends of the display area DPA. The drain line DL also extends to the outside of the display area DPA. In this liquid crystal display device, the drain line DL coupled to the red, green, and blue pixels is connected to one end of the switches SWR, SWG, and SWB, respectively. The other ends of the three switches SWR, SWG, and SWB connected to the drain line DL of a red (R) signal, a green (G) signal and a blue (B) signal are connected together and connected to One of the video signal input terminals VIDEOIN formed on the display panel LCP.

The switch SWR related to the pixel PXR displaying the red image is controlled by a signal Φ1, the switch SWG related to the pixel PXG displaying the green image is controlled by a signal Φ2, and the switch SWB related to the pixel PXB displaying the blue is transparent A signal Φ3 control. All the drain lines DL coupled to the pixels PXR for displaying red in the display area DPA are coupled to a relative number of the video signal input terminal VIDEOIN via the relative switch SWR controlled by the signal Φ1; coupled to the display area DPA All the drain lines DL of the pixel PXG displaying green are coupled to the corresponding ones of the video signal input terminal VIDEOIN via the relative switch SWG controlled by the signal Φ2; and are coupled to all the pixels PXB used to display blue in the display area DPA The drain line DL is coupled to the corresponding number of the video signal input terminal VIDEOIN via the relative switch SWB controlled by the signal Φ3. In other words, each of the video signal input terminals VIDEOIN is coupled to three drain lines DL, and the drain lines DL are three switches SWR, SWG controlled by three signals Φ1, Φ2, and Φ3, respectively. , SWB is coupled to three pixels for displaying red (R) signal, green (G) signal, and blue (B) signal.

The video signal input terminal VIDEOIN formed on the display panel LCP is connected to the TCP1, TCP2, and TCP3 terminals of the tape carrier package, and is connected to the drain driver installed on the line tape carrier package TCP1, TCP2, and TCP3 via the wiring above. DRV1, DRV2, and DRV3 (the following suffix numbers 1, 2, 3, ... are sometimes discarded without causing confusion). In FIG. 16, the video signal input terminal VIDEOIN and some terminals of the tape carrier packages TCP1, TCP2, and TCP3 are separated from each other, but in fact, they are connected to each other through an anisotropic guide sheet. The three signals Φ1, Φ2, and Φ3 used to control the switches SWR, SWG and SWB formed on the display panel LCP are supplied from a control circuit TCON outside the display panel LCP.

Figure 15 shows an internal structure of the drain driver DRV. The drain driver includes: an input latch I-LTC for holding image data in digital form supplied from an external circuit; an output latch P-LTC for receiving image data from the input latch I-LTC; and The digital-to-analog converter DAC is used to convert the image data held in the output latch P-LTC into an analog signal, in order to supply the image signal to the image signal input terminal VIDEOIN of the display panel LCP.

In the above-mentioned display device, when a specific one of the scan lines GL is selected during a period, first, a first type image signal supplied from the drain drivers DRV1, DRV2, and DRV3 is made by making the signal Φ1 The red display pixel PXR is written in the on state via the switch SWR, and then during the same period, when a specific scan line of the scan lines GL is selected, a second type image signal is supplied from the drain drivers DRV1, DRV2, and DRV3 The green display pixel PXG can be written into the green display pixel PXG through the switch SWG by turning the signal Φ2 into a conductive state, and then during the same period, when a specific scan line of the scan lines GL is selected, the data supplied from the drain drivers DRV1, DRV2, and DRV3 A third type of image signal is written into the blue display pixel PXB through the switch SWB by turning the signal Φ3 into a conductive state. In other words, during a period, when a specific one of the scan lines GL is selected, the drain driver DRV will continuously output the image signal of the red display pixel PXR and the green display pixel PXG in a time division multiplexing manner. The image signal and the image signal of the blue display pixel PXB. This configuration can reduce the number of drain drivers DRV to one third of the number of drain drivers required in a conventional display device.

Figure 13 shows a second conventional liquid crystal display device. The liquid crystal display device also includes a plurality of scan lines GL, a plurality of drain lines DL, and a plurality of pixels each having a thin film transistor and a pixel electrode, and the scan lines GL are connected to two gate drivers VSR. This second conventional liquid crystal display device is different from the above-mentioned first conventional liquid crystal display device. The difference is that the display area LCP of the second conventional liquid crystal display device is divided into a plurality of display blocks.

In the second conventional liquid crystal display device, each of the display blocks has a plurality of drain lines DL, each of which is connected to a corresponding one of the plurality of switches outside the display area DPA. The other end of each of the switches is connected to the corresponding one of the plurality of drain bus wires. The switches connected to the drain line DL in the same display area are controlled by a common signal.

In the second conventional liquid crystal display device, the display area DPA is divided into three display blocks BK1, BK2, and BK3. In each square, n dots are coupled to each of the scan lines GL.

In a first display block BK1 shown in FIG. 13, there are red display pixels PR1, PR2,..., PRn; green display pixels PG1, PG2, PGn; and blue display pixels PB1, PB2,..., PBn, all of which display The pixels are coupled to the same one of the scan lines GL. The drain lines DL coupled to the red display pixels, the green display pixels, and the blue display pixels respectively pass through the switching elements SR1, SR2,..., SRn outside the display area DPA; the switching elements SG1, SG2,..., SGn; switches; The components SB1, SB2,..., SBn are coupled to the bus wires BR1, BR2,..., BRn of a drain bus; the bus wires BG1, BG2,..., BGn; and the bus wires BB1, BB2,..., BBn .

In a second display block BK2 shown in FIG. 13, there are red display pixels PRn+1, PRn+2,..., PR2n: green display pixels PGn+1, PGn+2,..., PG2n; and blue display pixels All pixels of PBn+1, PBn+2,..., PB2n are coupled to the same one of the scan lines GL as in the first display block BK1. The drain lines DL coupled to the red display pixels, the green display pixels, and the blue display pixels respectively pass through the switching elements SRn+1, SRn+2,..., SR2n outside the display area EPA; the switching elements SGn+1, SGn +2,..., SG2n; and the switching elements SBn+1, SBn+2,..., SB2n and coupled to the drain bus bus wire BR1, BR2,..., BRn; bus wire BG1, BG2,..., BGn ; With the bus wires BB1, BB2,..., BBn.

In a third display block BK3 shown in FIG. 13, there are red display pixels PR2n+1, PR2n+2,..., PR3n; green display pixels PG2n+1, PG2n+2,..., PG3n; and blue display pixels All display pixels of PB2n+1, PB2n+2, ..., PB3n are coupled to the same one of the scan lines GL as in the first display block BK1. The drain lines DL coupled to the red display pixels, the green display pixels, and the blue display pixels respectively pass through the switching elements SR2n+1, SR2n+2,..., SR3n outside the display area DPA; the switching elements SG2n+1, SG2n +2,..., SG3n; and the switching elements SB2n+1, SB2n+2,..., SB3n and coupled to the drain bus wire BR1, BR2,..., BRn; bus wire BG1, BG2,..., BGn ; With the bus wires BB1, BB2,..., BBn.

As mentioned above, since there are n red signal bus wires, n green signal bus wires, and n blue signal bus wires, a total of 3n bus wires are formed outside the display area DPA. The opposite bus wires of the drain bus are connected to the corresponding ones of the output terminals of the drain driver.

The turn-on and turn-off control of the plurality of switches SR1, SG1, SB1, SR2, SG2, SB2,..., SRn, SGn, SBn coupled between the drain line of the first display block BK1 and the drain bus is through a The signal Φ1 is executed; a plurality of switches SRn+1, SGn+1, SBn+1, SRn+2, SGn+2, SBn+2 coupled between the drain line and the drain bus of the second display block BK2 ,..., SR2n, SG2n, and SB2n are turned on or off by a signal Φ2; and a plurality of switches SR2n+1, SG2n+ are coupled between the drain line of the third display block BK3 and the drain bus. 1. The on and off control of SB2n+1, SR2n+2, SG2n+2, SB2n+2,..., SR3n, SG3n, SB3n is performed through a signal Φ3. The signals Φ1, Φ2 and Φ3 are supplied by an external control circuit TCON. The drain line DL, the switch coupled between the drain line DL and the drain bus, the drain bus wire, and the output terminal of the drain driver DRV in each of the display blocks are the same number. The display blocks BK1, BK2, ... and the control signals Φ1, Φ2, ... are the same number.

In the above-mentioned liquid crystal display device, when a specific one of the scan lines GL is selected during a period, a first group of image signals initially supplied from the drain driver DRV to the drain bus is through the switch SR1 , SG1, SB1, SR2, SG2, SB2,..., SRn, SGn, SBn are written into the pixels of the first display block BK1. The switches are coupled to the first display block by turning the signal Φ1 into a conductive state. Then, during the period when a specific one of the scan lines GL is selected, a second group of image signals supplied from the drain driver DRV to the drain bus is through the switches SRn+1, SGn+1, SBn+1, SRn+2, SGn+2, SBn+2,..., SR2n, SG2n, SB2n are written into the pixels of the second display block BK2, wherein the switches are used to make the signal Φ2 a Is coupled to the drain line DL of the second display block BK2 in the on state; then, during the period when a specific one of the scan lines GL is selected, the drain driver DRV is supplied to a third drain line of the drain bus. The group image signal is written into the pixels of the third display block BK3 via the switches SR2n+1, SG2n+1, SB2n+1, SR2n+2, SG2n+2, SB2n+2,..., SR3n, SG3n, SB3n, where The switches are coupled to the drain line DL of the third display block BK3 by turning the signal Φ3 into a conductive state. In this liquid crystal display device, during the period when a specific one of the scan lines GL is selected, the drain driver DRV can continuously output a first group of image signals of the first display block BK1 in a time division multiplexing manner , A second group of image signals of the second display block BK2, and a third group of image signals of the third display block BK3. This construction makes it possible to reduce the number of drain drivers DRV to one third of the number of drain drivers required in a conventional display device.

In the above two liquid crystal display devices, the display area is divided into a plurality of groups, and during the horizontal scanning period of one of the scanning lines GL, the driver writes the image signal into the plurality of groups in a time division multiplexing manner. Relative to some groups of pixels. As a result, it can drive more drain lines DL than the number of output terminals of the drain driver DRV.

Specifically, the first conventional display device divides the image signal line into three groups of a red (R) signal group, a green (G) signal group, and a blue (B) signal group, so that its drain driver DRV can drive three times the number of drain lines DL of its output terminals. The second conventional display device divides the display area DPA into three parts, so that its drain driver DRV can drive three times the number of its output terminals DL.

FIG. 17 depicts, for example, a timing chart of the image signal of the first conventional liquid crystal display device. The following description relates to the problems of the first conventional liquid crystal display device of FIGS. 16 and 17. Generally, a liquid crystal display device can simultaneously receive 6-bit digital data IR for displaying 64 shades of gray red, 6-bit digital data IG displaying 64 shades of gray, and display 64 shades of gray at the same time from an external device such as a computer. The blue 6-bit digital data IB, that is, 18 bits are received at the same time.

In FIG. 17, the image data IR corresponding to 3n pixels related to a specific one of the scanning lines GL is R1, R2,..., Rn, Rn+1, Rn+2,..., R2n, R2n+1,... The image data IG corresponding to the 3n pixels of the specific scanning line GL and the IB corresponding to the 3n pixels of the specific scanning line GL are continuously supplied to the liquid crystal display device in the order of R3n. Display device. Here, the 3n pixel image data IR, IG, and IB corresponding to the next one of the scan lines GL after the specific scan line GL are represented by single quotation marks ('), such as R'1,... , R'3n, G1',..., G'3n, B'1,..., B'3n, and after the next scan line GL, the image data corresponding to 3n pixels related to one of the scan lines GL IR, IG and IB are represented by double quotation marks (") respectively, such as R"1, R"3n, G"1,..., G"3n, B"1,..., B"3n.

In a liquid crystal display device using a drain driver having only an input latch I-LTC system and a digital-to-analog converter DAC system, it is necessary to incorporate an image data aligner ALN in front of the drain driver DRV. The image data related to a specific one of the scanning lines GL is continuously supplied from an external device to the liquid crystal display device at a specified time, and the liquid crystal display device needs to be synchronized with the signal Φ1, the signal Φ2, and the signal Φ3, respectively. Among the data, the image data supplied to the red display pixels, the image data supplied to the green display pixels, and the image data supplied to the blue display pixels are selected, and then these digital data are continuously converted into analog data and outputted. However, the design of the above-mentioned drain driver DRV does not perform this processing; therefore, the circuit only used for the above-mentioned processing needs to be combined in front of the drain driver DRV. During a horizontal scanning period H, the image data supplied from an external device (in FIG. 17, the reference symbol BLK represents a blanking period) needs to be temporarily stored, and the red (R), green (G), and blue (B) signals The image data needs to be selected from the stored image data, and then they need to be continuously supplied to the drain driver DRV.

For example, consider that the image data aligner ALN supplies the image data O1 to the drain driver DRV1 in order to supply the image signal to the first to nth dots. The image data O1 includes data in the following sequence: during the period of selecting a specific one of the scan lines GL, the red display data R1, R2,..., Rn selected from the image data IR; During the period of a specific one of the GL, the green display data G1, G2,..., Gn selected from the image data IG; and during the period of selecting the specific one of the scan lines GL from the image data IB The selected blue color displays data B1, B2,..., Bn. The image data O2 and O3 supplied through the image data aligner ALN are respectively supplied to: the drain driver DRV2 for supplying image signals to the (n+1)th to 2nth picture points; and the drain driver DRV3 for use In order to supply the image signal to the (2n+1)th to 3nth picture points, and the image data O2 and O3 include red display data, green display data and blue display data of similar structure.

FIG. 14 is a timing chart describing, for example, an image signal of a second conventional liquid crystal display device. The following description relates to the problems of the second conventional liquid crystal display device of FIGS. 13 and 14. Generally, the drain driver DRV incorporates image data into an input latch I-LTC, and then transmits the image data stored in the input latch I-LTC to an output latch P-LTC, and then converts the digital image data into The analog signal is then supplied to the display panel LCP. Therefore, the time interval is required for transmitting the image data stored in the input latch I-LTC to the output latch P-LTC.

However, as shown in Figure 14, the external device continuously outputs the image data IR, IG, IB corresponding to each 3n image point. Therefore, if the image data IR, IG, IB are directly supplied from the external device to the drain driver, the The time interval during which the image data stored in the input latch I-LTC is transmitted to the output latch P-LTC is unnecessary.

As a result, the data aligner ALN needs to be used in front of the drain driver. The data aligner ALN is supplied to the drain driver DRV, and the image data has a time interval required to transmit the image data between the latches of the drain driver DRV. In FIG. 14, reference symbol O-ARR represents the output of the material aligner ALN. A traditional data aligner stores image data supplied from an external device in a plurality of memories, processes the stored image data, and then supplies the processed image data to the drain driver.

A main object of the present invention is to provide a display device that, from the point of view of the problems of the conventional display device, can reduce the number of components by further reducing the number of components compared with the conventional display device having a reduced number of drain drivers by adding a simple structure to it. cost.

The above and other objects, and new features of the present invention will become more apparent from the following description together with the accompanying drawings.

The representative structure of the present invention is as follows: According to a specific embodiment of the present invention, a display device is provided including: a plurality of scan lines; n three-piece combinations of the first, second, and third combinations; Each of the first combination formed by a drain line of the first type intersected by a scan line and a first switch having a first end coupled to the drain line of the first type, wherein the first switch Controlled by a first control signal; formed by a drain line of the second type intersecting a plurality of scan lines, and a second switch having a first end coupled to the drain line of the second type Each of the second combination, wherein the second switch is controlled by a second control signal; is controlled by a third type drain line that intersects a plurality of scan lines, and has a first type coupled to the third type Each of the third combination formed by a third switch at one end is controlled by a third control signal; n nodes, and the opposite one of the n nodes is connected to the n nodes at the same time The second end of the first, second, and third switch in the opposite one of the three-piece combination; arranged near the intersection of a plurality of scan lines and the first, second, and third types of drain lines A plurality of pixels, the opposite one of the plurality of pixels has a thin film transistor, and a first end of the thin film transistor is coupled to the opposite one of the first, second, and third types of drain lines, the thin film A second terminal pair of the transistor is coupled to the opposite one of the plurality of scan lines, and a third terminal of the thin film transistor is coupled to a pixel electrode of the opposite pixel of the plurality of pixels; and a drain driver , For supplying image signals to n nodes, wherein the drain driver includes: a first type of latch circuit, which is controlled by a fourth control signal to maintain a first type of n digital data, The first type of n-digit data is related to the first type of drain line; a second type of latch circuit is controlled by a fifth control signal to maintain a second type of n-bit data Data, the second type of n-digit data is related to the second type of drain line; and a third type of latch circuit, which is controlled by a sixth control to maintain the third type of n-digit The data signal, the third type of n-digit data is related to the third type of drain line. The first type of latch circuit, the second type of latch circuit, and the third type of latch circuit supply signals to n nodes in a time division multiplexing manner; and the first type of n-bit data, the first type The two types of n-digit data and the third type of n-digit data are simultaneously supplied to the display device.

According to another specific embodiment of the present invention, a display device is provided including: n red related drain lines, which are coupled to a plurality of red display pixels; n green related drain lines, which are coupled to a plurality of red display pixels; A plurality of green display pixels adjacent to the display pixel; n blue related drain lines, which are coupled to a plurality of blue display pixels adjacent to the plurality of green display pixels. A plurality of scan lines, which intersect with n red-related drain lines, n green-related drain lines, and n blue-related drain lines; the red, green, and blue display pixels are respectively arranged in the plural scans The line is in the vicinity of the drain line related to red, green, and blue. The opposite one of the red, green, and blue display pixels has a thin film transistor, and the thin film transistor has: a first end, which is coupled to the red related drain line, the green related drain line, and the blue The opposite one of the related drain lines; a second end of the thin film transistor, which is coupled to the corresponding one of a plurality of scan lines; and a third end of the thin film transistor, which is coupled to the red , The pixel electrode of the opposite one of the green and blue display pixels; n nodes, the opposite one of the n nodes is connected to three adjacent drain lines at the same time through three switches respectively, included in the red related drain line One of them, one of the green related drain lines, and one of the blue related drain lines. An input latch circuit for receiving 3n digital image data corresponding to 3n pixels; an output latch circuit for receiving 3n digital image data from the input latch circuit; and a 3n digital-to-analog converter for receiving data from The 3n digital image data of the latch circuit is output, and n conversion signals are supplied to n nodes in a time division multiplexing manner.

According to another embodiment of the present invention, there is provided a display device including: a first display area has n drain lines; a second display area has n drain lines; first and second display areas A plurality of scan lines common to the block and intersect the drain lines of the first and second display blocks; a plurality of pixels are arranged on the plurality of scan lines and the drain lines of the first and second display blocks Near the intersection, opposite one of the plurality of pixels has a thin film transistor, and a first end of the thin film transistor is coupled to the opposite one of the drain lines of the first and second display blocks. A second end is coupled to the corresponding one of the plurality of scan lines, and a third end of the thin film transistor is coupled to the pixel electrode of the corresponding one of the plurality of pixels; n drain bus wires, the drain Each of the pole bus wires is coupled to a corresponding one of the drain line of the first display block via a first switch circuit controlled by a first control signal, and each of the drain bus wires It is coupled to the corresponding one of the drain line of the second display block via a second switch circuit controlled by a second control signal, and is coupled to n digital-to-analog converters, the n digital-to-analog converters Each of is coupled to the opposite one of the n-drain bus wire; a latch circuit, which is coupled to the n digital-to-analog converter; and a delay device, which is coupled to the latch circuit, wherein the The delay device includes an input terminal for receiving digital image data; a third switch circuit. The first terminal of the third switch circuit is coupled to the input terminal, and a delay circuit is coupled to the input terminal; One end is coupled to the output end of the delay circuit, and the output end is coupled to the second end of the third switch circuit and the second end of the fourth switch circuit, and the third switch circuit is in the first and second display One of the blocks outputs image data corresponding to a plurality of pixels, and the fourth switch circuit outputs digital image data corresponding to a plurality of pixels in the other of the first and second display blocks.

According to another embodiment of the present invention, a display device is provided including: m display blocks, each of the m display blocks has a 3n drain line; a plurality of scan lines common to the m display blocks, and Intersect the drain line of the m display block; the plurality of pixels are arranged near the intersection of the plurality of scan lines and the drain line of the m display block, the opposite one of the plurality of pixels has a thin film transistor, and the thin film transistor A first end of the thin film transistor is coupled to the corresponding one of the drain line of the m display block, a second end of the thin film transistor is coupled to the corresponding one of a plurality of scan lines, and a third of the thin film transistor The terminal is a pixel electrode coupled to one of a plurality of pixels; each of the 3n bus wires and each of the 3n bus wires is a relatively first type drain controlled by a control signal of one selected by the m display block Line is coupled to the corresponding one of the 3n drain line of the opposite one of the plurality of display blocks, and the control signal is common to the first type switch in the opposite one of the m display blocks; and k drain The opposite of the k-drain driver is coupled to the 3n bus wire via a switch circuit controlled by a control signal for selecting one of the k-drain drivers, and the switch circuit has a 3n second type switch , Each of which is connected between the corresponding one of the 3n bus wire and the corresponding one of the k-drain driver whose 3n output is short. Each of the k-drain drivers has: an output latch A circuit for receiving digital image data from an external circuit; and an input latch circuit for receiving digital image data from the input latch circuit, and for outputting the digital image data to the 3n output terminal, and constructing the The relative one of the k-drain drivers, so that one of the k-drain drivers can receive the digital image data of one of the m display blocks from the external circuit, and the other of the k-drain drivers It outputs the previously received digital image data of the other one of the m display blocks to the 3n bus wire.

According to another embodiment of the present invention, a display device is provided that includes: p display blocks, each of which has a plurality of drain lines; r display blocks each of which has a plurality of drain lines; p and r display areas There are a plurality of scan lines in the block, and they intersect the drain lines of the p and r display blocks; the plurality of pixels are arranged near the intersection of the scan lines and the drain lines of the p and r display blocks, and the plurality of pixels The opposite one has a thin film transistor, and the first end of the thin film transistor is coupled to the corresponding one of the drain lines of the p and r display blocks, and a second end of the thin film transistor is coupled to a plurality of A corresponding one of the scan line, and a third end of the thin film transistor is a pixel electrode coupled to the opposite one of a plurality of pixels; a first bus bar includes a plurality of bus wires, and is controlled by a relative control signal Relative to the first type of switching circuit, it is coupled to a relative number of the p display blocks; each of the plurality of bus wires of the first bus bar is the drain electrode of the relative number of the p display blocks The corresponding one of the lines is related; a second bus bar includes a plurality of bus bar wires, and is coupled to a relative number of the r display blocks through a relative second type switch circuit controlled by a relative control signal. Each of the plurality of bus wires of the second bus bar is related to the corresponding one of the relatively few drain lines of the r display blocks. A first drain driver is coupled to the first bus; and a second drain driver is coupled to the second bus. The first and second drain drivers sometimes supply image signals that are at least partially different from each other. Give multiple pixels.

Specific embodiments according to the present invention will now be described in more detail with reference to the drawings.

Fig. 1 illustrates a first specific embodiment of a display device according to the present invention.

A plurality of scan lines GL and a plurality of drain lines DL are arranged in the display area DPA of a display panel PNL composed of an isolation substrate such as a glass substrate. A thin film transistor is manufactured in each pixel of a plurality of pixels arranged in the matrix construction near the scan line GL and the drain line DL, wherein the thin film transistor has: a gate electrode connected to the scan lines One of GL; a drain, which is connected to one of the drain lines DL; and a source, which is connected to a pixel electrode.

The display of FIG. 1 is only a three-piece combination of a red display pixel PXR, a green display pixel PXG, and a blue display pixel PXB, and these three primary color display pixels are coupled to the plurality of pixels in the display area. One of the scan lines GL. A three-component combination of three primary color display pixels forms a dot. Although not shown in FIG. 1, the above-mentioned three combinations of the three primary color image elements are repeatedly arranged on each of the scanning lines GL. That is, one scan line GL has a plurality of coupled dots, and the plurality of scan lines GL are arranged parallel to each other in the vertical direction of FIG. 1 so that the display area DPA can be formed. Each of the three transistor sources of the three combinations of three pixels in FIG. 1 is connected to the pixel electrode of the corresponding one of the pixels.

Each of the scan lines GL manufactured in the display area DPA extends to the outside of the display area DPA, and is connected to the gate driver VSR outside the display area DPA. The drain line DL also extends to the outside of the display area DPA and is connected to a switch circuit outside the display area DPA.

In FIG. 1, the drain line DLR related to the red display pixel is connected to one end of a first switch SWR, and the drain line DLG related to the green display pixel is connected to one end of a second switch SWG, and is connected to one end of a second switch SWG. The drain line DLB related to the display pixel is connected to one end of a third switch SWR. The other ends of the three switches SWR, SWG, SWB are commonly connected to a first node N1. The on or off control of the first switch SWR is performed through a first signal ΦR, the on or off control of the second switch SWG is performed through a second signal ΦG, and the on or off control of the third switch SWB is performed through a first signal. Three signals ΦB are executed. The plurality of dots are arranged along each of the scan lines GL as described above, and in FIG. 1, each of the three combinations of three drain lines DLR, DLG, and DLB, and each of them The three combinations of three switches SWR, SWG, SWB controlled by three signals ΦR, ΦG, and ΦB are repeatedly arranged in one direction of the scanning lines GL. That is, the manufacturing node is equal to the number of dots arranged along each of the scan lines GL. In this specification, the multiple drain lines DLR coupled to the red display pixels form a group, the multiple drain lines DLG coupled to the green display pixels form another group, and the multiple drain lines DLB coupled to the blue display pixels are Still forming another group.

The other terminal node N1 connecting the first, second, and third switches SWR, SWG, SWB is connected to one of the terminals VIDEOIN manufactured on the display panel PNL. The number of VIDEOINs of the terminals manufactured on the display panel PNL is equal to the number of dots arranged along a scan line GL, that is, one third of the number of pixels is coupled to the scan line GL. Each of these end VIDEOINs is connected to the opposite first end of the three elastic cord carrier packages TCP1, TCP2, and TCP3 installed on the drain drivers DRV1, DRV2, and DRV3. This specific embodiment uses three tape carrier packages, but the number of tape carrier packages in the present invention is not limited to three, and can be based on the number of points on the display panel PNL or the number of ends of the tape carrier package And change. The opposite second ends of the three elastic cord carrier packages TCP1, TCP2, and TCP3 simultaneously supply image data from external devices, etc. The plural bit data IR corresponding to the red display pixel, the plural bit data IG corresponding to the green display pixel, and the plural bit data IB corresponding to the blue display pixel are simultaneously obtained from the external equipment of the liquid crystal display device (not shown in the figure). Display) is supplied to the liquid crystal display device.

For example, each of the three pixels displaying red (R), green (G), and blue (B) can generate a 64-gray image (that is, about 260,000 different colors are generated in one image point) In the case of, the digital data of each of the pixels is formed by 6 bits; therefore, the external device can simultaneously output 18-bit image data corresponding to a picture point. The image data supplied to the tape carrier packages TCP1, TCP2, and TCP3 are supplied to the drain drivers DRV1, DRV2, DRV3 installed on them. The drain drivers DRV1, DRV2, and DRV3 convert the supplied digital image data into analog image signals, and then the converted image signals are supplied to the corresponding terminals of the pixels PXR, PXG, and PXB through the terminals VIDEOIN, nodes N1, and PXB. ..., switches SWR, SWG, SWB, and drain lines DLR, DLG, DLB manufactured on the display panel PNL.

In this specific embodiment, for example, the drain driver DRV1 among the drain drivers DRV1, DRV2, DRV3 is manufactured on a semiconductor chip, and the semiconductor chip is mounted on the wire tape carrier package TCP1, but has The semiconductor chip of the drain driver DRV1 manufactured above is directly mounted on the display panel PNL.

Each of the drain drivers DRV1, DRV2, DRV3 includes: an input latch I-LTC for receiving 18-bit image data corresponding to a picture point each time in synchronization with a clock signal, and then from External equipment supply; an output latch P-LTC to receive the entire image data stored in the input latch I-LTC each time; and a digital-to-analog converter DAC to convert the output latch P-LTC The stored image data is converted into an analog image signal; and an internal control circuit ITC is used to control the input latch I-LTC and the output latch P-LTC according to an external supply signal ΦD.

The display device of this embodiment further includes an external control circuit TCON supplying signals to control the shift register included in the gate driver VSR; supplying the first, second and third signals ΦR, ΦG, ΦB , To control the switch circuits SWR, SWG, SWB manufactured on the display panel PNL. The external control circuit TCON supplies the signal ΦD to the internal control circuit ITC in the drain driver DRV, and supplies a reference voltage Vref to the digital-to-analog converter DAC to generate the gray level image signal supplied to the pixel.

FIG. 2 shows the detailed structure of the drain driver DRV1 among the drain drivers DRV1, DRV2, and DRV3 shown in FIG. The three drain drivers DRV1, DRV2 and DRV3 are shown in FIG. 1. They have the same structure, and only the drain driver DRV1 will be described. The three image data IR, IG and IB are simultaneously input to the drain driver DRV1. Although it is not shown in detail in the figure, when each of the pixels produces a 64-gray image, the drain driver DRV1 requires 18 input terminals for one image point. If the drain driver DRV1 is constructed to receive image data corresponding to two image points at the same time each time, 36 input ports will be required. Whether the image data corresponding to one or two image points is constructed and input at the same time is determined by the trade-off between the working speed of the drain driver DRV1 and the number of input terminals; therefore, the number of image data input at the same time is equal to The invention is irrelevant.

The input image data is continuously supplied to the input latch I-LTC. The input latch I-LTC includes a red image data latch I-LTC-R and a green image data latch I-LTC related to the red (R), green (G) signal, and blue (B) signal, respectively -G, latch I-LTC-B with a blue image data. The relative data latches I-LTC-R, I-LTC-G, and I-LTC-B use image data in synchronization with a clock signal ΦTr from the internal control circuit ITC.

After each of the input data latches I-LTC-R, I-LTC-G, and I-LTC-B receives image data corresponding to a predetermined number n of image points of 3n pixels, it will correspond to The n pixels (corresponding to one of the corresponding one of the red (R), green (G), and blue (B) input data latches The pixel produces a 64-gray image corresponding to 6n bits) and transmits it to the output latch P-LTC.

Each red image data corresponding to each pixel in the red image data stored in the red image data input latch I-LTC-R is sent to and stored in the red latch element R1 in the output data latch P-LTC The corresponding one of, R2,..., Rn. Each green image data corresponding to the corresponding one of the pixels in the green image data stored in the green image data input latch I-LTC-G is sent to and stored in the green latch element in the output data latch P-LTC Corresponding one of G1, G2,..., Gn. Each blue image data corresponding to one of the pixels in the blue image data stored in the blue image data input latch I-LTC-B is sent to and stored in the output data latch P-LTC A corresponding one of the blue latch elements B1, B2, ..., Bn.

The image data stored in the 3n latch element of the output latch P-LTC is converted by the digital-to-analog converter DAC into an analog image signal representing the gray level according to the image data, wherein the converter DAC is coupled to the latches The relative lock elements correspond to some. The n digital-to-analog converters respectively coupled to n red latch elements R1, R2,..., Rn, and labeled DAC1, DAC4, DAC7,..., DAC3n-2 are synchronized with a signal Φ1 and will change from n red The converted image signal output of the image data stored in the latch element. Thereafter, they are respectively coupled to n green latch elements G1, G2,..., Gn, and n digital-to-analog converters labeled DAC2, DAC5, DAC8,..., DAC3n-1 are synchronized with a signal Φ2 and will The converted image signal output of the image data stored in the n green latch elements, and then are respectively coupled to the n blue latch elements B1, B2,..., Bn, and the ones labeled DAC3, DAC6, DAC9,..., DAC3n The n digital-to-analog converters are synchronized with a signal Φ3 to output the converted image signal of the image data stored in the n blue latch elements.

By performing the above processing, the digital image data corresponding to n dots is converted into analog image signal, and it is based on the red image signal corresponding to n red display pixels, the green image signal corresponding to n green display pixels, and the corresponding n blue The blue image signal of the color display pixel is supplied in the form of the output terminal O1, O2,..., On of the drain driver DRV1 to the display panel PNL.

The internal control circuit ITC supplies the signal Φ1, Φ2, Φ3 to the output latch P-LTC and the digital-to-analog converter DAC. The signal Φ1, Φ2, Φ3 can be generated in various ways, and can be counted in the supply image data The clock included or generated by the clock supplied by an external control circuit. The method of generating the signals Φ1, Φ2, and Φ3 is not limited to the description related to this specific embodiment.

The external device continuously supplies image data corresponding to 3n dots related to one of the scan lines GL of the display panel PNL. Therefore, in this specific embodiment, each of the three drain drivers DRV1, ERV2, and DRV3 coupled to the display panel PNL is a time-division multiplexing manner that corresponds to n points from The image data among the 3n image data provided by the external device receives its input latch I-LTC. Therefore, the operation start times of the three input latches I-LTC in the drain drivers DRV1, DRV2, and DRV3, respectively, are different from each other. The operation start clock is supplied from the external control circuit TCON to the opposite drain drivers DRV1, DRV2, and DRV3, or the input latch I-LTC in one of the drain drivers can be constructed according to the input from the drain drivers. A signal from another driver to start its operation, where the signal indicates whether its input latch operation is complete. However, the three color image signals are synchronously supplied from the drain drivers DRV1, DRV2, and DRV3 to the display panel PNL. Each of the signals Φ1, Φ2, and Φ3 is usually in the three drain drivers DRV1, DRV2, DRV3.

FIG. 3 describes the timing relationship between the signals of the display device of this specific embodiment related to FIGS. 1 and 2. The display panel PNL shown in FIG. 1 can display 3n dots in the direction of the scan line GL. Therefore, the formation on the display panel PNL is that 3n switches SWR are coupled to the drain line DLR related to the red display pixel; 3n switches SWG are coupled to the drain line DLG related to the green display pixel; and 3n switches SWB are coupled To the drain line DLB associated with the blue display pixel. There are 3n nodes N1, each of which connects the end points of three adjacent switches SWR, SWG, and SWB together. Three drain drivers DRV1, DRV2, DRV3 for supplying image signals are coupled to 3n nodes N1. Each of the DRV1, DRV2, and DRV3 can drive n pixels (that is, 3n pixels) in the horizontal direction.

In FIG. 3, IR, IG, and IB respectively represent red, green, and blue image data supplied from an external device to the display device of this embodiment. The image data corresponding to the 3n red display pixels related to one of the scanning lines GL is continuously supplied as indicated by the symbols R'1, R'2,..., R'n, R'n+1,..., R'3n, corresponding to The image data of the 3n green display pixels related to one of the scanning lines GL is continuously supplied as indicated by the symbols G'1, G'2,..., G'n, Gn+1,..., G'3n, and corresponding The image data of the 3n blue display pixels related to one of the scanning lines GL is continuously supplied as indicated by the symbols B'1, B'2,..., B'n, B'n+1,..., B'3n . A period of supplying image data corresponding to the 3n dots formed on a specific scan line GL is represented by the symbol H, and a blanking time BLK is defined as when the supply of image data corresponding to the specific scan line GL is completed to the corresponding next A time interval after the start of the supply of image data for a scan line GL. Here, the symbol R'1 indicates the image data displayed on the first red display pixel coupled to a specific scan line GL, and the symbol R'n indicates the image data displayed on the nth red display pixel coupled to the specific scan line GL The displayed image data. Symbols R"1 and R"n indicate the image data displayed on the first and nth red display pixels coupled to the next scan line GL, respectively, and the symbols R1 and Rn indicate that they are coupled before the specific scan line GL The image data displayed on the first and nth red display pixels of the scan line. G'1, G'n, G"1, G"n, G1, Gn, B'1, B'n, B"1, B"n, B1, and Bn represent image data in the same way.

The image data corresponding to the 3n dots related to one of the scan lines GL is simultaneously supplied to the three drain drivers DRV1, DRV2, DRV3 provided on the display panel PNL, and the first drain driver DRV1 receives the corresponding data at 3n. The input latch I-LTC image data of the first to the nth picture points among the picture points, the second drain driver DRV2 receives the corresponding (n+1)th to the 2nth picture points among the 3n picture points The input latch I-LTC, and the third drain driver DRV3 receives the image data corresponding to the (2n+1)th to 3nth input latch I-LTC in the 3n point. This operation will be repeated on the image data related to the remaining scan lines GL.

In Figure 3, I-LTC-R, I-LTC-G, and I-LTC-B are the input latches I-LTC-R, I-LTC-G, and I-LTC-G, respectively, of the first drain driver DRV1. I-LTC-B. After the image data corresponding to one H period is input to the input latch I-LTC of the first, second, and third drain drivers DRV1, DRV2, DRV3, the input of each of the drain drivers DRV1, DRV2, DRV3 The image data stored in the latches I-LTC-R, I-LTC-G, and I-LTC-B are transmitted to the output latch P-LTC in synchronization with a signal Φ0 shown in FIGS. 2 and 3. In Figure 3, R1,..., Rn, G1,..., Gn and B1,..., Bn are the output latch elements R1,..., Rn, G1,..., Gn, and B1, respectively, in the drain driver DRV1. ..., the image data stored in Bn.

After the image data corresponding to a scan line GL is supplied to all three drain drivers DRV1, DRV2, DRV3, the image data will be transmitted from the input latch I-LTC to the output latch P-LTC; therefore, in a specific period During this period, the image data stored in the output latch P-LTC corresponds to one of the scan lines GL, where the scan line GL is related to the image data received by the input latch I-LTC during a specific period In front of the other scan line GL.

In the state where the output latch P-LTC holds the image data, the signals Φ1, Φ2, and Φ3 are continuously turned into the conductive state as shown in FIG. 3, where the signal Φ1 is supplied to the latch elements R1, R2,..., Rn, It is used to store the red display image data; the signal Φ2 is supplied to the latch elements G1, G2,..., Gn to store the green display image data; and the signal Φ3 is supplied to the latch elements B1, B2,..., Bn for use The image data is displayed in blue. With this operation, when the signal Φ1 is in the on state, the red display image data stored in the latch elements R1, R2,..., Rn are converted into digital-to-analog converters DAC1, DAC4,..., DAC3n-2, respectively The analog image signal is output through the output terminals O1, O2,..., On of the drain driver DRV1; after that, when the signal Φ2 is in the on state, it is stored in the green display of the latch elements G1, G2,..., Gn The image data is converted into analog image signals through the digital-to-analog converters DAC2, DAC5,..., DAC3n-1, and output through the output terminals O1, O2,..., On of the drain driver DRV1, and then becomes the signal Φ3 In the on state, the blue display image data stored in the latch elements B1, B2,..., Bn are converted into analog image signals through the digital-to-analog converters DAC3, DAC6,..., DAC3n, respectively, and passed through the drain driver The output terminals of DRV1 are O1, O2, ..., On and output.

The signals ΦR, ΦG, ΦB used to control the switch circuits SWR, SWG, SWB coupled to the output terminal of the drain driver DRV1 will be used to control the output latch P-LTC and the digital-to-analog converter DAC in the drain driver DRV1 The signals of Φ1, Φ2, and Φ3 become conductive in synchronization, so that the switch circuits SWR, SWG, and SWB are conductive.

In Figure 1, the image signal corresponding to the red display image data is output based on the signal Φ1 from the red-related digital-to-analog converter DAC of the three drain drivers DRV1, DRV2, and DRV3, and is the 3nth signal that is turned on by the signal ΦR. A switch SWR corresponds to some and is supplied to the corresponding ones of the red display pixels PXR. Thereafter, the first switch SWR is turned off according to the signal ΦR, and the output from the digital-to-analog converter DAC related to the red display data in the drain drivers DRV1, DRV2, DRV3 is stopped by the signal Φ1. After that, the image signal corresponding to the green display image data is output according to the signal Φ2 from the green-related digital-to-analog converter DAC of the three drain drivers DRV1, DRV2, DRV3, and is the 3n second signal turned on by the signal ΦG. The switches SWG correspond to some and the green display pixels PXG are supplied to correspond to some. Thereafter, the second switch SWG is closed according to the signal ΦG, and then the output from the digital-to-analog converter DAC related to the green display data in the drain drivers DRV1, DRV2, DRV3 is stopped through the signal Φ2.

Thereafter, the image data corresponding to the blue display image data is output based on the signal Φ3 from the blue-related digital-to-analog converter DAC of the three drain drivers DRV1, DRV2, DRV3, and is 3n turned on by the signal ΦB Some of the third switches SWB are supplied to the corresponding ones of the blue display pixels PXB. Thereafter, the second switch SWB is turned off according to the signal ΦB, and the output from the digital-to-analog converter DAC related to the blue display data in the drain drivers DRV1, DRV2, DRV3 is stopped through the signal Φ3. The above operations will be repeated on each of the scan lines GL to generate an image in the display area DPA. The image signal corresponding to a specific one of the scan lines GL from the relative drain drivers DRV1, DRV2, DRV3 is synchronized with each other and supplied to the corresponding ones of the nodes N1 of the display panel PNL, and the drain drivers DRV1, DRV2 The signals Φ1, Φ2, and Φ3 of one of the DRV3 are synchronized with the corresponding ones of the other signals Φ1, Φ2, and Φ3 of the drain drivers DRV1, DRV2, and DRV3.

In the case of this embodiment, the red (R) image data, the green (G) image data, and the blue (B) image data are traditional display devices that are continuously supplied, and then the drain driver divides the red (R) image data, the green (G) image data, and the blue (B) image data. (R) image signal, green (G) image signal, and blue (B) image signal supply pixels, the image data is divided into red (R) data, green (G) data, and blue (B) data. It is necessary to add a data aligner before the pole driver DRV, and then supply the separated data to the drain driver.

However, in the display device according to this embodiment of the present invention, the drain driver DRV includes an input latch and an output latch to store a corresponding amount equal to three times the number of image data output by the drain driver DRV each time In addition, the number of digital-to-analog converters is equal to three times the number of image data output by the drain driver DRV each time; as a result, the number of parts required for traditional display devices can be reduced.

The number of map points related to a scan line GL varies with the size of the display panel PNL and the display resolution; therefore, in traditional display devices, the data aligner structure implemented in front of the drain driver DRV needs to be based on the map points Corrected for changes in quantity. However, in the display device of this embodiment, the need for a data aligner can be eliminated, and as in the case of a conventional display device that does not use time-division multiplexing driving, it is only necessary to supply the image data to the drain driver at the same time. DRV. As a result, the display device of this embodiment can be easily changed using the specifications of the display device.

In the above-mentioned first embodiment, the input latch and output latch that can store image data corresponding to 3n pixels are provided in the drain driver DRV, and the drain driver DRV is constructed to supply the image signal every time For n pixels, each image data corresponding to one pixel is composed of a plurality of bits, and a 3n digital-to-analog converter DAC is provided to each of the output latches. The digital image data corresponding to the red (R) pixels, green (G) pixels, and blue (B) pixels are converted into analog signals in a time division multiplexing manner. Therefore, the structure can be modified so that a digital-to-analog converter DAC is commonly provided to the red (R), green (G), and blue (B) pixels. In this case, the operating speed of the digital-to-analog converter DAC needs to be increased, and the total area DAC occupied by the digital-to-analog converter in the drain driver DRV can be reduced.

In this specific embodiment, the three image signal line driver circuit supplies image signals to n pixels, that is, 3n pixels are coupled to the display panel PNL, and the 3n pixels are coupled to a scan line GL, but the present invention It is not limited to this structure. For example, a drain driver DRV that supplies image data to n dots can be coupled to the display panel PNL to display n dots in a scan line, or to supply image data to two drain drivers DRV for n dots It can be coupled to the display panel PNL to display 2n dots in a scan line.

In this specific embodiment, the three drain lines DL corresponding to the red (R), green (G) and blue (B) signals related to a picture point are divided by one time during the period when a scan line GL is selected. Multiplexed way to drive. However, the six drain lines DL corresponding to the two points are driven in a time division multiplexing mode during the period of selecting a scan line GL. In this case, the six switches that are respectively coupled to the six adjacent drain lines DL and controlled using a time division multiplexing method need to be provided to the display panel PNL, and the latch element, and in each of the drain drivers DRV The number of digital-to-analog converters in one needs to be equal to twice the number in the case of Figure 2.

In the first embodiment, the signals ΦR, ΦG, ΦB used to control the switches SWR, SWG, SWB on the display panel PNL, and the signals used to control the gate driver VSR are supplied from the external control circuit TCON and supplied to The signals ΦD of the drain drivers DRV1, DRV2, DRV3 and the reference voltage Vref supplied to the digital-to-analog converter DAC are also supplied from the external control circuit TCON. The signals Φ1, Φ2, Φ3, and ΦTr used to control the latch I-LTC, P-LTC, and digital-to-analog converter DAC in the drain driver DRV are based on the supply from the external control circuit TCON. In the internal control circuit ITC signal ΦD. The places where the above-mentioned control signals are generated are not limited to those in this specific embodiment. All the above control signals are generated based on external control signals.

FIG. 4 illustrates a second embodiment of a display device according to the present invention. Formed in the display area of the display panel PNL are a plurality of scanning lines GL, a plurality of image signal lines (hereinafter referred to as drain lines) DL, and a plurality of pixels arranged in a matrix configuration, and each has a thin film transistor, wherein A gate of the thin film transistor is connected to the corresponding one of the scan lines GL; a drain is connected to the corresponding one of the drain lines DL; a source is connected to the corresponding one of the pixels The pixel electrode. In this embodiment, the display area DPA is divided into a first display area BK1, a second display area BK2, and a third display area BK3 arranged in the direction of the scan line GL. In each of the display blocks BK1, BK2, BK3, n dots (that is, 3n pixels) are formed in the scan line direction, and the 3n drain line DL shown here is in the display blocks BK1, BK2, and BK2. Configured in each display block of BK3. Among the pixels related to a scan line GL, FIG. 4 shows the first red display pixel PR1, the second red display pixel PR2, and the n-th red display pixel PRn in the first display block BK1; The (n+1)th red display pixel PRn+1 in the display block BK2 (although this pixel is the first red display pixel in the second display block BK2, this continuous marking system is used below based on simplified description) , And the 3n-th red display pixel PR3n in the third display block BK3. Although omitted in FIG. 4, the i-th green display pixel PGi and a drain line DL coupled to it, and the i-th blue display pixel PBi and a drain line coupled to it are between the i-th red display pixel PRi and The (i+1)th red display pixels PRi+1 are arranged between, where n=1, 2, and 3. The scan line GL arranged in the display area DPA is connected to the gate driver VSR outside the display area DPA. The drain line DL also extends to the outside of the display area DPA, and is connected to the switch circuits SR1, SR2,..., SR3n outside the display area DPA.

The drain line DL in the first display block BK1 is connected to the opposite first end of a first switch circuit, and the drain line DL in the second display block BK2 is connected to the opposite first end of a second switch circuit. Terminal, and the drain line DL in the third display block BK3 is connected to the opposite first terminal of a third switch circuit. The opposite second ends of the first, second, and third switch circuits are connected to a corresponding bus bar wire of a bus bar.

The drain line DL coupled to the first red display pixel PR1 in the first display block BK1 is connected to a first bus wire BR1 of the drain bus via the first switch SR1 in the first switch circuit. In the first display block BK1, the drain lines DL respectively coupled to the second red display pixel PR2 and the n-th display pixel PRn are respectively connected to the first drain bus bar via the second switch SR2 and the n-th switch SRn. The second bus bar wire BR2 and the n-th bus bar wire BRn. The drain line DL coupled to the (n+1)th red display pixel PRn+1 in the second display block BK2 is connected to the drain via the (n+1)th switch SRn+1 in the second switch circuit The first bus bar wire BR1 of the bus bar. The drain line DL coupled to the 3n-th red display pixel PR3n in the third display block BK3 is connected to the n-th bus wire BRn of the drain bus via the 3n-th switch SR3n in the third switch circuit.

The on and off control of the n switches SR1, SR2,..., SRn included in the first switch circuit related to the first display block BK1 is performed through a common signal Φ1; in the first switch circuit related to the second display block BK2 The on or off control of the n switches SRn+1, SRn+2,..., SR2n included in the two switch circuits is performed through a common signal Φ2; and the third switch circuit included in the third switch circuit related to the third display block BK3 The turn-on or turn-off control of the n switches SR2n+1, SR2n+2, ..., SR3n is performed through a common signal Φ3.

Although only the red display pixels are shown in Figure 4, the green display pixels and blue display pixels are arranged in the first, second, and third display blocks BK1, BK2, and BK3 in the same manner as the red display pixels. There are also an i-th switch SGi related to the green display pixel and an i-th switch SBi related to the blue display pixel arranged between the i-th switch SRi and the (i+1)-th switch SRi+1, where i is 1, 2, 3,.... In the case of the image signal bus, the i-th bus wire BGi related to the green display pixel and the i-th bus wire BBi related to the blue display pixel are between the i-th bus wire BRi and the (i+1)th bus wire BRi and (i+1) Arranged between the bus wires BRi+1.

In other words, each of the 3n drain lines DL in the first display block BK1 is coupled to the 3n bus wire of the drain bus via the first switch circuit composed of 3n switches controlled by the signal Φ1. Corresponds to one, and each of the 3n drain lines DL in the second and third display blocks BK2 and BK3 is a corresponding one of the 3n bus wires connected to the drain bus, wherein the first switch circuit It is connected via the second and third switch circuits, and each switch circuit is usually composed of 3n switches controlled by the second and third signals Φ2, Φ3, respectively. Usually via the first, second, and third switch circuits respectively connected to the three corresponding drain bus lines DL in the first, second, and third display blocks BK1, BK2, and BK3. Each of the 3n bus wires is a corresponding one of the 3n output terminals of the drain driver DRV. In this embodiment, the drain driver is manufactured on a semiconductor chip, and the semiconductor chip is mounted on the display panel PNL.

The drain driver DRV includes: an input latch I-LTC to continuously receive digital image data supplied from an external device; an output latch P-LTC to store in the input latch I-LTC every time it receives The entire image data and storage of them; and the digital-analog converter DAC, which converts the image data stored in the output latch P-LTC into analog image signals, and supplies the analog signals to corresponding pixels. This display device includes: an external control circuit TCON for supplying signals Φ1, Φ2, Φ3 to the first, second, and third switch circuits on the display panel PNL; Latch the signals PLS of I-LTC and P-LTC; and supply a reference voltage Vref to the digital-to-analog converter DAC in the drain driver DRV; and a delay device DLY for processing the image supplied from an external device Data, and supply the processed image data to the drain driver DRV.

In the case of the first embodiment, the image data in the same format is input to the delay device DLY. The input image data is simultaneously supplied to a first delay switch SW1 and a first delay circuit DL1. The image data supplied to the first delay circuit DL1 is delayed for a specified time, and then simultaneously supplied to a second delay switch SW2 and a second delay circuit DL2. The delayed image data supplied to the second delay circuit DL2 is delayed again for a specified time, and is supplied to a third delay switch SW3. The on or off control of the first, second, and third switches SW1, SW2, and SW3 included in the delay device DLY is performed through signals ΦD1, ΦD2, and ΦD3 supplied from the external control circuit TCON, respectively.

The operation of the display device shown in FIG. 4 is described in FIG. 5. Symbols IR, IG, and IB indicate image data related to the red (R), green (G), and blue (B) signals supplied from the external device to the delay device DLY. A plurality of bits of red image data IR, a plurality of bits of green image data IG, and a plurality of bits of blue data IB constituting a picture point are simultaneously supplied to the delay device DLY each time. Each image data corresponding to a picture point and the number of which is equal to the number of picture points coupled to a scan line GL is continuously supplied, and after the supply of the image data corresponding to a scan line GL is completed after a blanking time BLK, the corresponding The supply of image data for the scan line GL will start. The digital image data in the same format as in the case of the first embodiment is supplied to the display device from an external device.

In FIG. 5, the image data related to a specific one of the scan lines GL is based on the first image point (R1, G1, B1), the second image point (R2, G2, B2), and the third image point. (R3n, G3n, B3n), and the image data related to one of the scan lines GL behind the specific scan line GL is based on the first image point (R'1, G'1, B'1) , The second picture point (R'2, G2, B'2), ..., the 3nth picture point (R'3n, G'3n, B'3n).

Every time when the image data corresponding to a scan line GL starts to be supplied, that is, at the start time of a horizontal scan period, the first delay switch SW1 controlled by the signal ΦD1 is turned on. This conduction state will be maintained until the image data related to the nth picture point is supplied. Therefore, the supplied image data is supplied to the first delay circuit DL1, and at the same time passes through the first delay switch SW1, and is output to the drain driver DRV via the output terminal O-DLY of the delay device DLY. The image data output to the drain driver DRV includes: image data of red display pixels R1, R2,..., Rn; image data of green display pixels G1, G2,..., Gn; and blue display pixels B1, B2,..., Bn's image data.

The image data externally supplied to the first delay circuit DL1 is delayed for a specified time, and then output to the second delay switch SW2 as shown by the symbols O-DL1 in FIG. After Gn and Bn pass through the first delay switch SW1, the second delay switch SW2 is turned on for a specified time by using the signal ΦD2. The second delay switch SW2 is supplied to the drain driver DRV. The time interval between the time when the image data at the nth picture point passes through the first delay switch SW1 and the time when the second delay switch SW2 turns on needs to be equal to the delay time of the first delay circuit DL1. As in the relationship between the signals ΦD1 and ΦD2 in FIG. 5, the first delay switch SW1 will be turned off immediately after the image data related to the n-th picture point passes through the first delay switch SW1. Since the input latch I-LTC of the drain driver DRV is not capable of receiving the image data corresponding to the image point after the nth image point, the first delay switch SW1 needs to be turned off before at least the second delay switch SW2 turns on. state.

Before the image data related to the (n+1)th picture point is input to the input latch I-LTC through the second delay switch SW2, the drain driver DRV can be corresponding to the subsequent input to the input latch through the first switch SW1. The image data of the first to nth picture points of the lock I-LTC are sent to the output latch P-LTC. After that, the drain driver DRV then inputs the image data related to the picture point starting with the (n+1)th picture point to the input latch I-LTC through the second delay switch SW2, and at the same time, the output latch Lock the P-LTC store and correspond to the 3n image points including the first to the nth image point image data by using the digital-analog converter DAC to convert the analog image signal supplied to the image, and then supply the analog image signal Give the drain bus.

On the other hand, in the display panel PNL, the first switch circuit about the rise time of the signal ΦD2 used to control the second delay switch SW2 is determined by the signal Φ1 used to control the 3n switch included in the first switch circuit. Becomes a conductive state. As a result, the first to nth image signals corresponding to the first display block supplied from the drain driver DRV to the drain bus are written via the drain line DL in the first display block BK1. Wait for the pixel selected by one of the scan lines GL. During the period when the image data is written into the pixel, the image data corresponding to the (n+1)th to the 2nth dots from the first delay circuit DL1 is continuously written into the input of the drain driver DRV through the second delay switch SW2 Latch I-LTC. After the above, in the same manner as above, when the image data corresponding to the 2nth picture point passes through the second delay switch SW2, the first switch circuit of the display panel PNL will be turned off through the signal Φ1, and corresponds to the ( n+1) to the point 2n and the image data stored in the input latch I-LTC of the drain driver DRV is sent to the output latch P-ITC. After the first switch circuit is turned off, the first switch of the display panel PNL The two switching circuits will become conductive through Φ2. With this operation, the image signals corresponding to the (n+1)th to 2nth pixel points are converted by the digital-to-analog converter DAC of the drain driver DRV and written in the pixels of the second display block BK2. The pixel where the image signal is written in the second display block BK2 is coupled to the scan line GL, and the scan line GL is coupled to the pixel where the image data is written before the first display block BK1.

The delay device DLY transmits the signal ΦD3 at a specified time after the image data corresponding to the 2n-th picture point passes through the second delay switch SW2 to turn the third delay switch SW3 into a conductive state. The above specified time is equal to a delay time that the second delay circuit DL2 delays the output from the first delay circuit DL1. With this operation, the third delay switch SW3 will correspondingly start with the (2n+1)th pixel and output the pixel image data among the image data output from the second delay circuit DL2 to the drain driver DRV. The drain driver DRV continuously inputs the image data corresponding to the image point starting from the (n+1)th image point into the input latch I-LTC, and is supplied through the third delay switch SW3. After the third delay switch SW3 outputs the image data corresponding to the 3nth point, the image data stored in the input latch I-LTC of the drain driver DRV is sent to the output latch P-LTC. Before the image data is transmitted, the second switch circuit of the display panel PNL will be turned off, and the third switch circuit will be turned on through the signal Φ3. Thereafter, the delay device DLY will repeatedly correspond to the image data R'1, R'2,..., R'3n, G'1, G'2,..., G'3n, and B'1 of the next scan line GL The same operation of B'2,..., B'3n, and it is supplied from an external device.

It is desirable that the delay time of each of the first delay circuit DL1 and the second delay circuit DL2 is one third of a blanking time BLK included in the image data supplied from the external device. With this structure, the drain driver DRV uses one third of the blanking time BLK of the external device as the set time. This results in the latch I-LTC timing control P-LTC and DAC, and digital-analog The converter will become easier. In addition, although it is necessary to delay the image data output from the external device by the time corresponding to n points, the selection of the scan line GL and the control of the PNL switch circuit of the display panel become easier.

In the second specific embodiment, the display area DPA is divided into three display areas, but the present invention is not limited to this structure, and the display area DPA can be divided into 2, 4, 5, 6 or more multiple displays Block.

Fig. 6 illustrates a third embodiment of a display device according to the present invention. The display panel PNL of the display device of this specific embodiment is similar to the second specific embodiment, and the following description will focus on the difference between this specific embodiment and the second specific embodiment. The display area DPA is composed of a first display block BK1, a second display block BK2, and a third display block BK3, and each block has n dots arranged in the direction of the scan line GL. In this display device, a part of a display block is overlapped with a part of another display block; therefore, a part of a switch circuit related to a display block is connected to another display block. It is shared by a part of another switch circuit.

Specifically, a region corresponding to the two image points is shared by the first display block BK1 and the second display block BK2; therefore, the pixels PRn-1 and PRn belonging to the first display block BK1 also belong to the second display block BK1. Display block BK2. The drain line DL to the pixel PRn-1 is coupled to the bus wire BRn-1 of a drain bus via a switch SRn-1 included in a first switch circuit, and also via a second switch A switch SRn-1' included in the circuit is coupled to a bus wire BR1 of the drain bus. A drain line DL coupled to the pixel PRn is coupled to a bus wire BRn of the drain bus via a switch SRn included in the first switch circuit, and also via a switch included in the second switch circuit SRn' is coupled to a bus wire BR2 of the drain bus. Although only the drain line DL, the switch, and the bus wire of the drain bus related to the red display pixel are shown in FIG. 6, as in the case of the previous specific embodiment, they are respectively related to the green display pixel and the blue display pixel. The related drain line DL, switch, and bus wire of the drain bus. The 3n switch in the first switch circuit including the switches SRn-1 and SRn is controlled by the signal Φ1, and the 3n switch in the second switch circuit including the switches SRn-1' and SRn' is controlled by the signal Φ2. Although omitted in FIG. 6, the second display block BK2 and the third display block BK3 also share the area corresponding to the two dots; therefore, the construction of the second display block BK2 and the third display block BK3 is similar to the above Construct.

In the display device shown in FIG. 6, the (3n-4) dots are coupled to a scan line GL, that is, 3(3n-4) pixels are coupled to a scan line GL. Each of the display blocks has 3n switches, and the number of bus wires of the drain bus is 3n.

The 3n bus wire of the drain bus is coupled to the drain driver DRV via 3n terminals arranged on the display panel PNL. The drain driver DRV is manufactured on a semiconductor chip, and the semiconductor chip is mounted on the display panel PNL by using an anisotropic conductive plate or similar material, and supplies digital image data from external devices. The supplied image data is sent to the input and output latch circuits I-LTC, P-LTC through the two delay circuits DL1, DL2 and three delay switches SW1, SW2, SW3, and then the input and output latch circuits I- The digital image data stored in LTC and P-LTC are converted into analog image signals through the digital-to-analog converter DAC, and then supplied to the drain bus. The delay circuits DL1, DL2, delay switches SW1, SW2, SW3, latch circuits I-LTC, P-LTC, and digital-to-analog converter DAC in this specific embodiment are implemented in a manner similar to that described in the second specific embodiment. operate.

In addition, the drain driver DRV manufactured on a semiconductor chip includes: a control circuit TC for outputting signals for controlling the delay switches SW1, SW2, SW3; latch circuits I-LTC, P-LTC; and digital-to-analog conversion DAC; a control signal for controlling the first, second, and third switch circuits of the display panel PNL; and a control signal for controlling the drain driver DRV.

The non-uniform display between the two display blocks is suppressed by overlapping the display blocks as described above, and the number of components constituting the display device can be reduced by incorporating the delay circuit in the drain driver DRV.

The semiconductor chip is arranged on a flexible circuit substrate and is coupled to the display panel PNL via the flexible circuit substrate. Moreover, in this specific embodiment, the display area DPA is divided into three display areas. From the characteristics of the drain driver DRV, the switching circuit characteristics of the display panel PNL, cost, and other considerations, the display area DPA can be divided into 2, 4 Or more display blocks.

In addition, the multiple three-piece combinations of the first, second, and third display blocks BK1, BK2, and BK3 in this specific embodiment are laterally and repeatedly arranged, so that a larger size display area can be obtained. In this case, if the delay circuit is manufactured on a semiconductor chip manufactured by the drain driver DRV, the complicated design of the external delay circuit can be eliminated, and many types of display devices can be provided by providing an external delay device to a plurality of drain drivers DRV is supplied at low cost. Moreover, from the outside of the semiconductor chip, it is possible to establish: the delay time relative to the delay circuit; the signal timing of the control delay switch, and the signal of the digital-to-analog converter and the latch circuit; and the signal timing of the PNL switch circuit of the display panel to Improve the above beneficial effects. In this case, it is also possible to supply and establish the above-mentioned data through the image data input terminal and the image signal output terminal of the drain driver DRV, so as to process the data formed in the non-volatile and volatile memory by using an internal processing circuit. The data stored in a register is used to establish the above-mentioned delay time, timing and others. The above-mentioned establishment delay time, timing, and others can be applied to the delay device DLY and the drain driver DRV.

FIG. 7 depicts image data and signal waveforms at the relative position of the display device of this embodiment. In the specific embodiment of FIG. 6, some image points are shared by adjacent display areas, so the image data and signal waveforms shown in FIG. 7 are slightly different from the second specific embodiment. To always keep the image data sent from the input latch I-LTC to the output latch P-LTC in the drain driver DRV for a fixed time (that is, a set time), when it is supplied to the input latch The last image data of the lock passes through a specific delay switch time and a time interval between the current delay switch on-time in a horizontal scanning period which is equal to one third of the blanking time BLK. To fully select the delay time of the delay circuit is equal to one-third of the blanking time BLK, and equal to the product of the time required for the external device to output the image data corresponding to a point and the number of points shared by the two display blocks. sum.

In the case that the above-mentioned display device is coupled to an external device that can supply image data corresponding to two picture points to a drain driver DRV at a time, it is necessary to fully provide two delay circuits to the two picture points in the delay device. video material.

FIG. 8 illustrates a fourth embodiment of a display device according to the present invention. In this display device, the display area DPA is divided into five display blocks BK1 to BK5, and as in the case of the third embodiment, the two image points are shared by two adjacent display blocks. The drain line in the opposite display area is coupled to the drain bus BL through the opposite switch circuit. The turn-on or turn-off control of the relative switch circuit is performed through the relative control signal.

Specifically, in the first display block BK1, n dots (that is, 3n pixels) are coupled to a scan line GL. In Fig. 8, only one pixel PX is displayed. Each of the 3n drain lines DL coupled to the pixel column of the first display block BK1 is connected to the outside of the switch circuit of the display area DPA. Each of these switching circuits includes a 3n switch. For example, the first switch circuit includes switches SR1, SG1, SB1, SR2, SG2, SB2,..., SRn, SGn, SBn, and the 3n drain line DL is respectively connected to the 3n switches SR1, SG1, SB1, SR2, and SG2. , SB2,..., SRn, SGn, SBn. As in the previous specific embodiment, FIG. 8 only shows the drain lines coupled to the first, (n-2), and nth red display pixels and coupled to the first, (n-2), and first, (n-2), and nth red display pixels, respectively. The switches SR1, SRn-2, and SRn of the n red display pixels. It has a drain line DL coupled to the green display pixel and switches connected to SG1, SG2, ..., SGn; and a drain line coupled to the blue display pixel, and SB1, SB2 connected to the adjacent red related drain line DL ,..., SBn switches, and red related switches.

The second ends of the 3n switches SR1, SG1, SB1, SR2, SG2, SB2, ..., SRn, SGn, SBn included in the first switch circuit are corresponding ones of the 3n bus wires connected to the drain bus BL, and 3n The on or off control of the switches SR1, SG1, SB1, SR2, SG2, ..., SRn-1, SGn-1, SBn-1, SRn, SGn, SBn is controlled by the transmission control signal Φ1.

In the second display block BK2, there are n dots, including (n-1)th to (2n-2)th dots (that is, 3n pixels) coupled to the scan line GL. The 3n pixels are respectively connected to the 3n switches SRn-1', SGn-1', SBn-1', SRn', SGn', SBn', SRn+1, SGn included in the second switch circuit via drain lines. +1, SBn+1, SRn+2, SGn+2, SBn+2,..., SR2n-3, SG2n-3, SB2n-3, SR2n-2, SGn-2, SBn-2. FIG. 8 only shows the drain line DL coupled to the nth and (2n-3)th red display pixels, and the switches SRnand SR2n-3 respectively connected to the two drain lines DL. As in the case of the 3n switch included in the first switch circuit, the second end of the 3n switch included in the second switch circuit is connected to the corresponding ones of the 3n bus wires of the drain bus BL. The switching on and off of the 3n switch in the second switching circuit is performed through the control signal Φ2. The first display block BK1 and the second display block BK2 share two image points (that is, six pixels); therefore, as in the previous specific embodiment, the shared two image points (that is, the (n-1) and the six pixels of the nth image) are coupled to the drain bus via the switches SRn-1, SGn-1, SBn-1, SRn, SGn, SBn included in the first switch circuit A first group of bus conductors of the row BL are also coupled to the A second group of bus wires in the drain bus BL. Moreover, in the third display block BK3, the fourth display block BK4, and the fifth display block BK5, the above construction is provided repeatedly.

Including switches SR2n-3', SG2n-3', SB2n-3', SR2n-2', SGn-2', SBn-2', SR2n-1, SG2n-1, SB2n-1, SR2n, SG2n, SB2n, ..., SR3n-5, SG3n-5, SB3n-5, SR3n-4, SG3n-4, SB3n-4 and the third switch circuit related to the third display block BK3 is controlled by the signal Φ3. Including switches SR3n-5', SG3n-5', SB3n-5', SR3n-4', SG3n-4', SB3n-4', SR3n-3, SG3n-3, SB3n-3, SR3n-2, SG3n- 2. SB3n-2,..., SR4n-7, SG4n-7, SB4n-7, SR4n-6, SG4n-6, SB4n-6 and the fourth switch circuit related to the fourth display block BK4 is controlled by the signal Φ4 . Including switches SR4n-7', SG4n-7', SB4n-7', SR4n-6', SG4n-6', SB4n-6', SR4n-5, SG4n-5, SB4n-5, SR4n-4, SG4n- 4. SB4n-4,..., SR5n-9, SG5n-9, SB5n-9, SR5n-8, SG5n-8, SB5n-8 and the fifth switch circuit related to the fifth display block BK5 is controlled by the signal Φ5 .

In this specific embodiment, the number of dots of a scan dot line GL coupled to the display panel PNL is 5n-8, so the number of pixels coupled to the scan line GL is 3 (5n-8).

Each of the bus wires constituting the drain bus BL is connected to a first drain switch S6 and a second drain switch S7 at the same time, and is coupled to a first drain switch through the first drain switch S6. The pole driver DRV1 is also connected to a second drain driver DRV2 via the second drain switch S7. In this specific embodiment, the two drain drivers DRV1 and DRV2 are directly mounted on the display panel PNL, but the present invention is not limited to this configuration, and the two drain drivers DRV1 and DRV2 are coupled to the display panel via a flexible wiring board. And the two drain drivers DRV1 and DRV2 are directly formed on the substrate by using a low-temperature polysilicon technology or similar technology.

The two drain drivers DRV1 and DRV2 simultaneously supply digital image data IR, IG, and IB. The first drain driver DRV1 supplies a signal to the gate driver VSR to drive the scan line GL, and the control signal is used to control the switch circuit, including switches SR1, SG1, SB1 related to the display blocks BK1,..., BK5 ,..., SR5n-8, SG5n-8, SB5n-B; and used to control the drain switches S6 and S7. The external control circuit TCON is provided for the purpose of supplying signals to control the drain drivers DRV1 and DRV2, but the present invention is not limited to this configuration, and the configuration of the external control circuit TCON can be used to control the signals of the gate driver VSR, The switch circuit including switches SR1, SG1, SB1,..., SR5n-8, SG5n-8, SB5n-8, and drain switches S6, S7.

In addition, this specific embodiment can be modified as follows.

The external control circuit TCON is for supplying signals for controlling the drain switches S6 and S7, and the first drain driver DRV1 is for supplying control signals to control the first switch including switches SR1, SG1, SB1,..., SRn, SGn, SBn Circuit; includes the third switch circuit of switches SR2n-3', SG2n-3', SB2n-3', ..., SR3n-4, SG3n-4, SB3n-4; and the fifth switch circuit SR4n-7', SG4n- 7', SB4n-7',..., SR5n-8, SG5n-8, SB5n-8; and the second drain driver DRV2 is to supply control signals to control the switches SRn-1', SGn-1', SBn- 1',..., SR2n-2, SG2n-2, SB2n-2 second switch circuit; and including switches SR3n-5', SG3n-5', SB3n-5',..., SR4n-6, SG4n-6, The fourth switch circuit of SB4n-6.

FIG. 9 illustrates the details of the first drain driver DRV1 shown in FIG. 8. In this embodiment, the drain driver DRV1 is manufactured on a semiconductor wafer. The first drain driver DRV1 supplies image data corresponding to one image point each time. As in the previous embodiment, each image data corresponding to the red (R), green (G), and blue (B) signals is formed by a plurality of bits. At the same time, the image data is also supplied to the second drain driver DRV2 shown in FIG. 8 at the same time. The image data IR, IG, and IB supplied from the external device via the terminal are the input latch I-LTC input in the latch LTC. The image data stored in the input latch I-LTC is transmitted to the output latch P-LTC of the latch LTC according to a signal supplied from the internal control circuit ITC of the drain driver DRV1, and then from the output latch P- The digital image data of the LTC is converted into an analog signal through a digital-to-analog converter DAC, and then the analog signal is supplied to the display panel PNL through an external terminal.

The internal control circuit ITC is based on the external control circuit TCON of FIG. 8 to output a timing signal for controlling the transmission of the latched LTC image data and the output of the digital-to-analog converter DAC via the input signal of the control signal input terminal IT. The internal control circuit ITC is to output the signal used to control the gate driver VSR of the display panel PNL, including the switch circuit of switches SR1, SG1, SB1,..., SR5n-8, SG5n-8, SB5n-8; and output via the control signal Drain switches S6 and S7 at terminal OT. In FIG. 9, a reference voltage is omitted, and the factor bit-to-analog converter DAC is used to generate an analog image signal.

FIG. 10 illustrates the signal and data timing in the fourth embodiment described in FIGS. 8 and 9. The two drain drivers DRV1 and DRV2 simultaneously provide image data corresponding to a picture point from an external device each time, where the picture point includes a red display pixel, a green display pixel, and a blue display pixel as in the previous embodiment. . INP in FIG. 10 represents video data supplied from an external device.

The image data corresponding to the first to nth image points related to a scan line GL are input during the time interval from t=t0 to t=t1, where the image data corresponds to the first display block BK1, Then the (2n-2)th image data corresponding to the second display block BK2 is input at time t=t2, and then the (3n-4)th image data corresponding to the third display block BK3 is in Time t=t3 input, and then corresponding to the fourth display block BK4 (4n-6) image data is input at time t=t4, and then correspond to the fifth display block BK5 (5n-8) The point image data is input at time t=t5. Then, after a blanking time BLK from t=t5 to t=t6, at time=t6, the input of image data corresponding to the scan line GL will start.

The first drain driver DRV1 inputs the image data supplied during time t=t0 to t=t1 into the input latch I-LTC of the first drain driver DRV1, that is, it uses and corresponds to the first display block 3n image data related to the first to nth image points of BK1.

The second drain driver DRV2 will start a short operation before time t1, and input the image data of the (n-1) to (2n-2) points corresponding to the second display block BK2 supplied from the external device to this input Latch I-LTC. The first drain driver DRV1 uses the image data corresponding to the nth image point at time t1; thereafter, it transmits the image data stored in the input latch I-LTC to the output latch P-LTC. The image data sent to the output latch P-LTC is converted into an analog signal through the digital-to-analog converter DAC, and the analog signal is supplied to the output terminal of the drain driver DRV1. The symbol SU in FIG. 10 indicates the time required to complete the transmission of the image data from the input latch I-LTC to the output latch P-LTC, and the subsequent digital-to-analog conversion of the image data.

The first drain switch S6 and the first switch circuit including the switches SR1, SG1, SB1,..., SRn, SGn, SBn and controlled by the signal Φ1 of the display panel PNL will be turned on, and will correspond to the first to the nth figure points The output of the image signal from the first drain driver DRV1 related to the pixels of is synchronized, wherein the first to nth picture points correspond to the first display block BK1. As a result, the image signals corresponding to the 3n pixels from the first drain driver DRV1 are respectively supplied to the 3n drain lines in the first display block BK1, and pass through the first drain switch S6, the drain bus BL, and the first drain switch S6. A switch circuit is written to the corresponding pixel.

The picture point image data corresponding to the (2n-2)th picture point is written into the input latch I-LTC of the second drain driver DRV2. After the image data corresponding to the n points are input to the input latch I-LTC of the second drain driver DRV2, at time t2, the image data stored in the I-LTC of the second drain driver DRV2 is sent to the second drain The output latch P-LTC of the pole driver DRV2, and then the image data stored in the output latch P-LTC is converted into an analog image signal through the digital-analog converter DAC. After the set time of time t2, the analog image signal generated by the second drain driver DRV2 is regarded as the DRV2-OUT output of the second drain driver DRV2 as shown in FIG. 10, and needs to be turned off before outputting DRV2-OUT A first switch circuit including switches SR1, SG1, SB1, ..., SRn, SGn, SBn, and a first drain switch S6.

At the set time after time t2, the image signal output from the second drain driver DRV2 corresponding to the second display block BK2 is synchronized with the output of the second drain driver DRV2 by making the second drain switch S7 and The second switch circuit including switches SRn-1', SGn-1', SBn-1', ..., SR2n-2, SG2n-2, SB2n-2 is turned on to write the pixels of the second display block BK2.

In addition, shortly before the time t2, the first drain driver DRV1 will restart operation, and the first drain driver DRV1 will input the image data corresponding to the pixel starting from the (2n-3)th pixel into the input latch I -LTC, where the (2n-3)th picture point corresponds to the third display block BK3. In this way, the above operation is repeated in the third, fourth and fifth display blocks BK3, BK4, BK5, and then after the blanking time BLK, the above operation will be repeated on the image data corresponding to the next scan line GL.

In this way, the image data corresponding to the (5n-8)th image point related to a scan line GL and supplied from an external device is written by alternately operating each of the first and second drain drivers DRV1 and DRV2 Enter the pixels in the first to fifth display blocks BK1,..., BK5.

In this embodiment, the two image points are shared by two adjacent display blocks BK1 and BK2, and shortly before time t1, the second drain driver DRV2 will start to input image data into the second drain driver DRV2. Enter the latch I-LTC. The operation start timing of the second drain driver DRV2 is determined according to the number of pixels shared by two adjacent display blocks. As described above, when the image data is written in the period of the pixel writing time of the first to fifth display blocks BK1 to BK5, the corresponding one of the scan lines GL will remain in the selected state.

In this specific embodiment, the operation of the drain switches S6, S7 is to include switches SR1, SG1, SB1, ..., SR5n-8, SG5n-8, SB5n- which are coupled between the drain line DL and the bus bar BL. The switch circuit of 8 is synchronized, but the present invention is not limited to this construction.

In order to fully charge the drain bus BL to the potential of the image signal, the drain switches S6 and S7 can be turned on earlier than the switches SR1, SG1, SB1,..., SR5n-8, SG5n-8, SB5n -8 switch circuit conduction time. Similarly, the switch circuit including the switches SR1, SG1, SB1,..., SR5n-8, SG5n-8, SB5n-8 can be turned off later than the drain switches S6 and S7.

In addition, during the period when the switch circuit including the switches SR1, SG1, SB1,..., SR5n-8, SG5n-8, SB5n-8 and the drain switches S6 and S7 is closed, the A pre-charging circuit short-circuited between the busbar wires. This construction makes it possible to move the potential of each of the bus wires of the drain bus BL at approximately the gray-scale voltage center. As a result, this enables high-speed writing of subsequent image signals.

When the display device is driven in a dot inversion mode, it can implement a pre-charging circuit that forms the short-circuit odd-numbered bus wires and the even-numbered bus wires of the drain bus BL.

In this specific embodiment, the drain switches S6 and S7 are provided from the drain bus BL to the separate one of the two drain drivers DRV1 and DRV2 during the period when one of the two drain drivers DRV1 and DRV2 is operating. However, the structure on the display panel PNL can be simplified. The two drain drivers DRV1 and DRV2 are directly connected to the drain bus BL without the need to implement the drain switches S6 and S7. However, in this case, the two drain drivers DRV1 and DRV2 It needs to be controlled so that the image signal is not output from the digital-to-analog converter DAC in the drain driver, which does not output the image signal written to the pixel.

In the specific embodiment, the image signals written into the first, third, and fifth display blocks BK1, BK3, BK5 are generated by the first drain driver DRV1 and written into the second and fourth display blocks. The image signals of BK2 and BK4 are generated by the second drain driver DRV2; however, to make the loads of the first and second drain drivers DRV1 and DRV2 equal, the modification of this construction can make the first and second drain drivers DRV1 The operation sequence of DRV2 is reversed on the continuous scan line GL. Needless to say, the number of display blocks is not limited to five, and other odd or even numbers can be selected without departing from the spirit and scope of the present invention.

In addition, the switch circuit (SR4n-7, SG4n-7, SB4n-7, ..., SR5n in this specific embodiment) related to the display block (the fifth display block BK5 in this specific embodiment) arranged on the extreme right side -8, SG5n-B, SB5n-8) can be eliminated by adjusting the timing of turning off the scan line GL.

FIG. 11 illustrates a fifth embodiment of a display device according to the present invention. In this display device, the display area DPA is divided into five display blocks BK1 to BK5.

The plurality of drain lines DL in the first display block BK1 are coupled to a first drain bus BL1 arranged on the top of the display panel PNL via a first switch circuit S1 arranged on the top of the display panel PNL . In addition, the drain lines DL in the third display block BK1 and the fifth display block BK5 are coupled to the first switch circuit S3 and a fifth switch circuit S5 respectively disposed on the top of the display panel PNL. One drain bus BL1.

In addition, the drain lines DL in the second display block BK2, the fourth display block BK4, and the sixth display block BK6 respectively pass through a second switch circuit S2, a fourth switch circuit S2 and a fourth switch circuit S2 disposed at the bottom of the display panel PNL. The switch circuit S4 and a sixth switch circuit S6 are coupled to a second drain bus BL2 arranged at the bottom of the display panel PNL.

The first drain bus BL1 is connected to a first drain driver DRV1 arranged at one end of the display panel PNL, and the second drain bus BL2 is also connected to a second drain arranged at one end of the display panel PNL Drive DRV2. The first DRV1 and the second drain driver DRV2 are supplied in the form of digital image data from the outside of the display device.

In this specific embodiment, some map points are shared by two adjacent display blocks, and the drain line related to the shared map point is obtained by a switch included in one of the switch circuits arranged on the top of the display panel PNL. It is coupled to the first drain bus BL1, and is also coupled to the second drain bus BL2 via a switch included in one of the switch circuits arranged at the bottom of the display panel PNL.

Specifically, the drain line related to the dots shared by the first display block BK1 and the second display block BK2 is coupled to the first drain bus BL1 via the switch included in the first switch circuit S1, It is also coupled to the second drain bus BL2 via a switch included in the second switch circuit S2. The turn-on or turn-off control of the plurality of switches included in the first switch circuit on the top of the display panel PNL is performed through the signal Φ1 from the first drain driver DRV1. The third switch circuit S3 and the fifth switch circuit S5 are respectively controlled by the signals Φ3 and Φ5 from the first drain driver DRV1. The on or off control of the second switch circuit S2, the fourth switch circuit S4, and the sixth switch circuit S6 on the bottom of the display panel PNL is performed by the signals Φ2, Φ4, and Φ6 from the second drain driver DRV2, respectively. The third switch circuit S3 and the fifth switch circuit S5 are respectively controlled by the signals Φ3 and Φ5 from the first drain driver DRV1. The signals for controlling the two drain drivers DRV1 and DRV2 and the signals for controlling the gate driver VSR for driving the scan line GL formed in the display area DPA are supplied from an external control circuit TCON outside the display panel PNL.

In this embodiment, the n dots are each of the scan lines GL coupled to each of the display areas; therefore, the (6n-10)th dot (that is, the 3rd (6n) -10) Pixel) is coupled to each of the scan lines GL over the entire area of the display panel PNL. Therefore, the number of drain lines DL in each of the display blocks is 3n, and each of the two drain buses BL1 and BL2 at the top and bottom of the display panel PNL has 3n bus wires.

However, through the first and second drain drivers DRV1 and DRV2 with unequal driving capabilities, the number of drain lines DL in each of the first, third, and fifth display blocks BK1, BK3, and BK5 can be selected to be different. It is equal to the number of drain lines DL in each of the second, fourth, and sixth display blocks BK2, BK4, and BK6. This construction makes it possible to increase the area occupied by the drain buses BL1 and BL2 on the top and bottom of the display panel PNL, and reduce the area occupied by the other of the drain buses BL1 and BL2. area.

In this specific embodiment, the signals used to control the first, third, and fifth switching circuits S1, S3, S5 and the signals used to control the second, fourth, and sixth switching circuits S2, S4, S6 are respectively It is supplied from the drain driver DRV1 and the drain driver DRV2, but the configuration can be modified so that only one of the two drain drivers DRV1, DRV2 can supply all signals; or so that an external control circuit TCON can control the switching circuit.

In this embodiment, the two drain buses BL1 and BL2 are respectively arranged on the top and bottom of the display panel PNL, but the two drain buses BL1 and BL2 can be arranged on the top and bottom of the display panel PNL at the same time.

Needless to say, the number of display areas is not limited to six, but the display area DPA can be divided into an even or odd number other than six. In addition, the two configurations of this embodiment are side configurations, and four drain buses and four drain drivers DRV can be used for this modification.

FIG. 12 depicts the timing of signals and data in the specific embodiment described in FIG. 11. The main difference between the timings of FIGS. 10 and 12 is that the switch circuit provided to the display block is in a period during the on state. The writing of the image signal to the pixels of the first display block BK1 is performed even during a period in which the image signal is written to the pixels of the second display block BK2, and will continue until the image data is written into the third display block BK3 pixels start at time t3.

The two bus bars BL1 and BL2 are provided in the specific embodiment described in FIGS. 11 and 12; as a result, compared with the case of the fourth specific embodiment, sufficient time is available for writing the image signal into the pixel.

The above-mentioned "top of the display panel PNL" and "bottom of the display panel PNL" are used by selecting a horizontal scanning line GL expansion direction, and are not limited to the used position.

In the fourth and fifth embodiments, the switch included in the switch circuit related to the display area is formed of a polysilicon thin film transistor. The drain driver DRV manufactured on the semiconductor chip is directly mounted on the display panel PNL, but the present invention is not limited to this structure. The drain driver DRV can be formed by polysilicon on the display panel PNL as in the case of a switching circuit, or it can be coupled to the display panel PNL by mounting the drain driver on a flexible substrate.

In addition, the "drain bus" and the "bus wire" forming the drain bus are arbitrarily used in this specification, and can be referred to by other names without departing from the spirit and scope of the present invention.

In this specific embodiment, each of the display blocks is formed by a plurality of adjacent dots, but the invention is not limited to this construction. For example, the display area DPA may be formed by six display areas including a first, a second, a third, a fourth, a fifth, and a sixth display area, wherein the display areas respectively include the (6N+1)th Point, point (6N+2), point (6N+3), point (6N+4), point (6N+5), and point (6N+6), where N=0,1,2,....

When the external device is configured to supply image data corresponding to two image points at the same time each time, the structure can be modified so that one of the image data corresponding to one of the two image points can be supplied to one of the two drives DRV1 and DRV2 The other of the image data corresponding to the other of the two image points is supplied to the other of the two drivers, and each of the two drivers DRV1 and DRV2 is operated as described in the above specific embodiment.

In the first to fifth embodiments described above, the thin film transistors included in the pixels formed in the display area DPA and the thin film transistors included in the gate driver VSR formed on the periphery of the display area DPA (not shown in the figure) ) Is formed of polysilicon. The switch included in the switch circuit formed between the drain line DL on the periphery of the display area DPA and the drain driver DRV is formed of a polysilicon thin film transistor.

In addition, the characteristics of the thin film transistors formed in the display area DPA are different from those of the thin film transistors formed outside the display area DPA . Although the present invention is not limited to this structure, the thin film transistors can be placed between the drain line DL and the DRV is formed between the drain drivers. By making the electron mobility of the thin film transistor included in the pixel smaller than the electron mobility of the thin film transistor on the periphery of the display area DPA, the leakage current in the pixel thin film transistor can be suppressed, and the amount of electricity on the periphery of the display area DPA can be increased. The working speed of thin film transistors. Similarly, the characteristics of the thin film transistors included in the gate driver VSR are different from those of the pixel thin film transistors or the thin film transistors formed between the drain line DL and the drain driver DRV. In this specification, polycrystalline silicon means that a crystalline silicon is larger than amorphous silicon, which includes at least unlimited access to single crystal silicon, and that the single crystal silicon manufactured directly on the display panel PNL is not used in the present invention. Totally excluded from crystal manufacturing.

In the first to fifth embodiments, the two gate drivers VSR are arranged on the left and right outside the display area DPA. They do not need to operate at the same time, but they are constructed so that one of the two gate drivers VSR can drive them. Some odd scan lines of the scan line GL, and the other of the two gate drivers VSR can drive some even scan lines of the scan line GL. This configuration can reduce the operating speed required by the two-gate driver VSR, and provide a wider latitude in the design or manufacture of the gate driver VSR. Needless to say, the present invention is not limited to a configuration in which some consecutive scan lines GL are driven by other two gate drivers VSR, and the scan lines GL can alternately drive every plurality of scan lines GL through the two gate drivers VSR.

In the display device where the two-gate driver VSR is provided on the left and right outside the display area DPA, basically only one of the two-gate driver VSR is designed to operate, and if a problem occurs in one of the two-gate driver VSR , The other of the two-gate driver VSR can be designed and used. With this construction, even if one of the two-gate driver VSR becomes a defect in the manufacturing or assembly process, the product yield can be improved by using the other of the two-gate driver VSR instead.

In addition, the gate driver VSR is manufactured on a single crystal silicon semiconductor wafer in a conventional manner, and then directly mounted on the display panel PNL, or in the case of in-line tape carrier packaging, the semiconductor with the gate driver VSR manufactured thereon The chip is mounted on an elastic substrate, and then the tape carrier package is coupled to the display panel PNL.

In addition, in the case that the drain driver DRV is formed of polysilicon thin film transistors manufactured on the display panel PNL, the entire drain driver DRV does not need to be formed of polysilicon thin film transistors. The construction can be only a digital-to-analog converter. DAC is formed by polysilicon thin film transistors.

In addition, in the first to fifth embodiments, the image data supplied from the outside of the display device is in digital form, but the first to fifth embodiments can be modified to supply analog data. In this case, a device for converting analog data into digital data needs to be used in front of the drain driver DRV.

In addition, the display devices of the first to fifth embodiments can be applied to various types of display devices, including organic or inorganic EL type display devices that can use electroluminescent elements in addition to liquid crystal display devices that use liquid crystals.

There are two types of liquid crystal display devices. One of the two types is to generate a display by generating an electric field on a liquid crystal layer inserted between a pixel electrode formed on one of the two oppositely isolated substrates and an opposite electrode formed on the other of the two oppositely isolated substrates , Thereby driving the liquid crystal layer; and the other of the two types (the so-called in-plane switching (IPS) type) is through the pixel electrode and an opposite electrode formed on the same one of two opposed isolation substrates with a liquid crystal layer interposed therebetween A side electric field is generated between them to generate a display, thereby driving the liquid crystal layer. The construction and concept of the present invention can be applied to two types.

By using a switch circuit between the drain line DL of a display panel and the drain driver DRV to drive the drain driver in a time division multiplexing manner, the implementation of a display device can reduce the number of drain drivers DRV. Compared with the traditional display device, the cost of parts can be reduced.

<p>R1,R2,...,RnRed latch element</p><p>B1,B2,...,BnBlue latch element</p><p>G1,G2,...,GnGreen latch element</p><p>DACDigital-to-analog converter</p><p>TCP1, TCP2, TCP3Line with carrier packaging</p><p>LCPLCD display panel</p><p>DLDip Line</p><p>GLScan line</p><p>SWR,SWG,SWB, SR1,SR2,...,SRnswitch</p><p>PXR, PXG, PXB pixels</p><p>DPADisplay area</p><p>I-LTCInput latch</p><p>P-LTCOutput latch</p><p>DRV1, DRV2, DRV3Drain Driver</p><p>VSRGate Driver</p><p>BB1,BB2,...,BBnBus wire</p><p>BK1, BK2, BK3Display block</p><p>O2, O3output</p><p>Φ1,Φ2,Φ3signal</p><p>TCONExternal control circuit</p><p>ALNImage Data Arranger</p>

In all the drawings, the same reference numerals refer to similar elements, among which: FIG. 1 is a circuit diagram describing a first specific embodiment of a display device according to the present invention.

2 is a block diagram of a drain driver in a first embodiment of a display device according to the present invention.

FIG. 3 is a timing diagram describing a first specific embodiment of a display device according to the present invention.

Fig. 4 is a circuit diagram illustrating a second embodiment of a display device according to the present invention.

FIG. 5 is a timing diagram describing a second specific embodiment of a display device according to the present invention.

Fig. 6 is a circuit diagram illustrating a second embodiment of a display device according to the present invention.

FIG. 7 is a timing diagram describing a third embodiment of a display device according to the present invention.

FIG. 8 is a circuit diagram illustrating a fourth embodiment of a display device according to the present invention.

FIG. 9 is a block diagram of a drain driver in a fourth embodiment of a display device according to the present invention.

FIG. 10 is a timing diagram describing a fourth embodiment of a display device according to the present invention.

FIG. 11 is a circuit diagram illustrating a fifth embodiment of a display device according to the present invention.

FIG. 12 is a timing diagram describing a fifth embodiment of a display device according to the present invention.

Fig. 13 is a circuit diagram describing a second conventional display device.

FIG. 14 is a timing chart describing the second conventional display device.

Figure 15 is a block diagram depicting a conventional drain driver diagram.

FIG. 16 is a circuit diagram describing a first conventional display device; and

FIG. 17 is a timing chart describing the first conventional display device.